Low voltage difference linear voltage regulator circuit, low voltage difference linear voltage regulator and electronic equipment

Abstract

The present invention discloses a low-voltage-difference linear voltage regulator circuit, a low-voltage-difference linear voltage regulator, and an electronic device, which relate to the field of integrated circuit technology. The circuit comprises: a basic low-voltage-difference linear voltage regulator unit connected to a low-voltage stabilization unit; the basic low-voltage-difference linear voltage regulator unit is configured to generate an output voltage using the low-voltage stabilization unit; the low-voltage stabilization unit is configured to reduce the impedance of two non-main poles in the basic low-voltage-difference linear voltage regulator unit to increase the loop bandwidth and enhance the loop stability. The low-voltage-difference linear voltage regulator circuit is manufactured using a 180nm process, can be externally connected to a large-capacity capacitor, operates at a temperature of 77K~300K, and meets a load current of 0~50mA. The low-voltage-difference linear voltage regulator circuit of the present invention has a stronger output driving capability. The stability of the FVF loop is enhanced so that a large-capacity capacitor can be externally connected to the output end, which reduces overshoot during transient response, has a strong ability to resist shock, and also reduces output noise to a certain extent.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low voltage dropout linear voltage regulator circuit, a low voltage dropout linear regulator, and electronic equipment. Background Art

[0002] Some conventional LDO (Low Dropout Regulator) circuits based on the FVF (Flipped Voltage Follower) structure can achieve output-following input functionality, with low output impedance and strong output drive capability. However, their output voltage swing is small, making it difficult to achieve low-voltage following performance.

[0003] To address this issue, another solution has been proposed: adding a buffer before the power transistor. However, due to process limitations, the LDO output of this architecture can only be connected to a small capacitor, otherwise it will affect the stability of the FVF loop. Therefore, the output on-chip capacitance of this LDO structure is generally in the picofarad (pF) range, which greatly limits its ability to withstand shock. Summary of the Invention

[0004] In view of the above problems, the present invention provides a low voltage difference linear voltage regulator circuit, a low voltage difference linear regulator and an electronic device that solve the above problems or partially solve the above problems.

[0005] A first aspect of an embodiment of the present invention provides a low voltage difference linear voltage stabilization circuit, the low voltage difference linear voltage stabilization circuit comprising: a basic low voltage difference linear voltage stabilization unit and a low voltage stabilization unit;

[0006] The basic low voltage difference linear voltage stabilizing unit is connected to the low voltage stabilizing unit;

[0007] The basic low-dropout linear voltage stabilization unit is configured to generate an output voltage using the low-voltage stabilization unit, and the output voltage can follow the low-voltage input voltage;

[0008] The low voltage stabilization unit is configured to reduce the impedance of two non-main poles in the basic low-dropout linear voltage stabilization unit to increase the loop bandwidth and enhance the loop stability;

[0009] The low-voltage-difference linear voltage regulator circuit is manufactured using a 180nm process, can be connected to an external large-capacity capacitor, operates at a temperature of 77K to 300K, and meets a load current of 0 to 50mA.

[0010] Optionally, the basic low voltage difference linear voltage stabilization unit includes: an error amplification structure, a voltage generation structure, and a flip voltage follower structure;

[0011] The error amplification structure is used to amplify the input voltage so that the voltage of the intermediate node of the voltage generation structure is equal to the input voltage;

[0012] The voltage generating structure is used to generate a target bias voltage so that the output voltage generated by the inverted voltage follower structure is equal to the voltage of the intermediate node.

[0013] Optionally, the error amplification structure includes: an error amplifier; the voltage generation structure includes: a first transistor, a third transistor, and a fifth transistor; the flip voltage follower structure includes: a second transistor, a fourth transistor, and a pass transistor;

[0014] The inverting terminal of the error amplifier is connected to the first terminal of the third transistor and the third terminal of the fifth transistor respectively, the non-inverting terminal receives the input voltage, and the third terminal of the fifth transistor is the intermediate node;

[0015] The output end of the error amplifier is connected to the second end of the third transistor and the second end of the fourth transistor respectively, and the output end of the error amplifier generates the target bias voltage;

[0016] The first terminal of the fifth transistor receives a power supply voltage, and the second terminal receives a first bias voltage;

[0017] The third terminal of the third transistor is connected to the third terminal and the second terminal of the first transistor and the second terminal of the second transistor respectively;

[0018] A first terminal of the first transistor is grounded;

[0019] The first end of the pass transistor receives the power supply voltage, the second end is connected to the low voltage stabilization unit, and the third end is connected to the first end of the fourth transistor, and the first end of the fourth transistor serves as a main pole to output the output voltage;

[0020] The third terminal of the fourth transistor is connected to the third terminal of the second transistor and the low voltage stabilizing unit respectively;

[0021] A first terminal of the second transistor is grounded.

[0022] Optionally, the error amplification structure includes: an error amplifier; the voltage generation structure includes: a first transistor, a third transistor, a fifth transistor and a grounding capacitor; the flip voltage follower structure includes: a second transistor, a fourth transistor and a pass transistor

[0023] The inverting terminal of the error amplifier is connected to the first terminal of the third transistor and the third terminal of the fifth transistor respectively, the non-inverting terminal receives the input voltage, and the third terminal of the fifth transistor is the intermediate node;

[0024] The output end of the error amplifier is connected to the second end of the third transistor, the second end of the fourth transistor, and the first end of the grounded capacitor respectively, and the output end of the error amplifier generates the target bias voltage;

[0025] The second end of the grounding capacitor is grounded;

[0026] The first terminal of the fifth transistor receives a power supply voltage, and the second terminal receives a first bias voltage;

[0027] The third terminal of the third transistor is connected to the third terminal and the second terminal of the first transistor and the second terminal of the second transistor respectively;

[0028] A first terminal of the first transistor is grounded;

[0029] The first end of the pass transistor receives the power supply voltage, the second end is connected to the low voltage stabilization unit, and the third end is connected to the first end of the fourth transistor, and the first end of the fourth transistor serves as a main pole to output the output voltage;

[0030] The third terminal of the fourth transistor is connected to the third terminal of the second transistor and the low voltage stabilizing unit respectively;

[0031] A first terminal of the second transistor is grounded.

[0032] Optionally, the low voltage stabilization unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor;

[0033] The first terminal of the sixth transistor receives the power supply voltage;

[0034] The second end of the sixth transistor is connected to the third end of the sixth transistor, the second end of the pass transistor, the first end of the seventh transistor, the third end of the ninth transistor, and the third end of the tenth transistor, respectively. The third end of the sixth transistor is the second non-main pole of the two non-main poles.

[0035] The second end of the seventh transistor is connected to the third end of the fourth transistor, and the second end of the seventh transistor is the first non-main pole of the two non-main poles;

[0036] The third terminal of the seventh transistor is connected to the third terminal of the eighth transistor and the second terminal of the ninth transistor respectively;

[0037] The second terminal of the eighth transistor receives the third bias voltage, and the first terminal is grounded;

[0038] The first terminal of the tenth transistor receives the power supply voltage, and the second terminal receives the second bias voltage;

[0039] A third terminal of the ninth transistor is grounded.

[0040] Optionally, the basic low-dropout linear voltage stabilization unit utilizes the gain negative feedback characteristic of the operational amplifier to make the voltage of the intermediate node equal to the input voltage;

[0041] The first transistor and the second transistor have matching characteristics, and the third transistor and the fourth transistor have matching characteristics, so that the output voltage is equal to the voltage of the intermediate node, and then the output voltage is equal to the input voltage.

[0042] Optionally, the gate-source voltage of the sixth transistor and the seventh transistor is used to reduce the voltage of the first non-main pole, thereby allowing the output voltage to follow a lower input voltage;

[0043] utilizing the characteristics of the sixth transistor and the ninth transistor so that the current flowing through the sixth transistor and the ninth transistor adaptively changes with the change of the load current;

[0044] The low voltage stabilization unit is used to reduce the impedance of the second non-main pole to pull the pole of the second non-main pole farther away, and the parameters of the second transistor and the fourth transistor are adjusted respectively so that the zero poles between the first non-main pole and the binding line zero point cancel each other, thereby increasing the loop bandwidth and enhancing the loop stability.

[0045] Optionally, the large-capacity capacitor has a capacitance greater than μF.

[0046] A second aspect of an embodiment of the present invention provides a low voltage dropout linear regulator, comprising: a low voltage dropout linear regulator circuit as described in any one of the first aspects.

[0047] A third aspect of an embodiment of the present invention provides an electronic device, comprising the low voltage dropout linear regulator as described in the second aspect.

[0048] The low-voltage-difference linear voltage regulator circuit provided by the present invention includes: a basic low-voltage-difference linear voltage regulator unit and a low-voltage stabilization unit. The basic low-voltage-difference linear voltage regulator unit is connected to the low-voltage stabilization unit; the basic low-voltage-difference linear voltage regulator unit is configured to generate an output voltage using the low-voltage stabilization unit, and the output voltage can follow the input voltage of the low voltage; the low-voltage stabilization unit is configured to reduce the impedance of the two non-main poles in the basic low-voltage-difference linear voltage regulator unit to increase the loop bandwidth and enhance the loop stability. Among them, the low-voltage-difference linear voltage regulator circuit is manufactured using a 180nm process, which can be externally connected to a large-capacity capacitor, operates at a temperature of 77K~300K, and meets a load current of 0~50mA.

[0049] The low-voltage-dropout linear voltage regulator circuit proposed in this invention creatively adds a low-voltage stabilization unit to the traditional FVF structure, achieving a buffer function while also supporting load currents ranging from light loads of 0 mA to heavy loads of 50 mA. Due to the low-voltage stabilization unit, the output impedance of the FVF structure is lower than that of a traditional source follower, resulting in stronger output drive capability. Furthermore, the voltage of the first non-primary pole is pushed even lower, enabling the output voltage to follow a lower input voltage. Furthermore, the low-voltage stabilization unit structure distances the second non-primary pole. When the load current increases, the second non-primary pole is also pulled further apart, achieving zero-pole cancellation between the first non-primary pole and the tie-line zero point, thereby enhancing the stability of the FVF loop. This allows for the use of a large-capacity capacitor externally connected to the output terminal, reducing overshoot during transient response, providing strong shock resistance, and reducing output noise to a certain extent. The low-voltage-dropout linear voltage regulator circuit of this invention has high practical value. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0051] Figure 1 This is the traditional LDO circuit structure diagram based on FVF structure;

[0052] Figure 2 This is another traditional LDO circuit diagram based on FVF structure;

[0053] Figure 3 This is a modular schematic diagram of a low voltage difference linear voltage regulator circuit according to an embodiment of the present invention;

[0054] Figure 4 This is a circuit structure diagram of a relatively preferred low voltage difference linear voltage regulator circuit in an embodiment of the present invention;

[0055] Figure 5 This is a circuit structure diagram of another preferred low voltage difference linear voltage regulator circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the above-mentioned objects, features and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present invention, are only part of the embodiments of the present invention, not all of the embodiments, and are not intended to limit the present invention.

[0057] The inventors found that some of the conventional LDO (Low Dropout Regulator) circuits based on FVF (Flipped Voltage Follower) structure, referring to Figure 1 As shown, although it can achieve output V OUT Follow input V IN function, and the output impedance is low, with strong output driving capability. But its output voltage V OUT The swing is small, and it is difficult to achieve the effect of low voltage following. That is, when the input voltage V IN When the voltage is low, the output voltage V OUT Difficult to follow.

[0058] In order to solve this problem, another LDO circuit is proposed. Figure 2 As shown in the figure, a buffer is added before the power tube. Since the input capacitance and output resistance of the buffer are generally small, the two non-main poles ( Figure 2 Medium M 21 The drain and M pass The gate of the transistor is pulled further away to improve stability; at the same time, adding a buffer can effectively 21 The drain voltage decreases, the output voltage V OUT It can achieve lower voltage tracking and increase output swing. However, due to process limitations and the influence of PVT (process, temperature, environment and other factors), the output end of the LDO of this architecture can only be connected with a smaller capacitor ( Figure 2 Middle capacitor C L ), otherwise it will affect the stability of the FVF loop. Therefore, the LDO structure generally has an on-chip capacitance at the output, which is generally in the order of a few picofarads (pF), and its ability to resist shock is relatively small and greatly limited.

[0059] In order to solve the above problems, the inventors creatively proposed a low voltage dropout linear voltage regulator circuit, a low voltage dropout linear voltage regulator and an electronic device of the present invention. The technical solution of the present invention is explained and illustrated in detail below.

[0060] Reference Figure 3 , shows a modular schematic diagram of a low-voltage-dropout linear voltage regulator circuit according to an embodiment of the present invention. The low-voltage-dropout linear voltage regulator circuit according to the embodiment of the present invention includes: a basic low-voltage-dropout linear voltage regulator unit and a low-voltage stabilization unit. The basic low-voltage-dropout linear voltage regulator unit is connected to the low-voltage stabilization unit; the basic low-voltage-dropout linear voltage regulator unit is configured to generate an output voltage using the low-voltage stabilization unit, and the output voltage can follow the low-voltage input voltage.

[0061] The low voltage stabilization unit is configured to reduce the impedance of the two non-main poles in the basic low voltage difference linear voltage regulator unit to increase the loop bandwidth and enhance the loop stability. Among them, the low voltage difference linear voltage regulator circuit is made using a 180nm process, which can be connected to a large-capacity capacitor, operates at a temperature of 77K~300K, and meets the load current of 0~50mA. That is, the low voltage difference linear voltage regulator circuit based on the flip voltage follower proposed in the present invention is different from the traditional low voltage difference linear voltage regulator circuit that cannot be connected to a large-capacity capacitor, cannot track the low voltage input voltage, and can only work under non-low temperature conditions. It can not only be connected to a large-capacity capacitor, but also can follow a lower input voltage, meet the load current conditions and can also work under low temperature conditions.

[0062] A preferred basic low-dropout linear voltage regulator unit includes an error amplifier structure, a voltage generation structure, and a flip-flop voltage follower structure. The error amplifier structure amplifies the input voltage so that the voltage at the intermediate node of the voltage generation structure is equal to the input voltage. The voltage generation structure generates a target bias voltage so that the output voltage generated by the flip-flop voltage follower structure is equal to the voltage at the intermediate node.

[0063] Specifically, the error amplification structure includes an error amplifier; the voltage generation structure includes a first transistor, a third transistor, and a fifth transistor; a grounding capacitor is optional, as explained below. The flipped voltage follower structure includes a second transistor, a fourth transistor, and a pass transistor; and the low voltage stabilization unit includes a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor.

[0064] In order to better understand the connection relationship between the above basic error amplification structure, voltage generation structure, flip voltage follower structure and low voltage stabilization unit, refer to Figure 4 The circuit structure diagram of a better low voltage difference linear voltage regulator circuit is shown in FIG. Figure 4 The circuit structure diagram without grounding capacitor is shown.

[0065] The inverting terminal of the error amplifier is connected to the first terminal of the third transistor M3 and the third terminal of the fifth transistor M5 respectively, and the non-inverting terminal receives the input voltage V IN , the third terminal of the fifth transistor M5 is the middle node, Figure 4 A is used to represent the intermediate node.

[0066] The output terminal of the error amplifier is connected to the second terminal of the third transistor M3 and the second terminal of the fourth transistor M4 respectively. The output terminal of the error amplifier generates a target bias voltage V set ; The first end of the fifth transistor M5 receives the power supply voltage V DD , the second end receives the first bias voltage V BP1 .

[0067] The third end of the third transistor M3 is connected to the third end of the first transistor M1 , the second end of the first transistor M1 , and the second end of the second transistor M2 . The first end of the first transistor M1 is grounded.

[0068] Through transistor M PASS The first end receives the power supply voltage V DD The second end is connected to the low voltage stabilization unit, the third end is connected to the first end of the fourth transistor M4, and the first end of the fourth transistor M4 serves as the main pole to output the voltage V OUT .

[0069] The third end of the fourth transistor M4 is connected to the third end of the second transistor M2 and the low voltage stabilization unit respectively; the first end of the second transistor M2 is grounded. Figure 4 C L Indicates an external large-capacity capacitor.

[0070] above Figure 4 Since the error amplifier itself has the characteristic of gain negative feedback, its loop stability is good, so the target bias voltage V set It is relatively stable and does not require a ground capacitor. set The stability of the output voltage V OUT stability, so if the output voltage V OUT When the stability requirement is low, the ground capacitor is not required to increase the target bias voltage V set stability, which can reduce the area cost to a certain extent; and if the output voltage V OUT When the stability requirement is very high, it is necessary to add an additional ground capacitor to increase the target bias voltage V set The stability of the grounding capacitor is ensured, but the capacity of the grounding capacitor is very small, which will occupy a certain area and slightly increase the area overhead.

[0071] Reference Figure 5Another circuit structure diagram of a better low voltage difference linear voltage regulator circuit is shown in FIG. Figure 5 The diagram shows the circuit structure with grounding capacitors. Figure 5 The inverting terminal of the error amplifier is connected to the first terminal of the third transistor M3 and the third terminal of the fifth transistor M5 respectively, and the non-inverting terminal receives the input voltage V IN , the third terminal of the fifth transistor M5 is the middle node, Figure 5 A is used to represent the intermediate node.

[0072] The output terminal of the error amplifier is connected to the second terminal of the third transistor M3, the second terminal of the fourth transistor M4, and the grounding capacitor C X The first end of the error amplifier is connected to the output of the target bias voltage V set ; Grounding capacitance C X The second end of the fifth transistor M5 is grounded. The first end of the fifth transistor M5 receives the power supply voltage V DD , the second end receives the first bias voltage V BP1 .

[0073] The third end of the third transistor M3 is connected to the third end of the first transistor M1 , the second end of the first transistor M1 , and the second end of the second transistor M2 . The first end of the first transistor M1 is grounded.

[0074] Through transistor M PASS The first end receives the power supply voltage V DD The second end is connected to the low voltage stabilization unit, the third end is connected to the first end of the fourth transistor M4, and the first end of the fourth transistor M4 serves as the main pole to output the voltage V OUT .

[0075] The third end of the fourth transistor M4 is connected to the third end of the second transistor M2 and the low voltage stabilization unit respectively; the first end of the second transistor M2 is grounded.

[0076] The first terminal of the sixth transistor M6 receives the power supply voltage V DD The second end of the sixth transistor M6 and the third end of the sixth transistor M6, through the transistor M PASS The second end of the seventh transistor M7, the first end of the ninth transistor M9, the third end of the tenth transistor M 10 The third end of the sixth transistor M6 is connected to the second non-main pole of the two non-main poles. Figure 4 、 5 C is used to represent it.

[0077] The second end of the seventh transistor M7 is connected to the third end of the fourth transistor M4, and the second end of the seventh transistor M7 is the first non-main pole of the two non-main poles. Figure 4 、 5The third terminal of the seventh transistor M7 is connected to the third terminal of the eighth transistor M8 and the second terminal of the ninth transistor M9 respectively.

[0078] The second terminal of the eighth transistor M8 receives the third bias voltage V BN , the first end is grounded; the tenth transistor M 10 The first end receives the power supply voltage V DD , the second end receives the second bias voltage V BP2 ; The third terminal of the ninth transistor M9 is grounded. Figure 5 C L Indicates an external large-capacity capacitor.

[0079] Since it is necessary to connect a large-capacity capacitor to the output of the low-voltage-difference linear voltage regulator circuit, the capacitance of the large-capacity capacitor is greater than 5uF (a capacitor in the order of microfarads (μF)). If there is no low-voltage stabilization unit, the voltage of the first non-main pole B is higher, resulting in the output voltage V OUT It cannot follow lower input voltages (e.g. voltages below 2.5V) but can only follow higher input voltages. It also needs to be able to work normally under load currents of 0~50mA and temperatures of 77K~300K. OUT That node), so the influence of the binding wire inductance and resistance of the output node needs to be considered, so the entire integrated circuit is more difficult to stabilize when using the 180nm process.

[0080] After adding the low voltage stabilization unit, combined with the above Figure 4 、 Figure 5 As shown in the circuit structure diagram, the low voltage stabilization unit utilizes the gate-source voltage V GS , can reduce the voltage of the first non-main pole B, thereby making the output voltage V OUT It can follow a lower input voltage and, at the same time, utilize the channels of the sixth transistor M6 and the seventh transistor M7 to reduce the impedance of the first non-main pole B.

[0081] At the same time, the characteristics of the sixth transistor M6 and the ninth transistor M9 are utilized so that the current flowing through the sixth transistor M6 and the ninth transistor M9 changes adaptively with the change of the load current, thereby saving the power consumption of the entire circuit.

[0082] The entire low-voltage stabilization unit is also utilized to reduce the impedance of the second non-main pole C, thereby extending the pole of the second non-main pole C. By adjusting the parameters of the second transistor M2 and the fourth transistor M4 (generally adjusting the width-to-length ratio), the zero-pole between the first non-main pole B and the tie-line zero (the main node generates the tie-line zero) cancels out, thereby enhancing the FVF loop stability and increasing the loop bandwidth. Moreover, when the load current increases, the pole of the second non-main pole C is also extended, making the loop more stable, thus making better use of the external large-capacity capacitor.

[0083] Based on the above low voltage dropout linear voltage regulator circuit, an embodiment of the present invention further provides a low voltage dropout linear voltage regulator, and the low voltage dropout linear voltage regulator includes: any one of the above low voltage dropout linear voltage regulator circuits.

[0084] Based on the above-mentioned low-dropout linear regulator, an embodiment of the present invention further provides an electronic device, which includes the above-mentioned low-dropout linear regulator.

[0085] In summary, the low-voltage difference linear voltage regulator circuit provided by the present invention includes: a basic low-voltage difference linear voltage regulator unit and a low-voltage stabilization unit. The basic low-voltage difference linear voltage regulator unit is connected to the low-voltage stabilization unit; the basic low-voltage difference linear voltage regulator unit is configured to generate an output voltage using the low-voltage stabilization unit, and the output voltage can follow the input voltage of the low voltage; the low-voltage stabilization unit is configured to reduce the impedance of the two non-main poles in the basic low-voltage difference linear voltage regulator unit to increase the loop bandwidth and enhance the loop stability. Among them, the low-voltage difference linear voltage regulator circuit is made using a 180nm process, which can be externally connected with a large-capacity capacitor, operates at a temperature of 77K~300K, and meets a load current of 0~50mA.

[0086] The low-voltage-dropout linear voltage regulator circuit proposed in this invention creatively adds a low-voltage stabilization unit to the traditional FVF structure, achieving a buffer function while also supporting load currents ranging from light loads of 0 mA to heavy loads of 50 mA. Due to the low-voltage stabilization unit, the output impedance of the FVF structure is lower than that of a traditional source follower, resulting in stronger output drive capability. Furthermore, the voltage of the first non-primary pole is pushed even lower, enabling the output voltage to follow a lower input voltage. Furthermore, the low-voltage stabilization unit structure distances the second non-primary pole. When the load current increases, the second non-primary pole is also pulled further apart, achieving zero-pole cancellation between the first non-primary pole and the tie-line zero point, thereby enhancing the stability of the FVF loop. This allows for the use of a large-capacity capacitor externally connected to the output terminal, reducing overshoot during transient response, providing strong shock resistance, and reducing output noise to a certain extent. The low-voltage-dropout linear voltage regulator circuit of this invention has high practical value.

[0087] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0088] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0089] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A low voltage difference linear voltage regulator circuit based on a flip voltage follower, characterized in that: The low voltage difference linear voltage stabilization circuit includes: a basic low voltage difference linear voltage stabilization unit and a low voltage stabilization unit; The basic low voltage difference linear voltage stabilizing unit is connected to the low voltage stabilizing unit; The basic low voltage drop linear voltage stabilization unit is configured to generate an output voltage using the low voltage stabilization unit, and the output voltage can follow the low voltage input voltage; The low voltage stabilization unit is configured to reduce the impedance of two non-main poles in the basic low-dropout linear voltage stabilization unit to increase the loop bandwidth and enhance the loop stability; The low-voltage-dropout linear voltage regulator circuit is manufactured using a 180nm process, can be connected to a large-capacity capacitor, operates at a temperature of 77K to 300K, and meets a load current of 0 to 50mA. The low voltage stabilization unit includes: a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; a first end of the sixth transistor receives a power supply voltage; a second end of the sixth transistor is connected to a third end of the sixth transistor, a second end of the pass transistor in the basic low voltage difference linear voltage stabilization unit, a first end of the seventh transistor, a third end of the ninth transistor, and a third end of the tenth transistor, respectively; and the third end of the sixth transistor is the second non-main pole of the two non-main poles; The second end of the seventh transistor is connected to the basic low-voltage difference linear voltage regulator unit, and the second end of the seventh transistor is the first non-main pole of the two non-main poles; the third end of the seventh transistor is connected to the third end of the eighth transistor and the second end of the ninth transistor respectively; the second end of the eighth transistor receives a third bias voltage, and the first end is grounded; the first end of the tenth transistor receives the power supply voltage, and the second end receives the second bias voltage; the third end of the ninth transistor is grounded.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The basic low voltage difference linear voltage stabilizing unit includes: an error amplification structure, a voltage generation structure, and a flip voltage follower structure; The error amplification structure is used to amplify the input voltage so that the voltage of the intermediate node of the voltage generation structure is equal to the input voltage; The voltage generating structure is used to generate a target bias voltage so that the output voltage generated by the inverted voltage follower structure is equal to the voltage of the intermediate node.

3. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The error amplification structure includes: an error amplifier; the voltage generation structure includes: a first transistor, a third transistor, and a fifth transistor; the flip voltage follower structure includes: a second transistor, a fourth transistor and the pass transistor; The inverting terminal of the error amplifier is connected to the first terminal of the third transistor and the third terminal of the fifth transistor respectively, the non-inverting terminal receives the input voltage, and the third terminal of the fifth transistor is the intermediate node; The output end of the error amplifier is connected to the second end of the third transistor and the second end of the fourth transistor respectively, and the output end of the error amplifier generates the target bias voltage; The first terminal of the fifth transistor receives a power supply voltage, and the second terminal receives a first bias voltage; The third terminal of the third transistor is connected to the third terminal and the second terminal of the first transistor and the second terminal of the second transistor respectively; A first terminal of the first transistor is grounded; The first end of the pass transistor receives the power supply voltage, the second end is connected to the second end of the sixth transistor, and the third end is connected to the first end of the fourth transistor, and the first end of the fourth transistor serves as a main pole to output the output voltage; The third terminal of the fourth transistor is connected to the third terminal of the second transistor and the second terminal of the seventh transistor respectively; A first terminal of the second transistor is grounded.

4. The low voltage difference linear voltage regulator circuit according to claim 2, characterized in that: The error amplification structure includes: an error amplifier; the voltage generation structure includes: a first transistor, a third transistor, a fifth transistor and a grounding capacitor; the flip voltage follower structure includes: a second transistor, a fourth transistor and the pass transistor The inverting terminal of the error amplifier is connected to the first terminal of the third transistor and the third terminal of the fifth transistor respectively, the non-inverting terminal receives the input voltage, and the third terminal of the fifth transistor is the intermediate node; The output end of the error amplifier is connected to the second end of the third transistor, the second end of the fourth transistor, and the first end of the grounded capacitor respectively, and the output end of the error amplifier generates the target bias voltage; The second end of the grounding capacitor is grounded; The first terminal of the fifth transistor receives a power supply voltage, and the second terminal receives a first bias voltage; The third terminal of the third transistor is connected to the third terminal and the second terminal of the first transistor and the second terminal of the second transistor respectively; A first terminal of the first transistor is grounded; The first end of the pass transistor receives the power supply voltage, the second end is connected to the second end of the sixth transistor, and the third end is connected to the first end of the fourth transistor, and the first end of the fourth transistor serves as a main pole to output the output voltage; The third terminal of the fourth transistor is connected to the third terminal of the second transistor and the second terminal of the seventh transistor; A first terminal of the second transistor is grounded.

5. The low voltage difference linear voltage regulator circuit according to claim 3 or 4, characterized in that: The basic low-dropout linear voltage regulator unit utilizes the gain negative feedback characteristic of the error amplifier to make the voltage of the intermediate node equal to the input voltage; The first transistor and the second transistor have matching characteristics, and the third transistor and the fourth transistor have matching characteristics, so that the output voltage is equal to the voltage of the intermediate node, and then the output voltage is equal to the input voltage.

6. The low voltage difference linear voltage regulator circuit according to claim 3 or 4, characterized in that: Using the gate-source voltages of the sixth transistor and the seventh transistor to reduce the voltage of the first non-main pole, thereby allowing the output voltage to follow a lower input voltage; utilizing the characteristics of the sixth transistor and the ninth transistor so that the current flowing through the sixth transistor and the ninth transistor adaptively changes with the change of the load current; The low voltage stabilization unit is used to reduce the impedance of the second non-main pole to pull the pole of the second non-main pole farther away, and the parameters of the second transistor and the fourth transistor are adjusted respectively so that the zero poles between the first non-main pole and the binding line zero point cancel each other, thereby increasing the loop bandwidth and enhancing the loop stability.

7. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The large-capacity capacitor has a capacitance greater than μF.

8. A low voltage dropout linear regulator, characterized in that: The low-voltage-dropout linear regulator comprises: a low-voltage-dropout linear regulator circuit according to any one of claims 1 to 7.

9. An electronic device, characterized in that: The electronic device includes the low-dropout linear regulator according to claim 8.

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