Data transmission method and apparatus, device, and storage medium
By determining the target proportion of the preset clock signal in SDIO data transmission, the signal offset problem caused by external factors is solved, and the stability of data transmission is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIAMEN UNISOC TECH CO LTD
- Filing Date
- 2024-08-07
- Publication Date
- 2026-07-07
AI Technical Summary
During SDIO data transmission, external factors can cause signal offset to exceed the reasonable range, resulting in low data transmission stability.
By determining the number of initial period time blocks corresponding to the preset clock signal, calculating the target proportion, and sending data signals according to the target proportion, the fixed proportion between the two communicating parties is maintained to ensure correct sampling.
It improves the stability of data transmission and ensures that both communicating parties can correctly sample valid data.
Smart Images
Figure CN119105988B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the technical field of data processing, specifically relating to a data transmission method, apparatus, device, and storage medium. Background Technology
[0002] Secure Digital Input Output (SDIO) is an interface specification developed based on the Secure Digital standard. An SDIO interface can be configured in a host device to extend its functionality. For example, a host device can communicate with slave devices such as Bluetooth modules and wireless network cards via the SDIO interface.
[0003] During SDIO data transmission, the controller of either the host or slave device can acquire or send SDIO data according to the specified timing sequence. The controller chip may experience timing instability due to external factors such as voltage and temperature, resulting in signal offset. When the offset is within a reasonable range, data transmission between the two devices remains unaffected.
[0004] During the aforementioned data transmission process, when the influence of external factors is significant, the signal deviation exceeds the reasonable range, resulting in low data transmission stability. Summary of the Invention
[0005] This application relates to a data transmission method, apparatus, device, and storage medium, which addresses the shortcomings of existing technologies where signal deviation exceeds a reasonable range and data transmission stability is low when external factors have a significant impact.
[0006] In a first aspect, embodiments of this application provide a data transmission method, including:
[0007] Determine the number of initial period time blocks corresponding to the preset clock signal;
[0008] Based on the preset clock signal, a target percentage is determined, whereby the target percentage represents the ratio of the number of first time blocks to be delayed in the preset clock signal to the number of initial period time blocks.
[0009] Data signals are sent based on the target percentage.
[0010] In one possible implementation, determining the target percentage based on the preset clock signal includes:
[0011] Determine the type of device transmitting the data signal, including master type and slave type;
[0012] The number of the first time blocks is determined based on the preset clock signal and the device type;
[0013] The ratio of the number of the first time blocks to the number of the initial periodic time blocks is determined as the target proportion.
[0014] In one possible implementation, the device type is a host type, and determining the number of the first time blocks based on the preset clock signal and the device type includes:
[0015] Determine the sampling time corresponding to the preset clock signal;
[0016] The transmission time period corresponding to the data signal is determined through link training;
[0017] Determine the valid time corresponding to the transmission time period;
[0018] The number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the valid time is determined as the first time block number.
[0019] In one possible implementation, determining the transmission time period corresponding to the data signal through link training includes:
[0020] Multiple sampling information is acquired through the host device;
[0021] Determine whether there are multiple samples with similarity less than a threshold among multiple samples;
[0022] If they exist, determine the sampling times corresponding to the multiple sampling information with similarity less than the threshold, and determine the time period in which the multiple sampling times are located as the transmission time period corresponding to the data signal.
[0023] In one possible implementation, multiple sampling information is acquired via a host device, including:
[0024] The host device sends the i-th request information to the slave device.
[0025] The host device determines the i-th sampling time, which is the sampling time corresponding to delaying the preset clock signal by i time blocks.
[0026] The host device samples the i-th response information sent by the slave device at the i-th sampling time to obtain the i-th sampled information.
[0027] Where i takes the values 1, ..., n in sequence, and n is the number of the initial periodic time blocks.
[0028] In one possible implementation, the device type is a slave type, and determining the number of the first time blocks based on the preset clock signal and the device type includes:
[0029] Obtain the delay parameter from the transport protocol;
[0030] The number of the first time blocks is determined based on the delay parameter and the preset clock signal.
[0031] In one possible implementation, transmitting a data signal based on the target percentage includes:
[0032] Determine the number of current period time blocks corresponding to the preset clock signal;
[0033] The target number of time blocks is determined based on the target percentage and the number of time blocks in the current cycle.
[0034] The target clock signal is obtained by delaying the preset clock signal according to the target number of time blocks;
[0035] Simultaneously, the target clock signal and data signal are sent.
[0036] Secondly, embodiments of this application provide a data transmission apparatus, including:
[0037] The first determining module is used to determine the number of initial period time blocks corresponding to the preset clock signal;
[0038] The second determining module is used to determine a target proportion based on the preset clock signal, wherein the target proportion represents the ratio of the number of first time blocks to be delayed to the number of initial period time blocks of the preset clock signal;
[0039] The transmission module is used to send data signals according to the target proportion.
[0040] In one possible implementation, the second determining module is specifically used for:
[0041] Determine the type of device transmitting the data signal, including master type and slave type;
[0042] The number of the first time blocks is determined based on the preset clock signal and the device type;
[0043] The ratio of the number of the first time blocks to the number of the initial periodic time blocks is determined as the target proportion.
[0044] In one possible implementation, the device type is a host type, and the second determining module is specifically used for:
[0045] Determine the sampling time corresponding to the preset clock signal;
[0046] The transmission time period corresponding to the data signal is determined through link training;
[0047] Determine the valid time corresponding to the transmission time period;
[0048] The number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the valid time is determined as the first time block number.
[0049] In one possible implementation, the second determining module is specifically used for:
[0050] Multiple sampling information is acquired through the host device;
[0051] Determine whether there are multiple samples with similarity less than a threshold among multiple samples;
[0052] If they exist, determine the sampling times corresponding to the multiple sampling information with similarity less than the threshold, and determine the time period in which the multiple sampling times are located as the transmission time period corresponding to the data signal.
[0053] In one possible implementation, the second determining module is specifically used for:
[0054] The host device sends the i-th request information to the slave device.
[0055] The host device determines the i-th sampling time, which is the sampling time corresponding to delaying the preset clock signal by i time blocks.
[0056] The host device samples the i-th response information sent by the slave device at the i-th sampling time to obtain the i-th sampled information.
[0057] Where i takes the values 1, ..., n in sequence, and n is the number of the initial periodic time blocks.
[0058] In one possible implementation, the device type is a slave type, and the second determining module is specifically used for:
[0059] Obtain the delay parameter from the transport protocol;
[0060] The number of the first time blocks is determined based on the delay parameter and the preset clock signal.
[0061] In one possible implementation, the transmission module is specifically used for:
[0062] Determine the number of current period time blocks corresponding to the preset clock signal;
[0063] The target number of time blocks is determined based on the target percentage and the number of time blocks in the current cycle.
[0064] The target clock signal is obtained by delaying the preset clock signal according to the target number of time blocks;
[0065] Simultaneously, the target clock signal and data signal are sent.
[0066] Thirdly, this application provides a chip on which a computer program is stored, and when the computer program is executed by the chip, it implements the data transmission method as described in any of the first aspects.
[0067] Fourthly, this application provides a chip module on which a computer program is stored, and when the computer program is executed by the chip module, it implements the data transmission method as described in any of the first aspects.
[0068] Fifthly, embodiments of this application provide an electronic device, including: a memory, a processor, and a transceiver;
[0069] The memory stores computer-executed instructions;
[0070] The processor executes computer execution instructions stored in the memory to implement the data transfer method as described in any of the first aspects.
[0071] In a sixth aspect, embodiments of this application provide a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the data transmission method described in any one of the first aspects.
[0072] In a seventh aspect, embodiments of this application provide a computer program product, including a computer program that, when executed by a processor, implements the data transmission method described in any one of the first aspects.
[0073] This application provides a data transmission method, apparatus, device, and storage medium. In this method, the number of initial periodic time blocks corresponding to a preset clock signal is determined. Based on the preset clock signal, a target proportion is determined, whereby the target proportion represents the ratio of the number of first time blocks to be delayed from the preset clock signal to the number of initial periodic time blocks. Data signals are then transmitted based on the target proportion. This ensures that both communicating parties maintain a fixed proportion during transmission, guaranteeing that both parties can correctly sample valid data and improving the stability of data transmission. Attached Figure Description
[0074] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0075] Figure 1 This is a schematic diagram of an application scenario provided by an embodiment of this application;
[0076] Figure 2 A timing diagram of a controller output signal provided in an embodiment of this application;
[0077] Figure 3 A timing diagram of another controller output signal provided in an embodiment of this application;
[0078] Figure 4 A timing diagram of another controller output signal provided in an embodiment of this application;
[0079] Figure 5 A flowchart illustrating a data transmission method provided in an embodiment of this application;
[0080] Figure 6 A flowchart illustrating another data transmission method provided in an embodiment of this application;
[0081] Figure 7 A timing diagram of another controller output signal provided in an embodiment of this application;
[0082] Figure 8 A timing diagram of another controller output signal provided in an embodiment of this application;
[0083] Figure 9 A flowchart illustrating another data transmission method provided in an embodiment of this application;
[0084] Figure 10 This is a schematic diagram of the structure of a data transmission device provided in an embodiment of this application;
[0085] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.
[0086] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0087] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0088] It should be noted that although the terms "first," "second," etc., are used to describe various types of information in the embodiments of this application, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. Optionally, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information.
[0089] It should be understood that the terms "comprising" or "including" indicate the presence of the previously mentioned features, steps, or operations, but do not preclude the presence, occurrence, or addition of one or more other features, steps, or operations. The terms "and / or," etc., used in this application can be interpreted as inclusive, or mean any one or any combination thereof. Optionally, "A and / or B" means "any one of the following: A; B; A and B." Additionally, the character " / " generally indicates that the preceding and following objects are in an "or" relationship.
[0090] In related technologies, Secure Digital Input Output (SDIO) is an interface specification developed based on the Secure Digital Standard. An SDIO interface can be configured in a host device to expand its functionality. For example, a host device can communicate with slave devices such as Bluetooth modules and wireless network cards via the SDIO interface.
[0091] During SDIO data transmission, the controller of the host device or the controller of the slave device can collect or send SDIO data according to the timing required by the specification.
[0092] Below, in conjunction with Figure 1 This section provides examples of application scenarios for transmitting SDIO data.
[0093] Figure 1 This is a schematic diagram illustrating an application scenario provided by an embodiment of this application. Please refer to [link / reference]. Figure 1 , Figure 1It may include a master controller 101 corresponding to the host device and a slave controller 102 corresponding to the slave device. SDIO data can be transmitted between the master controller 101 and the slave controller 102. In SDIO data transmission, there may be 3 transmission lines between the master controller 101 and the slave controller 102, namely CLK, CMD, and DAT[7:0].
[0094] The master controller 101 can perform initialization operations after detecting a slave device. The initialization operations may include sending multiple commands and parameters via CMD to identify the type, function, and supported operating modes of the slave device.
[0095] The controller 102 can respond to the initialization request of the host device and send relevant information about the slave device to the host device via CMD. The relevant information may include the device's identity, version number, supported command set, etc.
[0096] The main controller 101 can send multiple commands to the slave devices via CMD. These commands can be used to control data transmission, configure device parameters, request status information, etc.
[0097] After receiving a command from the controller 102 via CMD, the controller 102 executes the corresponding operation and returns response information to the host device via CMD. The response information can be used to indicate the execution result of the command or to provide the requested data.
[0098] The main controller 101 can send read and write commands to the slave devices via CMD.
[0099] The read command can be used to indicate the address and length of the data to be read, so that the slave device can read the data from the specified address and transmit it to the master device bit by bit or byte by byte via DAT[7:0].
[0100] The write command can be used to indicate the address to which data is to be written and to provide the data to be written, so that the data is transferred from the host device to the slave device via DAT[7:0] and stored at the specified address.
[0101] During data transmission, the main controller 101 can provide a clock signal via CLK. The clock signal can synchronize data transmission between the host and the device, ensuring the accuracy and integrity of the data.
[0102] Below, in conjunction with Figure 2 The data transmission process will be further illustrated with examples.
[0103] Figure 2 This is a timing diagram illustrating the output signal of a controller according to an embodiment of this application. Please refer to... Figure 2 , Figure 2It can include the clock signal corresponding to CLK, and the signals corresponding to CMD or DAT[7:0].
[0104] In the clock signal corresponding to CLK, there is a sampling bit on each rising edge. The sampling bit is used to indicate the time point when the data on CMD or DAT[7:0] is sampled.
[0105] There are multiple valid windows in the signal corresponding to CMD or DAT[7:0]. The valid windows can be determined based on the low input voltage (V). iL ) and high input voltage (V IH The sampling bit, along with other parameters, is determined. When the sampling bit is within the valid window, the data's level state can be accurately identified and interpreted as the corresponding logic value, ensuring the accuracy of data transmission. When the sampling bit is not within the valid window, it may lead to reading errors, affecting the reliability of the entire data transmission.
[0106] To ensure that the sampling bit is within the valid window, link training can be performed before data transmission to determine the number of delay time blocks for the CLK signal, and the CLK signal can be delayed according to the number of delay time blocks.
[0107] Below, in conjunction with Figure 3 The process of delaying the CLK signal will be further illustrated with an example.
[0108] Figure 3 This is a timing diagram illustrating another controller output signal provided in an embodiment of this application. Please refer to... Figure 3 , Figure 3 It can include the clock signal corresponding to CLK, and the signals corresponding to CMD or DAT[7:0].
[0109] In the initial state, assuming that the clock signal has two delay time blocks, after link training, it is determined that if the sampling bit is in the optimal position within the effective window, three more delay time blocks need to be added.
[0110] After delaying the clock signal, the sampling bit is located at the optimal position within the effective window.
[0111] In practical applications, the chip housing the controller may experience timing instability due to external factors such as voltage and temperature, resulting in signal offset. When the offset is within a reasonable range, data transmission between the two parties remains unaffected.
[0112] Below, in conjunction with Figure 4 Examples are given to illustrate the instability in timing caused by external factors such as voltage and temperature.
[0113] Figure 4This is a timing diagram illustrating another controller output signal provided in an embodiment of this application. Please refer to... Figure 4 , Figure 4 It can include the clock signal corresponding to CLK, and the signals corresponding to CMD or DAT[7:0].
[0114] Under normal conditions, assuming 3 delay time blocks are added, the sampling bit is located at the optimal position within the effective window.
[0115] If the chip containing the controller is affected by external factors such as voltage and temperature, the delay time block generated by the delay device becomes smaller, causing the sampling point to drift to the edge region.
[0116] During the aforementioned data transmission process, when the influence of external factors is significant, the signal deviation exceeds the reasonable range, resulting in low data transmission stability.
[0117] To address the aforementioned technical problems, embodiments of this application provide a data transmission method. This method involves determining a target ratio, where the target ratio represents the ratio of the number of first time blocks to be delayed for a preset clock signal to the number of initial periodic time blocks. Based on the target ratio, data signals are transmitted. This ensures that both communicating parties maintain a fixed ratio during transmission, guaranteeing that both parties can correctly sample valid data and improving the stability of data transmission.
[0118] The technical solutions shown in this application will now be described in detail through specific embodiments. It should be noted that the following embodiments may exist independently or in combination with each other; for the same or similar content, the description will not be repeated in different embodiments.
[0119] Figure 5 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. The execution entity in this embodiment can be a controller. Please refer to... Figure 5 The method includes:
[0120] S501. Determine the number of initial period time blocks corresponding to the preset clock signal.
[0121] The preset clock signal can be the clock signal corresponding to CLK.
[0122] The initial period time block number can be used to represent the number of time blocks corresponding to one cycle of the clock signal in the initial state.
[0123] Optionally, the number of initial period time blocks corresponding to the preset clock signal can be determined based on the period delay tracking module.
[0124] Optionally, the number of initial periodic time blocks corresponding to a preset clock signal can be determined based on a time block number prediction model.
[0125] It should be noted that the number of initial period time blocks corresponding to the preset clock signal can be determined according to any feasible implementation method, and the embodiments of this application do not limit this.
[0126] S502. Determine the target percentage based on the preset clock signal.
[0127] The target percentage is used to represent the ratio of the number of first time blocks to the number of initial period time blocks for the preset clock signal to be delayed.
[0128] The first time block number can be the number of time blocks corresponding to the sampling point of the preset clock signal and the valid time. The valid time can be the best sampling time in the valid window of the signal corresponding to CMD or DAT[7:0].
[0129] Optionally, the number of first time blocks to be delayed for the preset clock signal can be determined based on the preset clock signal, and the target proportion can be determined based on the number of initial period time blocks and the number of first time blocks.
[0130] Optionally, the device type for transmitting data signals is determined; the number of first time blocks is determined based on a preset clock signal and the device type; and the ratio of the number of first time blocks to the number of initial periodic time blocks is determined as the target proportion.
[0131] Optionally, a preset clock signal can be input into the target percentage prediction model to determine the target percentage.
[0132] It should be noted that the target percentage can be determined according to any feasible implementation method and a preset clock signal, and the embodiments of this application do not limit this.
[0133] S503. Send data signals according to the target percentage.
[0134] The data signal can be the signal corresponding to CMD or DAT[7:0].
[0135] Optionally, a delay model can be set according to the target proportion. Based on the delay model, a preset clock signal is delayed to obtain the target clock signal, and the target clock signal and data signal are sent simultaneously.
[0136] Delay models can be used to determine delay parameters. Delay parameters can be used to delay a preset clock signal.
[0137] Optionally, the number of target time blocks can be determined based on the target proportion, and the target clock signal can be obtained by delaying the preset clock signal based on the number of target time blocks, while the target clock signal and data signal are sent simultaneously.
[0138] It should be noted that data signals can be sent according to any feasible implementation method and the target proportion, and the embodiments of this application do not limit this.
[0139] The data transmission method provided in this embodiment determines the number of initial periodic time blocks corresponding to a preset clock signal, and determines a target proportion based on the preset clock signal. The target proportion represents the ratio of the number of first time blocks to be delayed to the number of initial periodic time blocks of the preset clock signal. Data signals are then transmitted based on the target proportion. In this way, by maintaining a fixed proportion during transmission between the communicating parties, it is ensured that both parties can correctly sample valid data, thereby improving the stability of data transmission.
[0140] Below, in conjunction with Figure 6 The process of sending data signals according to the target proportion (S503) is explained.
[0141] Figure 6 This is a flowchart illustrating another data transmission method provided in an embodiment of this application. Based on the above embodiments, see [link to relevant documentation]. Figure 6 The method includes:
[0142] S601. Determine the number of current cycle time blocks corresponding to the preset clock signal.
[0143] The preset clock signal can be affected by external factors such as voltage and temperature, resulting in different numbers of periodic time blocks.
[0144] The current cycle time block count can be used to represent the number of time blocks corresponding to one cycle of the clock signal in the current state.
[0145] Optionally, the number of current period time blocks in the preset clock signal can be determined based on the period delay tracking module.
[0146] Optionally, the number of time blocks in the current period corresponding to the preset clock signal can be determined based on the time block number prediction model.
[0147] It should be noted that the number of current period time blocks in the preset clock signal can be determined according to any feasible implementation method, and the embodiments of this application do not limit this.
[0148] S602. Determine the target number of time blocks based on the target percentage and the number of time blocks in the current cycle.
[0149] The target number of time blocks can be the number of time blocks required to delay a preset clock signal.
[0150] The target percentage can be multiplied by the number of time blocks in the current period to determine the target number of time blocks.
[0151] S603. Based on the number of target time blocks, delay the preset clock signal to obtain the target clock signal.
[0152] For example, assuming the target time block number is 5, the preset clock signal is delayed by 5 time blocks to obtain the target clock signal.
[0153] For example, assuming the target time block number is 10, the preset clock signal is delayed by 10 time blocks to obtain the target clock signal.
[0154] S604 simultaneously transmits the target clock signal and data signal.
[0155] If the controller is the master controller, it can simultaneously send the target clock signal and data signal to the slave controller.
[0156] If the controller is a slave controller, the slave controller can simultaneously send the target clock signal and data signal to the master controller.
[0157] Below, in conjunction with Figure 7 and Figure 8 The above processes S601-S604 will be illustrated with examples.
[0158] Figure 7 This is a timing diagram illustrating another controller output signal provided in an embodiment of this application. Please refer to... Figure 7 , Figure 7 This can include the clock signal corresponding to CLK and the signal corresponding to DAT.
[0159] Assuming the target proportion is 1 / 4, the number of current cycle time blocks in the preset clock signal is determined to be 20.
[0160] The target time block is determined to be 5. The preset clock signal is delayed to obtain the target clock signal, and the target clock signal and data signal are sent at the same time.
[0161] Figure 8 This is a timing diagram illustrating another controller output signal provided in an embodiment of this application. Please refer to... Figure 8 , Figure 8 This can include the clock signal corresponding to CLK and the signal corresponding to DAT.
[0162] Assuming the target proportion is 1 / 4, the number of current cycle time blocks in the preset clock signal is determined to be 40.
[0163] The target time block number is determined to be 10. The preset clock signal is delayed to obtain the target clock signal, and the target clock signal and data signal are sent at the same time.
[0164] The implementation details of each step in this application embodiment can be found in the description of the corresponding steps or operations in the above method embodiments; repeated content will not be repeated.
[0165] The data transmission method provided in this embodiment determines the number of current period time blocks corresponding to the preset clock signal, determines the target number of time blocks based on the target proportion and the number of current period time blocks, and then delays the preset clock signal to obtain the target clock signal based on the target number of time blocks. Simultaneously, the target clock signal and the data signal are transmitted. This ensures that both communicating parties maintain a fixed proportion during transmission, guaranteeing that both parties can correctly sample valid data and improving the stability of data transmission.
[0166] Below, in conjunction with Figure 9 The process of determining the target percentage based on the preset clock signal (S502) will be explained.
[0167] Figure 9 This is a flowchart illustrating another data transmission method provided in an embodiment of this application. Based on the above embodiments, see [link to relevant documentation]. Figure 9 The method includes:
[0168] S901. Determine the type of device that transmits data signals.
[0169] If the device type is host type, then execute S902;
[0170] If the device type is slave, then execute S906.
[0171] It can obtain device information and determine the type of device sending data signals based on the device information.
[0172] Device types can include master type and slave type.
[0173] For example, mobile phones, tablets, and laptops can be host devices, while WiFi modules, GPS receivers, and TV cards can be slave devices.
[0174] S902. Determine the sampling time corresponding to the preset clock signal.
[0175] The sampling time can be the moment when data is sampled.
[0176] It can obtain a preset voltage value and determine the sampling time corresponding to the preset clock signal based on the rising edge of the preset clock signal and the preset voltage value.
[0177] S903. Determine the transmission time period corresponding to the data signal through link training.
[0178] The transmission time period can be the time period corresponding to the valid window.
[0179] Optionally, multiple test signals can be sent to obtain response signals corresponding to each test signal, and the transmission time period corresponding to the data signal can be determined based on the multiple response signals.
[0180] Optionally, the transmission time period corresponding to the data signal can be determined through link training in the following way: acquire multiple sampling information through the host device; determine whether there are multiple sampling information with similarity less than a threshold among the multiple sampling information; if so, determine the sampling time corresponding to the multiple sampling information with similarity less than the threshold respectively, and determine the time period of the multiple sampling times as the transmission time period corresponding to the data signal.
[0181] The sampling information can be the analysis results of the receiving end corresponding to the host device.
[0182] Similarity can be determined by bit error rate or by degree of similarity; no specific limitation is made here.
[0183] The time period containing multiple sampling times can be obtained by continuously processing multiple sampling times.
[0184] Optionally, multiple sampling information can be obtained through the host device in the following manner: the host device sends the i-th request information to the slave device, obtains the i-th response information sent by the slave device, determines the i+1-th request information based on the i-th response information, repeats the above steps until a preset number of response information is determined, and determines the preset number of response information as sampling information.
[0185] Optionally, multiple sampling information can be obtained through the host device in the following manner: the host device sends the i-th request information to the slave device; the host device determines the i-th sampling time, which is the sampling time corresponding to delaying the preset clock signal by i time blocks; the host device samples the i-th response information sent by the slave device at the i-th sampling time to obtain the i-th sampling information; where i takes the values 1, ..., n in sequence, and n is the number of initial periodic time blocks.
[0186] It should be noted that multiple sampling information can be obtained through the host device according to any feasible implementation method, and the embodiments of this application do not limit this.
[0187] S904. Determine the valid time corresponding to the transmission time period.
[0188] The effective time can be determined based on the transmission parameters.
[0189] The effective time can be used to indicate the optimal time to sample the data signal in order to ensure the stability of data transmission.
[0190] S905. The number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the valid time is determined as the first time block number.
[0191] After S905, S908 is executed.
[0192] It can be determined whether there is a delay in the preset clock signal. If so, the number of initial time blocks corresponding to the delay of the preset clock signal is determined. The number of initial time blocks is subtracted from the number of clock time blocks corresponding to the sampling time to obtain the second time block. The number of time blocks between the second time block and the center time block corresponding to the valid time is determined as the number of first time blocks. If not, the number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the valid time is determined as the number of first time blocks.
[0193] When it is determined that there is no delay in the preset clock signal, the number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the effective time can be determined as the first time block number.
[0194] S906. Obtain the delay parameters in the transmission protocol.
[0195] Delay parameters may include clock frequency, setup and hold time, data transfer rate, etc.
[0196] The delay parameters can be determined based on the transmission protocol, host device information, and slave device information.
[0197] S907. Determine the number of first time blocks based on the delay parameters and the preset clock signal.
[0198] The delay duration can be determined based on the delay parameters and the preset clock signal, and the number of first time blocks can be determined based on the delay duration.
[0199] S908. The ratio of the number of first time blocks to the number of initial periodic time blocks is determined as the target percentage.
[0200] For example, assuming the first time block number is 5, the initial period time block number is 20, and the target proportion is determined to be 1 / 4.
[0201] The implementation details of each step in this application embodiment can be found in the description of the corresponding steps or operations in the above method embodiments; repeated content will not be repeated.
[0202] The data transmission method provided in this embodiment determines the type of device sending the data signal. If the device type is a host, it determines the sampling time corresponding to a preset clock signal, determines the transmission time period corresponding to the data signal through link training, determines the effective time corresponding to the transmission time period, and determines the number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the effective time as the first time block number. If the device type is a slave, it obtains the delay parameter in the transmission protocol, determines the first time block number based on the delay parameter and the preset clock signal, and determines the ratio of the first time block number to the initial periodic time block number as the target proportion. In this way, both communicating parties maintain a fixed proportion during transmission to ensure that both parties can correctly sample effective data, improving the stability of data transmission.
[0203] Figure 10 This is a schematic diagram of a data transmission device provided in an embodiment of this application. Please refer to... Figure 10 The device 1000 includes a first determining module 1001, a second determining module 1002, and a transmission module 1003, wherein...
[0204] The first determining module 1001 is used to determine the number of initial period time blocks corresponding to the preset clock signal;
[0205] The second determining module 1002 is used to determine a target proportion based on the preset clock signal, wherein the target proportion represents the ratio of the number of first time blocks to be delayed to the number of initial period time blocks of the preset clock signal.
[0206] The transmission module 1003 is used to send data signals according to the target proportion.
[0207] In one possible implementation, the second determining module 1002 is specifically used for:
[0208] Determine the type of device transmitting the data signal, including master type and slave type;
[0209] The number of the first time blocks is determined based on the preset clock signal and the device type;
[0210] The ratio of the number of the first time blocks to the number of the initial periodic time blocks is determined as the target proportion.
[0211] In one possible implementation, the device type is a host type, and the second determining module 1002 is specifically used for:
[0212] Determine the sampling time corresponding to the preset clock signal;
[0213] The transmission time period corresponding to the data signal is determined through link training;
[0214] Determine the valid time corresponding to the transmission time period;
[0215] The number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the valid time is determined as the first time block number.
[0216] In one possible implementation, the second determining module 1002 is specifically used for:
[0217] Multiple sampling information is acquired through the host device;
[0218] Determine whether there are multiple samples with similarity less than a threshold among multiple samples;
[0219] If they exist, determine the sampling times corresponding to the multiple sampling information with similarity less than the threshold, and determine the time period in which the multiple sampling times are located as the transmission time period corresponding to the data signal.
[0220] In one possible implementation, the second determining module 1002 is specifically used for:
[0221] The host device sends the i-th request information to the slave device.
[0222] The host device determines the i-th sampling time, which is the sampling time corresponding to delaying the preset clock signal by i time blocks.
[0223] The host device samples the i-th response information sent by the slave device at the i-th sampling time to obtain the i-th sampled information.
[0224] Where i takes the values 1, ..., n in sequence, and n is the number of the initial periodic time blocks.
[0225] In one possible implementation, the device type is a slave type, and the second determining module 1002 is specifically used for:
[0226] Obtain the delay parameter from the transport protocol;
[0227] The number of the first time blocks is determined based on the delay parameter and the preset clock signal.
[0228] In one possible implementation, the transmission module 1003 is specifically used for:
[0229] Determine the number of current period time blocks corresponding to the preset clock signal;
[0230] The target number of time blocks is determined based on the target percentage and the number of time blocks in the current cycle.
[0231] The target clock signal is obtained by delaying the preset clock signal according to the target number of time blocks;
[0232] Simultaneously, the target clock signal and data signal are sent.
[0233] Figure 11 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Please refer to... Figure 11 The electronic device 1100 may include: a memory 1101, a processor 1102, and a transceiver 1103.
[0234] Memory 1101 is used to store program instructions;
[0235] The processor 1102 is used to execute the program instructions stored in the memory so that the electronic device 1100 performs any of the data transmission methods shown above.
[0236] Transceiver 1103 may include a transmitter and / or a receiver. The transmitter may also be referred to as a transmitter, transmitter port, or transmitter interface, and the receiver may also be referred to as a receiver, receiver port, or receiver interface, etc. Exemplarily, memory 1101, processor 1102, and transceiver 1103 are interconnected via bus 1104.
[0237] This application also provides a chip on which a computer program is stored. When the computer program is executed by the chip, it implements the above-mentioned data transmission method. The corresponding content and effects can be referred to the method embodiment section, and will not be repeated here.
[0238] This application also provides a chip module on which a computer program is stored. When the computer program is executed by the chip module, it implements the above-mentioned data transmission method. The corresponding content and effects can be referred to the method embodiment section, and will not be repeated here.
[0239] This application also provides a computer program product that can be executed by a processor, and when the computer program product is executed, the above-described data transmission method can be implemented.
[0240] The data transmission apparatus, electronic device, computer-readable storage medium, and computer program product of the embodiments of this application can execute the technical solutions shown in the above-described data transmission method embodiments. Their implementation principles and beneficial effects are similar, and will not be described again here.
[0241] All or part of the steps in the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a readable memory. When the program is executed, it performs the steps of the above-described method embodiments; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM), flash memory, hard disk, solid-state drive, magnetic tape, floppy disk, optical disc, and any combination thereof.
[0242] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-executable instructions. These computer-executable instructions can be provided to a processing unit of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0243] These computer-executable instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0244] These computer-executable instructions may also be loaded onto a computer or other programmable data processing equipment, causing a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0245] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.
Claims
1. A data transmission method, characterized in that, include: Determine the number of initial period time blocks corresponding to the preset clock signal; Based on the preset clock signal, a target percentage is determined, whereby the target percentage represents the ratio of the number of first time blocks to be delayed in the preset clock signal to the number of initial period time blocks. Determine the number of current period time blocks in the preset clock signal; wherein, the number of current period time blocks is used to represent the number of time blocks corresponding to one period of the clock signal in the current state; The target number of time blocks is determined based on the target percentage and the number of time blocks in the current cycle. The target clock signal is obtained by delaying the preset clock signal according to the target number of time blocks; Simultaneously, the target clock signal and data signal are sent.
2. The method according to claim 1, characterized in that, Determining the target percentage based on the preset clock signal includes: Determine the type of device transmitting the data signal, including master type and slave type; The number of the first time blocks is determined based on the preset clock signal and the device type; The ratio of the number of the first time blocks to the number of the initial periodic time blocks is determined as the target proportion.
3. The method according to claim 2, characterized in that, The device type is a host type. The number of the first time blocks is determined based on the preset clock signal and the device type, including: Determine the sampling time corresponding to the preset clock signal; The transmission time period corresponding to the data signal is determined through link training; Determine the valid time corresponding to the transmission time period; The number of time blocks between the clock time block corresponding to the sampling time and the center time block corresponding to the valid time is determined as the first time block number.
4. The method according to claim 3, characterized in that, The transmission time period corresponding to the data signal is determined through link training, including: Multiple sampling information is acquired through the host device; Determine whether there are multiple samples with similarity less than a threshold among multiple samples; If they exist, determine the sampling times corresponding to the multiple sampling information with similarity less than the threshold, and determine the time period in which the multiple sampling times are located as the transmission time period corresponding to the data signal.
5. The method according to claim 4, characterized in that, Multiple sampling information is obtained through the host device, including: The host device sends the i-th request information to the slave device. The host device determines the i-th sampling time, which is the sampling time corresponding to delaying the preset clock signal by i time blocks. The host device samples the i-th response information sent by the slave device at the i-th sampling time to obtain the i-th sampled information. Where i takes the values 1, ..., n in sequence, and n is the number of the initial periodic time blocks.
6. The method according to claim 2, characterized in that, The device type is a slave type. The number of the first time blocks is determined based on the preset clock signal and the device type, including: Obtain the delay parameter from the transport protocol; The number of the first time blocks is determined based on the delay parameter and the preset clock signal.
7. A data transmission device, characterized in that, The device includes: The first determining module is used to determine the number of initial period time blocks corresponding to the preset clock signal; The second determining module is used to determine a target proportion based on the preset clock signal, wherein the target proportion represents the ratio of the number of first time blocks to be delayed to the number of initial period time blocks of the preset clock signal; The transmission module is used to send data signals according to the target proportion; The transmission module is specifically used to determine the number of current period time blocks in the preset clock signal; wherein, the number of current period time blocks is used to represent the number of time blocks corresponding to one period of the clock signal in the current state; The target number of time blocks is determined based on the target percentage and the number of time blocks in the current cycle. The target clock signal is obtained by delaying the preset clock signal according to the target number of time blocks; Simultaneously, the target clock signal and data signal are sent.
8. An electronic device, characterized in that, include: Memory, processor, and transceiver; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-6.
9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions that, when executed by a processor, are used to implement the method as described in any one of claims 1-6.