A display panel and display device

Abstract

This application provides a display panel and display device. The display panel includes a pixel circuit, which includes a driving transistor, a first light-emitting control module, and a second light-emitting control module. A first output terminal of a first shift register circuit is electrically connected to a first signal line. A second output terminal of a second shift register circuit is electrically connected to a second signal line. Both the first and second light-emitting control modules are electrically connected to the driving transistor, and when both are turned on, they control the driving transistor to output a light-emitting driving current. This application enables the first and second light-emitting control modules to be turned on in a time-division multiplexing manner. Furthermore, by coordinating the on / off states of the first and second light-emitting control modules, the start and end times of the light-emitting driving current generated by the pixel circuit being transmitted to the light-emitting device can be adjusted, which is beneficial for adjusting the light-emitting duration to a non-integer or integer multiple of the clock cycle.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically to a display panel and display device. Background Technology

[0002] The display panel includes pixel circuits, which generate light-emitting driving current and transmit it to electrically connected light-emitting devices. The light-emitting devices emit light upon receiving this current, and the magnitude of the driving current affects their brightness. Some components in the pixel circuits experience current leakage, leading to errors in the current transmitted to the light-emitting devices, thus affecting their brightness. This can be compensated for by adjusting the duration of light emission. However, the adjustment of the light emission duration is typically done in units of the refresh time of a single pixel circuit line, and these adjustments are usually integer multiples of the unit time. For a working cycle with inherently short light emission durations, adjusting in multiples of the unit time cannot achieve the necessary timing precision, easily causing flickering issues in the light-emitting devices. Summary of the Invention

[0003] In view of this, this application provides a display panel and a display device to help solve the above problems.

[0004] In a first aspect, embodiments of this application provide a display panel, including: a pixel circuit, comprising a driving transistor, a first light-emitting control module, and a second light-emitting control module; the control terminal of the first light-emitting control module is electrically connected to a first signal line, and the control terminal of the second light-emitting control module is electrically connected to a second signal line; the first signal line can output a first level signal and a second level signal, and the control terminal of the first light-emitting control module is turned on when it receives the first level signal and turned off when it receives the second level signal; the second signal line can output a third level signal and a fourth level signal, and the control terminal of the second light-emitting control module is turned on when it receives the third level signal and turned off when it receives the fourth level signal;

[0005] The first shift register includes M cascaded first shift register circuits, the first output terminal of the first shift register circuit is electrically connected to the first signal line; the first shift register circuit receives a first start signal, a first clock signal, and a second clock signal;

[0006] The second shift register includes M cascaded second shift register circuits; the second output terminal of the second shift register circuit is electrically connected to the second signal line; the first shift register circuit receives the second start signal, the third clock signal, and the fourth clock signal;

[0007] Both the first light-emitting control module and the second light-emitting control module are electrically connected to the driving transistor, and when both are turned on, they control the driving transistor to output the light-emitting driving current.

[0008] Secondly, embodiments of this application provide a display device, including a display panel as provided in the first aspect.

[0009] In this embodiment, the signals output by the first shift register circuit and the second shift register circuit are configured to control the first light-emitting control module and the second light-emitting control module in the pixel circuit, respectively. This enables the first light-emitting control module and the second light-emitting control module to be turned on in a time-division multiplexing manner. This facilitates the adjustment of the start and end times of the light-emitting driving current generated by the pixel circuit to the light-emitting device by coordinating the on and off states of the first light-emitting control module and the second light-emitting control module. This allows for more flexible adjustment of the light-emitting time of the light-emitting device, enabling the adjustment of the light-emitting duration to a non-integer multiple or an integer multiple of the clock cycle, and providing more accurate compensation for the light-emitting brightness of the light-emitting device 200. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a plan view of a display panel provided in an embodiment of this application;

[0012] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of this application;

[0013] Figure 3 A schematic diagram of a first shift register circuit provided in an embodiment of this application;

[0014] Figure 4 A schematic diagram of a second shift register circuit provided in an embodiment of this application;

[0015] Figure 5 A timing diagram of a display panel provided in an embodiment of this application;

[0016] Figure 6 A timing diagram of another display panel provided in an embodiment of this application;

[0017] Figure 7 A timing diagram of another display panel provided in an embodiment of this application;

[0018] Figure 8A timing diagram of another display panel provided in an embodiment of this application;

[0019] Figure 9 A timing diagram of another display panel provided in an embodiment of this application;

[0020] Figure 10 A timing diagram of another display panel provided in an embodiment of this application;

[0021] Figure 11 A timing diagram of another display panel provided in an embodiment of this application;

[0022] Figure 12 A timing diagram of another display panel provided in an embodiment of this application;

[0023] Figure 13 A timing diagram of another display panel provided in an embodiment of this application;

[0024] Figure 14 A timing diagram of another display panel provided in an embodiment of this application;

[0025] Figure 15 A timing diagram of another display panel provided in an embodiment of this application;

[0026] Figure 16 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0027] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0028] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0029] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0030] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0031] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "roughly", "generally" and "generally" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0032] It should be understood that although terms such as "first," "second," etc., may be used to describe the light-emitting control module, level signal, start signal, clock signal, etc., in the embodiments of this application, these should not be limited to these terms. These terms are only used to distinguish the light-emitting control module, level signal, start signal, clock signal, etc., from each other. For example, without departing from the scope of the embodiments of this application, the first light-emitting control module may also be referred to as the second light-emitting control module, and similarly, the second light-emitting control module may also be referred to as the first light-emitting control module. Through meticulous and in-depth research, the applicant of this application has provided a solution to the problems existing in the prior art.

[0033] Figure 1 This is a plan view of a display panel provided in an embodiment of this application. Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of this application. Figure 3 This is a schematic diagram of a first shift register circuit provided in an embodiment of this application. Figure 4 This is a schematic diagram of a second shift register circuit provided in an embodiment of this application. Figure 5 This is a timing diagram of a display panel provided in an embodiment of this application.

[0034] This application provides a display panel A10, such as Figure 1 As shown, the display panel A10 includes pixel circuitry 100. Combined with... Figure 2 As shown, the pixel circuit 100 includes a driving transistor Md, and the pixel circuit 100 is electrically connected to the light-emitting device 200. The driving transistor Md in the pixel circuit 100 generates a light-emitting driving current to drive the light-emitting device 200 to emit light.

[0035] In pixel circuit 100, the driving transistor Md is prone to leakage current during one operating cycle, resulting in inaccurate light-emitting driving current output to light-emitting device 200. Optionally, one operating cycle of pixel circuit 100 includes one refresh frame and multiple sustain frames. Each refresh frame and sustain frame includes a light-emitting phase during which light-emitting device 200 emits light. During the refresh frame, the gate of driving transistor Md receives a data voltage Vdata input from data writing module 10. The magnitude of data voltage Vdata controls the magnitude of the light-emitting driving current generated by driving transistor Md, thereby controlling the brightness of light-emitting device 200. However, during the sustain frame, the gate of driving transistor Md maintains its potential and no longer receives the data voltage Vdata input from data writing module 10. The light-emitting driving current generated by driving transistor Md is also at a similar level to that generated during the refresh frame. However, since the source and drain of driving transistor Md are always at a potential difference, the gate potential of driving transistor Md is unstable. This usually causes the light-emitting driving current generated by driving transistor Md to gradually decrease between adjacent frames, resulting in a decrease in the brightness of light-emitting device 200.

[0036] The brightness of the light-emitting device 200 can be compensated by adjusting its illumination duration. In related technologies, after the pixel circuit receives the valid light-emitting signal output by the shift register circuit, the pixel circuit enters the light-emitting stage. During the light-emitting stage, the driving transistor generates current, and the light-emitting device emits light. It can be understood that the effective pulse duration of the light-emitting signal output by the shift register circuit is equal to the light-emitting time of the light-emitting device. Therefore, when it is necessary to adjust the light-emitting duration of the light-emitting device, it is done by adjusting the pulse duration of the effective light-emitting signal output by the shift register circuit. However, since the shift register operates in a cascaded manner, multiple pixel circuits in the display panel are turned on row by row under the control of the shift register circuit. The shift register circuit in cascaded operation receives a clock signal and operates according to the clock signal period, ensuring the orderly operation of multiple rows of pixel circuits. In the shift register, when each clock cycle arrives, the data in the shift register circuit is shifted one bit to the next shift register circuit. In this way, each rising or falling edge of the clock signal becomes the precise time point of data shifting, and the pulse duration received and generated by the shift register circuit is in units of clock cycles. Therefore, the duration of the effective light-emitting signal output by the shift register circuit can only be adjusted in units of clock cycles, which in turn limits the adjustment of the light-emitting duration of the light-emitting device within the maintenance frame to clock cycles. However, since the duration of the effective light-emitting signal is adjusted in multiples of clock cycles in related technologies, the adjustment is prone to skipping steps, resulting in situations where each adjustment of the effective light-emitting signal requires at least a 2x clock cycle adjustment of the light-emitting time. When the light-emitting duration of the pixel circuit itself during the maintenance frame is short, such integer multiple adjustments have a significant impact on its brightness, easily leading to poor brightness compensation and even visual flickering. Therefore, it is crucial to find a way to flexibly and precisely adjust the light-emitting duration according to actual usage needs, avoiding the limitation of adjustment only being integer multiples of clock cycles, and allowing the adjustment of the light-emitting time to be a non-integer multiple of clock cycles, to improve the light-emitting compensation effect.

[0037] To flexibly adjust the emission duration of the light-emitting device 200, continue to refer to... Figure 2 As shown, this application proposes to provide a first light-emitting control module 20 and a second light-emitting control module 30 in the pixel circuit 100. The control terminal 20A of the first light-emitting control module 20 is electrically connected to the first signal line SL1, and the control terminal 301 of the second light-emitting control module 30 is electrically connected to the second signal line SL2.

[0038] The first signal line SL1 can output a first level signal V1 and a second level signal V2. The control terminal 20A of the first light-emitting control module 20 turns on when it receives the first level signal V1 and turns off when it receives the second level signal V2. In the pixel circuit 100, the first terminal of the first light-emitting control module 20 is electrically connected to the first power supply voltage PVDD, and the second terminal is electrically connected to the driving transistor Md. When the control terminal 201 of the first light-emitting control module 20 receives the first level signal V1, the first light-emitting control module 20 turns on and transmits the first power supply voltage PVDD to the first terminal of the driving transistor Md. The driving transistor Md generates a light-emitting driving current under the drive of the first power supply voltage PVDD, and the generated light-emitting driving current is output from the second terminal of the driving transistor Md.

[0039] The second signal line SL2 can output a third-level signal V3 and a fourth-level signal V4. The control terminal 301 of the second light-emitting control module 30 turns on when it receives the third-level signal V3 and turns off when it receives the fourth-level signal V4. The first terminal of the second light-emitting control module 30 is electrically connected to the second electrode of the driving transistor Md, and the second terminal is electrically connected to the first electrode of the light-emitting device 200. When the control terminal 30A of the second light-emitting control module 30 receives the third-level signal V3, the second light-emitting control module 30 turns on and transmits the received light-emitting driving current to the first electrode of the light-emitting device 200, causing the light-emitting device 200 to emit light.

[0040] In summary, the ability of the light-emitting device 200 to receive the light-emitting driving current requires the joint operation of the first light-emitting control module 20 and the second light-emitting control module 30. The first light-emitting control module 20 receives the first level signal V1 and turns on during the time that the driving transistor Md generates the light-emitting driving current. The light-emitting driving current generated by the driving transistor Md needs to be output from the second light-emitting control module 30 to the light-emitting device 200. Therefore, the light-emitting device 200 emits light when the second light-emitting control module 30 is turned on and can receive the light-emitting driving current. Thus, both the first light-emitting control module 20 and the second light-emitting control module 30 are electrically connected to the driving transistor Md, and when both are turned on, the driving transistor Md is controlled to output the light-emitting driving current to the light-emitting device 200. The time during which both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on is the time during which the light-emitting device 200 emits light.

[0041] As described above, when both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on, the first signal line SL1 transmits the first level signal V1 and the second signal line SL2 transmits the third level signal V3. The pulse duration of both the first level signal V1 and the third level signal V3 is measured in clock cycles. Therefore, if the light-emitting duration of the light-emitting device 200 is controlled solely by the first level signal V1 or the third level signal V3, the light-emitting time of the light-emitting device 200 is also measured in clock cycles H. However, this application uses the overlap time of the first level signal V1 and the third level signal V3. By utilizing the time delay between the first level signal V1 and the third level signal V3, the overlap time between the first level signal V1 and the second level signal V3 can be made a non-integer multiple of the clock cycle. This allows for a more precise compensation effect on the brightness of the light-emitting device 200 by adjusting its light-emitting duration to a non-integer multiple of the clock cycle.

[0042] In related technologies, pixel circuits typically have the control terminals of the first and second light-emitting control modules electrically connected to the same signal line. Correspondingly, the same signal line is electrically connected to the output terminal of a shift register circuit. When the shift register circuit outputs a valid pulse signal, the first and second light-emitting control modules are turned on simultaneously, and the light-emitting device emits light.

[0043] Combination Figures 3-5 As shown, in this technical solution, in order to enable the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on at the same time, the display panel A10 is further configured to include a first shift register 300 and a second shift register 400.

[0044] The first shift register 300 includes M cascaded first shift register circuits 301. Optionally, the M cascaded first shift register circuits 301 are electrically connected to M rows of pixel circuits 100. The first output terminal 301A of the first shift register circuit 301 is electrically connected to the first signal line SL1, enabling the first shift register circuit 301 to control the opening or closing of the first light-emitting control module 20. The first shift register circuit 301 receives a first start signal STV1, a first clock signal CK1, and a second clock signal CK2. After receiving the first start signal STV1, the first shift register circuit 301 starts working. The clock signals received by the first shift register circuit 301 include the first clock signal CK1 and the second clock signal CK2. Under the combined control of the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, the timing and pulse duration of the first level signal V1 and the second level signal V2 output by the first shift register circuit 301 are adjusted.

[0045] The second shift register 400 includes M-stage cascaded second shift register circuits 401. Optionally, each of the M-stage cascaded second shift register circuits 401 is electrically connected to an M-row pixel circuit 100. The second output terminal 401A of the second shift register circuit 401 is electrically connected to the second signal line SL2, enabling the second shift register circuit 401 to control the on / off state of the second light-emitting control module 20. Figure 2 As shown, the second shift register circuit 401 receives the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4. After receiving the second start signal STV2, the second shift register circuit 401 starts operating. Under the combined control of the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4, the timing and pulse duration of the third level signal V3 and the fourth level signal V4 output by the second shift register circuit 401 are adjusted.

[0046] like Figure 5 As shown, the overlap time between the first level signal V1 and the second level signal V3 is the time when both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on. At this time, the pixel circuit 100 is in the light-emitting stage E1, and the light-emitting device 200 can receive the light-emitting driving current and thus emit light. It should be noted that in Figure 5 The shaded portion in the last row represents the duration of the pixel circuit 100 in the light-emitting phase E1 and the non-light-emitting phase E2 during one working cycle.

[0047] In this embodiment, the signals output by the first shift register circuit 301 and the second shift register circuit 401 are configured to control the first light-emitting control module 20 and the second light-emitting control module 30 in the pixel circuit 100, respectively. This enables the first light-emitting control module 20 and the second light-emitting control module to be turned on in a time-division multiplexing manner. This facilitates the adjustment of the start and end times of the light-emitting driving current generated by the pixel circuit 100 to the light-emitting device 200 by the switching of the first light-emitting control module 20 and the second light-emitting control module 30. This allows for more flexible adjustment of the light-emitting time of the light-emitting device 200, enabling the adjustment of the light-emitting duration to a non-integer multiple or an integer multiple of the clock cycle, and providing more accurate compensation for the light-emitting brightness of the light-emitting device 200.

[0048] In one embodiment of this application, reference continues to be made to... Figures 3-5As shown, the first start signal STV1 and the second start signal STV2 proposed in this application are supplied by different signal lines. The first start signal STV1 and the second start signal STV2 are the signals that enable the cascading of the first shift register 300 and the second shift register 400, respectively. When the first start signal STV1 arrives at the first shift register 300, the multiple first shift register circuits 301 in the first shift register 300 sequentially receive the first start signal STV1 and start working. The operation of the first shift register circuit 301 is to generate a first level signal V1 or a second level signal V2 to control the on / off state of the first light-emitting control module 20. When the second start signal STV2 arrives at the second shift register 400, the multiple second shift register circuits 401 in the second shift register 400 sequentially receive the second start signal STV2 and start working. The operation of the second shift register circuit 401 is to generate a third level signal V3 or a fourth level signal V4 to control the on / off state of the second light-emitting control module 30.

[0049] In this embodiment, the first start signal STV1 and the second start signal STV2 are supplied by different signal lines. This is beneficial because the initial operating states of the first shift register circuit 301 and the second shift register circuit 401 are controlled by different signal lines. This helps to avoid confusion in the cascaded state of the first shift register 300 and the second shift register 400 when transmitting the first start signal STV1 or the second start signal STV2. It also helps to prevent the first shift register circuit 301 and the second shift register circuit 401 from starting or ending the output of the first level signal V1 and the third level signal V3 at the same time, thus losing the function of controlling the first light-emitting control module 20 and the second light-emitting control module 30 to turn on in a time-division multiplexing manner. Therefore, using two signal lines to control the operating states of the first shift register circuit 301 and the second shift register circuit 401 respectively is beneficial to flexibly control the first shift register circuit 301 and the second shift register circuit 401, thereby providing conditions for flexibly adjusting the effective light-emitting time of the light-emitting device 200.

[0050] It should be added that the pixel circuit 100 proposed in this application embodiment also includes a first reset module 40, a threshold compensation module 50, and a second reset module 60. The first reset module 40 is used to transmit a first reset voltage Vref1 to the gate of the driving transistor Md to reset the gate of the driving transistor Md, thereby ensuring that the driving transistor Md generates an accurate light-emitting driving current in the next working cycle. The threshold compensation module 50 is used to compensate the threshold voltage of the driving transistor Md to the gate of the driving transistor Md. The second reset module 60 is used to transmit a second reset voltage Vref2 to the first electrode of the light-emitting device 200 to reset the light-emitting device 200, thereby ensuring the accuracy of the light-emitting brightness of the light-emitting device 200 in the next working cycle. The pixel circuit 100 also receives a first scan signal S1 and a second scan signal S2, and the signals transmitted by the first scan signal S1 and the second scan signal S2 are used to control the corresponding modules to turn on or off.

[0051] In one embodiment of this application, the following is continued: Figures 3-5 As shown, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are supplied by different signal lines. As can be seen from the above embodiment, the operating state of the first shift register circuit 301 is jointly controlled by the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, while the operating state of the second shift register circuit 401 is jointly controlled by the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4. Therefore, supplying the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 by different signal lines facilitates the separate control of the operating states of the first shift register circuit 301 and the second shift register circuit 401, thereby enabling more accurate and convenient control of the output timing of the first level signal V1 and the third level signal V3, thus preparing for more precise adjustment of the light emission duration.

[0052] It should be noted that, optionally, the circuit structure of the first shift register circuit 301 is the same as that of the second shift register circuit 401. Both the first shift register circuit 301 and the second shift register circuit 401 proposed in this application embodiment include multiple transistors. Optionally, the description will be based on the example where all transistors are P-type transistors. When the transistor is a P-type transistor, it is turned on when its gate receives a low-level signal and turned off when it receives a high-level signal. Therefore, in this application embodiment, corresponding to the shift register circuit including P-type transistors, the arrival time of the falling edge of the first clock signal CK1 and the second clock signal CK2 is the effective time point for the switching of the operating state of the first shift register circuit 301. The arrival time of the falling edge of the third clock signal CK3 and the fourth clock signal CK4 is the effective time point for the switching of the operating state of the second shift register circuit 401. Since the first clock signal CK1 and the second clock signal CK2 simultaneously control the operating state of the first shift register circuit 301, the clock period H proposed in this application embodiment is the time between the falling edge of the first clock signal CK1 and the falling edge of the second clock signal CK2. Furthermore, since the third clock signal CK3 and the fourth clock signal CK4 simultaneously control the operating state of the second shift register circuit 401, the clock period H proposed in this embodiment is also the time between the falling edge of the third clock signal CK2 and the falling edge of the fourth clock signal CK4. Optionally, the clock period H of the first shift register circuit 301 is equal to the clock period H of the second shift register circuit 401, which is beneficial for unified control of the operation of the first shift register circuit 301 and the second shift register circuit 401 and avoids signal disorder.

[0053] Optionally, the effective level signal of the first start signal STV1 is a low-level signal. For example... Figure 5 As shown, when the first start signal STV1 transmits a valid level signal, the falling edge of the first start signal STV1 coincides with the falling edge of the second clock signal CK2. The corresponding first level signal V1 is not output immediately, but rather waits for the next falling edge of the clock signal after the falling edge of the first start signal STV1 becomes a valid pulse signal. Here, the falling edge of the first clock signal CK1 arrives first after the falling edge of the first start signal STV1, at which point the first level signal V1 also begins to be output. Clearly, the time between the falling edge of the second clock signal CK2 and the falling edge of the first clock signal CK1 is one clock period H. This output delay helps ensure that the first start signal STV1 moves stably bit by bit in the register, rather than reacting instantly. This ensures the stability and reliability of data transmission, thereby guaranteeing the stable operation of the shift register circuit and the accuracy of signal transmission.

[0054] Similarly, when the effective pulse signal of the first start signal STV1 ends, that is, when the rising edge of the first start signal STV1 arrives, the first level signal V1 does not immediately stop outputting. Instead, after the rising edge of the first start signal STV1 arrives and it turns into an ineffective pulse signal, it waits for the falling edge of the next clock signal to arrive before outputting.

[0055] Optionally, the effective level signal of the second start signal STV2 is also a low level signal. (Continue to refer to...) Figure 5 As shown, setting the effective level signals of the first start signal STV1 and the second start signal STV2 to both low level signals facilitates easier control of the first shift register circuit 301 and the second shift register circuit 401, reducing the difficulty of circuit fabrication and control. Figure 3 As shown, when the second start signal STV2 transmits a valid level signal, the falling edge of the second start signal STV2 coincides with the falling edge of the third clock signal CK3. The corresponding third level signal V3 is not immediately output; instead, it becomes a valid pulse signal after the falling edge of the second start signal STV2 arrives, and then waits for the falling edge of the next clock signal to arrive before being output. Here, the falling edge of the fourth clock signal CK4 arrives first after the falling edge of the second start signal STV2, at which point the third level signal V3 also begins to be output. Similarly, when the valid pulse signal of the second start signal STV2 ends, that is, when the rising edge of the second start signal STV2 arrives, the third level signal V3 does not immediately stop outputting; instead, it becomes an invalid pulse signal after the rising edge of the second start signal STV2 arrives, and then waits for the falling edge of the next clock signal to arrive before being output.

[0056] Furthermore, the following describes the working process of the shift register circuit proposed in the embodiments of this application. Optionally, the description is based on the example of a first level signal V1 being a low level signal, a third level signal V3 being a low level signal, a second level signal V2 being a high level signal, and a fourth level signal V4 being a high level signal.

[0057] Continue to refer to Figure 3 As shown, the first shift register circuit 301 further includes a first output unit 310. The first output unit 310 has a first terminal receiving a first level signal V1 and a second terminal electrically connected to the first output terminal 301A, and is used to output the first level signal V1. Optionally, the first output unit 310 includes a first transistor M1. The first electrode of the first transistor M1 receives the first level signal V1 and the second electrode is electrically connected to the first output terminal 301A.

[0058] The first shift register circuit 301 further includes a second output unit 320. The first terminal of the second output unit 320 receives a second level signal V2, and the second terminal is electrically connected to the first output terminal 301A, and is used to output the second level signal V2. Optionally, the second output unit 320 includes a second transistor M2. The first terminal of the second transistor M2 receives the second level signal V2, and the second terminal is electrically connected to the first output terminal 301A.

[0059] The first shift register circuit 310 further includes a first control unit 330. The first control unit 330 receives a first start signal STV1, a first clock signal CK1, and a second clock signal CK2, and is used to control the first output unit 310 or the second output unit 320 to turn on. Optionally, the first control unit 330 includes a third transistor M3 to an eleventh transistor M11, and the electrical connection of the third transistor M3 to the eleventh transistor M11 is as follows: Figure 3 As shown.

[0060] like Figure 5 As shown, one working cycle of the first shift register circuit 301 includes a first stage T1, a second stage T2, a third stage T3, and a fourth stage T4.

[0061] In the first stage T1: the first start signal STV1 received by the first control unit 330 is a valid pulse signal, the first clock signal CK1 is a high-level signal, and the second clock signal CK2 is a low-level signal. Then, the fourth transistor M4 and the tenth transistor M10 are turned on, the second node N2 is pulled low, and the third node N3 is raised. Consequently, the second transistor M2 is turned on, and the first transistor M1 is turned off. At this time, the first control unit 330 controls the first output unit 310 to turn off and controls the second output unit 320 to turn on. The second output unit 320 transmits the second-level signal V2 to the first output terminal 301A, causing the first light-emitting control module 20 in the pixel circuit 100 to turn off.

[0062] In the second stage T2: the first start signal STV1 received by the first control unit 330 is a valid pulse signal, the first clock signal CK1 is a low-level signal, and the second clock signal CK2 is a high-level signal. The first start signal STV1 writes the third node N3 low, turning on the third transistor M3 and turning off the fourth transistor M4. The second node N2 is written high by the second level signal V2, turning off the second transistor M2 and turning on the first transistor M1. At this time, the first control unit 330 controls the first output unit 310 to turn on and the second output unit 320 to turn off. The first output unit 310 transmits the first level signal V1 to the first output terminal 301A, causing the first light-emitting control module 20 in the pixel circuit 100 to turn on. Additionally, the second stage T2 also includes the case where the first start signal STV1 received by the first control unit 330 is a valid signal, the first clock signal CK1 is a high-level signal, and the second clock signal CK2 is a low-level signal. In this case, due to the effect of the first capacitor C1, the third node N3 remains at a low level. At this time, the third transistor M3 remains on, and the second level signal V2 continuously writes the second node N2 high, causing the second transistor M2 to turn off and the first transistor M1 to turn on. Meanwhile, the first control unit 330 continuously controls the first output unit 310 to turn on and the second output unit 320 to remain off. The first output unit 310 transmits the first level signal V1 to the first output terminal 301A, causing the first light-emitting control module 20 in the pixel circuit 100 to remain on.

[0063] In the third stage T3: The first start signal STV1 received by the first control unit 330 becomes an invalid signal, the first clock signal CK1 is a low-level signal, and the second clock signal CK2 is a high-level signal. Then, the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are turned on, the first node N1 is set to a low-level state, and the invalid signal transmitted by the first start signal STV1 sets the third node N3 to a high-level state, thus turning off the first transistor M1; the second clock signal CK2 transmits a high-level signal, so the fourth transistor M4 and the tenth transistor M10 are turned off, the second node N2 remains at a high level, and the second transistor M2 is also turned off. Therefore, the potential of the control terminal of the first light-emitting control module 20 is not updated, and the level of the first output terminal 301A remains at the first level signal V1 state, and the first light-emitting control module 20 remains on.

[0064] In the fourth stage T4: the first start signal STV1 received by the first control unit 330 continuously outputs an invalid signal, the first clock signal CK1 turns high, and the second clock signal CK2 turns low. Then, the fourth transistor M4 and the tenth transistor M10 are turned on, the second node N2 is pulled low, and the third node N3 is raised. Consequently, the first transistor M1 is turned off, and the second transistor M2 is turned on. At this time, the first control unit 330 controls the first output unit 310 to turn off and the second output unit 320 to turn on. The second output unit 320 transmits the second level signal V2 to the first output terminal 301A, causing the first light-emitting control module 20 in the pixel circuit 100 to turn off. Additionally, the fourth stage T4 also includes the case where the first start signal STV1 received by the first control unit 330 is an invalid signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. At this time, the first start signal STV1 writes the third node N3 high, and the conducting sixth transistor M6 transmits the first level signal V1 to write the first node N1 low; the fourth transistor M4 is turned off, and the second node N2 maintains the low level state of the previous stage, so the second transistor M2 continues to conduct, and the first transistor M1 continues to be turned off. At this time, the first control unit 330 continuously controls the first light-emitting control module 20 to turn off.

[0065] like Figure 4 As shown, the second shift register circuit 401 further includes a third output unit 410. The first terminal of the third output unit 410 receives the third level signal V3, and the second terminal is electrically connected to the second output terminal 401A, and is used to output the third level signal V3. Optionally, the third output unit 410 includes a transistor X1, the first terminal of which receives the third level signal V3, and the second terminal is electrically connected to the second output terminal 401A.

[0066] The second shift register circuit 401 further includes a fourth output unit 420. The first terminal of the fourth output unit 420 receives a fourth-level signal V4, and the second terminal is electrically connected to the second output terminal 401A, and is used to output the fourth-level signal V4. Optionally, the fourth output unit 420 includes a second transistor X2. The first terminal of the second transistor X2 receives the fourth-level signal V4, and the second terminal is electrically connected to the second output terminal 401A.

[0067] The second shift register circuit 401 also includes a second control unit 430. The second control unit 430 receives a second start signal STV2, a third clock signal CK3, and a fourth clock signal CK4, and uses these signals to control the third output unit 410 or the fourth output unit 420 to turn on. Optionally, the second control unit 430 includes transistors X3 to X11, and the electrical connection of transistors X3 to X11 is as follows: Figure 5 As shown.

[0068] Combination Figure 5 As shown, one operating cycle of the second shift register circuit 401 includes a fifth stage T5, a sixth stage T6, a seventh stage T7, and an eighth stage T8. Optionally, the circuit structures of the first shift register circuit 301 and the second shift register circuit 401 are the same. Optionally, the transistors included in the first shift register circuit 301 and the second shift register circuit 401 are of the same type.

[0069] In the fifth stage T5: the second start signal STV2 received by the second control unit 430 is a valid pulse signal, the third clock signal CK3 is a high-level signal, and the fourth clock signal CK4 is a low-level signal. Therefore, transistors X4 (number 4) and X10 (number 10) are turned on, node N5 is pulled low, node N6 is raised, transistor X2 (number 2) is turned on, and transistor X1 (number 1) is turned off. At this time, the second control unit 430 controls the third output unit 410 to turn off and the fourth output unit 420 to turn on. The third output unit 420 transmits the fourth-level signal V4 to the second output terminal 401A, causing the second light-emitting control module 30 in the pixel circuit 100 to turn off.

[0070] In stage T6: The second start signal STV2 received by the second control unit 430 is a valid pulse signal, the third clock signal CK3 is a low-level signal, and the fourth clock signal CK4 is a high-level signal. Therefore, the second start signal STV2 writes the sixth node N6 low, turning on transistor X3 and turning off transistor X4. The fifth node N5 is written high by the fourth level signal V4, turning off transistor X2 and turning on transistor X1. At this time, the second control unit 430 controls the third output unit 410 to turn on and the fourth output unit 420 to turn off. The third output unit 410 transmits the third level signal V3 to the second output terminal 401A, causing the second light-emitting control module 30 in the pixel circuit 100 to turn on. Additionally, stage T6 also includes the case where the second start signal STV2 received by the second control unit 430 is a valid pulse signal, the third clock signal CK3 is a high-level signal, and the fourth clock signal CK4 is a low-level signal. In this case, due to the effect of capacitor C1, the sixth node N6 remains at a low level. At this time, transistor X3 remains on, and the fourth level signal V4 continuously writes the fifth node N5 high, causing transistor X2 to turn off and transistor X1 to turn on. Meanwhile, the second control unit 430 continuously controls the third output unit 410 to turn on and the fourth output unit 420 to remain off. The third output unit 410 transmits the third level signal V3 to the second output terminal 401A, causing the second light-emitting control module 30 in the pixel circuit 100 to remain on.

[0071] In stage T7: The second start signal STV2 received by the second control unit 430 becomes invalid, the third clock signal CK3 is low, and the fourth clock signal CK4 is high. Then transistors X6 (6), X11 (11), and X12 (12) are turned on, and node N4 is set to low. The invalid signal transmitted by the second start signal STV2 sets node N6 to high, so transistor X1 (1) is turned off. The fourth clock signal CK4 transmits a high signal, so transistors X4 (4) and X10 (10) are turned off, node N5 remains high, and transistor X2 (2) is also turned off. Therefore, the potential of the control terminal of the second light-emitting control module 30 is not updated, and the level of the second output terminal 401A remains at the third level signal V3, and the second light-emitting control module 30 remains on.

[0072] In stage T8: The second start signal STV2 received by the second control unit 430 continuously outputs an invalid signal, the third clock signal CK3 turns high, and the fourth clock signal CK4 turns low. Then, transistors X4 (4) and X10 (10) are turned on, node N5 is pulled low, node N6 is raised, transistor X1 (1) is turned off, and transistor X2 (2) is turned on. At this time, the second control unit 430 controls the third output unit 410 to turn off and the fourth output unit 420 to turn on. The fourth output unit 420 transmits the fourth level signal V4 to the second output terminal 401A, causing the second light-emitting control module 30 in the pixel circuit 100 to turn off. Additionally, stage T8 also includes the case where the second start signal STV2 received by the second control unit 430 is an invalid signal, while the third clock signal CK3 is low and the fourth clock signal CK4 is high. At this time, the second start signal STV2 writes the sixth node N6 high, and the conducting transistor X6 transmits the third level signal V3 to write the fourth node N4 low; transistor X4 turns off, and the fifth node N5 maintains the low level state of the previous stage, so transistor X2 continues to conduct and transistor X1 continues to turn off. At this time, the second control unit 430 continuously controls the second light-emitting control module 30 to turn off.

[0073] In one embodiment of this application, the following is continued: Figures 3-5As shown, the periods of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all N1*H, where N1 is an integer greater than or equal to 1. Based on the above, since the periods of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are the same, the clock period H of the first shift register circuit 301 and the second shift register circuit 401 is also the same. Therefore, the clock period H can be used to describe the time of the first shift register circuit 301 in one operating state or to describe the time of the second shift register circuit 401 in one operating state. In this embodiment, N1 = 2 is used as an example for explanation.

[0074] Figure 6 This is a timing diagram of another display panel provided in an embodiment of this application.

[0075] like Figure 6 As shown, the pixel circuit 100 includes at least a first operating cycle Time1. Optionally, one operating cycle Time1 of the pixel circuit 100 includes at least one refresh frame Time1A and at least one sustain frame Time1B. Both refresh frame Time1A and sustain frame Time1B include at least one light-emitting stage E1. During light-emitting stage E1, both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on. During the non-light-emitting stage E2 in refresh frame Time1A and sustain frame Time1B, at most one of the first light-emitting control module 20 and the second light-emitting control module 30 is turned on. Therefore, the time during which the pixel circuit 100 is in light-emitting stage E1 is determined by the simultaneous onset time of the first light-emitting control module 20 and the second light-emitting control module 30, which is determined by the signals output from the output terminals of the first shift register circuit 301 and the second shift register circuit 401. At this time, the time when the first level signal V1 and the third level signal V3 are output simultaneously is the time when the pixel circuit 100 enters the light-emitting stage E1. When the first level signal V1 and the third level signal V3 are not output simultaneously, it is the non-light-emitting stage E2 of the pixel circuit 100. When the second level signal V2 and the fourth level signal V4 are output, the pixel circuit 100 is also in the non-light-emitting stage.

[0076] Figure 6The text indicates that the pixel circuit 100 has the same light emission duration in both the refresh frame Time 1A and the sustain frame Time 1B. Since the pixel circuit 100 experiences leakage in the sustain frame Time 1B, a decrease in brightness occurs when the light emission duration of the sustain frame Time 1B is still equal to that of the refresh frame Time 1A. Therefore, the light emission duration of the sustain frame Time 1B can be adjusted, for example, by extending the light emission duration of the sustain frame Time 1B to compensate for the reduced brightness. Because adjusting the light emission duration of the sustain frame Time 1B is common in practical applications, this application will use adjusting the light emission duration in the sustain frame Time 1B as an example for explanation. The following embodiments will... Figure 6 The timing shown is used to adjust the light emission duration in the maintenance frame Time1B. Of course, in some other embodiments, the light emission adjustment provided in this application embodiment can also be used to set or adjust the light emission stage E1 duration in the refresh frame Time1A by a non-integer multiple of the clock period H.

[0077] In the first operating cycle Time 1 of the pixel circuit 100 in this embodiment, when the pixel circuit 100 is in the refresh frame Time 1A, the rising edge and falling edge of the first start signal STV1 are set to be N2*H earlier than the rising edge and falling edge of the second start signal STV2, where N2 is an integer greater than or equal to 1. Based on the above-mentioned operation of the shift register circuit, it can be seen that the rising edge and falling edge of the first level signal V1 output by the corresponding first shift register circuit 301 are also N2*H earlier than the rising edge and falling edge of the third level signal V3 output by the second shift register circuit 401.

[0078] The effective pulse duration for activating both the first light-emitting control module 20 and the second light-emitting control module 30 is N3*H, where N3 is an integer greater than or equal to 1. The effective pulse duration for activating both the first light-emitting control module 20 and the second light-emitting control module 30 is also the duration for which the first level signal V1 and the third level signal V3 are simultaneously output.

[0079] Using the working timing of the first shift register circuit 301 and the second shift register circuit 401 in the refresh frame Time1A as the initial working timing, when the pixel circuit 100 enters the maintenance frame Time1B, adjustments are made under the above working timing to adjust the duration of simultaneous output of the first level signal V1 and the third level signal V3.

[0080] In this embodiment, the initial operating timing of the first shift register circuit 301 and the second shift register circuit 401 is configured such that the rising and falling edges of the first start signal STV1 are both N2*H earlier than the rising and falling edges of the second start signal STV2. This facilitates the realization that the rising and falling edges of the first level signal V1 are both N2*H earlier than the rising and falling edges of the second level signal V2, thereby enabling the first light-emitting control module 20 to start up N2*H earlier than the second light-emitting control module 30. This prepares for the extended light-emitting duration in the maintenance frame Time1B to be a non-integer multiple of the clock period H.

[0081] For example, in this embodiment, the effective pulse duration of the first start signal STV1 is 4*H and the ineffective pulse duration is 4*H. The effective pulse duration of the second start signal STV2 is also 4*H and the ineffective pulse duration is 4*H. Then, the pulse duration of the first level signal V1 and the pulse duration of the third level signal V3 are also 4*H, and the pulse duration of the second level signal V2 and the fourth level signal V4 are also 4*H. Taking N1=1 and N2=1 as an example, it can be explained. Based on the above, it can be seen that in the first working cycle Time1, the time difference between the first level signal V1 and the third level signal V3 is 1*H, and the duration of the simultaneous output of the first level signal V1 and the third level signal V3 is 3*H. Therefore, the duration of the light emission stage E1 of the pixel circuit 100 in the refresh frame Time1A is also 3*H, and N3=3 at this time. Since the first level signal V1 and the third level signal V3 both have an effective pulse duration of 1*H that do not overlap, if it is necessary to extend the light emission duration to 3.5*H while maintaining frame Time1B, the relevant control signals of the first shift register circuit 301 or the second shift register circuit 302 can be shifted directly based on the first start signal STV1 and the second start signal STV2 set at this time, so that the time for the first level signal V1 and the third level signal V3 to be output simultaneously is extended by a non-integer multiple of the clock period H.

[0082] In one embodiment of this application, reference continues to be made to... Figure 6 As shown, the falling and rising edges of the first clock signal CK1 are both advanced by N2*H compared to the rising and falling edges of the third clock signal CK3. The falling and rising edges of the second clock signal CK2 are both advanced by N2*H compared to the rising and falling edges of the fourth clock signal CK4.

[0083] Since the pulse duration of the first start signal STV1 and the second start signal STV2 can only be extended or shortened in integer multiples of the clock period H, it is difficult to achieve a non-integer multiple of the clock period H by simply adjusting the first start signal STV1 and the second start signal STV2. Furthermore, the signals of the first start signal STV1 and the second start signal STV2 affect the register circuit in conjunction with the clock signal; therefore, adjusting the first start signal STV1 and the second start signal STV2 alone may not accurately achieve a non-integer adjustment of the light emission duration.

[0084] In this embodiment, the falling edge and rising edge of the first clock signal are both advanced by N2*H compared to the rising edge and falling edge of the third clock signal. The falling edge and rising edge of the second clock signal are both advanced by N2*H compared to the rising edge and falling edge of the fourth clock signal. This facilitates the unification of the timing signals controlling the first shift register circuit 301 and the second shift register circuit 401, allowing them to work together to extend the light emission duration by a non-integer multiple of the clock period H.

[0085] In one embodiment of this application, during the first working cycle Time1, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted by X1*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. This allows the first level signal V1 to also shift for the same duration as the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, which helps maintain the pulse duration of the first level signal V1 unchanged, shifting only its output time. Furthermore, since the output time of the third level signal V3 remains unchanged, the simultaneous output time of the first level signal V1 and the third level signal V3 also changes.

[0086] Furthermore, since the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 move simultaneously, the restriction that the clock period H can only be an integer multiple of the clock period H when the first start signal STV1 moves is avoided. This allows the duration of the simultaneous movement of the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 to be a non-integer multiple of the clock period H. Consequently, the output time of the first level signal V1 is shifted by a non-integer multiple of the clock period H compared to the start time of output in the refresh frame Time1A. This facilitates extending or shortening the duration of the simultaneous output of the first level signal V1 and the third level signal V3 by a non-integer multiple of the clock period H.

[0087] Alternatively, similarly, in the first working cycle Time1, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted by X1*H, while the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 remain fixed. In this case, the third level signal V3 can also be shifted for the same duration as the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4. This helps maintain the pulse duration of the third level signal V3 unchanged, shifting only its output time. This allows the output time of the third level signal V3 to be shifted by a non-integer multiple of the clock period H compared to the time it begins to output in the refresh frame Time1A. This achieves the simultaneous output of the first level signal V1 and the third level signal V3, extending or shortening the duration by a non-integer multiple of the clock period H.

[0088] Both methods described above can achieve an effective pulse duration of (N3±X1)*H for both the first light-emitting control module 20 and the second light-emitting control module 30; 0<X1≤N2. At this time, the first level signal V1 or the third level signal V3 also shifts by X1*H, resulting in a change in the duration of simultaneous output of the first level signal V1 and the second level signal V2 from N3*H to (N3±X1)*H. For example, if N2=1, then the shifted duration of the first level signal V1 or the second level signal V2 is within the range of 0<X1≤1, including clock cycles for which the shifted duration of the first level signal V1 or the third level signal V3 is a non-integer multiple. For example, when X1 = 0.5, the duration of the first level signal V1 or the third level signal V3 is 0.5*H, which adjusts the light-emitting duration of the light-emitting device 200 to (3±0.5)*H. This achieves the purpose of adjusting the light-emitting duration in non-integer multiples of the clock period H, which is conducive to more flexible adjustment of the light-emitting duration, making the brightness compensation of the light-emitting device 200 more accurate and improving the display effect of the display panel A10.

[0089] Figure 7 This is a timing diagram of another display panel provided in an embodiment of this application.

[0090] In one embodiment of this application, combined with Figure 6 , Figure 7 As shown, in the first working cycle Time1, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, set in the sustain frame Time1B, are simultaneously shifted right by X1*H. The second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. At this time, compared to... Figure 6 The timing of the output of the first level signal V1 as described above. Figure 7If the first level signal V1 is shifted to the right by X1*H, the duration of simultaneous output of the first level signal V1 and the third level signal V3 is extended by X1*H. This results in an effective pulse duration of (N3+X1)*H for both the first light-emitting control module 20 and the second light-emitting control module 30. This facilitates the non-integer adjustment of the light-emitting duration, improves the light-emitting brightness of the light-emitting device 200 in maintaining frame Time1, and effectively improves the problem of decreased light-emitting brightness caused by leakage current in the pixel circuit 100.

[0091] For example, such as Figure 7 As shown, with X1 = 0.5, since the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are all shifted to the right by 0.5*H, the first level signal V1 is also shifted to the right by 0.5*H. The duration of the simultaneous output of the first level signal V1 and the third level signal V3 is extended to 3.5*H.

[0092] Figure 8 This is a timing diagram of another display panel provided in an embodiment of this application.

[0093] In one embodiment of this application, combined with Figure 6 , Figure 8 As shown, in the first working cycle Time1, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted left by X1*H. The first start signal STV1, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. At this time, compared to... Figure 6 The timing of the output of the third-level signal V3 as described above. Figure 8 If the third-level signal V3 is shifted left by X1*H, the duration for which the first-level signal V1 and the third-level signal V3 are simultaneously output can also be extended by X1*H. This results in an effective pulse duration of (N3+X1)*H for both the first and second light-emitting control modules to be activated. This facilitates non-integer adjustment of the light-emitting duration, allowing for more precise control of the light-emitting device 200's light-emitting duration.

[0094] For example, such as Figure 8 As shown, with X1 = 0.5, since the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are all shifted to the left by 0.5*H, the third level signal V3 is also shifted to the left by 0.5*H. The duration of the simultaneous output of the first level signal V1 and the third level signal V3 is extended to 3.5*H.

[0095] Figure 9 This is a timing diagram of another display panel provided in an embodiment of this application.

[0096] In one embodiment of this application, in conjunction with the figures, Figure 9As shown, in the first working cycle Time1, the effective pulse duration of both the first start signal STV1 and the second start signal STV2 is extended by X2*H, where X2 is an integer greater than or equal to 1. From the above, it can be seen that the effective pulse duration of the first start signal STV1 is the same as the duration of the first level signal V1 transmitted by the first signal line SL1, and the effective pulse duration of the second start signal STV2 is the same as the duration of the third level signal V3 transmitted by the second signal line SL2. Therefore, when only the effective pulse duration of the first start signal STV is extended by X2*H, the output duration of the first level signal V1 is also extended by X2*H; similarly, when only the effective pulse duration of the second start signal STV is extended by X2*H, the output duration of the third level signal V3 is also extended by X2*H. Correspondingly, the duration of simultaneous output of the first level signal V1 and the third level signal V3 is also extended by X2*H. X2 is an integer, so this is beneficial for achieving a larger light emission duration required by the light-emitting device 100 in maintaining the frame Time1B. For example, if X2 = 1, the duration of simultaneous output of the first level signal V1 and the third level signal V3 is extended to (3+1)*H.

[0097] Furthermore, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted by X1*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 remain fixed. Alternatively, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted by X1*H, while the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 remain fixed. This allows the duration of the simultaneous output of the first level signal V1 and the third level signal V3 to be extended to (N3+X2±X1)*H, resulting in an effective pulse duration of (N3+X2±X1)*H for both the first light-emitting control module 20 and the second light-emitting control module 30.

[0098] For example, refer to Figure 9 As shown, when X2 = 1 and X1 = 0.5, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted to the right by 0.5*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 remain fixed. This extends the effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 to (3+1+0.5)*H, achieving an extension of 1.5*H in the light-emitting duration. This solution is advantageous for applications requiring significant light-emitting compensation, and allows for precise adjustment of the light-emitting duration based on substantial compensation, thus improving the applicability of the solution and enhancing the compensation effect on the display panel A10.

[0099] Figure 10 This is a timing diagram of another display panel provided in an embodiment of this application.

[0100] In one embodiment of this application, combined with Figure 6 , Figure 10 As shown, in the first working cycle Time1, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted left by X1*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. At this time, compared to... Figure 6 The timing of the output of the first level signal V1 as described above. Figure 10 The first level signal V1 is shifted left by X1*H, which shortens the duration of simultaneous output of the first level signal V1 and the third level signal V3 by X1*H. This results in an effective pulse duration of (N3-X1)*H for both the first and second light-emitting control modules, which is beneficial for achieving non-integer adjustment of the light-emitting duration. Furthermore, this solution is applicable to situations where it is necessary to reduce the light-emitting brightness of the light-emitting device 200 while maintaining the brightness of frame Time 1. It allows for flexible adjustment of the light-emitting brightness of the display panel 100. For example, when an abnormal display occurs in the display panel A10, the light-emitting brightness of the display panel A10 can be flexibly reduced or increased, which improves the applicability of this solution.

[0101] For example, such as Figure 10 As shown, with X1 = 0.5, since the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are all shifted to the left by 0.5*H, the first level signal V1 is also shifted to the left by 0.5*H. The duration of the simultaneous output of the first level signal V1 and the third level signal V3 is shortened to 2.5*H.

[0102] Figure 11 This is a timing diagram of another display panel provided in an embodiment of this application.

[0103] In one embodiment of this application, combined with Figure 6 ,like Figure 11 As shown, in the first working cycle Time1, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted right by X1*H, while the first start signal STV1, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. At this time, compared to... Figure 5 The timing of the output of the third-level signal V3 as described above. Figure 11 If the third level signal V3 is shifted to the right by X1*H, the duration for which the first level signal V1 and the third level signal V3 are simultaneously output is also shortened by X1*H, and the effective pulse duration for both the first and second light-emitting control modules to be turned on is (N3-X1)*H.

[0104] For example, such as Figure 11As shown, with X1 = 0.5, since the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are all shifted to the right by 0.5*H, the third level signal V3 is also shifted to the right by 0.5*H. The duration of the simultaneous output of the first level signal V1 and the third level signal V3 is shortened to 2.5*H.

[0105] Figure 12 This is a timing diagram of another display panel provided in an embodiment of this application.

[0106] In one embodiment of this application, combined with Figure 6 , Figure 12 As shown, in the first working cycle Time1, the effective pulse duration of both the first start signal STV1 and the second start signal STV2 is shortened by X2*H, where X2 is an integer greater than or equal to 1. Therefore, the durations of the first level signal V1 and the third level signal V3 are also shortened by X2*H, thereby shortening the duration of simultaneous output of the first level signal V1 and the third level signal V3 by X2*H. X2 being an integer is beneficial for situations where the light-emitting device 100 requires a larger reduction in the light-emitting duration during the maintenance frame Time1B. For example, if X2 = 1, the duration of simultaneous output of the first level signal V1 and the third level signal V3 is shortened to (3-1)*H.

[0107] Furthermore, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted by X1*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 remain fixed. Alternatively, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted by X1*H, while the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 remain fixed. This shortens the duration of simultaneous output of the first level signal V1 and the third level signal V3 to (N3-X2±X1)*H, resulting in an effective pulse duration of (N3-X2±X1)*H for both the first and second light-emitting control modules.

[0108] For example, refer to Figure 12 As shown, when X2 = 1 and X1 = 0.5, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted left by 0.5*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. This extends the effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 to (3-1-0.5)*H, and shortens the light-emitting duration by 1.5*H.

[0109] Figure 13 This is a timing diagram of another display panel provided in an embodiment of this application.

[0110] In one embodiment of this application, combined with Figure 6 , Figure 13 As shown, in the first working cycle Time1, the effective pulse duration of both the first start signal STV1 and the second start signal STV2 is extended by X2*H, where X2 is an integer greater than or equal to 1. The effective pulse duration that can control both the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on is (N3+X2)*H.

[0111] In this embodiment, the clock signals are all fixed, and the effective pulse durations of the first start signal STV1 and the second start signal STV2 are simultaneously extended. This allows the pulse durations of the first level signal V1 and the third level signal V3 to also be extended simultaneously, which is beneficial for adjusting the light emission duration to an integer multiple of the clock period H. For example, as... Figure 13 As shown, optionally, if X2 = 2, the pulse duration of both the first level signal V1 and the third level signal V3 is extended by 2*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 is also extended by 2*H, thereby adjusting the light emission duration of the light-emitting device 200 in the maintenance frame Time1B to 5*H.

[0112] Figure 14 This is a timing diagram of another display panel provided in an embodiment of this application.

[0113] In one embodiment of this application, combined with Figure 6 , Figure 14 As shown, in the first working cycle Time1, the effective pulse duration of both the first start signal STV1 and the second start signal STV2 is shortened by X2*H, where X2 is an integer and 1≤X2<N3. Since the effective light-emitting duration of the light-emitting device 200 in the refresh frame Time1A is N3*H, setting X2 within the range of 1≤X2<N3 helps to avoid the light-emitting device 200 failing to emit light. At this time, the effective pulse duration controlling both the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on is (N3-X2)*H.

[0114] For example, such as Figure 14 As shown, optionally, setting X2=1 will shorten the pulse duration of both the first level signal V1 and the third level signal V3 by 1*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 will also be shortened by 1*H, thereby adjusting the light emission duration of the light-emitting device 200 in the maintenance frame Time1B to 2*H.

[0115] Figure 15 This is a timing diagram of another display panel provided in an embodiment of this application.

[0116] In one embodiment of this application, as shown in the figure... Figure 6 , 15 As shown, in the first working cycle Time1, the time of the first working cycle Time1 remains unchanged, and the effective pulse duration of the first start signal STV1 is shortened by X2*H, where X2 is an integer and 1≤X2<N3. Since the time of the first working cycle Time1 remains unchanged, shortening the effective pulse duration of the first start signal STV1 by X2*H also represents extending the ineffective pulse duration of the first start signal STV1 by X2*H. Figure 15 As shown, in the first start signal STV1, at the rising edge where the effective pulse signal switches to the ineffective pulse signal, the rising edge arrives X2*H earlier. At this time, the pulse duration of the first level signal V1 is also shortened by X2*H, the pulse duration of the second level signal V2 is extended by X2*H, and the pulse duration of the third level signal V3 is fixed. Therefore, the duration for which the first level signal V1 and the third level signal V3 are output simultaneously is also shortened by X2*H, so the effective pulse duration for controlling both the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on is (N3-X2)*H. For example, as... Figure 15 As shown, X2 = 1 is set so that the time of the first working cycle Time1 remains unchanged and the effective pulse duration of the first start signal STV1 is shortened to 3*H. The effective pulse duration of the first light-emitting control module 20 and the second light-emitting control module 30 is 2*H.

[0117] In this embodiment, the second starting signal STV2 is fixed, and only the effective pulse duration of the first starting signal STV1 is changed, so as to shorten the effective pulse duration when both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on. This helps to reduce the number of signals that need to be adjusted and improve the efficiency of signal adjustment.

[0118] Figure 16 This is a schematic diagram of a display device provided in an embodiment of this application.

[0119] This application provides a display device A20, such as... Figure 16 As shown, the display device A20 includes the display panel A10 as provided in the above embodiment. The display device A20 can be a device with display function, such as a television, computer, or mobile phone.

[0120] In the display device A20, the signals output by the first shift register circuit 301 and the second shift register circuit 401 are configured to control the first light-emitting control module 20 and the second light-emitting control module 30 in the pixel circuit 100, respectively. This enables the first light-emitting control module 20 and the second light-emitting control module to be turned on in a time-division multiplexing manner. This facilitates the adjustment of the start and end times of the light-emitting driving current generated by the pixel circuit 100 to the light-emitting device 200 by the switching of the first light-emitting control module 20 and the second light-emitting control module 30. This allows for more flexible adjustment of the light-emitting time of the light-emitting device 200, enabling the adjustment of the light-emitting duration to a non-integer multiple or an integer multiple of the clock cycle, and providing more accurate compensation for the light-emitting brightness of the light-emitting device 200.

[0121] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: The pixel circuit includes a driving transistor, a first light-emitting control module, and a second light-emitting control module. The control terminal of the first light-emitting control module is electrically connected to a first signal line, and the control terminal of the second light-emitting control module is electrically connected to a second signal line. The first signal line can output a first level signal and a second level signal. The control terminal of the first light-emitting control module is turned on when it receives the first level signal and turned off when it receives the second level signal. The second signal line can output a third level signal and a fourth level signal. The control terminal of the second light-emitting control module is turned on when it receives the third level signal and turned off when it receives the fourth level signal. The first shift register includes M cascaded first shift register circuits, the first output terminal of the first shift register circuit is electrically connected to the first signal line; the first shift register circuit receives a first start signal, a first clock signal, and a second clock signal; The second shift register includes M cascaded second shift register circuits; the second output terminal of the second shift register circuit is electrically connected to the second signal line; the first shift register circuit receives a second start signal, a third clock signal, and a fourth clock signal; The first light-emitting control module and the second light-emitting control module are both electrically connected to the driving transistor, and when both are turned on, they control the driving transistor to output a light-emitting driving current. The periods of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are all N1*H, where N1 is an integer greater than or equal to 1; H is the time between the falling edge of the first clock signal and the falling edge of the second clock signal. The pixel circuit includes at least a first operating cycle, in which: The rising and falling edges of the first start signal are both N2*H earlier than the rising and falling edges of the second start signal; N2 is an integer greater than or equal to 1. The rising and falling edges of the first level signal are both N2*H earlier than the rising and falling edges of the third level signal; The effective pulse duration for controlling both the first and second light-emitting control modules to be turned on is N3*H, where N3 is an integer greater than or equal to 1.

2. The display panel according to claim 1, characterized in that, The first start signal and the second start signal are supplied by different signal lines.

3. The display panel according to claim 2, characterized in that, The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are supplied by different signal lines; The first shift register circuit also includes: The first output unit is electrically connected to the first output terminal and is used to output the first level signal; The second output unit is electrically connected to the first output terminal and is used to output the second level signal; A first control unit receives a first start signal, a first clock signal, and a second clock signal, and is used to control the first output unit or the second output unit to turn on. The second shift register circuit also includes: The third output unit is electrically connected to the second output terminal and is used to output the third level signal; The fourth output unit is electrically connected to the second output terminal and is used to output the fourth level signal; The second control unit receives a second start signal, a third clock signal, and a fourth clock signal, and controls the third output unit or the fourth output unit to turn on.

4. The display panel according to claim 1, characterized in that, The falling edge and rising edge of the first clock signal are both N2*H earlier than the rising edge and falling edge of the third clock signal; The falling edge and rising edge of the second clock signal are both N2*H earlier than the rising edge and falling edge of the fourth clock signal.

5. The display panel according to claim 4, characterized in that, In the first working cycle, the first start signal, the first clock signal, and the second clock signal move simultaneously by X1*H, while the second start signal, the third clock signal, and the fourth clock signal are fixed; or, in the first working cycle, the second start signal, the third clock signal, and the fourth clock signal move simultaneously by X1*H, while the first start signal, the first clock signal, and the second clock signal are fixed. The effective pulse duration for both the first and second light-emitting control modules is (N3±X1)*H; 0<X1≤N2.

6. The display panel according to claim 5, characterized in that, During the first working cycle, the first start signal, the first clock signal, and the second clock signal are simultaneously shifted to the right by X1*H; the effective pulse duration for both the first light-emitting control module and the second light-emitting control module is (N3+X1)*H.

7. The display panel according to claim 5, characterized in that, During the first working cycle, the second start signal, the third clock signal, and the fourth clock signal are simultaneously shifted left by X1*H; the effective pulse duration for both the first light-emitting control module and the second light-emitting control module is (N3+X1)*H.

8. The display panel according to claim 5, characterized in that, In the first working cycle, the effective pulse duration of both the first start signal and the second start signal is extended by X2*H, where X2 is an integer greater than or equal to 1; The effective pulse duration for controlling both the first and second light-emitting control modules to be turned on is (N3+X2±X1)*H.

9. The display panel according to claim 5, characterized in that, During the first working cycle, the first start signal, the first clock signal, and the second clock signal are simultaneously shifted left by X1*H; the effective pulse duration of both the first light-emitting control module and the second light-emitting control module is (N3-X1)*H.

10. The display panel according to claim 5, characterized in that, During the first working cycle, the second start signal, the third clock signal, and the fourth clock signal are simultaneously shifted to the right by X1*H; the effective pulse duration of both the first light-emitting control module and the second light-emitting control module is (N3-X1)*H.

11. The display panel according to claim 5, characterized in that, In the first working cycle, the effective pulse duration of both the first start signal and the second start signal is shortened by X2*H, where X2 is an integer greater than or equal to 1; The effective pulse duration for controlling both the first and second light-emitting control modules to be turned on is (N3-X2±X1)*H.

12. The display panel according to claim 1, characterized in that, In the first working cycle, the effective pulse duration of both the first start signal and the second start signal is extended by X2*H, where X2 is an integer greater than or equal to 1; The effective pulse duration for controlling both the first and second light-emitting control modules to be turned on is (N3+X2)*H.

13. The display panel according to claim 1, characterized in that, In the first working cycle, the effective pulse duration of both the first start signal and the second start signal is shortened by X2*H, where X2 is an integer and 1≤X2<N3; The effective pulse duration for controlling both the first and second light-emitting control modules to be turned on is (N3-X2)*H.

14. The display panel according to claim 1, characterized in that, In the first working cycle, the time of the first working cycle remains unchanged and the effective pulse duration of the first start signal is shortened by X2*H, where X2 is an integer and 1≤X2<N3; The effective pulse duration for controlling both the first and second light-emitting control modules to be turned on is (N3-X2)*H.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1-14.

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