A driving method and chip for Micro-LED display

Abstract

This application discloses a driving method and chip for Micro-LED displays, belonging to the field of LED display technology, including: obtaining the total number of pixels of the image to be displayed; dividing the image to be displayed into multiple sub-areas based on the total number of pixels, each sub-area containing a pixel array composed of multiple driving units; transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; the driving unit receives a row signal, grayscale data, a reference current, and a clock signal as input signals; when receiving the row signal, the driving unit converts the grayscale data into a PWM signal, the duty cycle of the PWM signal being determined by the grayscale data; controlling the output time of the reference current according to the PWM signal, thereby generating a driving current corresponding to the grayscale data, and driving the pixel to emit light. In view of the high power consumption of Micro-LED display driver chips in the prior art, this application reduces power consumption while improving display uniformity.

Description

Technical Field

[0001] The present application relates to the field of LED display technology, and more specifically, to a driving method and chip for Micro-LED display. Background Art

[0002] With the rapid development of information technology, people are demanding increasingly higher performance from display devices. As a new display technology, Micro-LED is attracting widespread attention in the industry due to its advantages such as high resolution, low power consumption, and fast response time. Micro-LED technology is derived from traditional LED displays, but by combining it with advanced semiconductor processes, it integrates hundreds or even thousands of display units per unit area, significantly improving display resolution and fineness.

[0003] However, the high-density pixel array of Micro-LED poses a severe challenge to its driving circuit. Traditional LED driver chips are limited by their low integration and are difficult to be directly applied to Micro-LED displays. In order to give full play to the advantages of Micro-LED technology, it is urgent to develop a new type of driver chip that is highly integrated, low-power, and highly reliable. The existing LED driver chips have the following main shortcomings: First, the power consumption is high, which makes it difficult to meet the low power consumption requirements of portable devices; second, the display uniformity is poor, which easily leads to problems such as inconsistent brightness and color deviation.

[0004] The Chinese patent application, application number CN202210042636.7, published on April 15, 2022, discloses a highly integrated row and column LED display driver chip, which integrates row and column drivers inside the chip; the chip includes a current reference unit, an image parameter write unit, an SRAM unit, a configurable register unit, a row switch output array unit, and a column constant current output array unit; the input signal is sent to the current reference unit and the image parameter write unit, passes through the SRAM unit and the configurable register unit, and is output under the control of the row switch output array unit and the column constant current output array unit. However, this solution mainly adopts a global constant current drive method, that is, the same drive current is provided to all pixels through the column constant current output array unit, ignoring the differences in electrical characteristics between different pixels, resulting in pixel brightness uniformity that needs to be further improved. Summary of the Invention

[0005] 1. Technical problems to be solved

[0006] In response to the problem of high power consumption of Micro-LED display driver chips in the existing technology, the present application provides a driving method and chip for Micro-LED display. By dividing the pixel unit and the driving unit into multiple sub-areas and configuring an independent protocol interface for each sub-area, parallel transmission of grayscale data is achieved, thereby reducing power consumption; at the same time, by collecting temperature signals at different positions on the chip and dynamically adjusting the brightness of the pixel unit according to the temperature difference, the display uniformity is improved; and a two-stage trigger is used to generate a PWM signal to accurately control the conduction time of the driving transistor, thereby reducing power consumption while improving display uniformity.

[0007] 2. Technical solution

[0008] The purpose of this application is achieved through the following technical solutions.

[0009] One aspect of the present application provides a driving method for Micro-LED display, including: obtaining the total number of pixels of an image to be displayed; dividing the image to be displayed into multiple sub-areas based on the total number of pixels, each sub-area containing a pixel array composed of multiple driving units; transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; the driving unit receives a row signal, grayscale data, a reference current and a clock signal as input signals; when receiving the row signal, the driving unit converts the grayscale data into a PWM signal, and the duty cycle of the PWM signal is determined by the grayscale data; controlling the output time of the reference current according to the PWM signal, thereby generating a driving current corresponding to the grayscale data, and driving the pixel to emit light.

[0010] Furthermore, generating the driving current also includes: detecting whether a row signal is received: if the row signal is not received, setting the control signal SELB to a high level, writing the grayscale data into the first register and the second register, and setting the output end of the register to a high level or a low level according to the grayscale data; wherein the first register and the second register are used to temporarily store the grayscale data; if the row signal is received, setting the control signal SEL to a high level, and setting the SET signal to a low level at the same time, controlling the first switch tube PM1 and the second switch tube PM2 to be disconnected, and the third switch tube PM3 to be connected; so that the reference current is output to the driving current end via the third switch tube PM3.

[0011] SELB is a control signal used to control the operating state of the driver unit. When the driver unit does not receive a row signal, the SELB signal is set high, causing the driver unit to enter a data write state. Externally transmitted grayscale data is written into the first and second registers, and the data output terminals of the registers are set to a high or low level depending on the grayscale data value. SEL is also a control signal with the opposite function of SELB. When the driver unit receives a row signal, the SEL signal is set high, causing the driver unit to enter an operating state. The first and second switching transistors PM1 and PM2 are controlled to be disconnected, and the third switching transistor PM3 is turned on, causing the reference current to be output through PM3 to the driving current terminal, driving the pixel to emit light. The SET signal is used to control the conduction state of the switches in the driver unit. When the driver unit receives a row signal, the SET signal is set low, cooperating with the SEL signal to control the disconnection of PM1 and PM2 and the turn-on of PM3.

[0012] PM1 is a switching transistor in the driver unit and is connected in series with the second switching transistor, PM2, in the reference current output path. PM1 is controlled by the SEL and SET signals. When SEL is low, PM1 conducts; when SEL is high and SET is low, PM1 is disconnected. PM1 and PM2 work together to control whether the reference current is output to the drive current terminal. PM2 is connected in series with PM1 and is controlled in the same manner as PM1. When both PM1 and PM2 are disconnected, the reference current is blocked and cannot be output to the drive current terminal. PM3 is another switching transistor in the driver unit, connected in parallel with PM1 and PM2. When SEL is high and SET is low, PM3 conducts, allowing the reference current to be output through PM3 to the drive current terminal. When the CLK_PWM signal coincides with the rising edge of the clock CLK, PM3 is disconnected, ceasing the output of the drive current.

[0013] Furthermore, if the driving unit receives a row signal, before setting the SEL signal to a high level, the method further includes: counting the number of cycles of the clock signal CLK by a counter; and when the count value is greater than 2, setting the control signal SEL to a high level.

[0014] Among them, CLK is a clock signal in the drive unit, which is used to control the working rhythm and timing of each sub-unit in the drive unit. It is a periodic square wave signal that plays a role in synchronization and timing during the working process of the drive unit. When the drive unit receives the line signal, the counter starts to count the number of cycles of CLK. Every time CLK completes a complete cycle, the counter count value will increase by 1. This process continues until the count value reaches the preset threshold (2 in the scheme). When the count value of the counter is greater than the preset threshold (2), the control signal SEL is set to a high level, and the drive unit officially enters the working state. The purpose of this is to give the drive unit a certain response time after receiving the line signal, and wait until its internal circuit state is stable before starting to work, so as to improve the reliability of the work. The clock signal CLK is also used to generate the PWM control clock signal CLK_PWM. When CLK_PWM coincides with the rising edge of CLK, it means that a PWM cycle ends, the output end of the D flip-flop is set to a low level, PM3 is turned off, and the output of the drive current stops. In this way, the drive current pulse width is controlled by the PWM signal. The CLK signal is also used to generate the clock signal CLK1 synchronized with it. When the control signal SELB is set to a low level, CLK1 is synchronized with CLK to provide a working clock for the series-connected D flip-flops, enabling them to sequentially read the grayscale data stored in the registers, shift them, and finally output a PWM signal.

[0015] Furthermore, it also includes: the driving unit determines the rising edge of the clock CLK through the CLK_PWM signal; when the CLK_PWM signal coincides with the rising edge of the clock CLK, the preset low level is written into the data input end of the D trigger, and a low level is output at the output end Q of the D trigger, thereby turning off the third switch PM3 and stopping the output of the driving current; the control signal SELB is set to a low level, so that the clock signal CLK1 is synchronized with the input clock CLK, and the output ends of the first register and the second register are set to a high level; through multiple series-connected D triggers, according to the clock signal CLK1, the grayscale data stored in the first register and the second register are read in sequence, and the grayscale data is converted into a PWM signal output by shifting.

[0016] CLK_PWM is a PWM control clock signal used to detect the rising edge of the clock signal CLK. When the CLK_PWM signal coincides with the rising edge of CLK, a PWM cycle ends. At this point, a preset low level is written to the data input of the D-type flip-flop, causing its output Q to output a low level, thereby turning off the third switching transistor PM3 and stopping the output of the drive current. The period of the CLK_PWM signal determines the period of the PWM signal, and thus the pulse width of the drive current. The D-type flip-flop is a common sequential logic circuit used to generate PWM signals in this solution. It has a data input D and a clock input. When the clock signal rises, the level at the D-type input is transmitted to the output Q. By connecting multiple D-type flip-flops in series and sequentially connecting the output of the previous D-type flip-flop to the input of the next D-type flip-flop at each rising clock edge, data shifting can be achieved, ultimately outputting a PWM signal. The duty cycle of the PWM signal depends on the data (grayscale data) written to the D-type flip-flop.

[0017] CLK1 is a clock signal synchronized with the clock signal CLK, providing the operating clock for the series-connected D flip-flops. When the control signal SELB is set to a low level, CLK1 synchronizes with CLK, allowing the D flip-flops to sequentially read the grayscale data stored in the first and second registers at each rising edge of CLK and convert it into a PWM signal output through a shift operation. The frequency of CLK1 determines the resolution of the PWM signal. The first and second registers are memories in the drive unit used to temporarily store grayscale data. When the SELB signal is high, the input grayscale data is written to these two registers. When the SELB signal is low, the output of the registers is set to a high level, allowing the stored grayscale data to be read by the series-connected D flip-flops. By alternating the two registers, the grayscale data for the next frame can be received in advance without affecting the current display, thereby improving display efficiency.

[0018] In this scheme, when the CLK_PWM signal coincides with the rising edge of CLK, a preset low level is written into the D flip-flop, causing the output Q to go low, shutting down PM3 and stopping the output drive current, thus ending a PWM cycle. Simultaneously, the SELB signal is set low, CLK1 synchronizes with CLK, and the outputs of the first and second registers are set high, allowing the stored grayscale data to be sequentially read and shifted through the series-connected D flip-flops, ultimately outputting a new PWM signal and starting a new display cycle.

[0019] Furthermore, generating a PWM signal according to the clock signal CLK1 includes: the driving unit sets the control signal SELB to a low level to synchronize the clock signal CLK1 with CLK; and simultaneously sets the data output terminals of the first register and the second register to a high level; starting from the first D flip-flop, at the rising edge of each clock signal CLK1: using the output terminal Q of the previous level D flip-flop as the data input terminal of the current level D flip-flop, and transferring the level state of the input terminal of the current level D flip-flop to the output terminal Q as the data input terminal of the next level D flip-flop; and so on, until the last level D flip-flop, outputting the PWM signal through the output terminal Q of the last level D flip-flop.

[0020] In a D flip-flop, the Q terminal is the output terminal of the flip-flop. When the rising edge of the clock signal arrives, the D flip-flop transfers the level state of the data input terminal D to the output terminal Q and maintains this state until the next rising edge of the clock. In this scheme, multiple D flip-flops are connected in series to form a shift register, which is used to convert parallel grayscale data into a serial PWM signal. The specific operation process is as follows: When the control signal SELB is set to a low level, the clock signal CLK1 is synchronized with CLK, providing the operating clock for the D flip-flops. At the same time, the data output terminals of the first and second registers are set to a high level, allowing the stored grayscale data to be read by the D flip-flops. When the first clock signal CLK1 rises, the first D flip-flop reads the output of the first register (the first grayscale data) into the data input terminal D and transfers it to the output terminal Q on the next rising edge of CLK1. The output terminal Q of the first D flip-flop is connected to the data input terminal D of the second D flip-flop. When the next rising edge of CLK1 arrives, the second D flip-flop reads the state of Q (the first grayscale data) and transfers it to its own output terminal Q on the next rising edge of CLK1. Similarly, with each rising edge of CLK1, the grayscale data shifts sequentially through the D flip-flop chain until the last D flip-flop is reached. The output Q of the last D flip-flop outputs the PWM signal. The duty cycle of the PWM signal depends on the grayscale data written to the D flip-flop. If the grayscale data is high, the PWM signal is high during that clock cycle; otherwise, it is low. By controlling the proportion of high levels in the grayscale data, the duty cycle of the PWM signal can be adjusted, thereby adjusting the brightness of the pixel.

[0021] Furthermore, the default protocol is the QSPI protocol. QSPI (Quad Serial Peripheral Interface) is a high-speed serial communication protocol commonly used for data transmission between processors and peripherals. It is an extension of the SPI (Serial Peripheral Interface) protocol and can achieve higher data transmission rates by using four data lines (SPI only uses one).

[0022] Furthermore, the number of triggers connected in series corresponds one-to-one to the number of bits of the grayscale data.

[0023] Furthermore, in each driving unit, the row signal, grayscale data, reference current, and clock signal are received through independent input ports.

[0024] Furthermore, the driving method also includes: setting a temperature sensor on the Micro-LED to collect the temperature of different areas, and adjusting the grayscale data of different areas of the Micro-LED according to the temperature.

[0025] Another aspect of the embodiments of the present application further provides a driver chip for Micro-LED display, comprising: a plurality of parallel driver units, each driver unit corresponding to a pixel point, and generating a driving current according to the grayscale data of the pixel point to drive the pixel point to emit light; wherein the plurality of driver units form a pixel array, the plurality of pixel arrays form a sub-region, and the plurality of sub-regions form a display area; a row signal generation unit, generating a row signal and transmitting the row signal to the driver unit of each row; a data transmission unit, transmitting the grayscale data of each pixel point to the corresponding driver unit through the QSPI protocol; a clock generation unit, generating a clock signal CLK, a PWM control clock signal CLK_PWM, and a clock signal synchronized with CLK signal CLK1, and transmit the clock signal to the driving unit respectively; a reference current generating unit, generates a constant reference current, and transmits the reference current to the driving unit; a temperature correction unit, collects temperature data of the Micro-LED display area, and corrects the grayscale data of different areas according to the temperature data; wherein each driving unit includes: a first register and a second register, temporarily storing grayscale data; a first switching tube PM1, a second switching tube PM2 and a third switching tube PM3, controlling the output of the reference current; a counter, counting the clock signal CLK; a plurality of D flip-flops connected in series, the number of D flip-flops being the same as the number of bits of the grayscale data, and the plurality of D flip-flops connected in series converting the grayscale data into a PWM signal.

[0026] 3. Beneficial effects

[0027] Compared with the existing technology, the advantages of this application are:

[0028] Existing Micro-LED driver chips usually adopt a centralized data transmission and processing architecture. The grayscale data of all pixel units needs to be transmitted serially through a single interface, resulting in long transmission time and high power consumption. This application divides the display area into multiple sub-areas, and each sub-area is equipped with an independent QSPI interface, which can realize the parallel transmission of grayscale data between multiple sub-areas. This distributed data transmission architecture greatly shortens the data transmission time of a single pixel and reduces the power consumption during the transmission process. At the same time, multiple drive units in each sub-area can also work in parallel, further reducing the workload and power consumption per unit time.

[0029] Due to the tiny pixel size, Micro-LED is more sensitive to factors such as chip technology and material properties, and is prone to uneven display problems. This application integrates a temperature sensor array on the chip, which can collect temperature data from different areas in real time. Since temperature affects the luminous efficiency of Micro-LED, the pixel grayscale values ​​in different areas can be dynamically compensated according to the temperature difference between areas, thereby improving the display uniformity between areas. At the same time, this application also proposes an improved PWM signal generation method. Traditional PWM signals are directly generated by counters, and have limitations in resolution and linearity. This application uses a two-stage D flip-flop to first convert the grayscale data into a bit string of high and low levels, and then output the PWM waveform through a shift register. This method can achieve higher PWM resolution and better linearity between grayscale levels, which helps to improve display uniformity.

[0030] Increasing the display refresh rate and reducing power consumption are often contradictory. A higher refresh rate means that more data needs to be transmitted per unit time, and power consumption will increase accordingly. The present application sets up dual registers in each driver unit, which can receive the grayscale data of the next subframe in advance when the current subframe is displayed. By using the subframe gap to complete data transmission and storage in advance, the transmission time within the unit subframe can be shortened, and low instantaneous power consumption can still be maintained without reducing the refresh rate. In addition, the present application further reduces power consumption by optimizing the QSPI protocol, adopting dual-channel transmission, and increasing the clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is an exemplary flow chart of a driving method for Micro-LED display of the present application;

[0032] Figure 2 This is a schematic diagram of the driver chip driving array of this application;

[0033] Figure 3 Schematic diagram of the framework of a single drive unit;

[0034] Figure 4This is a schematic diagram of the circuit implementation of a single drive unit;

[0035] Figure 5 This is the working timing diagram of a single drive unit;

[0036] Figure 6 Schematic diagram of row and column integrated driver chip;

[0037] Figure 7 This is the structural block diagram of the temperature sensor. DETAILED DESCRIPTION

[0038] The present application is described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] Example 1

[0040] Figure 1 This is an exemplary flowchart of a driving method for Micro-LED display in the present application, including: obtaining the total number of pixels of an image to be displayed; dividing the image to be displayed into multiple sub-areas based on the total number of pixels, each sub-area containing a pixel array composed of multiple driving units; transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; the driving unit receives a row signal, grayscale data, a reference current and a clock signal as input signals; when receiving the row signal, the driving unit converts the grayscale data into a PWM signal, and the duty cycle of the PWM signal is determined by the grayscale data; controlling the output time of the reference current according to the PWM signal, thereby generating a driving current corresponding to the grayscale data, and driving the pixel to emit light.

[0041] A driver chip for Micro-LED displays. The chip has a total dot matrix of 12,960 pixels, divided into 16 sub-regions for efficient parallel transmission. Each sub-region corresponds to a pixel array containing 12,960 driver units. The chip uses the QSPI (Quad Serial Peripheral Interface) protocol to independently transmit data to each sub-region. This means that pixel brightness data is transmitted in parallel over 16 data lines, improving data throughput and transmission speed. Figure 2 A schematic diagram of the chip's overall architecture is provided. The 16 sub-areas are labeled Area 1 through Area 16, each equipped with an independent QSPI interface that can independently receive data and instructions from an external MCU (Micro Control Unit). This sub-area parallel transmission design fully utilizes the potential of the high-density Micro-LED array, maintaining a high refresh rate while reducing transmission power consumption.

[0042] Figure 3The structure of a single driver unit is shown. Each driver unit corresponds to a pixel and includes a row selection circuit, storage circuit, PWM generation circuit, driver circuit, and temperature compensation circuit. The row selection circuit receives the row signal and activates all driver units in that row when the row signal is valid. The storage circuit temporarily stores grayscale data from the QSPI interface. The PWM generation circuit generates a PWM waveform with a specific duty cycle based on the grayscale data and clock signal. The driver circuit further converts the PWM signal into a constant current with adjustable amplitude and applies it to the corresponding Micro-LED device. The temperature compensation circuit adjusts the drive current bias in real time based on the temperature sensor value.

[0043] The driver chip in this embodiment uses 8-bit grayscale data, meaning each pixel has 256 levels of adjustable brightness. This is achieved through precise control of the PWM duty cycle. Theoretically, 2^8 = 256 PWM waveforms with different duty cycles can be generated, corresponding to 256 different brightness levels. The higher the grayscale level, the greater the PWM duty cycle, the greater the average drive current, and the higher the pixel brightness. In addition, each driver unit incorporates a reference current input to provide an initial bias for the drive current. This reference current can be configured via external circuitry during chip initialization to accommodate different process conditions and display applications. The magnitude of the reference current affects the base brightness of the pixel and is generally set to a relatively low value to reduce power consumption. The clock signal provides synchronous timing for the entire chip and controls the operating timing of each driver unit. In practical applications, the clock frequency can be adjusted based on the dynamic range and refresh rate requirements of the displayed content to balance power consumption and display quality.

[0044] This driving method takes a four-bit grayscale data as an example. Figure 4 As shown in the figure, the drive unit mainly consists of a trigger circuit, a bias circuit, and a drive circuit. The first-stage trigger circuit includes a D flip-flop and a NAND gate, which are used to control the start and stop of the drive circuit. The second-stage trigger circuit includes four D flip-flops, which are used to generate PWM signals based on grayscale data and modulate the pulse width of the drive current.

[0045] Before the row signal arrives, the SELB signal is high. At this point, the second-stage flip-flop circuit's inputs, S<3:0> and R<3:0>, are set to the high and low levels corresponding to the grayscale data. Taking a 4-bit grayscale as an example, grayscale data "0000" corresponds to no brightness, "1111" corresponds to the brightest, and other values ​​correspond to the 16 grayscale levels. S<3:0> and R<3:0> transmit the grayscale data to the reset and set terminals of the corresponding D-type flip-flops, respectively, controlling their Q terminals to output a high or low level.

[0046] When the row signal arrives, after two clock cycles, the SEL signal is pulled high, and the SET signal is briefly pulled low. This negative pulse sets the Q terminal of the D flip-flop to "1" and the Qn terminal to "0." Simultaneously, CLK1, controlled by the SEL signal, begins synchronizing with the system clock CLK, serving as the operating clock for the cascade flip-flop. S<3:0> and R<3:0>, controlled by the SELB signal, are all set high to "1," placing the second-stage flip-flop in normal mode. This sets EN high and ENB low. This turns PM1 off and PM2 on, connecting the bias signal VBIAS to the driver transistor PM3. VBIAS provides a constant bias voltage, causing PM3 to operate in its saturation region, resulting in a constant drive current output at the Iout port, illuminating the Micro-LED device.

[0047] When the next CLK_PWM clock rising edge arrives, the input terminal "0" of the first-stage D flip-flop is sampled to the Q terminal, EN becomes low and ENB becomes high, PM3 is turned off, and the drive current stops outputting.

[0048] Next, at each rising edge of CLK1, the second-stage flip-flop circuit begins shifting and reading the grayscale data stored in the D flip-flop, generating a PWM waveform bit by bit. For example, for the grayscale data "1110," Q<3:0> are initially high. On the first rising edge of CLK1, the highest bit, "1," is shifted and output, and PWM remains high. On the second and third rising edges of CLK1, "1"s continue to be shifted and output, and PWM remains high. Until the fourth rising edge of CLK1, the lowest bit, "0," is shifted and output, and PWM goes low. This shows that the duration of PWM's high level is proportional to the number of "1"s in the grayscale data. This PWM signal controls the on-time of PM3, thereby adjusting the duration of the Micro-LED's illumination, achieving brightness modulation.

[0049] like Figure 5 As shown in the figure, assuming the input 4-bit grayscale data is "1111", indicating a full-bright display. Before the rising edge of CLK1, the PWM signal as well as CLK2, CLK3, and CLK4 are all preset to a high level of "1". This means that the driving transistor PM3 is in the on state, and the Micro-LED is initially illuminated.

[0050] When the first CLK1 rising edge arrives, the input terminal D of the first-stage D flip-flop receives the highest-order grayscale data "1" and transmits it to the Q terminal on the next CLK1 rising edge, causing CLK2 to change from "1" to "0". The falling edge of CLK2 triggers the second-stage D flip-flop, causing its input terminal D to receive the second-highest-order grayscale data "1".

[0051] Similarly, when the next rising edge of CLK1 arrives, the second-stage D flip-flop transmits "1" to the Q terminal, causing CLK3 to change from "1" to "0". The falling edge of CLK3 triggers the third-stage D flip-flop, causing its input terminal D to receive the second lowest grayscale data "1".

[0052] Similarly, each rising edge of CLK1 triggers the shift and transmission of one level of grayscale data, and the corresponding CLKx signal (x=2, 3, 4) also generates a falling edge. The PWM signal will not become "0" until the last grayscale data "1" is transmitted to CLK5.

[0053] Throughout this process, the PWM signal remains high for four CLK1 cycles, corresponding to maximum brightness. If the grayscale data is "1110," the PWM signal will change to "0" in the fourth CLK1 cycle, corresponding to the second-highest brightness. This shows that the number of "1s" in the grayscale data determines the duration of the PWM signal's high level, thereby adjusting the duration of the Micro-LED's lighting.

[0054] When the rising edge of CLK5 arrives, the ENB signal is pulled high, PM1 is turned on and PM2 is turned off, cutting off the bias signal Bias on PM3 and turning it off. At this time, the drive current stops outputting, the drive unit goes out, and the display cycle ends. Figure 5 Only the special case of 1111 all-on is illustrated. For other grayscale data, the duration of the PWM high level will vary, but the control principle and timing process are similar. Furthermore, this sequential circuit is composed entirely of D flip-flops, which utilize their clock synchronization and shift characteristics to achieve automatic conversion and transmission of grayscale data, avoiding complex control logic and simplifying circuit design.

[0055] Example 2

[0056] This embodiment proposes an on-chip temperature compensation solution, which integrates temperature sensors at the four corners of the chip to monitor the temperature distribution of the chip in real time and adjust the LED drive current according to the temperature change, thereby improving the display quality. Figure 6 As shown, an on-chip temperature sensor is placed at each of the four corners of the driver chip. This distributed sensor layout comprehensively monitors the chip's temperature distribution and promptly detects temperature anomalies in local areas. When the temperature of different areas of the chip changes, the corresponding sensor converts the temperature information into an electrical signal and outputs it to the control system.

[0057] Based on the received temperature data, the control system calculates the temperature distribution of the LED array and the required brightness compensation value for each area. The control system then converts this compensation value into a corresponding bias voltage or current. By adjusting the V bias signal of each driver unit, the control system dynamically changes the LED drive current, thereby offsetting brightness deviations caused by temperature changes and ensuring display uniformity.

[0058] Figure 7 The detailed structure of the temperature sensor is presented. It consists of three main components: a temperature sensing circuit, an amplifier module, and an ADC. The temperature sensing circuit is a temperature-dependent resistor network whose output voltage varies with temperature. The amplifier module amplifies the tiny temperature signal to an appropriate amplitude range. The ADC quantizes the analog temperature signal into a digital value for easy processing by the control system.

[0059] Temperature sensing circuits typically use silicon-based integrated resistors, leveraging the temperature coefficient of silicon to create a voltage divider circuit that varies with temperature. As the temperature rises, the silicon resistance decreases, causing the output voltage of the temperature sensing circuit to drop; the opposite occurs when the temperature drops.

[0060] The amplifier module typically consists of a multi-stage operational amplifier, using appropriate resistor negative feedback to amplify millivolt-level temperature signals to volt levels. To minimize the effects of offset and noise, the amplifier circuit employs modulation techniques such as chopping or chopped modulation to modulate the DC signal to a higher frequency. The amplified DC temperature signal is then demodulated and filtered.

[0061] The ADC uses a successive approximation architecture, which determines the digital quantization value of the input signal bit by bit through a series of comparison and approximation operations. SAR ADCs offer advantages such as fast conversion speed, low power consumption, and moderate accuracy, making them particularly suitable for on-chip temperature sensing applications. This embodiment uses an 8-bit SAR ADC, which provides 256 levels of temperature resolution, meeting the requirements of most applications.

[0062] The specific implementation is as follows: The temperature sensing circuit adopts a PTAT (Proportional To Absolute Temperature) structure based on a PNP transistor. Figure 6 As shown in the figure, two currents with integer current scaling factors flow through two identical PNP transistors, generating two voltage signals at their emitters. According to the transistor's volt-ampere characteristic equation, the difference between these two voltage signals is linearly related to absolute temperature, with the slope determined by the current ratio and the physical parameters of the transistors. Therefore, by detecting this differential voltage, a voltage signal proportional to temperature can be obtained. Compared with conventional PN junction temperature sensing methods, this circuit has excellent linearity and consistency, and is easy to integrate.

[0063] To facilitate quantization processing by the subsequent ADC, the tiny signal output by the temperature sensing circuit needs to be amplified. This design uses a fully differential switched-capacitor operational amplifier, controlled by two non-overlapping clocks, to differentially amplify the input signal by a factor of 20. Compared to single-ended amplification, the fully differential structure has a stronger ability to suppress common-mode noise and power supply noise, helping to improve the signal-to-noise ratio. At the same time, the rational design of the capacitor ratio and clock phase ensures that the amplitude of the amplified signal exactly corresponds to the quantization range of the ADC, simplifying the interface circuit. Simulation results show that the amplifier module can amplify the temperature sensing signal corresponding to 1°C to a value equivalent to 1LSB (Least Significant Bit) of the ADC, thereby achieving an optimal match between temperature detection accuracy and ADC resolution.

[0064] The ADC utilizes an 8-bit successive approximation architecture. It uses a binary search to complete digital conversion of analog signals within eight clock cycles. Given the slow temperature variations and low conversion rate requirements, synchronous SAR logic is employed to reduce circuit complexity and power consumption. The 8-bit resolution allows the temperature range from -40°C to 125°C to be quantized into 256 levels, resulting in a temperature resolution better than 0.5°C, fully meeting design requirements.

[0065] The above schematically describes the invention of the present application and its implementation methods. This description is not restrictive. Without departing from the spirit or basic features of the present application, the present application can be implemented in other specific forms. What is shown in the drawings is only one of the implementation methods of the invention of the present application. The actual structure is not limited to this. Any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it, without departing from the purpose of the present invention, a structural method and embodiment similar to the technical solution without creativity should fall within the scope of protection of this patent. In addition, the word "including" does not exclude other elements or steps, and the word "one" before an element does not exclude the inclusion of "multiple" elements. The multiple elements stated in the product claim can also be implemented by one element through software or hardware. Words such as first and second are used to indicate names and do not indicate any specific order.

Claims

1. A driving method for Micro-LED display, characterized in that: include: Get the total number of pixels of the image to be displayed; Divide the image to be displayed into multiple sub-areas according to the total number of pixels, each sub-area containing a pixel array composed of multiple driving units; Transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; The driving unit receives a row signal, grayscale data, a reference current and a clock signal as input signals; When receiving the row signal, the driving unit converts the grayscale data into a PWM signal. The duty cycle of the PWM signal is determined by the grayscale data. The output time of the reference current is controlled according to the PWM signal, thereby generating a driving current corresponding to the grayscale data and driving the pixel to emit light. Generating a driving current corresponding to the grayscale data also includes: Check whether the line signal is received: If no row signal is received, the control signal SELB is set to a high level, the grayscale data is written into the first register and the second register, and the output end of the register is set to a high level or a low level according to the grayscale data; wherein the first register and the second register are used to sample the grayscale data and send it to the set end and the reset end of the second-stage trigger; If a row signal is received, the control signal SEL is set to a high level, and the SET signal is briefly set to a low level, controlling the first switch tube PM1 to be turned off and the second switch tube PM2 to be turned on, so that the bias signal is connected to the gate of the third switch tube PM3; and the reference current is output to the drive current terminal through the third switch tube PM3.

2. The driving method for a Micro-LED display according to claim 1, wherein: If the driving unit receives a row signal, before setting the SEL signal to a high level, it also includes: The number of cycles of the clock signal CLK is counted by a counter; when the count value is greater than 2, the control signal SEL is set to a high level.

3. The driving method for a Micro-LED display according to claim 2, wherein: Also includes: The drive unit synchronizes the rising edge of the clock CLK through the CLK_PWM signal; When the rising edge of the CLK_PWM signal coincides with the rising edge of the synchronous clock CLK, the preset low level is transmitted to the D flip-flop, and a low level is output at the output terminal Q of the D flip-flop, thereby turning off the third switch PM3 and stopping the output of the driving current; Setting the control signal SELB to a low level, synchronizing the clock signal CLK1 with the input clock CLK, and setting the output terminals of the first register and the second register to a high level; Through multiple D flip-flops connected in series, the grayscale data stored in the second-stage flip-flops are read and transmitted in sequence according to the clock signal CLK, and the grayscale data is converted into a PWM signal output through a counter.

4. The driving method for a Micro-LED display according to claim 3, wherein: Generate PWM signal according to grayscale data, including: The driving unit sets the control signal SEL to a high level and SELB to a low level to synchronize the clock signal CLK1 with CLK; at the same time, the data output terminals of the first register and the second register are set to a high level; Starting from the first D flip-flop, at each rising edge of the clock signal CLK1: The output terminal Q of the previous level D flip-flop is used as the data input terminal of the current level D flip-flop, and the level state of the input terminal of the current level D flip-flop is transferred to the output terminal Q as the data input terminal of the next level D flip-flop; And so on until the last stage of D flip-flop, the PWM signal is output through the output terminal Q of the last stage of D flip-flop.

5. The driving method for Micro-LED display according to claim 4, characterized in that: The default protocol is QSPI protocol.

6. The driving method for a Micro-LED display according to claim 5, wherein: The number of flip-flops connected in series corresponds one to one to the number of bits of the grayscale data.

7. The driving method for Micro-LED display according to claim 6, characterized in that: In each driving unit, the row signal, grayscale data, reference current, and clock signal are received through independent input ports.

8. The driving method for Micro-LED display according to claim 7, wherein: The driving method further includes: By setting a temperature sensor on the Micro-LED, the temperature of different areas is collected, and the grayscale data of different areas of the Micro-LED is adjusted according to the temperature.

9. A driver chip for Micro-LED display, characterized in that: include: Multiple parallel driving units, each driving unit corresponds to a pixel point, and generates a driving current according to the grayscale data of the pixel point to drive the pixel point to emit light; wherein the multiple driving units form a pixel array, the multiple pixel arrays form a sub-region, and the multiple sub-regions form a display area; A row signal generating unit, generating a row signal and transmitting the row signal to a driving unit of each row; The data transmission unit transmits the grayscale data of each pixel to the corresponding driving unit through the QSPI protocol; A clock generation unit generates a clock signal CLK, a PWM control clock signal CLK_PWM, and a clock signal CLK1 synchronized with CLK, and transmits the clock signals to the driving unit respectively; a reference current generating unit, generating a constant reference current and transmitting the reference current to the driving unit; The temperature correction unit collects temperature data of the Micro-LED display area and corrects the grayscale data of different areas based on the temperature data; Each drive unit includes: The first register and the second register temporarily store grayscale data; The first switch transistor PM1, the second switch transistor PM2 and the third switch transistor PM3 control the output of the reference current; A counter for counting the clock signal CLK; Multiple D flip-flops connected in series, the number of which is the same as the number of bits of the grayscale data, convert the grayscale data into a PWM signal; Generating a driving current corresponding to the grayscale data also includes: Check whether the line signal is received: If no row signal is received, the control signal SELB is set to a high level, the grayscale data is written into the first register and the second register, and the output end of the register is set to a high level or a low level according to the grayscale data; wherein the first register and the second register are used to sample the grayscale data and send it to the set end and the reset end of the second-stage trigger; If a row signal is received, the control signal SEL is set to a high level, and the SET signal is briefly set to a low level, controlling the first switch tube PM1 to be turned off and the second switch tube PM2 to be turned on, so that the bias signal is connected to the gate of the third switch tube PM3; and the reference current is output to the drive current terminal through the third switch tube PM3.

Images