Low dropout linear regulator

Abstract

This invention discloses a low-dropout linear regulator, comprising: a first power transistor connected between a power supply terminal and a feedback node; a second power transistor connected between a power supply terminal and an output node, the output node being used to provide an output voltage to an external load; an error amplifier connected to the feedback node to receive a feedback voltage, used to drive the first and second power transistors based on a comparison between the feedback voltage and a reference voltage; and a feedback clamping circuit connected to the feedback node and the output node, used to clamp the feedback voltage and the output voltage to be equal. In the low-dropout linear regulator of this invention, the first power transistor can operate in a low-current and small-bandwidth state to save static power consumption and reduce the complexity of the compensation circuit, thereby improving loop stability while reducing the circuit's static current, which helps to improve circuit efficiency.

Description

Technical Field

[0001] This invention relates to the field of power supply technology, and more specifically to a low dropout linear regulator. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in power management ICs (PMICs) of portable electronic devices such as smartphones, tablets, and wearable devices. With technological advancements, these devices place increasingly higher demands on power management chips, requiring both high efficiency to extend battery life and low quiescent current to reduce standby power consumption. Furthermore, the complexity and versatility of portable electronic devices necessitate that LDOs possess excellent compensation capabilities to ensure stability under various load conditions.

[0003] Figure 1 A schematic circuit diagram of a conventional low-dropout linear regulator is shown. (e.g.) Figure 1 As shown, the low-dropout linear regulator 100 includes a power transistor Q1, an error amplifier EA, and a compensation circuit 110. The power transistor Q1 is the main output transistor of the chip, connected in the current conduction path between the input voltage Vin and the output voltage Vout. The inverting input of the error amplifier EA receives a reference voltage VREF, and the non-inverting input is connected to the output voltage Vout. The output of the error amplifier EA is connected to the control terminal of the power transistor Q1. The error amplifier EA is mainly used to obtain the difference between the output voltage Vout and the reference voltage VREF, and to control the conduction state of the power transistor Q1 based on this difference, thereby achieving negative feedback closed-loop regulation of the output voltage. The compensation circuit 110 is connected between the input voltage Vin and the output of the error amplifier EA, used to adjust the system's frequency response, increase the phase margin, and thus improve the system's loop stability.

[0004] See Figure 1The existing low-dropout linear regulator 100 has an on-chip dominant pole wp = 1 / (R1*Cc), an on-chip dynamic zero wz = 1 / (Rc*Cc), and an output pole wo = 1 / (Ro*Co), where R1 is the output impedance of the error amplifier EA, Rc is the resistance value of the dynamic compensation resistor in the compensation circuit 110, Cc is the capacitance value of the compensation capacitor in the compensation circuit 110, Ro is the output current impedance, and Co is the capacitance value of the output capacitor. In traditional designs, the general compensation approach is to let the on-chip dynamic zero wz of the LDO compensate for the output node wo; the closer the two are, the more stable the system. However, when the output capacitor Co has a wide range (e.g., 1–10μF) or a large load current range (0–300mA), the variation range of the output pole wo becomes very large. In this case, to achieve a better compensation effect, the compensation circuit 110 often needs to be designed to be more complex and consumes more static power.

[0005] Therefore, traditional LDO designs have certain limitations in reducing quiescent current and improving loop stability. Improving loop stability can lead to excessively high quiescent current, which in turn increases standby power consumption and shortens battery life. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a low-dropout linear regulator that can improve loop stability while reducing the circuit's quiescent current, thereby contributing to improved circuit efficiency.

[0007] According to one aspect of the present invention, a low dropout linear regulator is provided, comprising: a first power transistor connected between a power supply terminal and a feedback node; a second power transistor connected between the power supply terminal and an output node, the output node being used to provide an output voltage to an external load; an error amplifier connected to the feedback node to receive a feedback voltage, used to drive the first power transistor and the second power transistor according to a comparison result of the feedback voltage and a reference voltage; and a feedback clamping circuit connected to the feedback node and the output node, used to clamp the feedback voltage and the output voltage to be equal.

[0008] Optionally, the aspect ratio of the second power transistor is greater than that of the first power transistor.

[0009] Optionally, it further includes: a buffer, wherein the output of the error amplifier is connected to the input of the buffer and the control terminal of the first power transistor, and the output of the buffer is connected to the control terminal of the second power transistor.

[0010] Optionally, the feedback clamping circuit includes: a first transistor, a first terminal of which is connected to the feedback node; a second transistor, a first terminal of which is connected to the output node, and a control terminal of the first transistor connected to the control terminal and the second terminal of the second transistor; a third transistor, a first terminal and a control terminal of which are connected to the second terminal of the first transistor, and the second terminal of the third transistor is connected to ground; and a fourth transistor, a first terminal of which is connected to the second terminal of the second transistor, a control terminal of which is connected to the control terminal of the third transistor, and the second terminal of the fourth transistor is connected to ground.

[0011] Optionally, it also includes a bias current source connected between the first terminal of the third transistor and ground.

[0012] Optionally, it also includes a first compensation capacitor connected between the first terminal of the third transistor and ground.

[0013] Optionally, it further includes a compensation circuit connected between the power supply terminal and the output terminal of the error amplifier, the compensation circuit being used to provide zero-point compensation.

[0014] Optionally, the compensation circuit includes a second compensation capacitor and a compensation resistor connected in series between the power supply terminal and the output terminal of the error amplifier.

[0015] Optionally, the compensation resistor is a dynamic resistor.

[0016] Optionally, the first transistor and the second transistor are both PMOS transistors, and the third transistor and the fourth transistor are both NMOS transistors.

[0017] In summary, the embodiments of the present invention provide a master-slave architecture LDO that uses a second power transistor to drive a large external current and a large capacitor, and uses a first power transistor for feedback loop control of the circuit. Therefore, the first power transistor can operate in a low current and small bandwidth state to save static power consumption and reduce the complexity of the compensation circuit. This can improve loop stability while reducing the static current of the circuit, which helps to improve circuit efficiency.

[0018] Furthermore, the LDO in this embodiment of the invention also employs a feedback clamping circuit to ensure that the bias states of the first power transistor and the second power transistor are completely consistent, ensuring that the operating conditions of the two power transistors are consistent, thereby making their current drive capability and voltage characteristics more matched, ensuring the accuracy of the output voltage, and helping to improve the overall performance and stability of the LDO.

[0019] Furthermore, the master-slave architecture LDO of this embodiment can also improve the transient response capability of the circuit. When the load current changes suddenly, the simultaneous response of the first power transistor and the second power transistor can stabilize the output voltage more quickly and reduce the sudden changes and noise of the output voltage. Attached Figure Description

[0020] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0021] Figure 1 A schematic circuit diagram of a conventional low-dropout linear regulator is shown.

[0022] Figure 2 A schematic circuit diagram of a low-dropout linear regulator according to an embodiment of the present invention is shown. Detailed Implementation

[0023] Exemplary embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts.

[0024] In this specification, it should be noted that similar reference numerals already used to denote similar parts in other figures are used for these elements whenever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are not related to the basic configuration of this disclosure will be omitted. The terminology described in this specification should be understood as follows.

[0025] The advantages and features of this disclosure, and its implementation methods, will be set forth through the embodiments described below with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, so as to fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0026] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings used to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the illustrated details. Similar reference numerals always denote similar elements. In the following description, detailed descriptions will be omitted where it would inevitably obscure the focus of this disclosure if a detailed description of a related known function or construction were to be determined.

[0027] As will be fully appreciated by those skilled in the art, the features of the various embodiments of this disclosure may be combined or integrated with each other in whole or in part, and may be interoperable and technically driven with each other in various ways. The embodiments of this disclosure may be performed independently of each other, or may be performed together in a mutually dependent relationship.

[0028] In this application, a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. When the MOS is in the on state, current flows from the first terminal to the second terminal. The first terminal, second terminal, and control terminal of a PMOS are the source, drain, and gate, respectively, and the first terminal, second terminal, and control terminal of an NMOS are the drain, source, and gate, respectively.

[0029] The following specific examples illustrate embodiments of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] Figure 2 A schematic circuit diagram of a low-dropout linear regulator according to an embodiment of the present invention is shown. See also Figure 2 The low dropout linear regulator 200 of the present invention includes a first power transistor Q1, a second power transistor Q2, an error amplifier EA, a buffer BUF, an output capacitor Co, a compensation circuit 210, and a feedback clamping circuit 220.

[0031] In this circuit, the first power transistor Q1 has its first terminal connected to the power supply terminal Vin, its second terminal connected to the feedback node A1, and its control terminal connected to the output terminal of the error amplifier EA. The second power transistor Q2 has its first terminal connected to the power supply terminal Vin, and its second terminal connected to the output node A2. Output node A2 provides the output voltage Vout and output current Io to the external load. The control terminal of the second power transistor Q2 is connected to the output terminal of the buffer BUF. The output capacitor Co is connected between the output parasitic inductance Lo and ground, and is used to shape and filter the output voltage Vout.

[0032] In one exemplary embodiment, the first power transistor Q1 and the second power transistor Q2 are PMOS transistors. Of course, this invention is not limited to this; in other embodiments, the first power transistor Q1 and the second power transistor Q2 may also be other types of transistors, such as NMOS transistors, NPN Darlington transistors, and NPN bipolar transistors.

[0033] Error amplifier EA has a non-inverting input, an inverting input, and an output. The inverting input of error amplifier EA is used to receive the reference voltage VREF. The non-inverting input of error amplifier EA is connected to the feedback node A1 to receive the feedback voltage VFB. The output of error amplifier EA is connected to the control terminal of the first power transistor Q1 and the input terminal of the buffer BUF.

[0034] The compensation circuit 210 is connected between the power supply terminal Vin and the output terminal of the error amplifier EA. The compensation circuit 210 is used to obtain an on-chip dynamic zero within the circuit to compensate for the frequency of the system. No matter how the output current Io changes, the unity-gain bandwidth clock of the system is within the set range, thereby obtaining a high phase margin and achieving high stability over a wide range of full loads.

[0035] Furthermore, the compensation circuit 210 includes a compensation capacitor Cc and a compensation resistor Rc connected in series between the power supply terminal Vin and the output terminal of the error amplifier EA. For example, the compensation resistor Rc is a dynamic resistor, and a dynamic zero point can be obtained within the circuit by adjusting the resistance value of the compensation resistor Rc.

[0036] The feedback clamping circuit 220 is connected to the feedback node A1 and the output node A2. It is used to clamp the feedback voltage VFB to be equal to the output voltage Vout, thereby clamping the drain voltage of the first power transistor Q1 and the drain voltage of the second power transistor Q2 to be equal. This ensures that the bias state of the second power transistor Q2 can completely follow the first power transistor Q1, ensuring that the operating conditions of the two power transistors are consistent. This makes their current drive capability and voltage characteristics more matched, which helps to improve the performance and stability of the entire LDO.

[0037] Further, the feedback clamping circuit 220 of this embodiment includes transistors MP1, MP2, MN1, and MN2. Transistors MP1 and MP2 are PMOS transistors, and transistors MN1 and MN2 are NMOS transistors. The first terminal of transistor MP1 is connected to feedback node A1, and the control terminal of transistor MP1 is connected to the control terminal and the second terminal of transistor MP2. The first terminal of transistor MP2 is connected to output node A2. The control terminal and the first terminal of transistor MN1 are connected to the second terminal of transistor MP1. The first terminal of transistor MN2 is connected to the second terminal of transistor MP2, and the control terminal of transistor MN2 is connected to the first terminal and the control terminal of transistor MN1. The second terminals of transistors MN1 and MN2 are connected to ground. In this embodiment, transistors MP1, MP2, MN1, and MN2 constitute a feedback sampling current mirror, which clamps the voltage of feedback node A1 to be equal to the voltage of output node A2.

[0038] Furthermore, the low-dropout linear regulator 200 also includes a bias current source Ibias and a compensation capacitor Cm connected together. The bias current source Ibias is connected between the first terminal of transistor MN1 and ground to provide bias current for the first power transistor Q1. The compensation capacitor Cm is connected between the first terminal of transistor MN1 and ground to provide load capacitance for the first power transistor Q1.

[0039] In this embodiment, the error amplifier EA and the first power transistor Q1 constitute the feedback control loop of the low-dropout linear regulator 200. Since the output voltage Vout and the feedback voltage VFB are clamped to be equal by the feedback clamping circuit 220, the output voltage Vout can be controlled through this feedback control loop. For example, this feedback control loop mainly compares the feedback voltage VFB with the reference voltage VREF through the error amplifier EA, and then controls the gate voltages of the first power transistor Q1 and the second power transistor Q2 based on the difference between them. The first power transistor Q1 is directly driven by the output of the error amplifier EA, and the second power transistor Q2 is driven by the signal amplified by the output of the error amplifier EA through the buffer BUF. For example, when a load change causes the output voltage Vout to drop, the feedback voltage VFB is also pulled down accordingly, thereby reducing the difference between the feedback voltage VFB and the reference voltage VREF. Therefore, the output of the error amplifier EA also decreases, which in turn increases the gate-source voltage difference between the first power transistor Q1 and the second power transistor Q2, increasing the output current Io, and consequently causing the output voltage Vout to rise to a normal voltage level.

[0040] It should be noted that, Figure 2 The control loop of the low-dropout linear regulator 200 shown is an exemplary circuit diagram. In other embodiments, a series voltage divider resistor can be added to the feedback node A1 to divide the voltage. Of course, other functional modules can also be added to the low-dropout linear regulator 200, and this embodiment does not limit this.

[0041] Furthermore, the aspect ratio of the second power transistor Q2 is greater than that of the first power transistor Q1. Therefore, the second power transistor Q2 can be used to drive large external currents and large capacitors, while the feedback control loop of the first power transistor Q1 can operate under low current and small bandwidth conditions. For example, the area ratio of the second power transistor Q2 to the first power transistor Q1 is N:1. When the circuit is operating, the load current of the first power transistor Q1 is Ibias + Io / N, where Io is the output current of the second power transistor Q2. Therefore, compared to the second power transistor Q2, the load current of the first power transistor Q1 is reduced by a factor of N. Thus, the first power transistor Q1 can operate under low current conditions, and since the load capacitance of the first power transistor Q1 is fixed (i.e., provided by the internal compensation capacitor Cm), a relatively simple compensation method can ensure the loop stability of the first power transistor Q1. Therefore, the LDO of this invention can save static power consumption and reduce the complexity of the compensation circuit, thereby improving loop stability while reducing the circuit's static current, which helps to improve circuit efficiency.

[0042] In summary, the embodiments of the present invention provide a master-slave architecture LDO that uses a second power transistor to drive a large external current and a large capacitor, and uses a first power transistor for feedback loop control of the circuit. Therefore, the first power transistor can operate in a low current and small bandwidth state to save static power consumption and reduce the complexity of the compensation circuit. This can improve loop stability while reducing the static current of the circuit, which helps to improve circuit efficiency.

[0043] Furthermore, the LDO in this embodiment of the invention also employs a feedback clamping circuit to ensure that the bias states of the first power transistor and the second power transistor are completely consistent, ensuring that the operating conditions of the two power transistors are consistent, thereby making their current drive capability and voltage characteristics more matched, ensuring the accuracy of the output voltage, and helping to improve the overall performance and stability of the LDO.

[0044] Furthermore, the master-slave architecture LDO of this embodiment can also improve the transient response capability of the circuit. When the load current changes suddenly, the simultaneous response of the first power transistor and the second power transistor can stabilize the output voltage more quickly and reduce the sudden changes and noise of the output voltage.

[0045] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0046] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating the present invention and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A low-dropout linear regulator, comprising: The first power transistor is connected between the power supply and the feedback node; The second power transistor is connected between the power supply terminal and the output node, which is used to provide output voltage to an external load. An error amplifier, connected to the feedback node to receive a feedback voltage, is used to drive the first power transistor and the second power transistor based on a comparison between the feedback voltage and a reference voltage. as well as A feedback clamping circuit, connected to the feedback node and the output node, is used to clamp the feedback voltage and the output voltage to be equal. The feedback clamping circuit includes: A first transistor, wherein a first terminal of the first transistor is connected to the feedback node; The second transistor has a first terminal connected to the output node, and the control terminal of the first transistor is connected to the control terminal and the second terminal of the second transistor. A third transistor, wherein a first terminal and a control terminal of the third transistor are connected to a second terminal of the first transistor, and the second terminal of the third transistor is connected to ground; and A fourth transistor, wherein the first terminal of the fourth transistor is connected to the second terminal of the second transistor, the control terminal of the fourth transistor is connected to the control terminal of the third transistor, and the second terminal of the fourth transistor is connected to ground. The low-dropout linear regulator also includes: A bias current source connected between the first terminal of the third transistor and ground; and A first compensation capacitor is connected between the first terminal of the third transistor and ground.

2. The low-dropout linear regulator according to claim 1, wherein, The width-to-length ratio of the second power transistor is greater than that of the first power transistor.

3. The low dropout linear regulator of claim 2, wherein, Also includes: The buffer is connected to the input of the error amplifier and the control terminal of the first power transistor, and the output of the buffer is connected to the control terminal of the second power transistor.

4. The low-dropout linear regulator according to claim 1, wherein, Also includes: A compensation circuit is connected between the power supply terminal and the output terminal of the error amplifier, the compensation circuit being used to provide zero-point compensation.

5. The low dropout linear regulator of claim 4, wherein, The compensation circuit includes a second compensation capacitor and a compensation resistor connected in series between the power supply terminal and the output terminal of the error amplifier.

6. The low dropout linear regulator of claim 5, wherein, The compensation resistor is a dynamic resistor.

7. The low dropout linear regulator of claim 1, wherein, The first transistor and the second transistor are both PMOS transistors, and the third transistor and the fourth transistor are both NMOS transistors.

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