Compilation method, device, equipment and storage medium

Abstract

The present application discloses a compilation method, apparatus, device, and storage medium, belonging to the field of compilers. The method includes: loop unrolling an instruction sequence in a loop block (BB) to generate a triple BB and a triple DAG corresponding to the triple BB; the triple BB includes an instruction sequence that loops three times; the triple DAG is used to indicate the data dependencies between the instructions in the triple BB; window scheduling is performed based on the triple BB to determine a target scheduling window; the window scheduling is used to split the instruction sequence in the loop block into two parts based on the scheduling window; the target scheduling window is a scheduling window whose execution time meets a time condition, and the execution time is the time required to execute instructions within the window calculated based on the data dependencies in the triple DAG; and based on the scheduling result corresponding to the target scheduling window, the target code of the loop block in the target program is compiled. The above method can improve the compilation and execution efficiency of the loop block.

Description

Technical Field

[0001] The present application relates to the field of compilers, and in particular to a compilation method, apparatus, device, and storage medium. Background Art

[0002] In recent years, the rapid development of artificial intelligence (AI) has brought revolutionary technological changes to many fields, such as natural language processing, computer vision, e-commerce, smart cities, and drug research and development.

[0003] To build a complete application ecosystem, it is necessary to design and develop a supporting AI toolchain, of which the AI ​​compiler is a key component. The AI ​​compiler compiles the AI ​​model's algorithm into executable machine code, generating a target program that can run on the AI ​​chip based on the AI ​​model's program.

[0004] However, the basic computing unit operators of AI models contain a large number of loop instruction structures, which consume a large portion of the AI ​​chip's execution time. To reduce the execution time of loop instruction structures, soft pipelining optimization was introduced to optimize the compilation algorithm for loop instruction structures. Summary of the Invention

[0005] This application provides a compilation method, apparatus, device, and storage medium. The method provides a soft pipelining algorithm that can improve the compilation and execution efficiency of loop BBs. The technical solution includes the following contents.

[0006] According to one aspect of the present application, a compilation method is provided, which includes the following steps.

[0007] Loop-unrolling an instruction sequence in a loop BB (Basic Block) to generate a triple BB and a triple DAG (Directed Acyclic Graph) corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is used to indicate data dependencies between instructions in the triple BB;

[0008] Window scheduling is performed based on the triple BB to determine a target scheduling window; the window scheduling is used to split the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required to execute instructions in the window calculated based on the data dependency relationship in the triple DAG;

[0009] According to the scheduling result corresponding to the target scheduling window, the target code of the loop BB in the target program is compiled.

[0010] According to another aspect of the present application, a compilation device is provided, which includes the following modules.

[0011] a loop module, configured to loop-unroll an instruction sequence in a loop basic block BB to generate a triple BB and a triple directed acyclic graph (DAG) corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; and the triple DAG indicates data dependencies between instructions in the triple BB;

[0012] a scheduling module configured to perform window scheduling based on the triple BB and determine a target scheduling window; the window scheduling is configured to split the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second instruction sequence in the current loop is executed synchronously with the first instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time satisfies a time condition, and the execution time is the time required to execute instructions within the window, calculated based on data dependencies in the triple DAG;

[0013] The compiling module is used to compile the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0014] According to one aspect of the present application, a computer device is provided, comprising: a processor and a memory, wherein the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the above compilation method.

[0015] According to another aspect of the present application, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the above compilation method.

[0016] According to another aspect of the present application, a computer program product or computer program is provided, the computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the above-mentioned compilation method.

[0017] The beneficial effects brought about by the technical solutions provided in the embodiments of the present application include at least the following.

[0018] A soft pipelining algorithm is provided for compiling loop blocks in AI models. A window scheduling algorithm is used to split the loop block into two parts, allowing the instructions in the first part of the next loop to execute synchronously with the instructions in the second part of the current loop, saving instruction execution time. To find the optimal split position and minimize execution time, the loop block is replicated three times to create a triple loop block and a triple DAG. Multiple scheduling windows are then tested on the triple loop block. The scheduling window is used to select the instructions in the second part of the first loop block and the instructions in the second loop block. The execution time required for the two parts of the instructions in each scheduling window to execute synchronously is calculated based on the data dependencies of the instructions indicated in the triple DAG. The scheduling window with the shortest execution time is then selected from the multiple scheduling windows as the final target scheduling window. The split position corresponding to the target scheduling window is the optimal split position. Compiling the loop block according to the scheduling results from the target scheduling window improves loop block compilation efficiency and minimizes the execution time of the compiled target program's target code. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a schematic diagram of the processing process of the AI ​​compiler provided by one embodiment of the present application;

[0021] Figure 2 is a schematic diagram of pseudo code of a table scheduling algorithm provided by one embodiment of the present application;

[0022] Figure 3 is a schematic diagram of a modular scheduling algorithm provided by one embodiment of the present application;

[0023] Figure 4 This is a flowchart of a modular scheduling algorithm provided by one embodiment of the present application;

[0024] Figure 5 is a schematic diagram of a window scheduling algorithm provided by an embodiment of the present application;

[0025] Figure 6 This is a flowchart of a window scheduling algorithm provided by one embodiment of the present application;

[0026] Figure 7 is a schematic diagram of a window scheduling algorithm provided by an embodiment of the present application;

[0027] Figure 8This is a schematic diagram of a compilation method provided by an embodiment of the present application;

[0028] Figure 9 This is a flowchart of a compilation method provided by an embodiment of the present application;

[0029] Figure 10 This is a flowchart of a compilation method provided by an embodiment of the present application;

[0030] Figure 11 This is a flowchart of a compilation method provided by an embodiment of the present application;

[0031] Figure 12 This is a flowchart of a compilation method provided by an embodiment of the present application;

[0032] Figure 13 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0033] Figure 14 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0034] Figure 15 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0035] Figure 16 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0036] Figure 17 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0037] Figure 18 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0038] Figure 19 This is a schematic diagram of a specific compilation example provided by an embodiment of the present application;

[0039] Figure 20 This is an application diagram provided by an embodiment of the present application;

[0040] Figure 21 This is a schematic diagram of the application effect provided by an embodiment of the present application;

[0041] Figure 22 is a schematic diagram of a terminal device provided by an embodiment of the present application;

[0042] Figure 23 This is a flowchart of a compilation method provided by an embodiment of the present application;

[0043] Figure 24 This is a flowchart of a compilation method provided by an embodiment of the present application;

[0044] Figure 25 This is a structural block diagram of a compilation device provided by an embodiment of the present application;

[0045] Figure 26 This is a structural block diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0047] First, a brief introduction is given to the terms involved in the embodiments of this application.

[0048] AI refers to technologies that can represent human intelligence through ordinary computer programs. AI is a new technical science that studies and develops theories, methods, techniques, and application systems for simulating, extending, and expanding human intelligence.

[0049] Artificial Intelligence (AI) refers to the theories, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a comprehensive technology within computer science that seeks to understand the essence of intelligence and produce new intelligent machines that can respond in a manner similar to human intelligence. AI also involves studying the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making.

[0050] Artificial intelligence (AI) technology is a comprehensive discipline encompassing a wide range of fields, encompassing both hardware and software technologies. Foundational AI technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, big data processing, pre-trained models, operating / interaction systems, and mechatronics. Pre-trained models, also known as large models or basic models, can be fine-tuned and widely applied to downstream tasks across various AI disciplines. AI software technologies primarily encompass computer vision, speech processing, natural language processing, and machine learning / deep learning.

[0051] With the research and progress of artificial intelligence technology, artificial intelligence technology has been studied and applied in many fields, such as common smart homes, smart wearable devices, virtual assistants, smart speakers, smart marketing, unmanned driving, autonomous driving, drones, digital twins, virtual humans, robots, artificial intelligence generated content (Artificial Intelligence Generated Content, AIGC), conversational interaction, smart medical care, smart customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0052] Operator: Operator is the basic computing unit of machine learning models.

[0053] Software Pipelining: It is a type of loop instruction scheduling algorithm in the compiler field.

[0054] Modulo Scheduling: It is a classic soft-pipeline algorithm in the field of compilers.

[0055] List Scheduling: It is a type of non-loop instruction scheduling method in the compiler field and is the basic scheduling algorithm in the compiler.

[0056] Basic Block (BB): In the compiler, a block represents a linearly executed instruction. A BB has a single entry instruction and a single exit instruction. The compiler breaks down a program into a combination of basic blocks.

[0057] DAG (Directed Acyclic Graph): A directed graph is considered a directed acyclic graph if there are no edges from any vertex back to that vertex. In this application, a DAG is used to indicate dependencies between instructions. For example, if instruction A generates data and passes it to instruction B via a register, then in the DAG, there is a directed edge from node A to node B. The weight of this directed edge is the minimum number of ticks (delay) between instruction A emitting the data and passing it to instruction B.

[0058] II (Initiation Interval): refers to the time difference between the start of execution of the corresponding instructions of two loops in modular scheduling.

[0059] Heuristic Algorithms: In contrast to optimization algorithms, heuristic algorithms do not mathematically solve optimization problems. Instead, they are constructed based on intuition or experience and are widely used in the compiler field. This application uses a heuristic method to find a set of offset positions for the scheduling window.

[0060] Stall cycle: This refers to the number of processor cycles during which pipeline execution is paused due to data or resource conflicts. In window scheduling, the number of stall cycles introduced between cycles must be calculated for each table scheduling result.

[0061] AI compiler: A domain-specific compiler that converts machine learning models in different formats into compiler intermediate representation (IR) and optimizes it, ultimately generating executable code for the corresponding hardware platform. AI compilers typically use a classic front-end and back-end structure to connect the model generated by the machine learning framework with the underlying chip. The overall structure of the AI ​​compiler is as follows: Figure 1 shown.

[0062] exist Figure 1 In the process, the AI ​​compiler reads the machine learning model 101 generated from machine learning frameworks such as TensorFlow and Pytorch. The AI ​​compiler first performs model parsing 102 on the front end of the model 101, parsing it into a high-level IR (Intermediate Representation) (usually a computational graph), and then performs target-independent optimization (optimization independent of the target hardware) 103, such as arithmetic simplification, operator fusion, etc., and outputs the optimized high-level IR. Next, it enters the target-dependent optimization 104 on the back end, such as dedicated instruction mapping, memory allocation, memory access latency hiding, etc., and outputs device-dependent low-level IR; finally, it enters the code generation stage 105 on the back end to generate a target program 106 that can run on the AI ​​chip.

[0063] The compilation method provided in this application is in the code generation stage 105 in the AI ​​compiler.

[0064] During the code generation phase, the AI ​​compiler divides the acquired high-level computer language code into multiple basic blocks (BBs), which are linear segments of program code. For each BB, the compiler schedules the code within it, generating an instruction sequence. The compiler then packages the instructions within the sequence, generating multiple instruction packets. Each instruction packet is then converted into a series of binary data of fixed or variable length. These converted instruction packets are then sent to the hardware (AI chip) for execution, completing the BB compilation process. The AI ​​chip processes one instruction packet in parallel per clock cycle.

[0065] Instruction Scheduling: Instruction scheduling reorders the order in which instructions are issued, increasing the parallelism of instruction execution and reducing the total execution time of operators. Instruction scheduling is subject to various constraints when selecting instructions, such as instruction dependencies, hardware resources, and registers. The primary goal of instruction scheduling is to minimize pipeline stalls and find the optimal solution within these constraints.

[0066] Instruction scheduling optimization algorithms include table scheduling algorithm, modulo scheduling algorithm and window scheduling algorithm.

[0067] Table scheduling is a method of adjusting the order of instructions based on a greedy algorithm and a heuristic algorithm. The algorithm uses basic blocks as the base interval and continuously selects and adjusts the order of instructions within this range based on conditions such as instruction dependencies and hardware resource usage. Figure 2 The pseudo code of the table scheduling algorithm provided by the related art is shown.

[0068] exist Figure 2 In the code, Op represents an instruction, and D represents a directed acyclic graph of instruction dependencies, D = (N, E), where N is a node representing an instruction; E is an edge representing the minimum distance between two nodes. The variable Cycle is the simulated hardware clock cycle, initialized to 1, and incremented during code execution. Whenever Cycle+1 occurs, all instructions completed by the previous Cycle are deleted from the Active list, and each successor node of these instructions in D is checked, and the available instructions are moved to the Ready list. The Ready list contains all instructions that can be used in the current Cycle without affecting the correctness of continuous execution, and is initialized to all child nodes of the parent node in D. The Active list contains all instructions that can actually be emitted at the moment.

[0069] The module scheduling algorithm is a soft pipelining algorithm. In the code generation process of the AI ​​compiler backend, soft pipelining is an important optimization stage. As the operator of the basic computing unit of the AI ​​model, there are a large number of loop instruction structures, which consume the main chip execution time. Soft pipelining optimization is a type of compilation algorithm specifically used to optimize loop instruction structures. The mainstream soft pipelining optimization algorithm in the industry is the module scheduling algorithm. Its main algorithm ideas are as follows: Figure 3 shown.

[0070] exist Figure 3 In the example, assume that the total number of loops of a loop instruction structure is N. The instruction sequence in its core loop takes T beats per loop, where T can be divided into 3 equal segments. Figure 3In part (A), each loop starts after the previous loop is completed. Each loop is represented by I(n), where n∈[0, 1, 2, ..., N-2, N-1]. For a loop, each equally divided code segment is represented by S(n). Figure 3 Each code segment is divided into 3 segments, namely n∈[0, 1, 2]. The code after modular scheduling is as follows Figure 3 As shown in part (B), the instructions of loop I(n+1) can start executing in advance without waiting for loop I(n) to complete. The time difference between the start of I(n) and I(n+1) is called the start interval II. II is equal to the number of beats a section of code occupies in one loop. Figure 3 In part (B) of , II = T / 3. Analyzing the folded loop, we can find that there is a stable code structure, such as Figure 3 As shown in part (C), Figure 3 Part (C) is the code structure after modular scheduling. It consists of three phases: the fill phase, which includes the code at the beginning of the first two loops; the core phase, which includes the code for three consecutive loops; and the drain phase, which includes the code at the end of the last two loops.

[0071] For a specific instruction in a loop, if it issues on beat K relative to the first instruction in that loop, then its issue time in the folded core phase is T = K mod II. This is the origin of the name modulo scheduling. For example, if instruction A before folding issues on beat 16 relative to the first instruction in the loop, and II is 10 beats, then after folding, instruction A will issue on beat 6, and the core loop execution time will also be compressed to 10 beats.

[0072] The basic algorithm flow of modular scheduling is as follows Figure 4 shown.

[0073] Step 401, start.

[0074] Step 402: Construct a directed acyclic graph (DAG). A DAG (directed acyclic graph) is constructed based on the input instructions. The DAG is used to represent the dependency relationship between instructions.

[0075] Step 403: Calculate scheduling parameters, such as the initial and maximum values ​​of the start interval, the depth and height of nodes in the DAG graph, etc.

[0076] Step 404: Sort the instructions. Adjust the scheduling order of the instructions based on the node-related parameters calculated in step 403.

[0077] Step 405: traverse the start intervals in sequence, starting from the initial start interval, and try to find a reasonable scheduling result in sequence until the start interval reaches the maximum value.

[0078] Step 406: Use a search algorithm to traverse the instructions and calculate the scheduling result. Search each instruction in order to see if it can be successfully scheduled, that is, if the instruction does not have resource conflicts or unreasonable dependencies with the scheduled instructions.

[0079] Step 407: Determine whether to stop searching. If yes, go to step 408; if not, go back to step 405.

[0080] Step 408: Determine whether the scheduling is successful. If the scheduling is successful, execute step 409; if the scheduling is unsuccessful, execute step 410.

[0081] Step 409: Adjust the code. If the scheduling is successful, a complete code structure is generated according to the scheduling result, including the filling stage, the core stage, and the emptying stage.

[0082] Step 410: End. Scheduling fails, and the original code remains unchanged.

[0083] Window scheduling is also a soft pipelining algorithm. Compared to modular scheduling, it has a high scheduling success rate and guaranteed performance in AI accelerator architectures with high resource conflicts.

[0084] like Figure 5 As shown in (A) in the figure, assuming that loop BB has M instructions, and the window scheduler selects an offset position K to establish a scheduling window, the scheduling window contains MK instructions in cycle n-1 and K instructions in cycle n. These instructions in the scheduling window are table-scheduled. If the execution time of the scheduled instructions is the shortest, the current scheduling result is the optimal result. Finally, after traversing all offset positions, as shown in Figure 5 As shown in (B) in the figure, the final code including prolog (filling stage), kernel (core stage) and epilog (emptying stage) is generated according to the optimal window offset position.

[0085] In an optional embodiment, the window scheduling algorithm process is as follows: Figure 6 As shown, the method includes the following steps.

[0086] Step 501: Back up the original BB (circular BB).

[0087] Step 502: Make two copies of the original BB to generate a DoubleBB (twice the BB), and establish a DoubleDAG (twice the DAG).

[0088] Step 503: Starting from the first instruction of DoubleBB, the scheduling window is moved one by one.

[0089] Step 504: After the scheduling window is moved, the instruction that was moved out of the scheduling window is added to the end of the original DoubleDAG to update the DoubleDAG. For example, if the first instruction in the previous scheduling window was instruction A, then after the scheduling window is moved, instruction A will be added to the end of the DoubleDAG to update the DoubleDAG.

[0090] Step 505: Perform table scheduling within the scheduling window to obtain a scheduling result of the table scheduling.

[0091] Step 506: Analyze and update the scheduling result of the table scheduling, and calculate the added stall cycle according to the scheduling result.

[0092] Step 507: If the scheduling result of the current table scheduling does not exceed the limit and the scheduling window is not traversed completely, return to step 503.

[0093] Step 508: Determine whether the scheduling result is reasonable, including whether the performance after scheduling meets the requirements.

[0094] Step 509: If the scheduling result is reasonable, the code structure is expanded to finally include prolog (filling), kernel (core) and epilog (emptying).

[0095] Step 510: Otherwise, restore the original BB state before scheduling.

[0096] From the perspective of algorithm performance, window scheduling can be equivalent to a modular scheduling algorithm that is fixedly divided into two segments. This is the basis for window scheduling to improve instruction-level parallelism and achieve better performance.

[0097] Modulo scheduling algorithms typically use a greedy algorithm to search for instruction schedules. Given an II, the algorithm sequentially attempts to schedule all instructions between times 0 and (II-1). Modulo scheduling succeeds if all instructions can be dispatched at such times that all data dependencies between them are satisfied and the hardware resources used by the instructions do not conflict.

[0098] The problem with modular scheduling is that as the number of instructions to be scheduled increases and resource conflicts between instructions increase, the greedy algorithm's search capabilities are insufficient, often failing to schedule successfully. Using more complex search algorithms, such as backtracking, increases algorithm complexity exponentially, and the compilation process often fails due to excessive time consumption.

[0099] For AI accelerators, hardware instructions are often complex, sharing many hardware resources, making conflicts very likely. Furthermore, instruction execution takes a long time, often requiring more than 10 cycles to output a result, further increasing the difficulty of scheduling algorithms. Therefore, using modular scheduling in AI accelerator operator development often results in scheduling failures.

[0100] Because modulo scheduling is prone to failure, we attempted to use the aforementioned window scheduling in the AI ​​compiler. Window scheduling effectively addresses the issue of modulo scheduling failures, as the table scheduling algorithm used by window scheduling when traversing offsets consistently produces a scheduling result, and the performance difference is comparable to that of modulo scheduling.

[0101] However, window scheduling is also a complex scheduling algorithm. The above window scheduling method has two problems:

[0102] Problem (1) After the scheduling window is moved, the DoubleDAG needs to be updated. To establish the dependency between instructions in two cycles, two copies of the instructions need to be copied from the original BB to create a new BB (DoubleBB). Then, a DAG is created for this new BB, which is called DoubleDAG, to describe the dependency between instructions in the scheduling window. Each time the scheduling window is moved, the instructions before the scheduling window offset position need to be connected to the end of the DoubleDAG, that is, the DoubleDAG needs to be updated synchronously to ensure that the DoubleDAG contains the dependency of all instructions in the scheduling window.

[0103] The main purpose of updating the DoubleDAG is that by folding the instruction nodes before the scheduling window to the nodes below the DoubleDAG, the compiler can establish dependencies between instructions that are defined across loops and use the same registers.

[0104] like Figure 7 As shown, the shaded portion represents the scheduling window 107. When the scheduling window 107 moves to Figure 7 When the position in the scheduling window 107 is reached, all instructions before the scheduling window 107 (including instruction B') need to be moved from their original position in the DoubleDAG to the new position below the DoubleDAG. Note that no instruction movement actually occurs here, only the DoubleDAG is updated. At this time, instruction A and instruction B' have a new direct data dependency relationship, and instruction B and instruction B' correspond to the same instruction, so their emission time is the same. At this time, the data dependency relationship between instruction A and instruction B' can be used to determine the data dependency relationship between instruction A and instruction B, and then determine the stall cycle (pause time) that needs to be added after the table scheduling is completed.

[0105] The calculation formula for Stall Cycle (pause time) is as follows:

[0106] Stall Cycle=DefCycle+Latency(A,B)-MaxCycle-UseCycle

[0107] Where DefCycle is the time instruction A is issued; Latency(A,B) is the delay between the data output by instruction A and the input to instruction B; MaxCycle is the time when all instructions in the scheduling window have completed execution; and UseCycle is the time instruction B is issued. This formula means that if instruction A outputs data in the current cycle and the latency relationship is not met for instruction B in the next cycle, additional stall cycles are required.

[0108] For example, according to Figure 7 , then before executing instruction B of the second loop, it is necessary to ensure that instruction A' of the first loop is executed and the data reaches instruction B (that is, the emission time of instruction A' of the first loop plus the delay time of instruction A' must be before the emission time of instruction B of the second loop). If this relationship is not satisfied, it is necessary to increase the stall cycle to increase the execution time of the scheduling window, thereby delaying the start time of instruction B of the second loop, to ensure that the data of instruction A' of the first loop can be passed to instruction B of the second loop.

[0109] In the above process, appending an instruction to the lower part of DoubleDAG requires complex graph operations and a large amount of computation.

[0110] Problem (2) Moving the window instruction by instruction is inefficient. Although the aforementioned window scheduling algorithm includes Limit for early exit, the window movement process is still performed instruction by instruction. In actual applications, this is still very time-consuming, and the difference between two adjacent offset instructions is often not significant. Therefore, the search efficiency of the instruction-by-instruction sliding window is low.

[0111] In order to solve the above problem (1), this application proposes a TripleDAG method.

[0112] like Figure 8 As shown in the figure, TripleBB and its corresponding TripleDAG are established before instruction scheduling. During the sliding scheduling window, there's no need to adjust or update the TripleDAG because all dependencies are already built within it. Therefore, the stall cycles introduced by instructions A and B can be directly calculated, avoiding the need to update the DAG during scheduling.

[0113] For example, Figure 8 As shown, the shaded portion represents the scheduling window 107. When the scheduling window 107 moves to Figure 8 When the position in the scheduling window is determined, the data dependencies of all instructions within the scheduling window must be obtained to calculate the stall cycle. At this point, the data dependency of instructions A and B' can be directly determined based on the data dependency of instructions A and B' in the TripleDAG, given that instructions B and B' correspond to the same instruction and have the same issuance time. Furthermore, based on the data dependency of instructions A and B, the stall cycle (pause time) required after table scheduling is completed is determined.

[0114] As can be seen, because TripleDAG already contains the data dependency relationship between instructions A and B, there is no need to update TripleDAG after each scheduling window movement. The data dependency relationship between instructions A and B can be directly queried from TripleDAG, and then the data dependency relationship between instructions A and B can be determined. This greatly reduces the amount of computation and improves the computational efficiency of the stall cycle.

[0115] The loop in the operator is usually expanded 4 or 8 times, and the number of instructions is usually 100 to 200. At this time, the efficiency of moving the scheduling window instruction by instruction is very low, and because there are a large number of repeated instructions, the scheduling results of two adjacent windows are often the same or very different. Therefore, in order to solve the above problem (2), this application uses a different heuristic method to provide a more efficient search offset position. This application uses a heuristic algorithm with adaptive step size based on statistical results:

[0116] (1) When the number of instructions to be scheduled (the total number of instructions in the loop BB) is less than or equal to M, the offset step size of the scheduling window is adjusted to 1;

[0117] (2) When the number of instructions to be scheduled is greater than M and less than or equal to 2M, the offset step size of the scheduling window is adjusted to 2;

[0118] (3) When the number of instructions to be scheduled is greater than 2M and less than or equal to 3M, the offset step size of the scheduling window is adjusted to 4;

[0119] (4) When the number of instructions to be scheduled is greater than 3M and less than or equal to 4M, the offset step size of the scheduling window is adjusted to 6;

[0120] (5) When the number of instructions to be scheduled is greater than 4M, the offset step size of the scheduling window is adjusted to 8.

[0121] After testing, it was found that when an appropriate value of M was selected, the compilation speed increased by more than 50% to 60%, and the performance degradation did not exceed 5%.

[0122] The method provided in this application can be used in an AI compiler toolchain, located in the backend code generation module of the AI ​​compiler. Typical application scenarios include AI compilers used with AI chips. This method can significantly accelerate the compilation time of operator core loops.

[0123] In addition, the method provided in this application can also be used in traditional compilers to speed up the compilation time of the core loop generated by the compiler backend.

[0124] like Figure 9 As shown, the input of this system is the instruction sequence in the loop core BB (loop BB) 108. The loop core BB 108 must meet the following constraints: the loop body consists of only one BB and not multiple BBs; the number of instructions in the BB is within a certain range; and the BB should not contain assembly or other side-effect instructions (such as modifying the predetermined state of the machine).

[0125] The fast window scheduler 109 is the core facility of this application. It schedules the input instructions based on the input loop core instruction sequence using the window scheduling algorithm provided by this application. It requires the establishment of auxiliary data structures such as TripleBB and TripleDAG, and uses heuristic algorithms to improve window traversal efficiency. This reduces the compilation time of window scheduling while ensuring the performance of generated code.

[0126] The instruction scheduling result 110 generated by the fast window scheduler 109 includes the scheduled instruction, the time when the instruction is issued, the stage to which the instruction belongs, the optimal II obtained by scheduling, and the offset step of the corresponding scheduling window.

[0127] The soft-pipelined instruction expander 111 is typically a basic module provided by the compiler. It uses the instruction scheduling results 110 to first generate the core BB (execution time II) after window scheduling. It then adds the logic for the prologue (filling) and epilogue (draining) parts, ultimately generating the correct soft-pipelined code.

[0128] This application is for Figure 6 The DoubleBB window scheduling algorithm shown in the figure is improved. The main process is as follows Figure 10 As shown, Figure 6 The main differences of the method shown are step 602, step 603 and step 605. The method comprises the following steps.

[0129] Step 601: Back up the original BB to OriBB.

[0130] Step 602: Copy the backup OriBB three times to generate a new TripleBB and generate a corresponding TripleDAG.

[0131] Step 603: Obtain a set of window offset values ​​using a heuristic algorithm; extract a window offset value and obtain a scheduling window on TripleBB accordingly.

[0132] Step 604: Use table scheduling to schedule the instructions in the scheduling window. Table scheduling is a basic functional module provided by the compiler.

[0133] Step 605: Analyze the scheduling result of the table scheduling using TripleDAG, and store the analysis result in a corresponding data structure.

[0134] Step 606: If the search for all offset positions is completed, proceed to step 607; otherwise, return to step 603 to search for the next offset value.

[0135] Step 607 : Analyze the rationality of the scheduling result, such as whether the execution time after scheduling is improved, etc. If it is reasonable, proceed to step 609 ; otherwise, proceed to step 608 .

[0136] Step 608: Use OriBB to restore the original cycle BB.

[0137] Step 609: using the soft pipeline instruction expander provided by the compiler, obtain the corresponding soft pipeline code according to the scheduling result of the scheduling window.

[0138] At this point, the processing process of the fast soft pipelining algorithm based on window scheduling is completed.

[0139] The main purpose of analyzing the table scheduling results in step 605 of the above process is to determine the issue time of each instruction and the total execution time of the sequence of instructions (i.e., the corresponding II) from the scheduled instruction sequence output by the table scheduling. This execution time includes the maximum issue time and pause time of the instruction sequence.

[0140] Among them, the algorithm process for calculating the maximum instruction emission time is as follows: Figure 11 As shown, the following steps are included.

[0141] Step 701: Obtain a DAG generated during table scheduling, where the DAG consists of instructions in a scheduling window; obtain an instruction resource manager provided by the compiler, where the instruction resource manager is responsible for checking whether there is a resource conflict between instructions.

[0142] Among them, instructions are executed by hardware resources in the AI ​​chip. One instruction can be executed by one or more hardware resources. When the hardware resources corresponding to an instruction are occupied by other instructions, there is a resource conflict between the instruction and other instructions. When the hardware resources corresponding to the instruction are not occupied by other instructions, there is no resource conflict between the instruction and other instructions.

[0143] Optionally, if there is a resource conflict between the instruction and other instructions at the current transmission time, the transmission time of the instruction can be adjusted, and the detection of whether there is a resource conflict at the new transmission time can be continued.

[0144] Step 702: Initialize the current time to 0 beats.

[0145] Step 703: Take an instruction from the instruction sequence scheduled by the table.

[0146] Step 704: Determine whether the instruction should be issued at the current moment. Through DAG analysis, if there is no predecessor instruction, or the predecessor instruction has already been issued, and the current moment is greater than or equal to the predecessor instruction issuance time plus the corresponding data delay, then the instruction can be issued at the current moment, and the process proceeds to step 706; otherwise, the process proceeds to step 705. The predecessor instruction is the instruction that provides the input data for the current instruction. For example, if instruction A outputs data a, which is the input data that instruction B depends on, that is, if instruction B's input data is data a and instruction B's output data is data b, then instruction A is the predecessor instruction of instruction B.

[0147] Step 705: add one beat to the current moment.

[0148] Step 706: Use the instruction resource manager to determine whether there is a resource conflict between the current instruction and the previously scheduled instruction. If there is no resource conflict, proceed to step 707; otherwise, proceed to step 705.

[0149] Step 707: The current moment is the time of issuing the current instruction, and the resources occupied by the current instruction are recorded in the instruction resource manager.

[0150] Step 708: If all instructions have been traversed, go to step 709; otherwise, go to step 703.

[0151] Step 709: After all instructions have been traversed, the current time plus 1 is the maximum transmission time of the instruction sequence.

[0152] The process of calculating instruction pause time is as follows Figure 12 As shown, the following steps are included.

[0153] Step 801: Acquire the TripleDAG initially established for window scheduling.

[0154] Step 802: Initialize the maximum pause time to 0 beats.

[0155] Step 803: Take an instruction from the instruction sequence scheduled by the table.

[0156] Step 804 determines whether the current instruction will generate a pause time. The judgment is based on calculating the instruction's Stall Cycle (pause time) based on the instruction's data dependencies in the TripleDAG. If the Stall Cycle is greater than 0, proceed to step 805; otherwise, proceed to step 803.

[0157] Step 805: The Stall Cycle calculated according to the Stall Cycle calculation formula is the stall time caused by the current instruction.

[0158] Step 806: If the current pause time is greater than the maximum pause time, the maximum pause time is updated with the current pause time.

[0159] Step 807: If all instructions have been traversed, go to step 808; otherwise, go to step 803.

[0160] Step 808: Get the maximum pause time of the instruction sequence.

[0161] The following is an exemplary embodiment of the method provided by this application to illustrate the application process of this application. Select the loop core (loop BB) of an operator, and after a series of processing by the compiler, it reaches the soft pipelining stage. Its instruction sequence is as follows: Figure 13 shown.

[0162] Instruction names are represented by uppercase strings, such as PHI, VLD, and VNEG. Registers are represented by the "%" character followed by a lowercase string or number, such as %1 and %2. Constants are represented directly by numbers. Instructions that output data to registers use "=" to link the output register to the instruction name. Input registers and constants follow the instruction name, separated by a comma. Note that the PHI instruction is a compiler pseudo-instruction used to represent code as a static single assignment and does not participate in window scheduling.

[0163] like Figure 14 As shown, the original loop BB is expanded into TripleBB, and the registers used need to be updated synchronously during the expansion. That is, Figure 13 The first and second instructions in (PHI instructions are not copied), and the remaining 9 instructions are copied three times to obtain Figure 14 29 instructions in (2 PHI instructions plus 3×9 loop instructions).

[0164] exist Figure 14 In the TripleBB sequence shown, data is passed between instructions and between instructions and memory through registers. The data transfer between instructions is represented by a directed acyclic graph. TripleBB corresponds to a TripleDAG as follows Figure 15 shown.

[0165] exist Figure 15 In the epoch, instruction sequences are converted into nodes in chronological order, with the node numbers corresponding to the input order. A directed edge is added between instructions that transfer data, with its weight representing the number of ticks of latency associated with the data transfer. For example, a directed edge with a weight of 1 between nodes 0 and 2 indicates that the instruction corresponding to node 2 must be issued at least one tick after the instruction corresponding to node 0. A directed edge between nodes represents the transfer of data from the source node to the destination node in this loop. In the following description, nodes and instructions can be considered equivalent, with a one-to-one correspondence between the two.

[0166] Next, we use a heuristic algorithm to calculate the set of window offsets. Based on the heuristic algorithm described above, assuming M = 10 and the total number of instructions in the current loop BB is 11, we can calculate the scheduling window offset step size to be 2. Therefore, the set of scheduling window offset positions is {0, 2, 4}.

[0167] Taking node offset position 4 as an example, Figure 14 The instruction sequence with offset position 4 and scheduling window length equal to 9 is intercepted in the above example. The scheduling window includes Figure 16 The instruction sequence shown (the first two PHI instructions do not participate in window scheduling, so when the offset position is 4, the first instruction in the corresponding scheduling window is instruction 7).

[0168] right Figure 16 The instructions in the scheduling window shown are table scheduled, and the obtained instruction sequence after scheduling is as follows Figure 17 As shown, the order of several instructions has changed:

[0169] Next, use TripleDAG to schedule Figure 17 The instruction sequence in table scheduling is analyzed. For example, VADDS_f32 depends on the VEXP_f32 instruction, which is issued on beat 5, with a relative latency of 10 beats. Therefore, the earliest possible time for VADDS_f32 to be issued is beat 15. Since the current time is beat 16, it can be issued. Resource conflicts with other scheduled instructions are then determined, ultimately determining its issuance time as beat 16. At this point, all instructions have been analyzed, so the maximum issuance time for the instruction sequence is 17 beats.

[0170] Continue to determine the pause time of the instruction sequence. Still taking VADDS_f32 as an example, according to the calculation formula of Stall Cycle, its Stall Cycle = 16 + 3 - 16 - 0 = 3 beats. At this time, all instructions have been analyzed and the final pause time is 3 beats. Therefore, the final II is 17 + 3 = 20 beats, which corresponds to the offset position of 4. The specific scheduling results are as follows Figure 18 shown.

[0171] Similarly, when the offset position of the scheduling window is 0 and 2, the II obtained are 22 beats and 15 beats respectively. It can be seen that the II when the offset position is 2 is the shortest. Therefore, the scheduling result when the offset position is 2 is taken as the final scheduling result of the window scheduling.

[0172] Finally, based on the scheduling results, the soft pipeline instruction expander provided by the compiler generates the prologue, kernel and epilogue parts.

[0173] like Figure 19 The following table shows the kernel instructions. Note that the soft pipeline instruction expander has updated the PHI instruction based on the code semantics, while other instructions remain consistent with the previously scheduled results.

[0174] For example, the common operator Swish in neural networks is used to analyze the application effect of the method provided by this application in detail. In order to improve instruction parallelism, the core loop of Swish is expanded 8 times in advance. The following compares the effects of using modulo scheduling, DoubleBB window scheduling and the method of this application. The specific test parameter settings are as follows Figure 20 As shown in Table 1.

[0175] Under the above test parameters, each algorithm was executed 5 times and the average time consumed was calculated. The results are as follows Figure 21 As shown in Table 2.

[0176] As can be seen from the above results, on the AI ​​accelerator, the modular scheduling algorithm experienced a search failure and timeout after 8 swish operator expansions, resulting in scheduling failure. DoubleBB window scheduling requires traversing all offset positions and has a high algorithmic complexity, resulting in a runtime of 1.44 seconds. In contrast, the proposed method took 0.38 seconds, reducing compilation time by 73.6%. Both DoubleBB window scheduling and the proposed method searched for 50 beats of II, resulting in consistent performance in the generated code.

[0177] In addition, the large-scale test results of local projects are basically the same. Compared with DoubleBB window scheduling, the compilation time of the method of this application can be reduced by 60% to 80%, and the core loop execution performance is slightly reduced by less than 5%.

[0178] Therefore, the method of the present application can solve the problem of module scheduling failure in complex compilation scenarios; at the same time, compared with classic window scheduling, it can significantly reduce compilation time while ensuring that code performance remains basically unchanged.

[0179] Next, the compilation method provided by this application will be introduced.

[0180] Figure 22A schematic diagram of a terminal device provided by an exemplary embodiment of the present application is shown. The compilation method provided by this embodiment of the present application is executed by terminal device 112, which can be a mobile phone, computer, intelligent voice interaction device, smart home appliance, in-vehicle terminal, etc. The terminal device has a compiler installed, and the compilation method provided by this embodiment of the present application is executed by the compiler in the terminal device.

[0181] Figure 23 A flowchart of an instruction packing method provided by an exemplary embodiment of the present application is shown. Figure 22 The execution of the compiler in the terminal device is illustrated as an example, and the method includes the following steps.

[0182] Step 210 , loop-unroll the instruction sequence in the loop BB to generate a triple BB and a triple DAG corresponding to the triple BB; the triple BB includes an instruction sequence that loops three times; and the triple DAG is used to indicate the data dependency between the instructions in the triple BB.

[0183] Exemplarily, the loop BB can be a loop BB in an AI model. An AI model can include at least one loop BB, and each loop BB can be compiled using the method provided in the embodiments of the present application. Optionally, an operator in an AI model can include at least one loop BB.

[0184] A loop block (BB) has only a single entry instruction and a single end instruction, and includes a loop body that is repeatedly executed. A loop block (BB) may refer to a loop core BB, which has only one loop body. When a second loop body is nested within a first loop body and no other loop bodies are nested within the second loop body, the second loop body may be the loop core BB (the loop body includes at least one instruction). Exemplarily, the total number of instructions within the loop block (BB) is less than a threshold, and the loop block (BB) does not contain assembly instructions or other instructions with side effects (modification or predetermined state).

[0185] A loop BB contains a repetitive sequence of instructions, known as the loop body. This sequence of instructions is executed repeatedly until a termination condition is met. A loop BB has only one entry instruction and one exit instruction: the entry instruction starts the loop, and the exit instruction ends it.

[0186] Loop unrolling loop BB means copying loop BB three times to obtain a tripled loop BB. The tripled loop BB includes the instruction sequence that loops loop BB three times. That is, loop BB includes the loop BB of the first iteration, the loop BB of the second iteration, and the loop BB of the third iteration. The loop BBs of the three iterations are all obtained by copying the original loop BB. For example, if a loop BB includes instructions A, B, and C, then the tripled loop BB obtained after copying it three times includes: instructions A, B, C, A', B', C', A", B", and C". Instructions A, A', and A" correspond to instruction A; instructions B, B', and B" correspond to instruction B; and instructions C, C', and C" correspond to instruction C.

[0187] The triple DAG is constructed based on the data input and output relationships of each instruction indicated in the triple BB and the delay time of each instruction. The triple DAG includes the data dependency and delay time of each instruction in the triple BB.

[0188] In the triple DAG, each instruction of the triple BB corresponds to a node. When the output data of instruction A is the input data of instruction B, a directed line segment will be used in the triple DAG to connect node A corresponding to instruction A and node B corresponding to instruction B. The directed line segment points from node A to node B, and the weight value on the directed line segment is the delay time corresponding to instruction A.

[0189] Among them, data dependencies include: dependent relationships and dependent relationships. Dependent relationships refer to which other instructions the instruction depends on (that is, the output data of the instruction needs to be input into other instructions as input data), and dependent relationships refer to which other instructions the instruction depends on (that is, the input data of the instruction is the output data of other instructions).

[0190] An instruction can have at least one data dependency, which is represented as a directed line in the triple DAG. When there is a directed line between node A (instruction A) and node B (instruction B) in the triple DAG, it means that there is a data dependency between instruction A and instruction B. When the directed line is from node A to node B, it means that instruction A is dependent on instruction B (the input data of instruction B is the output data of instruction A).

[0191] Each data dependency has a corresponding latency. Specifically, the weight of each directed segment in the triple DAG is the latency. For example, if the directed segment between instructions A and B is labeled with a weight of 1, it means that the output data from instruction A needs to wait one tick before being transmitted to instruction B. For example, the latency is determined by instruction A and the hardware resources required to execute it.

[0192] Based on the data dependencies in the triple DAG, we can determine the emission time of each instruction within a scheduling window. This in turn determines the maximum emission time after all instructions within the scheduling window have completed execution, as well as the maximum pause time. This maximum pause time ensures that the input data required by each instruction in the next cycle reaches the instruction before its emission time. Therefore, we can calculate the execution time of each scheduling window based on the triple DAG, and select the scheduling window with the shortest execution time as the final target scheduling window.

[0193] Step 220, window scheduling is performed based on the triple BB to determine the target scheduling window. Window scheduling is used to split the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop. The target scheduling window is a scheduling window whose execution time meets the time condition. The execution time is the time required to execute the instructions in the window, calculated based on the data dependency relationship in the triple DAG.

[0194] Optionally, after obtaining the triple BB and triple DAG, multiple scheduling windows can be tested on the triple BB. Based on the instruction execution time in each scheduling window, a target scheduling window with the execution time that meets the required time conditions (time conditions) can be selected. For example, the time conditions can be: the shortest execution time, the execution time close to the target value, or the longest execution time.

[0195] For example, when performing window scheduling, the sliding range of the scheduling window includes: starting from the first instruction of the first loop and ending at the last instruction of the second loop. That is, the scheduling window slides only within the instruction sequence of the first two loops. The third loop in the triple BB is used to generate the triple DAG. Therefore, when the scheduling window slides to the instruction in the second loop, the execution time of the scheduling window can be calculated based on the data dependency relationship between the instructions in the second loop and the instructions in the third loop.

[0196] Step 230 : compile and obtain the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0197] For example, after determining the target scheduling window, the loop BB is compiled according to the scheduling result corresponding to the target scheduling window, so that the running time of the compiled target code can be minimized, thereby improving the compilation and running efficiency of the loop BB.

[0198] In summary, the method provided by the embodiments of the present application provides a soft-pipelining algorithm for compiling loop BBs in AI models. A window scheduling algorithm is used to split the loop BB into two parts, allowing the instructions in the first part of the next loop to execute synchronously with the instructions in the second part of the current loop, saving instruction execution time. To find the optimal split position and minimize execution time, the loop BB is replicated three times to obtain a triple BB and a triple DAG. Multiple scheduling windows are then tested on the triple BB. The scheduling window is used to select the instructions in the second part of the first loop BB and the instructions in the second loop BB. The execution time required for the two parts of the instructions to execute synchronously within each scheduling window is calculated based on the data dependencies of the instructions indicated in the triple DAG. The scheduling window with the shortest execution time is then selected from the multiple scheduling windows as the final target scheduling window. The split position corresponding to the target scheduling window is the optimal split position. Compiling the loop BB according to the scheduling results from the target scheduling window improves the compilation efficiency of the loop BB and minimizes the execution time of the target code of the compiled target program.

[0199] An exemplary embodiment of window scheduling based on triple BB and triple DAG is given.

[0200] Figure 24 A flowchart of an instruction packing method provided by an exemplary embodiment of the present application is shown. Figure 22 The compiler execution in the terminal device shown is illustrated as an example, based on Figure 23 In the illustrated embodiment, step 220 includes repeatedly executing steps 221 to 224 to traverse all candidate offset positions.

[0201] Step 221: Obtain a candidate scheduling window corresponding to a candidate offset position; the candidate scheduling window selects a window instruction sequence in the triple BB, where the window instruction sequence includes the second part of the instruction sequence in the first cycle and the first part of the instruction sequence in the second cycle in the triple BB; the second part of the instruction sequence and the first part of the instruction sequence are sequentially connected in the triple BB.

[0202] Exemplarily, the window length of the scheduling window is equal to the total number of instructions in the cycle BB. For example, if the cycle BB includes 10 instructions, the window length of the scheduling window is equal to 10 instructions.

[0203] If a loop BB consists of 10 instructions, theoretically, there can be 10 candidate scheduling windows. Starting from the first instruction of the first loop, each instruction can be the first instruction of a candidate scheduling window. That is, with a sliding step of one instruction, the sliding scheduling window can slide from the first instruction of the first loop to the last instruction of the first loop, resulting in a total of 10 candidate scheduling windows. By calculating the execution time corresponding to each of the 10 candidate scheduling windows, the candidate scheduling window with the shortest execution time can be selected as the target scheduling window.

[0204] However, when the number of instructions in a loop BB is large, for example, 100 or 1000 instructions, determining the candidate scheduling window using the above method requires calculating the execution time 100 or 1000 times, which is computationally intensive. Furthermore, for loop BBs with a large number of instructions, the execution time differences between adjacent candidate scheduling windows are small. Therefore, the present embodiment employs a heuristic algorithm to determine the sliding step size (offset step size) of the candidate scheduling window. The offset step size is determined based on the number of instructions in the loop BB; the larger the number of instructions, the larger the offset step size.

[0205] For example, the offset step of the scheduling window is determined according to the total number of instructions in the loop BB, and the candidate offset position is determined according to the offset step. The candidate offset position may refer to the first instruction in the candidate scheduling window.

[0206] Optionally, when the total number of instructions is less than or equal to the first value, the offset step is determined to be the first step; when the total number of instructions is greater than the first value and less than or equal to the second value, the offset step is determined to be the second step; when the total number of instructions is greater than the second value and less than or equal to the third value, the offset step is determined to be the third step; when the total number of instructions is greater than the third value and less than or equal to the fourth value, the offset step is determined to be the fourth step; when the total number of instructions is greater than the fourth value, the offset step is determined to be the fifth step.

[0207] The first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

[0208] For example, the first value is 10, the second value is 20, the third value is 30, and the fourth value is 40. The first step length is 1, the second step length is 2, the third step length is 4, the fourth step length is 8, and the fifth step length is 16. If the loop BB includes 33 instructions, the offset step length is 8, and the starting positions of the candidate scheduling windows are the 1st instruction, the 9th instruction, the 17th instruction, the 25th instruction, and the 33rd instruction, respectively, resulting in five candidate scheduling windows. Subsequently, any one of the five candidate scheduling windows can be selected to execute step 221.

[0209] Exemplarily, other methods can also be used to determine the candidate offset positions. For example, the predetermined instructions in the loop BB are used as candidate offset positions. The predetermined instructions can be instructions with a long execution time or instructions with a long delay time. For example, the predetermined instructions can be inverse instructions, exponential instructions, etc. By using the instruction with the longest delay time as the first instruction in the candidate scheduling window, other instructions can be executed synchronously with the first instruction, thereby shortening the execution time of the candidate scheduling window. Optionally, this method can be combined with the above-mentioned heuristic algorithm method, for example, determining the offset step of the scheduling window based on the total number of instructions in the loop BB, determining the first group of candidate offset positions based on the offset step; and determining the second group of candidate offset positions based on the predetermined instructions in the loop BB.

[0210] Exemplarily, candidate offset positions may also be determined based on predetermined data dependencies. For example, if instruction x is dependent on n instructions, then when n is greater than a threshold, instruction x may be selected as a candidate offset position. Alternatively, if instruction x is dependent on m instructions, then when m is greater than a threshold, instruction x may be selected as a candidate offset position. Similarly, this method may combine at least one of the aforementioned heuristic algorithms and predetermined instructions to determine candidate offset positions.

[0211] For example, a neural network model can be used to obtain candidate offset positions. For example, the neural network model can be trained to predict candidate offset positions. After training, the neural network model can be used to output candidate offset positions based on the input triple BB. Similarly, this method can combine at least one of the aforementioned heuristic algorithms, predetermined instructions, and predetermined data dependencies to determine candidate offset positions.

[0212] Step 222: Use a table scheduling algorithm to schedule the window instruction sequence in the candidate scheduling window to obtain a scheduling result corresponding to the candidate scheduling window.

[0213] Exemplarily, a table scheduling algorithm is used for the instruction sequence within the candidate scheduling window to obtain a table scheduling result after table scheduling.

[0214] For example, if a loop BB contains 10 instructions, a candidate scheduling window might include the last 6 instructions of the first loop BB and the first 4 instructions of the second loop BB. After table scheduling, the table scheduling algorithm adjusts the order of the 10 instructions based on the data dependencies of each instruction, resulting in a scheduled instruction sequence (the scheduling result). The order of the scheduled instruction sequence may differ from the order of the instruction sequence within the candidate scheduling window.

[0215] Step 223: Calculate the execution time corresponding to the candidate scheduling window based on the scheduling result and the triple DAG.

[0216] The execution time of instructions within a candidate scheduling window is equal to the sum of the maximum issue time and the maximum pause time. The maximum issue time is the time when the last instruction in the candidate scheduling window finishes executing after table scheduling. The maximum pause time is the maximum value of the pause times corresponding to all instructions in the candidate scheduling window.

[0217] Exemplarily, the maximum emission time corresponding to the candidate scheduling window is calculated according to the scheduling result; the maximum pause time corresponding to the candidate scheduling window is calculated according to the scheduling result and the triple DAG; and the sum of the maximum emission time and the maximum pause time is determined as the execution time corresponding to the candidate scheduling window.

[0218] Among them, the calculation method of the maximum transmission time includes: initializing the current time to 0; repeatedly executing the following steps 1) to 3), traversing all instructions in the scheduling results, determining the transmission time corresponding to each instruction, and adding one to the maximum value of the transmission time to determine the maximum transmission time.

[0219] Step 1) Obtain the i-th instruction from the scheduling result port, where i is a positive integer; if the i-th instruction is allowed to be issued at the current moment and there is no resource conflict between the i-th instruction and the scheduled instructions, determine the current moment as the issuance time of the i-th instruction.

[0220] For example, when the i-th instruction is allowed to be emitted at the current moment, and the input data on which the i-th instruction depends has arrived (that is, the current moment satisfies the delay time of the instruction on which the i-th instruction depends), and there is no resource conflict between the i-th instruction and the scheduled instructions, the current moment is determined to be the emission time of the i-th instruction.

[0221] Step 2) When the i-th instruction is not allowed to be issued at the current moment, or when the i-th instruction conflicts with a scheduled instruction in terms of resources, the current moment is determined to be incremented by one.

[0222] Step 3), when i is not equal to n, let i be equal to i+1, where n is the number of all instructions.

[0223] The maximum pause time calculation method includes: initializing the maximum pause time to 0; and repeatedly executing the following steps 1> to 3> to traverse all instructions in the scheduling result.

[0224] Step 1>, obtain the i-th instruction from the scheduling result, where i is a positive integer.

[0225] Step 2>: when the i-th instruction corresponds to a pause time and the pause time is greater than the maximum pause time, the pause time is determined as the new maximum pause time.

[0226] If the i-th instruction has no pause time, continue to step 3>. Alternatively, if the i-th instruction has a pause time but the pause time is not greater than the maximum pause time, continue to step 3>.

[0227] Step 3>, when i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

[0228] The pause time is calculated based on the data dependency corresponding to the i-th instruction in the triple DAG.

[0229] For example, assuming that the i-th instruction and the x-th instruction have a data dependency, where x is a positive integer, the pause time of the i-th instruction is calculated as follows: the sum of the launch time of the i-th instruction and the delay time is calculated to obtain a first value; the delay time is the delay time required for the data output by the i-th instruction to be input to the x-th instruction; the difference between the first value and the maximum launch time is calculated to obtain a second value; and the difference between the second value and the launch time of the x-th instruction is calculated to obtain the pause time corresponding to the i-th instruction.

[0230] That is, the pause time = the issuance time of the i-th instruction + the delay time for the output data of the i-th instruction to reach the x-th instruction - the time when all instructions in the candidate scheduling window are executed (maximum issuance time) - the issuance time of the x-th instruction.

[0231] As an example, a method for determining instruction dependencies based on a triple DAG is provided. Assume that a loop BB includes instructions 1 and 2, and the triple BB includes the following: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2, obtained by copying the loop BB. The triple DAG indicates that second instruction 1 depends on first instruction 2, and third instruction 1 depends on second instruction 2. The candidate scheduling window includes second instruction 1 and second instruction 2. If the i-th instruction is second instruction 2, then based on the indication in the triple DAG that third instruction 1 depends on second instruction 2, it is determined that second instruction 2 has a data dependency with second instruction 1.

[0232] Step 224: If the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as the new stored value.

[0233] For example, the initial value of the stored value can be set to a maximum value, such as 999. The stored value is the minimum execution time of the currently calculated candidate scheduling windows. If the execution time of the currently calculated candidate scheduling window is not less than the stored value, it means that the current candidate scheduling window is not the scheduling window with the shortest execution time, and the execution time of the next candidate scheduling window will be calculated.

[0234] Exemplarily, determine whether all candidate offset positions have been traversed. If not, select a candidate offset position from the untraversed candidate offset positions to continue executing step 221. If the traversal is completed, end and obtain the target scheduling window and the execution time corresponding to the target scheduling window.

[0235] In summary, the method provided by the embodiments of the present application provides a soft-pipelining algorithm for compiling loop BBs in AI models. A window scheduling algorithm is used to split the loop BB into two parts, allowing the instructions in the first part of the next loop to execute synchronously with the instructions in the second part of the current loop, saving instruction execution time. To find the optimal split position and minimize execution time, the loop BB is replicated three times to obtain a triple BB and a triple DAG. Multiple scheduling windows are then tested on the triple BB. The scheduling window is used to select the instructions in the second part of the first loop BB and the instructions in the second loop BB. The execution time required for the two parts of the instructions to execute synchronously within each scheduling window is calculated based on the data dependencies of the instructions indicated in the triple DAG. The scheduling window with the shortest execution time is then selected from the multiple scheduling windows as the final target scheduling window. The split position corresponding to the target scheduling window is the optimal split position. Compiling the loop BB according to the scheduling results from the target scheduling window improves the compilation efficiency of the loop BB and minimizes the execution time of the target code of the compiled target program.

[0236] Figure 25 The following is a block diagram of a compiling device provided by an exemplary embodiment of the present application, wherein the device includes:

[0237] A loop module 301 is configured to loop-unroll an instruction sequence in a loop basic block BB to generate a triple BB and a triple directed acyclic graph (DAG) corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; and the triple DAG indicates data dependencies between instructions in the triple BB.

[0238] Scheduling module 302 is configured to perform window scheduling based on the triple BB and determine a target scheduling window. The window scheduling is configured to split the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second instruction sequence in the current loop is executed synchronously with the first instruction sequence in the next loop. The target scheduling window is a scheduling window whose execution time satisfies a time condition. The execution time is the time required to execute instructions within the window, calculated based on data dependencies in the triple DAG.

[0239] The compiling module 303 is configured to compile the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window.

[0240] In an optional embodiment, the scheduling module 302 is configured to repeatedly perform the following steps to traverse all candidate offset positions:

[0241] Obtain a candidate scheduling window corresponding to a candidate offset position; select a window instruction sequence from the candidate scheduling window in the triple BB, where the window instruction sequence includes the second portion of the instruction sequence in the first cycle and the first portion of the instruction sequence in the second cycle in the triple BB; and sequentially connect the second portion of the instruction sequence and the first portion of the instruction sequence in the triple BB.

[0242] Schedule the window instruction sequence in the candidate scheduling window using a table scheduling algorithm to obtain a scheduling result corresponding to the candidate scheduling window;

[0243] Calculate the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG;

[0244] In a case where the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

[0245] In an optional embodiment, the scheduling module 302 is configured to calculate a maximum transmission time corresponding to the candidate scheduling window according to the scheduling result;

[0246] The scheduling module 302 is configured to calculate the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG;

[0247] The scheduling module 302 is configured to determine the sum of the maximum transmission time and the maximum pause time as the execution time corresponding to the candidate scheduling window.

[0248] In an optional embodiment, the scheduling module 302 is used to initialize the current time to 0;

[0249] The scheduling module 302 is configured to repeatedly perform the following steps to traverse all instructions in the scheduling result, determine the emission time corresponding to each instruction, and increase the maximum emission time by one to determine the maximum emission time:

[0250] Obtain the i-th instruction from the scheduling result port, where i is a positive integer;

[0251] If the i-th instruction is allowed to be issued at the current moment and there is no resource conflict between the i-th instruction and the scheduled instructions, determining the current moment as the issuance moment of the i-th instruction;

[0252] In a case where the i-th instruction is not allowed to be issued at the current moment, or a resource conflict occurs between the i-th instruction and a scheduled instruction, determining that the current moment is incremented by one;

[0253] When i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

[0254] In an optional embodiment, the scheduling module 302 is configured to initialize the maximum pause time to 0;

[0255] The scheduling module 302 is configured to repeatedly execute the following steps to traverse all instructions in the scheduling result:

[0256] Obtaining the i-th instruction from the scheduling result, where i is a positive integer;

[0257] If the i-th instruction corresponds to a pause time and the pause time is greater than the maximum pause time, the pause time is determined as the new maximum pause time;

[0258] If i is not equal to n, let i be equal to i+1, and n be the number of all instructions;

[0259] The pause time is calculated based on the data dependency corresponding to the i-th instruction in the triple DAG.

[0260] In an optional embodiment, the i-th instruction has a data dependency relationship with the x-th instruction, where x is a positive integer;

[0261] The scheduling module 302 is configured to calculate the sum of the emission time of the i-th instruction and the delay time to obtain a first value; the delay time is the delay time required for the data output by the i-th instruction to be input to the x-th instruction;

[0262] The scheduling module 302 is configured to calculate the difference between the first value and the maximum transmission time to obtain a second value;

[0263] The scheduling module 302 is configured to calculate the difference between the second value and the issuance time of the x-th instruction to obtain the pause time corresponding to the i-th instruction.

[0264] In an optional embodiment, the loop BB includes instruction 1 and instruction 2, and the triple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2 obtained by copying the loop BB; in the triple DAG, it is indicated that: the second instruction 1 depends on the first instruction 2, and the third instruction 1 depends on the second instruction 2; the candidate scheduling window includes the second instruction 1 and the second instruction 2;

[0265] The scheduling module 302 is configured to determine, when the i-th instruction is the second instruction 2, that the second instruction 2 has the data dependency relationship with the second instruction 1 based on the fact that the third instruction 1 is dependent on the second instruction 2 indicated in the triple DAG.

[0266] In an optional embodiment, the scheduling module 302 is configured to determine the offset step size of the scheduling window according to the total number of instructions in the loop BB;

[0267] The scheduling module 302 is configured to determine the candidate offset position according to the offset step size.

[0268] In an optional embodiment, the scheduling module 302 is configured to determine the offset step size as the first step size when the total number of instructions is less than or equal to a first value;

[0269] The scheduling module 302 is configured to determine that the offset step size is a second step size when the total number of instructions is greater than the first value and less than or equal to a second value;

[0270] The scheduling module 302 is configured to determine that the offset step size is a third step size when the total number of instructions is greater than the second value and less than or equal to a third value;

[0271] The scheduling module 302 is configured to determine that the offset step size is a fourth step size when the total number of instructions is greater than the third value and less than or equal to a fourth value;

[0272] The scheduling module 302 is configured to determine that the offset step size is a fifth step size when the total number of instructions is greater than the fourth value;

[0273] The first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

[0274] Figure 26The following is a block diagram of a computer device 2100 according to an exemplary embodiment of the present application. Computer device 2100 may be a portable mobile terminal, such as a smartphone, tablet computer, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop computer, or desktop computer. Computer device 2100 may also be referred to as user equipment, portable terminal, laptop terminal, desktop terminal, or other similar names.

[0275] Typically, the computer device 2100 includes a processor 2101 and a memory 2102 .

[0276] The processor 2101 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 2101 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), or PLA (Programmable Logic Array). The processor 2101 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 2101 may be integrated with a GPU (Graphics Processing Unit, video encoder), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 2101 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0277] The memory 2102 may include one or more computer-readable storage media, which may be non-transitory. The memory 2102 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 2102 is used to store at least one instruction, which is used to be executed by the processor 2101 to implement the compilation method provided in the method embodiment of the present application.

[0278] In some embodiments, computer device 2100 may optionally include a peripheral device interface 2103 and at least one peripheral device. Processor 2101, memory 2102, and peripheral device interface 2103 may be connected via a bus or signal lines. Each peripheral device may be connected to peripheral device interface 2103 via a bus, signal lines, or circuit boards. For example, the peripheral device may include at least one of a radio frequency circuit 2104, a display screen 2105, a camera assembly 2106, an audio circuit 2107, and a power supply 2108.

[0279] The peripheral device interface 2103 can be used to connect at least one I / O (Input / Output)-related peripheral device to the processor 2101 and the memory 2102. In some embodiments, the processor 2101, the memory 2102, and the peripheral device interface 2103 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 2101, the memory 2102, and the peripheral device interface 2103 can be implemented on separate chips or circuit boards, which is not limited in this embodiment.

[0280] The RF circuit 2104 is used to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The RF circuit 2104 communicates with communication networks and other communication devices via electromagnetic signals. The RF circuit 2104 converts electrical signals into electromagnetic signals for transmission, or converts received electromagnetic signals into electrical signals. Optionally, the RF circuit 2104 includes an antenna system, an RF transceiver, one or more amplifiers, a tuner, an oscillator, a digital signal processor, a codec chipset, a user identity module card, and the like. The RF circuit 2104 can communicate with other terminals via at least one wireless communication protocol. Such wireless communication protocols include, but are not limited to, the World Wide Web, metropolitan area networks, intranets, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and / or WiFi (Wireless Fidelity) networks. In some embodiments, the RF circuit 2104 may also include circuitry related to Near Field Communication (NFC), which is not limited in this application.

[0281] The display screen 2105 is used to display a UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 2105 is a touch screen display, the display screen 2105 also has the ability to collect touch signals on the surface or above the surface of the display screen 2105. The touch signal can be input as a control signal to the processor 2101 for processing. In this case, the display screen 2105 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, there can be one display screen 2105, which is set on the front panel of the computer device 2100; in other embodiments, there can be at least two display screens 2105, which are respectively set on different surfaces of the computer device 2100 or in a folding design; in other embodiments, the display screen 2105 can be a flexible display screen, which is set on the curved surface or folding surface of the computer device 2100. Even more, the display screen 2105 can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 2105 can be made of materials such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode).

[0282] The camera assembly 2106 is used to capture images or videos. Optionally, the camera assembly 2106 includes a front camera and a rear camera. Typically, the front camera is arranged on the front panel of the terminal, and the rear camera is arranged on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 2106 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0283] The audio circuit 2107 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals that are input into the processor 2101 for processing, or input into the radio frequency circuit 2104 to achieve voice communication. For the purpose of stereo sound collection or noise reduction, there may be multiple microphones, each located in different parts of the computer device 2100. The microphone may also be an array microphone or an omnidirectional collection microphone. The speaker is used to convert electrical signals from the processor 2101 or the radio frequency circuit 2104 into sound waves. The speaker may be a traditional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert electrical signals into sound waves audible to humans, but also convert electrical signals into sound waves inaudible to humans for purposes such as distance measurement. In some embodiments, the audio circuit 2107 may also include a headphone jack.

[0284] Power supply 2108 is used to power various components in computer device 2100. Power supply 2108 can be AC ​​power, DC power, a disposable battery, or a rechargeable battery. When power supply 2108 includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged via a wired line, while a wireless rechargeable battery is a battery that is charged via a wireless coil. The rechargeable battery can also be configured to support fast charging technology.

[0285] In some embodiments, the computer device 2100 further includes one or more sensors 2109 , including but not limited to an acceleration sensor 2110 , a gyroscope sensor 2111 , a pressure sensor 2112 , an optical sensor 2113 , and a proximity sensor 2114 .

[0286] The accelerometer 2110 can detect the magnitude of acceleration along the three coordinate axes of the coordinate system established by the computer device 2100. For example, the accelerometer 2110 can be used to detect the components of gravity acceleration along the three coordinate axes. The processor 2101 can control the display screen 2105 to display the user interface in a landscape or portrait view based on the gravity acceleration signal collected by the accelerometer 2110. The accelerometer 2110 can also be used to collect game or user motion data.

[0287] The gyroscope sensor 2111 can detect the orientation and rotation angle of the computer device 2100. It can also work with the accelerometer 2110 to collect 3D motions of the user on the computer device 2100. Based on the data collected by the gyroscope sensor 2111, the processor 2101 can implement the following functions: motion sensing (e.g., changing the UI based on the user's tilt), image stabilization during shooting, game control, and inertial navigation.

[0288] The pressure sensor 2112 can be installed on the side frame of the computer device 2100 and / or below the display screen 2105. When the pressure sensor 2112 is installed on the side frame of the computer device 2100, it can detect the user's grip signal of the computer device 2100. The processor 2101 can perform left-hand or right-hand recognition or shortcut operations based on the grip signal collected by the pressure sensor 2112. When the pressure sensor 2112 is installed below the display screen 2105, the processor 2101 controls the operational controls on the UI interface based on the user's pressure operation on the display screen 2105. The operational controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.

[0289] Optical sensor 2113 is used to detect ambient light intensity. In one embodiment, processor 2101 can control the display brightness of display screen 2105 based on the ambient light intensity detected by optical sensor 2113. For example, when the ambient light intensity is high, the display brightness of display screen 2105 is increased; when the ambient light intensity is low, the display brightness of display screen 2105 is decreased. In another embodiment, processor 2101 can also dynamically adjust the shooting parameters of camera assembly 2106 based on the ambient light intensity detected by optical sensor 2113.

[0290] Proximity sensor 2114, also known as a distance sensor, is typically located on the front panel of computer device 2100. Proximity sensor 2114 is used to detect the distance between the user and the front of computer device 2100. In one embodiment, when proximity sensor 2114 detects that the distance between the user and the front of computer device 2100 is gradually decreasing, processor 2101 controls display screen 2105 to switch from a screen-on state to a screen-off state. When proximity sensor 2114 detects that the distance between the user and the front of computer device 2100 is gradually increasing, processor 2101 controls display screen 2105 to switch from a screen-off state to a screen-on state.

[0291] Those skilled in the art will understand that Figure 26 The structure shown in the figure does not constitute a limitation on the computer device 2100, and the computer device 2100 may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0292] The present application also provides a computer-readable storage medium, wherein the storage medium stores at least one instruction, at least one program, code set, or instruction set, and the at least one instruction, at least one program, code set, or instruction set is loaded and executed by a processor to implement the compilation method provided by the above method embodiment. The present application provides a computer program product or computer program, which includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of a computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs the compilation method provided by the above method embodiment.

[0293] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0294] Those skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, which may be a read-only memory, a disk, or an optical disk, etc.

[0295] The above description is merely an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A compilation method, characterized in that: The method comprises: Loop-unrolling an instruction sequence in a loop basic block BB to generate a triple BB and a triple directed acyclic graph (DAG) corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; and the triple DAG is used to indicate data dependencies between instructions in the triple BB; Window scheduling is performed based on the triple BB to determine a target scheduling window; the window scheduling is used to split the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second part of the instruction sequence in the current loop is executed synchronously with the first part of the instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time meets the time condition, and the execution time is the time required to execute instructions in the window calculated based on the data dependency relationship in the triple DAG; Compiling and obtaining the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window; The performing window scheduling based on the triple BB to determine the target scheduling window includes: repeatedly performing the following steps to traverse all candidate offset positions: Obtain a candidate scheduling window corresponding to a candidate offset position; select a window instruction sequence from the candidate scheduling window in the triple BB, where the window instruction sequence includes the second portion of the instruction sequence in the first cycle and the first portion of the instruction sequence in the second cycle in the triple BB; and sequentially connect the second portion of the instruction sequence and the first portion of the instruction sequence in the triple BB. Schedule the window instruction sequence in the candidate scheduling window using a table scheduling algorithm to obtain a scheduling result corresponding to the candidate scheduling window; Calculate the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; In a case where the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

2. The method according to claim 1, characterized in that The calculating the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG includes: Calculate the maximum transmission time corresponding to the candidate scheduling window according to the scheduling result; Calculate the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; The sum of the maximum transmission time and the maximum pause time is determined as the execution time corresponding to the candidate scheduling window.

3. The method according to claim 2, characterized in that The calculating, according to the scheduling result, the maximum transmission time corresponding to the candidate scheduling window includes: Initialize the current time to 0; Repeat the following steps to traverse all instructions in the scheduling result, determine the emission time corresponding to each instruction, and add one to the maximum emission time to determine the maximum emission time: Obtain the i-th instruction from the scheduling result port, where i is a positive integer; If the i-th instruction is allowed to be issued at the current moment and there is no resource conflict between the i-th instruction and the scheduled instructions, determining the current moment as the issuance moment of the i-th instruction; In a case where the i-th instruction is not allowed to be issued at the current moment, or a resource conflict occurs between the i-th instruction and a scheduled instruction, determining that the current moment is incremented by one; When i is not equal to n, let i be equal to i+1, and n is the number of all instructions.

4. The method according to claim 2, characterized in that The calculating the maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG includes: Initialize the maximum pause time to 0; Repeat the following steps to iterate over all instructions in the scheduling result: Obtaining the i-th instruction from the scheduling result, where i is a positive integer; If the i-th instruction corresponds to a pause time and the pause time is greater than the maximum pause time, the pause time is determined as the new maximum pause time; If i is not equal to n, let i be equal to i+1, and n be the number of all instructions; The pause time is calculated based on the data dependency corresponding to the i-th instruction in the triple DAG.

5. The method according to claim 4, characterized in that The i-th instruction and the x-th instruction have a data dependency relationship, where x is a positive integer; and the method further includes: Calculating the sum of the emission time of the i-th instruction and the delay time to obtain a first value; the delay time is the delay time required for the data output by the i-th instruction to be input to the x-th instruction; Calculating a difference between the first value and the maximum emission time to obtain a second value; The difference between the second value and the issuance time of the x-th instruction is calculated to obtain the pause time corresponding to the i-th instruction.

6. The method according to claim 5, characterized in that The loop BB includes instruction 1 and instruction 2, and the triple BB includes: first instruction 1, first instruction 2, second instruction 1, second instruction 2, third instruction 1, and third instruction 2 obtained by copying the loop BB; in the triple DAG, it is indicated that: the second instruction 1 depends on the first instruction 2, and the third instruction 1 depends on the second instruction 2; the candidate scheduling window includes the second instruction 1 and the second instruction 2; The method further comprises: In a case where the i-th instruction is the second instruction two, according to the third instruction one indicated in the triple DAG as being dependent on the second instruction two, it is determined that the second instruction two has the data dependency relationship with the second instruction one.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Determining the offset step size of the scheduling window according to the total number of instructions in the loop BB; The candidate offset position is determined according to the offset step size.

8. The method according to claim 7, characterized in that Determining the offset step size of the scheduling window according to the total number of instructions in the loop BB includes: When the total number of instructions is less than or equal to a first value, determining the offset step size to be the first step size; When the total number of instructions is greater than the first value and less than or equal to a second value, determining the offset step size to be a second step size; When the total number of instructions is greater than the second value and less than or equal to a third value, determining the offset step size to be a third step size; When the total number of instructions is greater than the third value and less than or equal to a fourth value, determining the offset step size to be a fourth step size; When the total number of instructions is greater than the fourth value, determining the offset step size to be a fifth step size; The first value, the second value, the third value and the fourth value are in an arithmetic progression; the first step length, the second step length, the third step length, the fourth step length and the fifth step length increase in sequence.

9. A compiling device, characterized in that: The device comprises: a loop module, configured to loop-unroll an instruction sequence in a loop BB to generate a triple BB and a triple DAG corresponding to the triple BB; the triple BB includes the instruction sequence looped three times; the triple DAG is configured to indicate data dependencies between instructions in the triple BB; a scheduling module configured to perform window scheduling based on the triple BB and determine a target scheduling window; the window scheduling is configured to split the instruction sequence in the loop BB into two parts according to the scheduling window, so that the second instruction sequence in the current loop is executed synchronously with the first instruction sequence in the next loop; the target scheduling window is a scheduling window whose execution time satisfies a time condition, and the execution time is the time required to execute instructions within the window, calculated based on data dependencies in the triple DAG; A compiling module, configured to compile the target code of the loop BB in the target program according to the scheduling result corresponding to the target scheduling window; The scheduling module is configured to repeatedly perform the following steps to traverse all candidate offset positions: Obtain a candidate scheduling window corresponding to a candidate offset position; select a window instruction sequence from the candidate scheduling window in the triple BB, where the window instruction sequence includes the second portion of the instruction sequence in the first cycle and the first portion of the instruction sequence in the second cycle in the triple BB; and sequentially connect the second portion of the instruction sequence and the first portion of the instruction sequence in the triple BB. Schedule the window instruction sequence in the candidate scheduling window using a table scheduling algorithm to obtain a scheduling result corresponding to the candidate scheduling window; Calculate the execution time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; In a case where the execution time is less than the stored value, the candidate scheduling window is determined as the target scheduling window, and the execution time is determined as a new stored value.

10. The device according to claim 9, characterized in that The scheduling module is configured to calculate the maximum transmission time corresponding to the candidate scheduling window according to the scheduling result; The scheduling module is configured to calculate a maximum pause time corresponding to the candidate scheduling window according to the scheduling result and the triple DAG; The scheduling module is configured to determine the sum of the maximum transmission time and the maximum pause time as the execution time corresponding to the candidate scheduling window.

11. A computer device, characterized in that: The computer device includes: a processor and a memory, the memory stores a computer program, and the computer program is loaded and executed by the processor to implement the compilation method according to any one of claims 1 to 8.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is loaded and executed by a processor to implement the compilation method according to any one of claims 1 to 8.

13. A computer program product, characterized in that The computer program product stores a computer program, and the computer program is loaded and executed by a processor to implement the compilation method according to any one of claims 1 to 8.

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