Lookup table with data element lifting

Abstract

The invention relates to a lookup table with data element lifting. The lookup table read instruction calls data elements of a specified data size from the table and stores the called data elements in contiguous slots in the destination register. The described embodiments lift data elements to a larger size with selected symbols or zero extensions. A source operand register stores a vector offset from a table start address. A destination operand stores a result of the lookup table read. The lookup table instruction implies a base address register and a configuration register. The base address register stores a table base address. The configuration register sets various lookup table read operation parameters.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with application date of December 12, 2018, application number 201880075362.3, and invention name “Lookup table with data element promotion”. Technical Field

[0003] The present invention relates generally to digital data processing and, more particularly, to improvements in lookup table operations. Background Art

[0004] Modern digital signal processors (DSPs) face multiple challenges. Workloads continue to increase, requiring increasing bandwidth. System-on-a-chip (SOC) sizes and complexity continue to grow. Memory system latency can severely impact certain classes of algorithms. As transistors get smaller, memory and register reliability decreases. As software stacks get larger, the number of potential interactions and errors increases. Even wiring is becoming a challenge. Wide buses are difficult to route. Wire speeds continue to lag behind transistor speeds. Routing congestion is a constant challenge.

[0005] One technique that is useful for screening functions is table lookup. A data table is loaded into memory that stores a set of results corresponding to the input parameters at memory locations. To execute the function, the pre-computed results are called with the input parameters. This technique can be particularly valuable for rarely used and difficult to calculate mathematical functions. Summary of the invention

[0006] This description relates to lookup table operations. The size of the data elements stored in the table may not match the data size required by the data processor. Algorithms that require the same table data of two precisions previously required the storage and use of two tables. The table to be used is selected based on the required data size, which usually wastes memory space. Another problem is the granularity of the lookup table. The screening algorithm may require a table value for an input between the stored inputs.

[0007] The described embodiments may be implemented in a digital data processor. An instruction memory stores instructions specifying data processing operations. An instruction decoder sequentially calls instructions and determines the specified data processing operations and operands. An operation unit responds to a table lookup read instruction by: calling data elements from at least one table having a data size specified by the instruction; and storing the called data elements in consecutive slots in a destination register specified by the instruction.

[0008] Certain described embodiments implement two dedicated lookup table read operations. The first special operation promotes the data element called from the table to a larger size. The data element size is typically an integer power of two (2 N) bits. In one example embodiment, the table lookup read instruction supports no promotion, 2x promotion, 4x promotion, and 8x promotion. Promotion provides extension bits for each called data element. The table lookup instruction may treat the data element as an unsigned integer and zero-extend the data element to the extension bit. The table lookup instruction may treat the data element as a signed integer and sign-extend the data element to the extension bit.

[0009] The table lookup instruction specifies a source operand as a register storing a set of vector offsets from a table start address to an accessed data element. The table lookup instruction specifies a destination operand as a register storing the result of a table lookup read instruction. The table lookup instruction implies a table lookup base address register and a table lookup configuration register. In one embodiment, the table lookup read instruction specifies a table group of multiple tables from among multiple table groups. The table lookup base address register and the table lookup configuration register are bound to the specified table group. The base address register stores the table base address. The offset from this base address is derived from the source operand register. The configuration register sets a number of table lookup read operation parameters. These parameters include: promotion mode (none, 2x, 4x, and 8x); the amount of memory allocated to the corresponding table group (table size); whether the called data element will be treated as a signed integer or an unsigned integer; the size of the table data element; and the number of tables in the table group.

[0010] Tables for these lookup table read operations may be mapped into the first-level data cache directly addressable memory according to the commonly assigned US Patent No. 6,606,686 entitled "UNIFIED MEMORY SYSTEM ARCHITECTURE INCLUDING CACHE AND DIRECTLYADDRESSABLE STATIC RANDOMACCESS MEMORY", which is incorporated herein by reference. These tables may be loaded by normal memory operations. In one example embodiment, the data processor supports up to 4 sets of independent parallel lookup tables. Within a set, up to 16 tables may be searched in parallel with byte, halfword or word element sizes. According to this example embodiment, at least a portion of the first-level data cache dedicated to directly addressable memory has 16 banks. This allows access to 16 memory locations in parallel and supports up to 16 tables per table set. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A dual scalar / vector datapath processor according to one embodiment is described.

[0012] Figure 2 illustrate Figure 1 Registers and functional units in the dual scalar / vector datapath processor described in .

[0013] Figure 3 Describes the global scalar register file.

[0014] Figure 4 Describes the local scalar register file shared by the arithmetic functional units.

[0015] Figure 5 Describes the local scalar register file shared by the multiplication functional units.

[0016] Figure 6 Describes the local scalar register file shared by the load / store units.

[0017] Figure 7 Describes the global vector register file.

[0018] Figure 8 Describes the predicate register file.

[0019] Fig. 9 Describes the local vector register file shared by the arithmetic functional units.

[0020] Fig.10 Describes the local vector register file shared by the multiplication and related functional units.

[0021] Fig.11 Pipeline stages of a central processing unit according to an example embodiment are illustrated.

[0022] Fig.12 Sixteen instructions describing a single extraction packet.

[0023] Fig.13 An instruction encoding example according to one embodiment is described.

[0024] Fig.14 Illustrates the bit encoding of condition code extension slot 0.

[0025] Fig.15 Illustrate the bit encoding of condition code extension slot 1.

[0026] Fig.16 Specifies the bit encoding of constant extension slot 0.

[0027] Fig.17 is a partial block diagram illustrating constant expansion.

[0028] Fig.18 Carry control for SIMD operations according to example embodiments is described.

[0029] Fig.19 Describes the data fields of the instance lookup table configuration register.

[0030] Fig. 20Describes the data fields in the instance lookup table enable register that specify the types of operations allowed for a particular table group.

[0031] Fig.21 A lookup table organization for one table of the table group is described.

[0032] Fig. 22 The lookup table organization for the two tables of the table group is described.

[0033] Fig.23 The lookup table organization for the four tables of the table group is described.

[0034] Fig.24 The lookup table organization for the eight tables of the table group is described.

[0035] Fig.25 The lookup table organization for the sixteen tables of the table group is described.

[0036] Fig.26 An example of operation of a lookup table read instruction for four parallel tables, a data element size of bytes, and no promotion is illustrated according to an example embodiment.

[0037] Fig. 27 An example of operation of a lookup table read instruction for four parallel tables, a data element size of bytes, and 2x promotion is illustrated according to an example embodiment.

[0038] Fig.28 An example of operation of a lookup table read instruction for four parallel tables, a data element size of bytes, and 4x promotion is illustrated according to an example embodiment.

[0039] Fig.29A and 29B Together, example embodiments of the lifting implementation are described.

[0040] Fig.30 illustrate Fig.29A An example of an extension element as described in .

[0041] Fig.31 Description Control Fig.29A and 29B A multiplexing control encoder for the multiplexer described in . DETAILED DESCRIPTION

[0042] Figure 1 A dual scalar / vector data path processor 100 is illustrated according to an example embodiment. The processor 100 includes a separate level one instruction cache (L1I) 121 and a level one data cache (L1D) 123. The processor 100 includes a level two combined instruction / data cache (L2) 130 that holds both instructions and data. Figure 1The connection between the first level instruction cache 121 and the second level combined instruction / data cache 130 (bus 142) is illustrated. Figure 1 The connection (bus 145) between the primary data cache 123 and the secondary combined instruction / data cache 130 is illustrated. The secondary combined instruction / data cache 130 stores both instructions for backing up the primary instruction cache 121 and data for backing up the primary data cache 123. Figure 1 The CPU core 110, the first level instruction cache 121, the first level data cache 123, and the second level combined instruction / data cache 130 are formed on a single integrated circuit. This single integrated circuit optionally includes other circuits.

[0043] The central processing unit core 110 fetches instructions from the first level instruction cache 121 under the control of the instruction fetch unit 111. The instruction fetch unit 111 determines the next instruction to be executed and calls a fetch packet size set for such instructions. The nature and size of the fetch packet are further detailed below. Instructions are fetched directly from the first level instruction cache 121 on cache hits (if these instructions are stored in the first level instruction cache 121). On cache misses (the specified instruction fetch packet is not stored in the first level instruction cache 121), these instructions are then looked for in the second level combined cache 130. In one embodiment, the size of the cache line in the first level instruction cache 121 is equal to the size of the fetch packet. The memory location of these instructions is a hit or miss in the second level combined cache 130. Hits are serviced from the second level combined cache 130. Misses are serviced from a higher level cache (not illustrated) or from main memory (not illustrated). The requested instructions can be supplied to both the first level instruction cache 121 and the central processing unit core 110 at the same time to speed up use.

[0044] The central processing unit core 110 includes a plurality of functional units (also referred to as "execution units") for executing the data processing tasks specified by the instructions. The instruction dispatch unit 112 determines the target functional unit of each extracted instruction. In one embodiment, the central processing unit 110 operates as a very long instruction word (VLIW) processor capable of operating on multiple instructions in corresponding functional units at the same time. The compiler can organize the instructions to be executed together in execution packets. The instruction dispatch unit 112 guides each instruction to its target functional unit. In one embodiment, the functional unit assigned to the instruction is fully specified by the instruction generated by the compiler, because the hardware of the central processing unit core 110 does not participate in this functional unit assignment. The instruction dispatch unit 112 can operate on multiple instructions in parallel. The number of such parallel instructions is set by the size of the execution packet. This will be further described below.

[0045] Part of the dispatching task of the instruction dispatch unit 112 is to determine whether to execute an instruction on a functional unit in the scalar datapath side A 115 or the vector datapath side B 116. An instruction bit called the s bit within each instruction determines which datapath the instruction controls. This will be described in further detail below.

[0046] The instruction decode unit 113 decodes each instruction in the current execution packet. The decoding includes identification of the functional unit that executes the instruction, identification of the registers that supply data from among possible register files for the corresponding data processing operation, and identification of the register destination for the result of the corresponding data processing operation. As further explained below, the instruction may include a constant field in place of a register number operand field. The result of this decoding is a signal that is used to control the target functional unit to perform the data processing operation specified by the corresponding instruction on the specified data.

[0047] The central processing unit core 110 includes control registers 114. The control registers 114 store information for controlling the functional units in the scalar datapath side A 115 and the vector datapath side B 116. This information may include mode information or the like.

[0048] The decoded instructions from the instruction decoding unit 113 and the information stored in the control register 114 are supplied to the scalar data path side A 115 and the vector data path side B 116. Therefore, the functional units within the scalar data path side A 115 and the vector data path side B 116 perform the instruction specified data processing operation on the instruction specified data and store the result in the instruction specified data register. Each of the scalar data path side A 115 and the vector data path side B 116 includes a plurality of functional units that can operate in parallel. Figure 2These will be described in further detail.A data path 117 exists between the scalar data path side A 115 and the vector data path side B 116, allowing data to be exchanged.

[0049] The CPU core 110 includes additional non-instruction based modules. The simulation unit 118 allows the machine state of the CPU core 110 to be determined in response to instructions. This capability will typically be used for algorithm development. The interrupt / exception unit 119 enables the CPU core 110 to respond to external asynchronous events (interrupts) and to respond to attempts to perform improper operations (exception).

[0050] The central processing unit core 110 includes a streaming engine 125. The streaming engine 125 supplies two data streams from predetermined addresses, typically cached in the L2 combined cache 130, to the register file of the vector data path side B. This provides controlled data movement from memory (such as cached in the L2 combined cache 130) directly to the functional unit operand inputs. This is further detailed below.

[0051] Figure 1 The data width of the bus between the various parts of the example embodiment is described. The first level instruction cache 121 supplies instructions to the instruction fetch unit 111 via bus 141. In this example embodiment, bus 141 is a 512-bit bus. Bus 141 is unidirectional from the first level instruction cache 121 to the central processing unit 110. The second level combined cache 130 supplies instructions to the first level instruction cache 121 via bus 142. In this example embodiment, bus 142 is a 512-bit bus. Bus 142 is unidirectional from the second level combined cache 130 to the first level instruction cache 121.

[0052] The primary data cache 123 exchanges data with the register file in the scalar data path side A 115 via bus 143. In this example embodiment, bus 143 is a 64-bit bus. The primary data cache 123 exchanges data with the register file in the vector data path side B 116 via bus 144. In this example embodiment, bus 144 is a 512-bit bus. Buses 143 and 144 are described as bidirectional, thereby supporting both central processing unit 110 data reads and data writes. The primary data cache 123 exchanges data with the secondary combined cache 130 via bus 145. In this example embodiment, bus 145 is a 512-bit bus. Bus 145 is described as bidirectional, thereby supporting cache services for both central processing unit 110 data reads and data writes.

[0053] On a cache hit (if the requested data is stored in the L1 data cache 123), the CPU data request is directly fetched from the L1 data cache 123. On a cache miss (the specified data is not stored in the L1 data cache 123), the data is looked for in the L2 combined cache 130. The memory location of the requested data is a hit or miss in the L2 combined cache 130. A hit is serviced from the L2 combined cache 130. A miss is serviced from another level of cache (not illustrated) or from main memory (not illustrated). The requested instruction can be supplied to both the L1 data cache 123 and the central processing unit core 110 simultaneously to speed up use.

[0054] The second level combined cache 130 supplies the data of the first data stream to the streaming engine 125 via bus 146. In this example embodiment, bus 146 is a 512-bit bus. The streaming engine 125 supplies the data of this first data stream to the functional unit of the vector data path side B 116 via bus 147. In this example embodiment, bus 147 is a 512-bit bus. The second level combined cache 130 supplies the data of the second data stream to the streaming engine 125 via bus 148. In this example embodiment, bus 148 is a 512-bit bus. The streaming engine 125 supplies the data of this second data stream to the functional unit of the vector data path side B 116 via bus 149. In this example embodiment, bus 149 is a 512-bit bus. According to this example embodiment, buses 146, 147, 148 and 149 are described as unidirectional from the second level combined cache 130 to the streaming engine 125 and to the vector data path side B 116.

[0055] On a cache hit (if the requested data is stored in the L2 combined cache 130), the streaming engine data request is directly fetched from the L2 combined cache 130. On a cache miss (the specified data is not stored in the L2 combined cache 130), this data is sought from another level cache (not illustrated) or from main memory (not illustrated). In some embodiments, the L1 data cache 123 may cache data that is not stored in the L2 combined cache 130. If such operation is supported, then when the streaming engine data request misses in the L2 combined cache 130, the L2 combined cache 130 may snoop the L1 data cache 123 for the data requested by the streaming engine. If the L1 data cache 123 stores this data, its snoop response will contain the data, which is then supplied to service the streaming engine request. If the L1 data cache 123 does not store this data, its snoop response will indicate this, and the L2 combining cache 130 will then service this streaming engine request from another level of cache (not illustrated) or from main memory (not illustrated).

[0056] In one embodiment, both the L1 data cache 123 and the L2 combined cache 130 may be configured as selected amounts of cache or directly addressable memory in accordance with US Patent No. 6,606,686 entitled "Unified Memory System Architecture Including Cache and Directly Addressable Static Random Access Memory."

[0057] Figure 2 Further details of the functional units and register files within the scalar datapath side A 115 and the vector datapath side B 116 are described according to one example embodiment. The scalar datapath side A 115 includes a global scalar register file 211, an L1 / S1 local register file 212, an M1 / N1 local register file 213, and a D1 / D2 local register file 214. The scalar datapath side A 115 includes an L1 unit 221, an S1 unit 222, an M1 unit 223, an N1 unit 224, a D1 unit 225, and a D2 unit 226. The vector datapath side B 116 includes a global vector register file 231, an L2 / S2 local register file 232, an M2 / N2 / C local register file 233, and a predicate register file 234. Vector datapath side B 116 includes L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246. These functional units may be configured to read from or write to certain register files, as will be described in detail below.

[0058] The L1 unit 221 can accept two 64-bit operands and produce a 64-bit result. The two operands are each called from an instruction-specified register in the global scalar register file 211 or the L1 / S1 local register file 212. The L1 unit 221 can perform the following instruction-selected operations: 64-bit addition / subtraction operations; 32-bit minimum / maximum operations; 8-bit single instruction multiple data (SIMD) instructions, such as the sum of absolute values, minimum and maximum determination; circular minimum / maximum operations; and various move operations between register files. The result generated by the L1 unit 221 can be written to an instruction-specified register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0059] The S1 unit 222 can accept two 64-bit operands and produce a 64-bit result. The two operands are each called from an instruction-specified register in the global scalar register file 211 or the L1 / S1 local register file 212. In one embodiment, the S1 unit 222 can perform the same type of operations as the L1 unit 221. In other embodiments, there may be slight variations between the data processing operations supported by the L1 unit 221 and the S1 unit 222. The result generated by the S1 unit 222 can be written to an instruction-specified register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0060] The M1 unit 223 can accept two 64-bit operands and produce a 64-bit result. The two operands are each called from an instruction-specified register in the global scalar register file 211 or the M1 / N1 local register file 213. The M1 unit 223 can perform the following instruction-selected operations: 8-bit multiplication operations; complex dot product operations; 32-bit bit count operations; complex conjugate multiplication operations; and bitwise logical operations, moves, additions, and subtractions. The result generated by the M1 unit 223 can be written to an instruction-specified register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0061] The N1 unit 224 can accept two 64-bit operands and produce a 64-bit result. The two operands are each called from an instruction-specified register in the global scalar register file 211 or the M1 / N1 local register file 213. The N1 unit 224 can perform the same type of operation as the M1 unit 223. There may be some dual operations (called dual-issue instructions) that use both the M1 unit 223 and the N1 unit 224 together. The result generated by the N1 unit 224 can be written to an instruction-specified register in the global scalar register file 211, the L1 / S1 local register file 212, the M1 / N1 local register file 213, or the D1 / D2 local register file 214.

[0062] The D1 unit 225 and the D2 unit 226 can each accept two 64-bit operands and each produce a 64-bit result. The D1 unit 225 and the D2 unit 226 can perform address calculations and corresponding load and store operations. The D1 unit 225 is used for 64-bit scalar loads and stores. The D2 unit 226 is used for 512-bit vector loads and stores. The D1 unit 225 and the D2 unit 226 can also perform: swapping, packing and unpacking of load and store data; 64-bit SIMD arithmetic operations; and 64-bit bitwise logical operations. The D1 / D2 local register file 214 will usually store the base address and offset address used in the address calculation for the corresponding load and store. The two operands are each called from the instruction-specified registers in the global scalar register file 211 or the D1 / D2 local register file 214. Results calculated by the D1 unit 225 and / or the D2 unit 226 may be written into instruction-specified registers of the global scalar register file 211 , the L1 / S1 local register file 212 , the M1 / N1 local register file 213 , or the D1 / D2 local register file 214 .

[0063] The L2 unit 221 can accept two 512-bit operands and produce a 512-bit result. Each of the up to two operands is called from an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, or the predicate register file 234. The L2 unit 241 can execute instructions similar to the L1 unit 221, except that it executes on wider 512-bit data. The result generated by the L2 unit 241 can be written to an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, the M2 / N2 / C local register file 233, or the predicate register file 234.

[0064] The S2 unit 242 can accept two 512-bit operands and produce a 512-bit result. Each of the up to two operands is called from an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, or the predicate register file 234. The S2 unit 242 can execute instructions similar to the S1 unit 222, except that it executes on wider 512-bit data. The result generated by the S2 unit 242 can be written to an instruction-specified register in the global vector register file 231, the L2 / S2 local register file 232, the M2 / N2 / C local register file 233, or the predicate register file 234.

[0065] The M2 unit 243 can accept two 512-bit operands and produce a 512-bit result. The two operands are each called from an instruction-specified register in the global vector register file 231 or the M2 / N2 / C local register file 233. The M2 unit 243 can be similar to the M1 unit 222, except that it is executed on wider 512-bit data. The result generated by the M2 unit 243 can be written to the instruction-specified register of the global vector register file 231, the L2 / S2 local register file 232, or the M2 / N2 / C local register file 233.

[0066] The N2 unit 244 can accept two 512-bit operands and produce a 512-bit result. The two operands are each called from the instruction-specified registers in the global scalar register file 231 or the M2 / N2 / C local register file 233. The N2 unit 244 can perform the same type of operation as the M2 unit 243. There may be some dual operations (called dual-issue instructions) that use both the M2 unit 243 and the N2 unit 244 together. The result generated by the N2 unit 224 can be written to the instruction-specified register of the global vector register file 231, the L2 / S2 local register file 232, or the M2 / N2 / C local register file 233.

[0067] The C unit 245 can accept two 512-bit operands and produce a 512-bit result. The two operands are each called from the instruction-specified register in the global vector register file 231 or the M2 / N2 / C local register file 233. The C unit 245 can execute: "seek" and "search" instructions; up to 512 2-bit PN*8-bit multiplications; I / Q complex multiplications per clock cycle; 8-bit and 16-bit sum of absolute differences (SAD) calculations, up to 512 SADs per clock cycle; horizontal addition and horizontal minimum / maximum instructions; and vector permute instructions. In one embodiment, the C unit 245 includes 4 vector control registers (CUCR0 to CUCR3) used to control certain operations of the C unit 245 instructions. In certain C unit 245 operations, the control registers CUCR0 to CUCR3 are used as operands. For example, control registers CUCR0 to CUCR3 may be used to control a general purpose permute instruction (VPERM) or used as a mask for SIMD multiple dot product operations (DOTPM) and SIMD multiple sum of absolute differences (SAD) operations. Control register CUCR0 may be used to store a polynomial for a Galois field multiplication operation (GFMPY). Control register CUCR1 may be used to store a Galois field polynomial generator function.

[0068] The P-unit 246 may perform basic logic operations on registers of the local predicate register file 234. The P-unit 246 may have direct access to read from and write to the predicate register file 234. Operations performed by the P-unit 246 may include AND, ANDN, OR, XOR, NOR, BITR, NEG, SET, BITCNT, RMBDD, BIT extraction, and expansion. One use of the P-unit 246 may include manipulating SIMD vector comparison results for use in controlling another SIMD vector operation.

[0069] Figure 3 An example embodiment of a global scalar register file 211 is described. In the illustrated embodiment, there are 16 independent 64-bit wide scalar registers indicated as A0 to A15. Each register of the global scalar register file 211 can be read or written as 64-bit scalar data. All scalar data path side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can read or write to the global scalar register file 211. The global scalar register file 211 can be read as 32 bits or 64 bits, and can only be written as 64 bits. Instruction execution determines the read data size. The vector datapath side B 116 functional units (L2 unit 241 , S2 unit 242 , M2 unit 243 , N2 unit 244 , C unit 245 , and P unit 246 ) may read from the global scalar register file 211 via the crossbar path 117 , subject to restrictions described in detail below.

[0070] Figure 4 An example embodiment of the D1 / D2 local register file 214 is illustrated. In the illustrated embodiment, there are 16 independent 64-bit wide scalar registers indicated as D0 to D16. Each register of the D1 / D2 local register file 214 can be read or written as 64-bit scalar data. All scalar datapath side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) can write to the D1 / D2 local register file 214. Only the D1 unit 225 and the D2 unit 226 can read from the D1 / D1 local register file 214. The data stored in the D1 / D2 local register file 214 can include a base address and an offset address used in address calculations.

[0071] Figure 5 An example embodiment of the L1 / S1 local register file 212 is illustrated. Figure 5 The embodiment described in has eight independent 64-bit wide scalar registers designated AL0 through AL7. In certain instruction encoding formats (see Fig.13 ), the L1 / S1 local register file 212 may contain up to 16 registers. Figure 5 The embodiment of the present invention implements only 8 registers to reduce circuit size and complexity. Each register of the L1 / S1 local register file 212 can be read or written as 64-bit scalar data. All scalar data path side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226) can write to the L1 / S1 local register file 212. Only the L1 unit 221 and the S1 unit 222 can read from the L1 / S1 local register file 212.

[0072] Figure 6 An example embodiment of the M1 / N1 local register file 213 is illustrated. Figure 6 The embodiment described in has eight independent 64-bit wide scalar registers designated AM0 through AM7. In certain instruction encoding formats (see Fig.13 ), the M1 / N1 local register file 213 may contain up to 16 registers. Figure 6 Embodiment 6 of the present invention implements only 8 registers to reduce circuit size and complexity. Each register of the M1 / N1 local register file 213 can be read or written as 64-bit scalar data. All scalar data path side A115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226) can write to the M1 / N1 local register file 213. Only the M1 unit 223 and the N1 unit 224 can read from the M1 / N1 local register file 213.

[0073] Figure 7 An example embodiment of a global vector register file 231 is described. In the illustrated embodiment, there are 16 independent 512-bit wide vector registers. Each register of the global vector register file 231 can be read or written as 64-bit scalar data indicated as B0 to B15. Each register of the global vector register file 231 can be read or written as 512-bit vector data indicated as VB0 to VB15. The instruction type determines the data size. All vector data path side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can read or write to the global vector register file 231. The scalar data path side A 115 functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226) can read from the global vector register file 231 via the cross path 117 under the restrictions to be described in detail below.

[0074] Figure 8An example embodiment of a P local register file 234 is illustrated. In the illustrated embodiment, there are 8 independent 64-bit wide registers indicated as P0 to P7. Each register of the P local register file 234 can be read or written as 64-bit scalar data. The vector datapath side B 116 functional units L2 unit 241, S2 unit 242, C unit 244, and P unit 246 can write to the P local register file 234. Only the L2 unit 241, S2 unit 242, and P unit 246 can read from the P local register file 234. The P local register file 234 can be used to: write a one-bit SIMD vector comparison result from the L2 unit 241, S2 unit 242, or C unit 244; manipulate the SIMD vector comparison result through the P unit 246; use the manipulated result to control another SIMD vector operation.

[0075] Fig. 9 An example embodiment of the L2 / S2 local register file 232 is illustrated. Fig. 9 The embodiment described in has eight independent 512-bit wide vector registers. In certain instruction encoding formats (see Fig.13 ), the L2 / S2 local register file 232 may contain up to 16 registers. Fig. 9 The embodiment of the present invention implements only 8 registers to reduce circuit size and complexity. Each register of the L2 / S2 local vector register file 232 can be read or written as 64-bit scalar data indicated as BL0 to BL7. Each register of the L2 / S2 local vector register file 232 can be read or written as 512-bit vector data indicated as VBL0 to VBL7. The instruction type determines the data size. All vector data path side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can write to the L2 / S2 local register file 232. Only the L2 unit 241 and the S2 unit 242 can read from the L2 / S2 local vector register file 232.

[0076] Fig.10 An example embodiment of the M2 / N2 / C local register file 233 is illustrated. Fig.10 The embodiment described in has eight independent 512-bit wide vector registers. In certain instruction encoding formats (see Fig.13 ), the M2 / N2 / C local register file 233 may contain up to 16 registers. Fig.10The embodiment of the present invention implements only 8 registers to reduce circuit size and complexity. Each register of the M2 / N2 / C local vector register file 233 can be read or written as 64-bit scalar data indicated as BM0 to BM7. Each register of the M2 / N2 / C local vector register file 233 can be read or written as 512-bit vector data indicated as VBM0 to VBM7. All vector data path side B 116 functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can write to the M2 / N2 / C local vector register file 233. Only the M2 unit 233, N2 unit 244 and C unit 245 can read from the M2 / N2 / C local vector register file 233.

[0077] Thus, according to some described embodiments, a global register file may be accessed by all functional units on one side (e.g., scalar and vector), and a local register file may be accessed by only certain functional units on one side. Some additional embodiments according to this description may be practiced using only one type of register file corresponding to the described global register file.

[0078] The cross path 117 allows limited data exchange between the scalar datapath side A 115 and the vector datapath side B 116. During each operation cycle, one 64-bit data word may be called from the global scalar register file 211 to be used as an operand by one or more functional units of the vector datapath side B 116, and one 64-bit data word may be called from the global vector register file 231 to be used as an operand by one or more functional units of the scalar datapath side A 115. Any scalar datapath side A 115 functional unit (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) may read a 64-bit operand from the global vector register file 231. This 64-bit operand is the least significant bit of the 512-bit data in the accessed register of the global vector register file 231. Scalar data path side A 115 functional unit can use the same 64-bit cross-path data as operand during the same operation cycle. However, in any single operation cycle, only one 64-bit operand is transferred from vector data path side B 116 to scalar data path side A 115. Any vector data path side B116 functional unit (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245 and P unit 246) can read 64-bit operands from global scalar register stack 211. If the corresponding instruction is a scalar instruction, the cross-path operand data is regarded as any other 64-bit operand. If the corresponding instruction is a vector instruction, the upper 448 bits of the operand are filled with zeros. Vector data path side B116 functional unit can use the same 64-bit cross-path data as operand during the same operation cycle. In any single operation cycle, only one 64-bit operand is transferred from scalar data path side A 115 to vector data path side B116.

[0079] The streaming engine 125 transfers data in certain circumstances. Figure 1In an embodiment of the present invention, the streaming engine 125 controls two data streams. The streams contain sequences of elements of a specific type. Programs operating on the streams read the data sequentially, operating on each element in turn. The stream data may have the following basic properties: well-defined start and end times; fixed element size and type throughout the stream; and fixed element order. Therefore, the program cannot randomly seek in the stream. In addition, the stream data is read-only when active. Therefore, the program cannot write to the stream while reading from it. Once the stream is opened, the streaming engine 125: calculates addresses; extracts defined data types from the secondary unified cache 130 (which may require cache services from higher-level memory, i.e., in the case of a cache miss in the secondary unified cache 130); performs data type manipulations (e.g., such as zero extension, sign extension, and / or data element sorting / permutation, such as matrix transposition); and delivers the data directly to a programmed data register file within the CPU 110. Therefore, the streaming engine 125 is useful for real-time digital filtering operations on benign data. The streaming engine 125 releases these memory fetch tasks from the corresponding CPU 110, thereby enabling the CPU 110 to perform other processing functions.

[0080] The streaming engine 125 provides several benefits. For example, the streaming engine 125 allows multi-dimensional memory access, increases the available bandwidth to the functional units of the CPU 110, reduces the number of cache miss stalls due to stream buffers bypassing the primary data cache 123, reduces the number of scalar operations required to maintain loops, and manages address pointers. The streaming engine 125 can also handle address generation, which frees up address generation instruction slots and the D1 unit 225 and D2 unit 226 for other computations.

[0081] The CPU 110 operates on an instruction pipeline. As further described below, instructions are extracted in fixed-length instruction packets. All instructions have the same number of pipeline stages for extraction and decoding, but may have different numbers of execution stages.

[0082] Fig.11 An example embodiment of an instruction pipeline is illustrated having the following pipeline stages: a program fetch stage 1110, a dispatch and decode stage 1120, and an execute stage 1130. The program fetch stage 1110 includes three stages for all instructions. The dispatch and decode stage 1120 includes three stages for all instructions. The execute stage 1130 includes one to four stages depending on the instruction.

[0083] The fetch stage 1110 includes a program address generation stage 1111 (PG), a program access stage 1112 (PA), and a program receive stage 1113 (PR). During the program address generation stage 1111 (PG), a program address is generated in the CPU, and a read request is sent to the memory controller for the first-level instruction cache L1I. During the program access stage 1112 (PA), the first-level instruction cache L1I processes the request, accesses the data in its memory, and sends the fetch packet to the CPU boundary. During the program receive stage 1113 (PR), the CPU registers the fetch packet.

[0084] In the example embodiment, instructions are fetched at a time as sixteen 32-bit wide slots forming a fetch packet. Fig.12 This embodiment is described, wherein a single extraction packet contains sixteen instructions 1201 to 1216. The extraction packet is aligned on a 512-bit (16-word) boundary. In one embodiment, the extraction packet adopts a fixed 32-bit instruction length. Fixed-length instructions have advantages for several reasons. Fixed-length instructions can achieve easy decoder alignment. Correctly aligned instruction extraction can load multiple instructions into a parallel instruction decoder. When stored in a memory coupled with a fixed instruction packet extraction (the extraction packet is aligned on a 512-bit boundary), this correctly aligned instruction extraction can be achieved by a predetermined instruction alignment. Aligning the instruction extraction also allows the parallel decoder to operate on the instruction size extraction bit. Variable-length instructions may require an initial step of locating each instruction boundary before they can be decoded. Fixed-length instruction sets generally allow more regular layout of instruction fields. This simplifies the construction of each decoder, which is an advantage for a large number of VLIW central processors issued.

[0085] The execution of individual instructions is controlled by the p-bit portion of each instruction. This p-bit can be configured as bit 0 of a 32-bit wide slot. The p-bit of an instruction determines whether the instruction is executed in parallel with the next instruction. Instructions are scanned from lower addresses to higher addresses. If the p-bit of an instruction is 1, then the next subsequent instruction (higher memory address) is executed in parallel with the instruction (in the same cycle as it). If the p-bit of an instruction is 0, then the next subsequent instruction is executed in the cycle after the instruction.

[0086] The CPU 110 and the L1 instruction cache L1I 121 pipelines are decoupled from each other. The fetch packet returned from the L1 instruction cache L1I may take different numbers of clock cycles, depending on the external environment, such as whether there is a hit in the L1 instruction cache 121 or a hit in the L2 combined cache 130. Therefore, the program access stage 1112 (PA) may take several clock cycles instead of 1 clock cycle as in other stages.

[0087] Instructions executed in parallel constitute an execution packet. In one embodiment, an execution packet may include up to sixteen instructions (slots). Two instructions in an execution packet may not use the same functional unit. A slot may be one of five types: 1) a self-contained instruction executed on one of the functional units of CPU 110 (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246); 2) a unitless instruction, such as a NOP (no operation) instruction or multiple NOP instructions; 3) a branch instruction; 4) a constant field extension; and 5) a conditional code extension. Some of these slot types will be further explained below.

[0088] The dispatch and decode stage 1120 includes instruction dispatch to the appropriate execution unit stage 1121 (DS), instruction pre-decode stage 1122 (DC1), and instruction decode, operand read stage 1123 (DC2). During instruction dispatch to the appropriate execution unit stage 1121 (DS), fetch packets are divided into execution packets and assigned to the appropriate functional units. During the instruction pre-decode stage 1122 (DC1), the source registers, destination registers, and associated paths are decoded for execution of the instruction in the functional unit. During the instruction decode, operand read stage 1123 (DC2), more detailed unit decoding is completed, and operands are read from the register file.

[0089] The execution stage 1130 includes execution stages 1131 to 1135 (E1 to E5). Different types of instructions may require different numbers of these stages to complete their execution. These stages of the pipeline play an important role in understanding the device state at the CPU cycle boundaries.

[0090] During execution level 1131 (E1), conditions for instructions are evaluated and operands are operated on. Fig.11 As illustrated in , the Execute 1 stage 1131 may receive operands from one of the stream buffers 1141 and the register file, schematically shown as 1142. For load and store instructions, address generation is performed and address modifications are written to the register file. For branch instructions, the branch fetch packet in the PG stage is affected.

[0091] like Fig.11 As described in , load and store instructions access memory, schematically shown here as memory 1151. For single cycle instructions, the result is written to the destination register file. This assumes that all conditions for the instruction are evaluated to true. If the condition is evaluated to false, then after execution 1 stage 1131, the instruction does not write any results or perform any pipeline operations.

[0092] During execution level 2 1132 (E2), a load instruction sends an address to memory. A store instruction sends an address and data to memory. If saturation occurs, a single cycle instruction that saturates the result sets a bit (SAT) in the control status register (CSR). For a 2 cycle instruction, the result is written to the destination register file.

[0093] During execute level 3 1133 (E3), data memory accesses are performed. Any multiplication instruction that saturates the result sets the SAT bit in the control status register (CSR) if saturation occurs. For 3-cycle instructions, the result is written to the destination register file.

[0094] During execution level 4 1134 (E4), load instructions bring data to the CPU boundary. For 4 cycle instructions, the results are written to the destination register file.

[0095] During execution level 5 1135 (E5), a load instruction writes data to a register. Fig.11 Schematically illustrated in , where input is taken from memory 1151 to execute 5 stages 1135.

[0096] Fig.13 An instruction encoding format 1300 for a functional unit instruction according to an example embodiment is illustrated. Other instruction encodings are possible and within the scope of the description herein. In the illustrated embodiment, each instruction comprises 32 bits and controls the operation of one of the individually controllable functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, D2 unit 226, L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246). The bit fields of the instruction encoding 1300 are defined as follows.

[0097] The creg field 1301 (bits 29 to 31) and the z bit 1302 (bit 28) are fields used in conditional instructions. These bits are used for conditional instructions to identify the predicate (also called "condition") register and the condition. The z bit 1302 (bit 28) indicates whether the condition is based on a zero or non-zero in the predicate register. If z=1, then the test is for equal to zero. If z=0, then the test is for non-zero. For unconditional instructions, the creg field 1301 and the z bit 1302 are set to all zeros to allow unconditional instruction execution. The creg field 1301 and the z field 1302 are encoded in the instruction as shown in Table 1.

[0098] Table 1

[0099]

[0100] The execution of conditional instructions depends on the value stored in the specified conditional data register. In the illustrated example, the conditional register is a data register in the global scalar register file 211. The "z" in the z bit column refers to the zero / non-zero comparison selection mentioned above, and "x" is a don't care state. In this example, the use of three bits for the creg field 1301 in this encoding allows only a subset of the 16 global registers (A0 to A5) of the global scalar register file 211 to be specified as predicate registers. This selection is made to retain bits in the instruction encoding and reduce opcode space. The dst field 1303 (bits 23 to 27) specifies a register in the corresponding register file as the destination of the instruction result (e.g., the location where the result will be written).

[0101] The src2 / cst field 1304 (bits 18 to 22) may be interpreted differently depending on the instruction opcode field (bits 4 to 12 for all instructions and additionally bits 28 to 31 for unconditional instructions). The src2 / cst field 1304 indicates the second source operand, either from a register of the corresponding register file or as a constant depending on the instruction opcode field. Depending on the instruction type, when the second source operand is a constant, it may be treated as an unsigned integer and zero extended to the specified data length, or may be treated as a signed integer and a sign extended to the specified data length.

[0102] The src1 field 1305 (bits 13 to 17) specifies a register in the corresponding register file as the first source operand.

[0103] The opcode field 1306 (bits 4 to 12) for all instructions (and additionally bits 28 to 31 for unconditional instructions) specifies the type of instruction and indicates the appropriate instruction options. This includes an indication of the functional units used and the operations performed. Additional details about such instruction options are detailed below.

[0104] The e bit 1307 (bit 2) is used for immediate constant instructions, where the constant may be extended. If e=1, then the immediate constant is extended in the manner detailed below. If e=0, then the immediate constant is not extended. In the latter case, the immediate constant is specified by the src2 / cst field 1304 (bits 18 to 22). The e bit 1307 may only be used for some types of instructions. Therefore, by proper encoding, the e bit 1307 may be omitted from instructions that do not require it, and this bit may be used instead as an extra opcode bit.

[0105] The s bit 1308 (bit 1) indicates the scalar datapath side A 115 or the vector datapath side B 116. If s=0, then the scalar datapath side A 115 is selected, and the available functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225, and D2 unit 226) and register files (global scalar register file 211, L1 / S1 local register file 212, M1 / N1 local register file 213, and D1 / D2 local register file 214) will be corresponding to the following. Figure 2 Similarly, s=1 selects vector datapath side B 116, and the available functional units (L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244, C unit 245, and P unit 246) and register files (global vector register file 231, L2 / S2 local register file 232, M2 / N2 / C local register file 233, and predicate local register file 234) will be those corresponding to the vector datapath side A 115 illustrated in FIG. Figure 2 The functional units and register files of the vector datapath side B 116 illustrated in FIG.

[0106] The p bit 1308 (bit 0) is used to determine whether an instruction is executed in parallel with a subsequent instruction. The p bit is scanned from lower address to higher address. If p=1 for the current instruction, then the next instruction is executed in parallel with the current instruction. If p=0 for the current instruction, then the next instruction is executed in the cycle after the current instruction. All instructions executed in parallel constitute an execution packet. In one example embodiment, an execution packet may contain up to twelve instructions for parallel execution, where each instruction in the execution packet is assigned to a different functional unit.

[0107] In one example embodiment of processor 100, there are two different condition code extension slots (slot 0 and slot 1). In this example embodiment, the condition code extension slots may be 32 bits, such as in Fig.13 Each execution packet may contain each of these 32-bit condition code extension slots, which contains a 4-bit creg / z field (eg, similar to bits 28 to 31 of encoding 1300) for instructions in the same execution packet. Fig.14 illustrates an example encoding for condition code extension slot 0, and Fig.15 An example encoding for condition code extension slot 1 is illustrated.

[0108] Fig.14Example encoding 1400 for condition code extension slot 0 is illustrated. Field 1401 (bits 28 to 31) specifies the 4 creg / z bits assigned to L1 unit 221 instructions in the same execution packet. Field 1402 (bits 27 to 24) specifies the 4 creg / z bits assigned to L2 unit 241 instructions in the same execution packet. Field 1403 (bits 19 to 23) specifies the 4 creg / z bits assigned to S1 unit 222 instructions in the same execution packet. Field 1404 (bits 16 to 19) specifies the 4 creg / z bits assigned to S2 unit 242 instructions in the same execution packet. Field 1405 (bits 12 to 15) specifies the 4 creg / z bits assigned to D1 unit 225 instructions in the same execution packet. Field 1406 (bits 8 to 11) specifies the 4 creg / z bits assigned to D2 unit 226 instructions in the same execution packet. Field 1407 (bits 6 and 7) is unused / reserved. Field 1408 (bits 0 to 5) is encoded with a unique set of bits (CCEX0) to identify conditional code extension slot 0. Once this unique ID of conditional code extension slot 0 is detected, the corresponding creg / z bits are used to control the conditional execution of any L1 unit 221, L2 unit 241, S1 unit 222, S2 unit 242, D1 unit 224, and D2 unit 225 instructions in the same execution packet. These creg / z bits are interpreted as shown in Table 1. If the corresponding instruction is conditional (e.g., the creg / z bits are not all 0), the corresponding bits in conditional code extension slot 0 will overwrite the conditional code bits (bits 28 to 31 of the creg field 1301 and z bits 1302) in the instruction (e.g., encoded using encoding format 1300). In the illustrated example, no execution packet can have more than one instruction directed to a specific execution unit, and no instruction execution packet can contain more than one conditional code extension slot 0. Therefore, the mapping of the creg / z bits to functional unit instructions is unambiguous. As discussed above, setting the creg / z bits equal to "0000" makes the instruction unconditional. Therefore, a correctly encoded conditional code extension slot 0 can make some corresponding instructions conditional and some instructions unconditional.

[0109] Fig.15Example encoding 1500 for condition code extension slot 1 is illustrated. Field 1501 (bits 28 to 31) specifies the 4 creg / z bits assigned to the M1 unit 223 instructions in the same execution packet. Field 1502 (bits 27 to 24) specifies the 4 creg / z bits assigned to the M2 unit 243 instructions in the same execution packet. Field 1503 (bits 19 to 23) specifies the 4 creg / z bits assigned to the C unit 245 instructions in the same execution packet. Field 1504 (bits 16 to 19) specifies the 4 creg / z bits assigned to the N1 unit 224 instructions in the same execution packet. Field 1505 (bits 12 to 15) specifies the 4 creg / z bits assigned to the N2 unit 244 instructions in the same execution packet. Field 1506 (bits 5 to 11) is unused / reserved. Field 1507 (bits 0 to 5) is encoded with a unique set of bits (CCEX1) to identify conditional code extension slot 1. Once this unique ID of conditional code extension slot 1 is detected, the corresponding creg / z bits are employed to control conditional execution of any M1 unit 223, M2 unit 243, C unit 245, N1 unit 224, and N2 unit 244 in the same execution packet. These creg / z bits are interpreted as shown in Table 1. If the corresponding instruction is conditional (e.g., the creg / z bits are not all zero), then the corresponding bits in conditional code extension slot 1 will overwrite the conditional code bits (bits 28 to 31 of the creg field 1301 and z bits 1302) in the instruction (e.g., encoded using encoding format 1300). In the illustrated example, no execution packet can have more than one instruction directed to a particular execution unit, and no instruction execution packet can contain more than one conditional code extension slot 1. Therefore, the mapping of creg / z bits to functional unit instructions is unambiguous. As discussed above, setting the creg / z bits equal to "0000" makes the instruction unconditional. Thus, a correctly encoded conditional code extension slot 1 may make some corresponding instructions conditional and some instructions unconditional.

[0110] Both condition code extension slot 0 1400 and condition code extension slot 1 may include p bits to define an execution packet, as described above in conjunction with Fig.13 In one example embodiment, as described. Fig.14 and 15 As illustrated in , bit 0 of code extension slot 0 1400 and conditional code extension slot 1 1500 may provide p bits. Assuming that the p bits for code extension slots 1400, 1500 are always encoded as 1 (parallel execution), neither code extension slot 1400, 1500 should be the last instruction slot of the execution packet.

[0111] In one example embodiment of processor 100, there are two different constant extension slots. Each execution packet may contain each of these unique 32-bit constant extension slots, which contains 27 bits to be concatenated with the 5-bit constant field in instruction encoding 1300 as high-order bits to form a 32-bit constant. As noted in the instruction encoding 1300 description above, only some instructions define the 5-bit src2 / cst field 1304 as a constant rather than a source register identifier. At least some of those instructions may employ the constant extension slot to extend this constant to 32 bits.

[0112] Fig.16 Example code 1600 illustrating constant extension slot 0. Each execution packet may include one instance of constant extension slot 0 and one instance of constant extension slot 1. Fig.16 Description Constant extension slot 0 1600 includes two fields. Field 1601 (bits 5 to 31) constitutes the most significant 27 bits of the extended 32-bit constant, where the target instruction scr2 / cst field 1304 provides the five least significant bits. Field 1602 (bits 0 to 4) is encoded as a unique set of bits (CSTX0) to identify constant extension slot 0. In an example embodiment, constant extension slot 0 1600 is used to extend the constant of one of the L1 unit 221 instructions, the data in the D1 unit 225 instructions, the S2 unit 242 instructions, the offset in the D2 unit 226 instructions, the M2 unit 243 instructions, the N2 unit 244 instructions, the branch instructions, or the C unit 245 instructions in the same execution packet. Constant extension slot 1 is similar to constant extension slot 0, except that bits 0 to 4 are encoded as a unique set of bits (CSTX1) to identify constant extension slot 1. In an example embodiment, constant extension slot 1 is used to extend a constant of one of an L2 unit 241 instruction, data in a D2 unit 226 instruction, an S1 unit 222 instruction, an offset in a D1 unit 225 instruction, an M1 unit 223 instruction, or an N1 unit 224 instruction in the same execution packet.

[0113] Constant extension slot 0 and constant extension slot 1 are used as follows. The target instruction must be of a type that allows constant specification. As described above with respect to scr2 / cst field 1304, this is implemented by replacing an input operand register specification field with the least significant bit of the constant. The instruction decoder 113 determines this from the instruction opcode bit, referred to as the immediate field. The target instruction also includes a constant extension bit (e bit 1307) that is dedicated to signaling that the specified constant is not extended (e.g., constant extension bit = 0) or that the constant is extended (e.g., constant extension bit = 1). If the instruction decoder 113 detects constant extension slot 0 or constant extension slot 1, it further checks other instructions in that execution packet for the instruction corresponding to the detected constant extension slot. When the corresponding instruction has a constant extension bit (e bit 1307) equal to 1, constant extension will be performed.

[0114] Fig.17 is a block diagram 1700 illustrating constant extension logic that may be implemented in processor 100 . Fig.17 Assume that instruction decoder 113 detects constant extension slot and corresponding instruction in the same execution packet. Instruction decoder 113 supplies 27 extension bits (bit field 1601) from constant extension slot and 5 constant bits (bit field 1304) from corresponding instruction to serial connector 1701. Serial connector 1701 forms a single 32-bit word from these two parts. In the illustrated embodiment, 27 extension bits (bit field 1601) from constant extension slot are the most significant bits, and 5 constant bits (bit field 1305) are the least significant bits. This combined 32-bit word is supplied to one input of multiplexer 1702. 5 constant bits from corresponding instruction field 1305 supply the second input to multiplexer 1702. The selection of multiplexer 1702 is controlled by the state of constant extension bit. If constant extension bit (e bit 1307) is 1 (extended), multiplexer 1702 selects serial connection 32-bit input. If the constant extension bit is 0 (not extended), then multiplexer 1702 selects 5 constant bits from the corresponding instruction field 1305. Multiplexer 1702 supplies this output to the input of sign extension unit 1703.

[0115] The sign extension unit 1703 forms the final operand value from the input from the multiplexer 1703. The sign extension unit 1703 receives the control input scalar / vector and data size. The scalar / vector input indicates whether the corresponding instruction is a scalar instruction or a vector instruction. In this embodiment, the functional units (L1 unit 221, S1 unit 222, M1 unit 223, N1 unit 224, D1 unit 225 and D2 unit 226) of the data path side A 115 are limited to executing scalar instructions. Any instruction directed to one of these functional units is a scalar instruction. The data path side B functional units L2 unit 241, S2 unit 242, M2 unit 243, N2 unit 244 and C unit 245 can execute scalar instructions or vector instructions. The instruction decoder 113 determines whether the instruction is a scalar instruction or a vector instruction based on the opcode bit. In this embodiment, the P unit 246 can only execute scalar instructions. The data size can be 8 bits (byte B), 16 bits (half word H), 32 bits (word W), 64 bits (double word D), quad word (128 bits) data, or half vector (256 bits) data.

[0116] Table 2 lists the operation of the sign extension unit 1703 for various options.

[0117] Table 2

[0118]

[0119] Both constant extension slot 0 and constant extension slot 1 may contain p bits to define execution packets, as shown above in conjunction with Fig.13 In one example embodiment, as in the case of conditional code extension slots, bit 0 of constant extension slot 0 and constant extension slot 1 may provide p bits. Assuming that the p bits for constant extension slot 0 and constant extension slot 1 are always encoded as 1 (parallel execution), then both constant extension slot 0 and constant extension slot 1 should not be in the last instruction slot of the execution packet.

[0120] In some embodiments, an execution packet may include a constant extension slot 0 or 1 and one or more corresponding instructions marked as constant extension (e bit = 1). For constant extension slot 0, this would mean that one or more of the L1 unit 221 instructions, the data in the D1 unit 225 instructions, the S2 unit 242 instructions, the offset in the D2 unit 226 instructions, the M2 unit 243 instructions, or the N2 unit 244 instructions in the execution packet have an e bit of 1. For constant extension slot 1, this would mean that one or more of the L2 unit 241 instructions, the data in the D2 unit 226 instructions, the S1 unit 222 instructions, the offset in the D1 unit 225 instructions, the M1 unit 223 instructions, or the N1 unit 224 instructions in the execution packet have an e bit of 1. In such a case, in one embodiment, the instruction decoder 113 may determine that such a case is an invalid and unsupported operation. In another embodiment, this combination may be supported by applying the extension bit of the constant extension slot to each corresponding functional unit instruction marked as constant extension.

[0121] Special vector predicate instructions use registers in the predicate register file 234 to control vector operations. In the current embodiment, all SIMD vector predicate instructions operate on selected data sizes. The data size may include byte (8-bit) data, half-word (16-bit) data, word (32-bit) data, double-word (64-bit) data, quad-word (128-bit) data, and half-vector (256-bit) data. Each bit of the predicate register controls whether a SIMD operation is performed on the corresponding data byte. The operation of the P unit 246 allows a variety of composite vector SIMD operations based on more than one vector comparison. For example, two comparisons can be used to perform range determination. A candidate vector is compared with a first vector reference having a minimum value of a range packed in a first data register. A second comparison of the candidate vector is performed with a second reference vector having a maximum value of a range packed in a second data register. The logical combination of the two resulting predicate registers will allow vector conditional operations to determine whether each data portion of the candidate vector is within or outside the range.

[0122] The L1 unit 221, S1 unit 222, L2 unit 241, S2 unit 242, and C unit 245 typically operate in a single instruction multiple data (SIMD) mode. In this SIMD mode, the same instruction is applied to packed data from two operands. Each operand holds multiple data elements placed in predetermined slots. SIMD operations are enabled by carrying control at data boundaries. This carry control enables operations on varying data widths.

[0123] Fig.18 Carry control is described. AND gate 1801 receives the carry output of position N in the operand wide arithmetic logic unit (64 bits for the scalar data path side A 115 functional unit and 512 bits for the vector data path side B 116 functional unit). AND gate 1801 also receives a carry control signal, which will be further explained below. The output of AND gate 1801 is supplied to the carry input of position N+1 of the operand wide arithmetic logic unit. For example, the AND gate of AND gate 1801 is placed between each pair of bits at the possible data boundary. For example, for 8-bit data, this AND gate will be between position 7 and position 8, between position 15 and position 16, between position 23 and position 24, etc. Each of these AND gates receives a corresponding carry control signal. If the data size has a minimum value, each carry control signal is 0, thereby effectively blocking the carry transmission between adjacent bits. If the selected data size requires two ALU sections, then the corresponding carry control signal is 1. Table 3 below shows the carry control signals for the case of a 512-bit wide operand (such as the operand used by the vector datapath side B 116 functional unit), which can be divided into 8-bit, 16-bit, 32-bit, 64-bit, 128-bit or 256-bit sections. In Table 3, the upper 32 bits control the upper (bits 128 to 511) carry, and the lower 32 bits control the lower (bits 0 to 127) carry. There is no need to control the carry out of the most significant bit, so only 63 carry control signals are required.

[0124] Table 3

[0125]

[0126] Usually, for integer powers of 2 (2 N ) data size. However, this carry control technique is not limited to integer powers of 2. This technique is applicable to other data sizes and other operand widths.

[0127] The processor 100 includes dedicated instructions for performing table lookup operations implemented via one of the D1 unit 225 or the D2 unit 226. The tables used for these table lookup operations are mapped into the first-level data cache 123 directly addressable memory. An example of this table / cache configuration is described in accordance with US Patent No. 6,606,686 entitled "Unified Memory System Architecture Including Cache and Directly Addressable Static Random Access Memory". These tables can be loaded into the memory space containing the tables through normal memory operations (e.g., via a direct memory access (DMA) port), through a dedicated LUTINIT instruction (described below) or just a normal storage instruction. In an example embodiment, the processor 100 supports up to 4 separate parallel lookup table groups, and in a group, up to 16 tables can be searched in parallel with byte, halfword or word element size. According to this embodiment, at least a portion of the first-level data cache 123 dedicated to directly addressed memory has 16 banks. This allows parallel access to 16 memory locations and supports up to 16 tables per table group.

[0128] These lookup tables are accessed with independently specified base addresses and index addresses. A lookup table base address register (LTBR) specifies the base address for each set of parallel tables. Each lookup table instruction contains a set number for identifying which base address register to use for the instruction. Based on the use of the directly addressable portion of the primary data cache 123, each base address should be aligned with the cache line size of the primary data cache 123. In one embodiment, the cache line size may be 128 bytes.

[0129] The lookup table configuration register for each group of parallel tables is set to control information of the corresponding table group. Fig.19 1900. The data fields of the example lookup table configuration register 1900 are illustrated. The promotion field 1901 (bits 24 and 25) sets the type of promotion after storing an element into a vector register. The promotion field 1901 is decoded as shown in Table 4.

[0130] Table 4

[0131] promote describe 00 No improvement 01 2x boost 10 4x Boost 11 8x improvement

[0132] Field 1901 encodes 00 to indicate no promotion. Field 1901 encodes 01 to indicate 2x promotion. Field 1901 encodes 10 to indicate 4x promotion. Field 1901 encodes 11 to indicate 8x promotion. In one example embodiment, promotion of data is limited to data sizes up to the size of a doubleword (64 bits). Thus, in this embodiment: 2x promotion is valid for data element sizes of byte (promoting from byte (8 bits) to halfword (16 bits)), halfword (promoting from halfword (16 bits) to word (32 bits)), and word (promoting from word (32 bits) to doubleword (64 bits)); 4x promotion is valid for data element sizes of byte (promoting from byte (8 bits) to word (32 bits)) and halfword (promoting from word (16 bits) to doubleword (64 bits)); and 8x promotion is valid only for data element sizes of byte (promoting from byte (8 bits) to doubleword (64 bits)). Promotion will be further explained below.

[0133] Table size field 1902 (bits 16 to 23) sets the table size. Table size field 1902 is decoded as shown in Table 5.

[0134] Table 5

[0135]

[0136] The table base address stored in the corresponding lookup table base address register must align with the table size specified in the lookup table configuration register.

[0137] The signed field 1903 (bit 6) indicates whether the processor 100 treats the called lookup table element as a signed integer or an unsigned integer. If the signed field 1903 is 1, the processor 100 treats the lookup table element as a signed integer. If the signed field 1903 is 0, the processor 100 treats the lookup table element as an unsigned integer.

[0138] The element size (Esize) field 1904 (bits 3 to 5) indicates the lookup table element size. Figure 6 The element size field 1904 is decoded as shown in .

[0139] Table 6

[0140]

[0141] The number of tables (NTBL) field 1905 (bits 0 to 2) indicates the number of tables to be searched in parallel. The number of tables field 1905 is decoded as shown in Table 7.

[0142] Table 7

[0143] The Lookup Table Enable Register 2000 specifies the types of operations allowed for a particular table group. Fig. 20 As explained in Fig. 20 , this example employs fields in a single register to control a corresponding one of four table groups. Field 2001 controls table group 3. Field 2002 controls table group 2. Field 2003 controls table group 1. Field 2004 controls table group 0. Table enable fields 2001, 2002, 2003, and 2004 are each decoded as shown in Table 8.

[0144] Table 8

[0145] Table Enable describe 00 No lookup table operation 01 Read operations allowed 10 reserve 11 Allowed read and write operations

[0146] If the table setting field is 01, then read operations are allowed from the corresponding lookup table base address register and the corresponding lookup table configuration register. If the table group field is 11, then read operations are allowed from the corresponding lookup table base address register and the corresponding lookup table configuration register, and write operations are allowed to the corresponding lookup table base address register and the corresponding lookup table configuration register. If the table group field is 00, then no lookup table operation is allowed.

[0147] Each lookup table instruction specifies a vector register as an operand. This vector register is treated as a set of 32-bit lookup table indexes by the lookup table operation corresponding to the instruction. Table 9 shows the encoding of the vector index in the vector operand register based on the number of tables controlled by the table number field 1906 of the corresponding lookup table configuration register.

[0148] Table 9

[0149] Vector register bits index 1 table 2 tables 4 tables 8 tables 16 tables Vx[31:0] Index 0 efficient efficient efficient efficient efficient Vx[63:32] Index 1 - efficient efficient efficient efficient Vx[95:64] Index 2 - - efficient efficient efficient Vx[127:96] Index 3 - - efficient efficient efficient Vx[159:128] Index 4 - - - efficient efficient Vx[191:160] Index 5 - - - efficient efficient Vx[223:192] Index 6 - - - efficient efficient Vx[255:224] Index 7 - - - efficient efficient Vx[287:256] Index 8 - - - - efficient Vx[319:288] Index 9 - - - - efficient Vx[351:320] Index 10 - - - - efficient Vx[383:352] Index 11 - - - - efficient Vx[415:384] Index 12 - - - - efficient Vx[447:416] Index 13 - - - - efficient Vx[479:448] Index 14 - - - - efficient Vx[511:480] Index 15 - - - - efficient

[0150] The vector register bits specify various indexes depending on the number of tables specified in the number of tables field 1906 of the corresponding lookup table configuration register 1900. The address of the table element within the first table for the lookup table operation is the base address stored in the base address register plus the index specified by bits 0 through 31 of the vector register value. The address of the table element within the second table for the lookup table operation (assuming at least two tables are specified by the number of tables field 1906) is the base address stored in the base address register plus the index specified by bits 32 through 63 of the vector register. Similarly, the vector register specifies an offset for each table specified.

[0151] The following is the form of a Lookup Table Read (LUTRD) instruction according to one example embodiment.

[0152] LUTDR tbl_index, tbl_set, dst

[0153] Tbl_index is an instruction operand that specifies a vector register (e.g., within the general vector register file 231) by a register number. This is interpreted as an index number as shown in Table 9. Tbl_set is a number [0:3] that specifies the table set used in the instruction. This named table set number specifies: the corresponding lookup table base address register that stores the table base address, which can be a scalar register or a vector register; the corresponding lookup table configuration register ( Fig.19 ), which may be a scalar register or a vector register; and a corresponding operation portion of a lookup table enable register ( Fig. 20 ), which can be a scalar register or a vector register. The lookup table base address register corresponding to the named table group determines the base address of the table group. The index of the vector register named by Tbl_index is offset from this table group base address. The lookup table configuration register corresponding to the named table group determines: the promotion mode (Table 4); the amount of memory allocated to the table size (Table 5); the data element size (Table 6); and the number of tables in the table group. Dst is an instruction operand that specifies a vector register (e.g., within the general vector register file 231) as the destination for the table lookup operation by register number. The data called from the table specified by these other parameters is packed and stored in this destination register. The promotion process does not impose any performance penalty.

[0154] Fig.21 1900 specifies a table for that table group. The first level data cache 123 includes a portion of directly addressable memory, which includes a portion 2111 below the lookup table, the lookup table, and a portion 2112 above the lookup table. The corresponding lookup table group base address register 2101 specifies the start of the table group. Fig.21 In the example of , the table number field 1905 specifies a single table. The end of the memory allocated to the table group is specified by the table size field 1902. The index source register 2102 specifies a single offset (index iA) used to address the table. Fig.21 As shown in , a single table uses all 16 memory banks.

[0155] Fig. 22 1900 specifies two tables for that table group. The lookup table group base address register 2101 specifies the start of the table group. The number of tables field 1905 specifies two tables. The end of the memory allocated to the table group is specified by the table size field 1902. The index source register 2102 specifies two offsets used to address the tables. The first index iA ​​addresses table 1, and the second index iB addresses table 2. Table 1 data is stored in memory banks 1 to 8. Table 2 data is stored in memory banks 9 to 16.

[0156] Fig.231900 specifies four tables for that table group. The lookup table group base address register 2101 specifies the start of the table group. The number of tables field 1905 specifies four tables. The end of the memory allocated to the table group is specified by the table size field 1902. The index source register 2102 specifies four offsets used to address the tables. The first index iA ​​addresses table 1, the second index iB addresses table 2, the third index iC addresses table 3, and the fourth index iD addresses table 4. Table 1 data is stored in memory banks 1 to 4. Table 2 data is stored in memory banks 5 to 8. Table 3 data is stored in memory banks 9 to 12. Table 4 data is stored in memory banks 13 to 16.

[0157] Fig.24 1900 specifies eight tables for that table group. The lookup table group base address register 2101 specifies the start of the table group. The number of tables field 1905 specifies eight tables. The end of the memory allocated to the table group is specified by the table size field 1902. The index source register 2102 specifies eight offsets used to address the tables. The first index iA ​​addresses table 1, the second index iB addresses table 2, the third index iC addresses table 3, the fourth index iD addresses table 4, the fifth index iE addresses table 5, the sixth index iF addresses table 6, the seventh index iG addresses table 7, and the eighth index iH addresses table 8. Table 1 data is stored in memory banks 1 and 2. Table 2 data is stored in memory banks 3 and 4. Table 3 data is stored in memory banks 5 and 6. Table 4 data is stored in memory banks 7 and 8. Table 5 data is stored in memory banks 9 and 10. Table 6 data is stored in memory banks 11 and 12. The data of Table 7 is stored in memory banks 13 and 14. The data of Table 8 is stored in memory banks 15 and 16.

[0158] Fig.251900 specifies sixteen tables for that table group. The lookup table group base address register 2101 specifies the start of the table group. The number of tables field 1905 specifies sixteen tables. The end of the memory allocated to the table group is specified by the table size field 1902. The index source register 2102 specifies sixteen offsets used to address the table. The first index iA ​​addresses table 1, the second index iB addresses table 2, the third index iC addresses table 3, the fourth index iD addresses table 4, the fifth index iE addresses table 5, the sixth index iF addresses table 6, the seventh index iG addresses table 7, the eighth index iH addresses table 8, the ninth index iI addresses table 9, the tenth index iJ addresses table 10, the eleventh index iK addresses table 11, the twelfth index iL addresses table 12, the thirteenth index iM addresses table 13, the fourteenth index iN addresses table 14, the fifteenth index iO addresses table 15, and the sixteenth index iP addresses table 16. Table 1 data is stored in memory bank 1. Table 2 data is stored in memory bank 2. Table 3 data is stored in memory bank 3. Table 4 data is stored in memory bank 4. Table 5 data is stored in memory bank 5. Table 6 data is stored in memory bank 6. The data of Table 7 is stored in the memory bank 7. The data of Table 8 is stored in the memory bank 8. The data of Table 9 is stored in the memory bank 9. The data of Table 10 is stored in the memory bank 10. The data of Table 11 is stored in the memory bank 11. The data of Table 12 is stored in the memory bank 12. The data of Table 13 is stored in the memory bank 13. The data of Table 14 is stored in the memory bank 14. The data of Table 15 is stored in the memory bank 15. The data of Table 16 is stored in the memory bank 16.

[0159] Fig.26 An example illustrating the operation of a lookup table read instruction. Fig.26 In the example illustrated in FIG. 1 , the corresponding lookup table configuration register (1900) specifies four parallel tables, a data element size of byte (8 bits), and no promotion. To perform a lookup table operation, the lookup table enable register field (in register 2000) corresponding to the selected table group must enable read operations (01) or both read and write operations (11).

[0160] The lookup table base address register 2101 corresponding to the specified table group stores the base address for the lookup table group, such as Fig.26 The table data is stored in a portion of the L1 data cache 123 configured as directly accessible memory, such as described in US Patent No. 6,606,686 entitled "Unified Memory System Architecture Including Cache and Directly Addressable Static Random Access Memory".

[0161] Fig.26 The example illustrated in has four tables: Table 1 2611; Table 2 2612; Table 3 2613; and Table 4 2614. As shown in Table 9, this instruction with these selected options treats the data stored in the vector source index register 2102 as a set of four 32-bit fields that specify table offsets. The first field (bits Vx[31:0]) stores iA, an index into the first table 2611. In this example, this indexes into element A5. The second field (bits Vx[63:32]) stores iB, an index into the second table 2612. In this example, this indexes into element B1. The third field (bits Vx[95:64]) stores iC, an index into the third table 2613. In this example, this indexes into element C8. The fourth field (bits Vx[127:96]) stores iD, an index into the fourth table 2611. In this example, this indexes into element D10. The various indexes are memory address offsets from the base address for the table group to the specified data element. According to the operation of this lookup table read instruction, the indexed data element in table 1 2611 (A5) is stored in the first data slot in the destination register 2120. The indexed data element in table 2 2612 (B1) is stored in the second data slot in the destination register 2120. The indexed data element in table 3 2613 (C8) is stored in the third data slot in the destination register 2120. The indexed data element in table 4 2614 (D10) is stored in the fourth data slot in the destination register 2120. According to this example implementation, the other data slots of the destination register 2120 are filled with zeros.

[0162] The lookup table read instruction maps the data called from the table directly to the vector lanes of the destination register 2120. The instruction maps earlier elements to lower lane numbers and later elements to higher lane numbers. The lookup table read instruction stores the elements in the vector in increasing lane order. The lookup table read instruction fills each vector lane of the destination register 2120 with the elements called from the table. If the called data is not equal to the vector length, the lookup table read instruction fills the extra lanes of the destination register 2120 with zeros.

[0163] When the promotion mode is enabled (corresponding to the promotion field 1901≠00 of the lookup table configuration register 1900), the lookup table read instruction promotes each called data element to a larger size. Fig. 27 An example of the operation of a lookup table read instruction according to an example embodiment is illustrated. Fig. 27 Description is similar to except that 2x boost is enabled (boost field 1901 is 01). Fig.26 Operation. Fig.26 , each of the four indexes of the vector source index register 2102 calls a data element from a corresponding table. Fig. 27 Description and Fig.26 These data elements are placed differently in the destination register 2120. Each called data element is stored in a slot in the destination register 2120 along with an extension of equal size. This extension is formed to correspond to the signed / unsigned indication of the signed field 1904 of the corresponding lookup table configuration register. If the signed field 1904 indicates unsigned (0), then the extension will be filled with zeros. If the signed field 1904 indicates signed (1), then the extension slot is filled with the same value as the most significant bit (sign bit) of the corresponding data element. This treats the data element as a signed integer.

[0164] Fig.28 An example of the operation of a lookup table read instruction according to an example embodiment is illustrated. Fig.28 Description is similar to except that 4x boost is enabled (boost field 1901 is 10). Fig.26 Each of the four indexes of the vector source index register 2101 calls a data element from each table. Fig.28 Description and Fig.21 These data elements are placed differently in the destination register 2120. Each called data element is stored in a slot in the destination register 2420 along with three equal-sized extensions. These extensions are formed as signed / unsigned indications corresponding to the signed field 1904 of the corresponding lookup table configuration register.

[0165] A data element size of one byte will be similarly implemented. A boost factor of 8x can be similarly implemented. The principles described herein are applicable to other numbers of lookup tables within a selected table group.

[0166] Fig.29A and 29B An example embodiment of the lifting implementation scheme is described together. A temporary register 2950 receives table data called from a primary data cache 123. The temporary register 2950 includes 16 bytes arranged in 16 1-byte blocks, channels 1 to 16. It should be noted that the lengths of these channels are each equal to the minimum value of the data size that can be specified in the element size field 1905. In this example, it is 1 byte / 8 bits. Extension elements 2901 to 2908 form extensions to corresponding channels 1 to 8. Multiple multiplexers 2932 to 2946 couple input channels from temporary registers 2950 to corresponding channels of destination registers 2102. Not all input channels of the temporary register 2950 are coupled to each multiplexer 2932 to 2946. Many multiplexers 2932 to 2946 also receive extension inputs and one or more extension elements 2901 to 2908. Please note that no multiplexer supplies channel 1 of output register 2102. In the embodiment illustrated here, channel 1 of destination register 2102 is always supplied by channel 1 of temporary register 2905.

[0167] Fig.30 illustrate Fig.29A The sign bit (S) of data element N of temporary register 2950 supplies one input of corresponding extension multiplexer 3001. The sign bit of a signed integer is the most significant bit of the value, such as Fig.30 . Constant 0 supplies the second input of multiplexer 3001. Multiplexer 3001 and other similar multiplexers corresponding to other input data elements are controlled by a signed / unsigned signal. This signed / unsigned signal is based on the signed field 1904 of the corresponding lookup table configuration register 1900. If the signed field 1904 is 0, multiplexer 3001 (and corresponding multiplexers for other input channels) selects the constant 0 input. If the signed field 1904 is 1, multiplexer 3001 (and corresponding multiplexers for other input channels) selects the sign bit input. The selected extension is supplied to extension element 3002. Extension element 3002 expands the bit selected by multiplexer 3001 to the channel size. According to this example, the channel size is selected to be equal to the minimum table data element size of 1 byte. For a specified table data size equal to the lane size and where the signed field 1904 is 0, the next data slot is filled with 0s, thereby implementing zero extension. If the signed field 1904 is 1, then the next data slot is filled with the sign bit of the data element, thereby implementing sign extension. Multiplexers 2932 to 2946 select the appropriate extension corresponding to the specified table data element size. If the selected table data element size is a halfword, then the multiplexers 2932 to 2946 are controlled to select extensions from alternating extension elements. If the selected table data element size is a word, then the multiplexers 2932 to 2946 are controlled to select extensions from every fourth extension element.

[0168] Multiplexers 2932 to 2946 consist of Fig.31 1905), a promotion indication (promotion field 1901), and generates corresponding control signals for multiplexers 2932 to 2946. Not all input bytes may supply each output byte. Table 10 illustrates this control. Table 10 shows source data for each of the 16 channels of the destination register 2102 for various data sizes and promotion modes according to an example embodiment.

[0169] Table 10

[0170] 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 --1x 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 b-2x e8 8 e7 7 e6 6 e5 5 e4 4 e3 3 e2 2 e1 1 b-4x e4 e4 e4 4 e3 e3 e3 3 e2 e2 e2 2 e1 e1 e1 1 b-8x e2 e2 e2 e2 e2 e2 e2 2 e1 e1 e1 e1 e1 e1 e1 1 hw-2x e8 e8 8 7 e6 e6 6 5 e4 e4 4 3 e2 e2 2 1 hw-4x e4 e4 e4 e4 e4 e4 4 3 e2 e2 e2 e2 e2 e2 2 1 w-2x e8 e8 e8 e8 8 7 6 5 e4 e4 e4 e4 4 3 2 1

[0171] It should be noted that lane 1 of destination register 2102 is always the same as lane 1 of temporary register 2950, ​​regardless of the selected data size or promotion factor. The column dedicated to lane 1 contains all 1's, and Fig.29A102. A direct connection between lane 1 of temporary register 2950 and destination register 2102 is illustrated. The first row of Table 10 shows that for no promotion (1x), each lane of destination register 2101 is the same as temporary register 2930, regardless of the selected table data element data size. For a data size of bytes and a promotion factor of 2 (b-2x), multiplexer 2932 selects the extension (e1) of lane 1, multiplexer 2933 selects the data for input lane 2, multiplexer 2934 selects the extension (e2) of lane 2, multiplexer 2935 selects the data for input lane 3, multiplexer 2936 selects the extension (e3) of lane 3, and so on. For a data size of bytes and a boost factor of 4 (b-4x), multiplexers 2932 to 2934 select extension (e1) of channel 1, multiplexer 2935 selects data for input channel 2, and multiplexers 2936 to 2938 select extension (e2) of channel 2, multiplexer 2939 selects data for input channel 3, multiplexers 2940 to 2942 select extension (e3) of channel 3, etc. For a data size of bytes and a boost factor of 8 (b-8x), multiplexers 2932 to 2938 select extension (e1) of channel 1, multiplexer 2939 selects data for input channel 2, and multiplexers 2940 to 2946 select extension (e2) of channel 2. For a data size of halfword and a promotion factor of 2 (hw-2x), multiplexer 2932 selects data for channel 2, multiplexers 2933 and 2934 select an extension (e2) of channel 2, multiplexer 2935 selects data for channel 3, multiplexer 2936 selects data for channel 4, multiplexers 2937 and 2938 select an extension (e4) of channel 4, etc. For a data size of halfword and a promotion factor of 4 (hw-4X), multiplexer 2932 selects data for channel 2, multiplexers 2933 to 2938 select an extension (e2) of channel 2, multiplexer 2939 selects data for channel 3, multiplexer 2940 selects data for channel 4, and multiplexers 2941 and 2946 select an extension (e4) of channel 4. For a data size of word and a lifting factor of 3 (w-2x), multiplexer 2932 selects data for channel 2, multiplexer 2933 selects data for channel 3, multiplexer 2934 selects data for channel 4, multiplexers 2935-2938 select an extension (e4) of channel 4, multiplexer 2939 selects data for channel 5, multiplexer 2940 selects data for channel 6, multiplexer 2941 selects data for channel 7, multiplexer 2942 selects data for channel 8, and multiplexers 2943-2946 select an extension of channel 8. As previously described, these are all the combinations of data sizes and lifting factors supported in this example.

[0172] As will be appreciated, the above description and various techniques for lookup table operations are provided herein by way of example only. Therefore, it should be appreciated that this description should not be construed as being limited to only the examples provided above. It should be further appreciated that the various lookup table operation techniques described herein may be implemented in any suitable manner, including hardware (suitably configured circuitry), software (e.g., via a computer program including executable code stored on one or more non-transitory tangible computer-readable media), or via the use of a combination of both hardware elements and software elements.

[0173] Modifications are possible in the arrangements described, and other arrangements are possible within the scope of the claims.

Claims

1. A processor, comprising: a first memory configured to store instructions, wherein each instruction comprises a data processing operation and at least one data operand field; a second memory configured to store a table; a data register file comprising a source index register and a destination register, wherein the source index register is operable to store an index of each of the tables, the index being independent of the indexes of the rest of the tables; and at least one functional unit coupled to the data register file, the second memory, and a decoder, wherein in response to the decoder decoding table read instruction, the at least one operation unit is configured to: calling a set of data elements comprising an element from each of the tables at a respective address based on the index of the respective table in the source index register; as well as The set of data elements are stored in consecutive slots of the destination register.

2. The processor of claim 1, wherein: Each table contains a table enable register field.

3. The processor of claim 2, wherein: The table enable register field enables a read operation or enables both a read and write operation.

4. The processor of claim 1, wherein: Storing the set of data elements in consecutive slots of the destination register is based on a promotion mode; and The promotion mode specifies data size factors for the data elements stored in consecutive slots of the destination register.

5. The processor of claim 4, wherein: The data size factor is selected from one of 0, 2, 4 and 8.

6. The processor of claim 1, further comprising: A temporary register is configured to receive the set of data elements.

7. The processor of claim 6, further comprising: A plurality of multiplexers are operably coupled between the temporary register and the destination register.

8. The processor of claim 6, further comprising: A plurality of extension elements are operably coupled between the temporary register and the plurality of multiplexers.

9. The processor of claim 8, wherein: each extension element comprising an extension multiplexer, wherein a first input of the extension multiplexer is configured to receive a sign bit of a data element from the set of data elements and a second input of the extension multiplexer is configured to receive a zero; Wherein the extension multiplexer is controlled by a signal based on a signed field of a corresponding lookup table configuration register of the data register.

10. The processor of claim 9, wherein: The extension multiplexer selects the sign bit in response to the signed field being 1; and The extension multiplexer selects the 0 input in response to the signed field being 0.

11. A method comprising: storing instructions in the first memory, wherein each instruction comprises a data processing operation and at least one data operand field; storing indices of a plurality of tables in a source index register, wherein each index of the plurality of tables is independent of indices of the rest of the tables; calling a set of data elements comprising an element from each of the tables at a respective address based on the index of the respective table in the source index register; and The set of data elements are stored in consecutive slots of the destination register.

12. The method according to claim 11, wherein: Each table contains a table enable register field.

13. The method according to claim 12, wherein: The table enable register field enables a read operation or enables both a read and write operation.

14. The method according to claim 11, wherein: Storing the set of data elements in consecutive slots of the destination register is based on a promotion mode; and The promotion mode specifies data size factors for the data elements stored in consecutive slots of the destination register.

15. The method according to claim 14, wherein: The data size factor is selected from one of 0, 2, 4 and 8.

16. The method according to claim 11, further comprising: The set of data elements is received at a temporary register.

17. The method according to claim 16, further comprising: The set of data elements from the temporary register is provided to a plurality of multiplexers.

18. The method according to claim 16, further comprising: The set of data elements from the temporary register is provided to a plurality of extension elements.

19. The method according to claim 18, wherein: each extension element comprising an extension multiplexer, wherein a first input of the extension multiplexer is configured to receive a sign bit of a data element from the set of data elements and a second input of the extension multiplexer is configured to receive a zero; Wherein the extension multiplexer is controlled by a signal based on a signed field of a corresponding lookup table configuration register of the data register.

20. The method of claim 19, wherein: The extension multiplexer selects the sign bit in response to the signed field being 1; and The extension multiplexer selects the 0 input in response to the signed field being 0.

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