Memory page table caching method and device, computing equipment and storage medium

Abstract

The invention discloses a memory page table caching method and device, computing equipment and a storage medium, and belongs to the technical field of computers. The method comprises the steps of querying a page table cache based on a target virtual address to determine whether the target virtual address hits the page table cache; if the target virtual address does not hit the page table cache, each page table entry located in a target cache line is obtained from the page table based on the target virtual address, the target cache line is the cache line where the target page table entry is located, and the target page table entry is the page table entry corresponding to the target virtual address; if at least two first page table entries capable of being merged exist in the target cache line, the at least two first page table entries are merged into a first cache table entry, the first cache table entry is stored in the page table cache, and the at least two first page table entries comprise the target page table entry. According to the method, the physical memory capacity covered by the page table cache is increased, the hit rate of the page table cache is improved, the page table walking is reduced, and the memory access delay and overhead are further reduced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, computing equipment and storage medium for caching a memory page table. Background Art

[0002] When accessing memory, processors mostly use virtual addresses (VA) for memory addressing. Using VA can create an addressing space that is much larger than the actual physical address (PA). In the process of using VA for memory addressing, VA needs to be converted to PA, and then memory access is performed based on PA.

[0003] The memory stores a page table (PT), which is also called a memory page table. The PT includes multiple page table entries (PTEs), and one PTE indicates the mapping relationship between a VA and a PA. The processor includes a core, a memory management unit (MMU), a translation lookaside buffer (TLB), etc. In order to reduce the memory access overhead during the address translation process, the mapping relationship indicated by some PTEs is usually cached in the TLB, which is also called a page table cache. The TLB includes multiple cache entries, and one cache entry corresponds to one PTE. In this way, when performing the address translation from VA to PA, the MMU first queries the TLB. If the TLB misses, it queries the PT to obtain the corresponding PTE, refreshes the TLB through the queried PTE, and completes the address translation from VA to PA.

[0004] However, the storage space of TLB is limited, and the number of PTEs in PT is much greater than the number of cache entries in TLB, resulting in a limited physical memory size that can be covered by cache entries in TLB. In this way, TLB misses may occur during the address translation from VA to PA, which in turn increases the memory access overhead when TLB misses. Therefore, how to cache the memory page table has become a major issue of concern at present. Summary of the invention

[0005] The present application provides a memory page table cache method, device, computing device and storage medium, which can increase the physical memory capacity covered by entries in the page table cache, thereby improving the hit rate of the page table cache, reducing page table walks, and further reducing the latency and overhead of memory access. The technical solution is as follows:

[0006] In a first aspect, a method for caching a memory page table is provided, the method comprising: querying a page table cache based on a target virtual address to determine whether the target virtual address hits the page table cache, the page table cache being used to cache mapping relationships indicated by some page table entries in a page table; if the target virtual address does not hit the page table cache, then based on the target virtual address, obtaining from the page table each page table entry located in a target cache line, the target cache line being a cache line where a target page table entry is located, and the target page table entry being a page table entry corresponding to the target virtual address; if there are at least two first page table entries that can be merged in the target cache line, then merging the at least two first page table entries into a first cache table entry, and storing the first cache table entry in the page table cache, the at least two first page table entries including the target page table entry.

[0007] The target virtual address includes the target virtual page number, which includes a string at the head, a string in the middle, and a string at the tail. The number of characters included in the string at the tail is related to the maximum number of page table entries that can be merged into a cache entry in the page table cache. For example, a cache entry can merge up to N page table entries, and N = 2 X , then the number of characters included in the string at the end is greater than or equal to X, N is an integer greater than or equal to 1, and X is an integer greater than or equal to 0. The number of characters included in the string in the middle is related to the maximum number of cache lines in the page table cache. For example, the page table cache can cache a maximum of M cache lines, each cache line includes at least one cache entry, and M = 2 Y , the number of characters included in the middle string is equal to Y, M is an integer greater than or equal to 1, and Y is an integer greater than or equal to 0. The number of characters included in the head string is equal to the number of digits of the target virtual page number minus the number of digits of the middle string and the number of digits of the tail string.

[0008] The string in the middle of the target virtual page number is used as the target table entry index, and the string at the head and the string at the tail of the target virtual page number are combined to obtain the target table entry tag. Based on the target table entry index and the target table entry tag, the page table cache is queried to determine whether the target virtual address hits the page table cache.

[0009] By way of example, the page table cache includes a plurality of cache lines, each of which includes at least one cache entry, and each of which includes a mapping relationship between an entry tag, a merge flag, and a physical page number. Therefore, the cache line indicated by the target entry index is determined from the page table cache. For each cache entry in the cache line indicated by the target entry index, when the merge flag in the cache entry is a first value, the i-th bit of the entry tag in the cache entry is determined, and the i-th bit is the first bit in the entry tag from right to left with a value of 1. If the string between the i+1th bit and the highest bit of the entry tag in the cache entry is the same as the string between the i+1th bit and the highest bit of the target entry tag, then the cache entry is determined to be a cache entry that hits the target virtual address, that is, the target virtual address hits the page table cache. When the merge flag in the cache entry is a second value, if the entry tag in the cache entry is the same as the target entry tag, then the cache entry is determined to be a cache entry that hits the target virtual address, that is, the target virtual address hits the page table cache.

[0010] In the above method, based on the value of the merge flag in the cache table entry, the number of bits involved in the comparison in the target table entry tag and the table entry tag included in the cache table entry is determined, which can ensure that the table entry tag is correctly matched when the cache table entry is a merged table entry, avoid misjudgment of the matching result due to the merged page table entry, and thus ensure the accuracy of the match.

[0011] In the above method, a cache entry in the page table cache corresponds to at least one page table entry, which can increase the physical memory capacity covered by the cache entries in the page table cache, thereby improving the hit rate of the page table cache, reducing page table walks, and further reducing the delay and overhead of memory access.

[0012] Optionally, each of the page table entries in the page table includes a mapping relationship between a virtual page number and a physical page number; obtaining each page table entry located in a target cache line from the page table based on the target virtual address includes: querying the target page table entry from the page table based on the target virtual page number in the target virtual address, the target page table entry being a page table entry corresponding to the target virtual page number; obtaining each page table entry in the target cache line from the page table based on the storage location of the target page table entry.

[0013] The page table cache is used to cache the mapping relationship indicated by some page table entries in the page table, so the target virtual address may hit the page table cache or may not hit the page table cache. In the case where the target virtual address does not hit the page table cache, the page table entries in the page table are obtained by walking the page table. In the present application, the page table entries of a cache line are obtained by walking the page table, so that the page table entries that can be merged in this cache line are merged and stored in the page table cache, so that when performing address translation, the hit rate of the page table cache can be improved and the number of page table walks can be reduced.

[0014] After the target virtual address misses the page table cache, and each page table entry located in the target cache line is obtained from the page table based on the target virtual address, it can be determined whether there is a page table entry in the target cache line whose virtual page number is continuous with the virtual page number in the target page table entry, and whose physical page number is continuous with the physical page number in the target page table entry. If so, these continuous page table entries are determined as at least two first page table entries that can be merged. That is, the virtual page numbers included in the at least two first page table entries are continuous, and the physical page numbers included in the at least two first page table entries are also continuous.

[0015] Optionally, each of the first page table entries includes a mapping relationship between a virtual page number and a physical page number, and the first cache table entry includes a first table entry tag, a first merge flag and a first physical page number; merging the at least two first page table entries into a first cache table entry includes: determining the first table entry tag based on the minimum virtual page number among the virtual page numbers included in the at least two first page table entries; setting the first merge flag to a first value, the first value indicating that the first cache table entry is a merged table entry; setting the first physical page number to the physical page number included in the first page table entry corresponding to the minimum virtual page number.

[0016] Optionally, based on the minimum virtual page number among the virtual page numbers included in the at least two first page table entries, the first table entry label is determined, including: setting the rightmost bit position of the minimum virtual page number to 1 to obtain a reference virtual page number; combining the character string located at the head and the character string located at the tail of the reference virtual page number to obtain a benchmark table entry label; determining a first shift number based on the number of the at least two first page table entries; and shifting the value of the rightmost bit in the benchmark table entry label to the left according to the first shift number to obtain the first table entry label.

[0017] According to the first shift number, when the value of the rightmost bit in the benchmark table item label is shifted left by H-1 bits, the values ​​of the 1st to H-1th bits from right to left in the benchmark table item label are all set to 0 to obtain the first table item label.

[0018] Since the virtual page numbers of the at least two first page table entries participating in the merger are continuous, the character strings located at the head of the at least two first page table entries are the same. After the above transformation, the virtual page numbers included in the at least two first page table entries participating in the merger all correspond to the same entry tag. Therefore, the entry tag generated in the above manner can indicate at least two page table entries in the page table. That is, the first entry tag can indicate the at least two first page table entries in the page table.

[0019] Optionally, storing the first cache table entry to the page table cache includes: determining whether there is at least one cache table entry included in the page table cache that is included in the first cache table entry; if the at least one cache table entry exists in the page table cache, using the first cache table entry to overwrite one of the at least one cache table entry, and invalidating or deleting other cache table entries that are not overwritten in the at least one cache table entry.

[0020] At least one cache table entry in the page table cache that is included by the first cache table entry means: the virtual page number of the at least one cache table entry is within the range of the virtual page numbers of the at least two first page table entries, and the physical page number of the at least one cache table entry is within the range of the physical page numbers of the at least two first page table entries. In other words, the virtual page numbers of the at least two first page table entries constitute a virtual page number range, and the physical page numbers of the at least two first page table entries constitute a physical page number range. If the virtual page number indicated by a cache table entry in the page table cache is within the virtual page number range, and the physical page number indicated by the cache table entry is within the physical page number range, it is determined that the cache table entry is included by the first cache table entry, otherwise, it is determined that the cache table entry is not included by the first cache table entry.

[0021] As an example, the i-th bit in the first table entry tag is determined, and the i-th bit is the first bit in the first table entry tag whose value is 1. For a cache table entry in the page table cache, if the character string between the i+1th bit and the highest bit in the table entry tag included in the cache table entry is the same as the character string between the i+1th bit and the highest bit in the first table entry tag, it is determined that the cache table entry is included in the first cache table entry, otherwise, it is determined that the cache table entry is not included in the first cache table entry.

[0022] If there is at least one cache table entry in the page table cache that is included in the first cache table entry, the first cache table entry is used to overwrite one of the at least one cache table entries, and the other cache table entries that are not overwritten in the at least one cache table entry are invalidated or deleted. This can avoid the same page table entry from being cached repeatedly, saving the occupancy of the page table cache.

[0023] Since the at least two first page table entries include the target page table entry, after the at least two first page table entries are merged into one cache table entry and stored in the page table cache, when performing address translation subsequently, not only can the target virtual address be translated directly by querying the page table cache, but other virtual addresses covered by the at least two first page table entries can also be translated, thereby increasing the physical memory capacity covered by the page table cache, improving the hit rate of the page table cache, reducing page table walks, and thereby reducing the delay and overhead of memory access.

[0024] Optionally, the method also includes: if there are at least two second page table entries that can be merged in the target cache line, merging the at least two second page table entries into a second cache table entry, storing the second cache table entry in the page table cache, and the at least two second page table entries are page table entries other than the at least two first page table entries.

[0025] Optionally, the virtual page numbers included in the at least two first page table entries are continuous and the physical page numbers are also continuous, and the virtual page numbers included in the at least two second page table entries are continuous and the physical page numbers are also continuous;

[0026] The virtual page numbers included in the at least two first page table entries are discontinuous with the virtual page numbers included in the at least two second page table entries, and / or the physical page numbers included in the at least two first page table entries are discontinuous with the physical page numbers included in the at least two second page table entries.

[0027] Optionally, the method also includes: if there is no page table entry that can be merged in the target cache line, determining a target table entry tag based on the target virtual page number in the target virtual address; storing the target cache table entry in the page table cache, the target cache table entry including the target table entry tag, a target merge flag and a target physical page number, the target merge flag indicating that the target cache table entry is an unmerged table entry, and the target physical page number is the physical page number included in the page table entry corresponding to the target virtual address.

[0028] In a second aspect, a memory page table cache device is provided, the device having the function of implementing the memory page table cache method behavior in the first aspect. The device includes at least one module, the at least one module is used to implement the memory page table cache method provided in the first aspect.

[0029] In a third aspect, a computing device is provided, the computing device comprising a processor and a memory, the memory being used to store a computer program for executing the memory page table caching method provided in the first aspect. The processor is configured to execute the computer program stored in the memory to implement the memory page table caching method described in the first aspect.

[0030] Optionally, the computing device may further include a communication bus, which is used to establish a connection between the processor and the memory.

[0031] In a fourth aspect, a computer-readable storage medium is provided, wherein the storage medium stores instructions, and when the instructions are executed on a computer, the computer executes the steps of the memory page table caching method described in the first aspect.

[0032] In a fifth aspect, a computer program product comprising instructions is provided, and when the instructions are executed on a computer, the computer executes the steps of the memory page table caching method described in the first aspect. In other words, a computer program is provided, and when the computer program is executed on a computer, the computer executes the steps of the memory page table caching method described in the first aspect.

[0033] The technical effects obtained by the above-mentioned second, third, fourth and fifth aspects are similar to the technical effects obtained by the corresponding technical means in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0035] Figure 2 It is a flowchart of a memory access method provided in an embodiment of the present application;

[0036] Figure 3 It is a flow chart of a memory page table caching method provided in an embodiment of the present application;

[0037] Figure 4 It is a schematic diagram of the structure of a page table cache provided in an embodiment of the present application;

[0038] Figure 5 It is a schematic diagram of a matching process of a cache entry provided in an embodiment of the present application;

[0039] Figure 6 It is a schematic diagram of merging page table entries provided in an embodiment of the present application;

[0040] Figure 7 It is a structural diagram of a memory page table cache device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0042] For ease of understanding, before explaining in detail the memory page table caching method provided in the embodiment of the present application, the terminology and implementation environment involved in the embodiment of the present application are first introduced.

[0043] First, the terms involved in the embodiments of the present application are introduced.

[0044] 1. Virtual page (VP) and physical page (PP)

[0045] In memory paging management, the virtual address space (or virtual memory) and the physical address space (or physical memory) are divided into multiple storage units of equal capacity. The storage unit divided from the virtual address space is called a virtual page, and the storage unit divided from the physical address space is called a physical page. A physical page can also be called a page frame. The capacity of a virtual page is equal to that of a physical page. The capacity of a virtual page or a physical page can be 4 kilobytes, 2 megabytes, or 1 gigabyte, etc.

[0046] 2. Physical address

[0047] The physical address includes a physical page number (PPN) and a physical page offset (PPO). The physical page number indicates the physical page where the physical address is located, and the physical page offset refers to the offset of the physical address relative to the starting address of the physical page where the physical address is located.

[0048] The physical page number is the high-order part of the physical address, and the physical page offset is the low-order part of the physical address. In other words, the physical page number is the left part or the head of the physical address, and the physical page offset is the right part or the tail of the physical address.

[0049] For example, taking a 32-bit operating system as an example, the physical address is a 32-bit binary form, the physical page number is the upper 20 bits of the physical address (i.e., bits 12 to 31), and the physical page offset is the lower 12 bits of the physical address (i.e., bits 0 to 11).

[0050] 3. Virtual Address

[0051] A virtual address includes a virtual page number (VPN) and a virtual page offset (VPO). The virtual page number indicates the virtual page where the virtual address is located, and the virtual page offset refers to the offset of the virtual address relative to the start address of the virtual page where the virtual address is located.

[0052] The virtual page number is the high-order portion of the virtual address, and the virtual page offset is the low-order portion of the virtual address. In other words, the virtual page number is the left portion or the head of the virtual address, and the virtual page offset is the right portion or the tail of the virtual address.

[0053] For example, taking a 32-bit operating system as an example, the virtual address is in binary form of 32 bits, the virtual page number is the upper 20 bits of the virtual address (i.e., bits 12 to 31), and the virtual page offset is the lower 12 bits of the virtual address (i.e., bits 0 to 11).

[0054] It should be noted that a virtual page number corresponds to a physical page number. For a pair of physical address and virtual address with a mapping relationship, there is a certain mapping relationship or conversion relationship between the physical page number included in the physical address and the virtual page number included in the virtual address, and the physical page offset included in the physical address is the same as the virtual page offset included in the virtual address.

[0055] 4. Page Table

[0056] A page table is a data structure in memory. The page table includes multiple page table entries, each of which indicates a mapping relationship between a virtual address and a physical address. For example, each page table entry includes a mapping relationship between a virtual page number and a physical page number. The computing device can determine the physical page corresponding to the virtual page where the virtual address is located based on the mapping relationship between the virtual page number and the physical page number, and then determine the physical address corresponding to the virtual address based on the virtual page offset.

[0057] 5. Page Table Cache

[0058] The page table cache is a high-speed cache on the processor, also known as TLB. The page table cache includes multiple cache entries, each of which is used to store the mapping relationship indicated by the page table entry queried from the page table. The computing device stores the mapping relationship queried from the page table as a cache entry in the page table cache. Before the computing device queries the mapping relationship in the page table next time, it can query the cache entry in the page table cache first. If the computing device hits any cache entry in the page table cache, it obtains the mapping relationship stored in the cache entry without having to access the page table in the memory, which can save query time.

[0059] 6. Page table walk

[0060] If the computing device does not hit a cache entry in the page table cache, the computing device accesses the page table in the memory to query the mapping relationship in the page table, and stores the queried mapping relationship as a cache entry in the page table cache. This process is called a page table walk.

[0061] 7. Cache line (CL)

[0062] Cache is hardware that caches data in memory. Cache line is the basic unit of cache. Cache line size refers to the data size of a cache line. When a computing device accesses memory, it migrates data in memory to cache in units of cache line size. For example, if the cache line size is N bytes, when a computing device accesses memory, it migrates at least N bytes of data in memory to cache at a time. Therefore, in some cases, every N bytes in memory can also be called a cache line.

[0063] Secondly, the implementation environment involved in the embodiments of the present application is introduced.

[0064] Please refer to Figure 1 , Figure 1 1 is a schematic diagram of a computing device according to an embodiment of the present application. The computing device may be a server or other device, such as a host, a personal computer, etc. The computing device includes at least one processor 101, a communication bus 102, a memory 103, and at least one communication interface 104.

[0065] The processor 101 may be a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, or may be one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0066] The communication bus 102 is used to transmit information between the above components. The communication bus 102 can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 1 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0067] The memory 103 may be a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disc (including a compact disc read-only memory (CD-ROM), a compressed optical disc, a laser disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 103 may exist independently and be connected to the processor 101 via the communication bus 102. The memory 103 may also be integrated with the processor 101.

[0068] The communication interface 104 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 104 includes a wired communication interface and may also include a wireless communication interface. Among them, the wired communication interface may be, for example, an Ethernet interface. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. The wireless communication interface may be a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof, etc.

[0069] As an embodiment, the processor 101 may include one or more CPUs, such as Figure 1 CPU0 and CPU1 are shown in the figure.

[0070] As an example, the computing device 100 may include multiple processors, such as Figure 1 1 and 105. Each of these processors may be a single-core processor or a multi-core processor. A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0071] As an embodiment, the computing device 100 may further include an output device and an input device. The output device communicates with the processor 101 and may display information in a variety of ways. For example, the output device may be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 101 and may receive user input in a variety of ways. For example, the input device may be a mouse, a keyboard, a touch screen device, or a sensor device.

[0072] In some embodiments, the memory 103 is used to store the program code 110 for executing the solution of the present application, and the processor 101 can execute the program code 110 stored in the memory 103. The program code 110 may include one or more software modules, and the computing device 100 may implement the memory page table caching method provided in the embodiment of the present application through the processor 101 and the program code 110 in the memory 103.

[0073] The method provided by the embodiment of the present application can be applied to a memory access scenario, which can also be referred to as a data read and write scenario. In the memory access scenario, before executing a memory access instruction, the computing device first extracts the target virtual address to be converted from the memory access instruction, then determines the target physical address corresponding to the target virtual address, and then performs memory access based on the target physical address. In other words, the memory access instruction carries the target virtual address, and by determining the target physical address corresponding to the target virtual address, memory access is performed based on the target physical address.

[0074] Please refer to Figure 2 The processor of a computing device includes a core, an MMU, and a cache. The MMU is a hardware circuit inside the processor. The MMU may include a page table cache. Of course, the page table cache may also be located in other locations in the processor except the MMU. Next, the TLB is used as the page table cache as an example for explanation.

[0075] The core of the processor sends the memory access instruction to the MMU, and the MMU extracts the target VA to be converted from the memory access instruction, and matches the target VA with the table entry in the TLB to determine whether the target VA hits the TLB. In the case where the target VA hits the TLB, the target PA corresponding to the target VA is determined based on the TLB, and then the data corresponding to the target PA is obtained from the cache. If the data is not in the cache, the data corresponding to the target PA is obtained from the memory. In the case where the target VA misses the TLB, the MMU queries the PT based on the target VA to determine the target PTE, which indicates the mapping relationship between the target VA and the target PA. In this way, the MMU can refresh the TLB based on the target PTE and determine the target PA corresponding to the target VA, and then obtain the data corresponding to the target PA from the cache. If the data is not in the cache, the data corresponding to the target PA is obtained from the memory.

[0076] exist Figure 2 In order to facilitate understanding, PT including VPN, PTE number, PTE address and PPN is used as an example for introduction. In actual applications, PT mainly includes PPN. VPN, PTE number and PTE address are some index, address and other information of PT, which are generally not included in PT. Among them, PTE number refers to the number of PTE, and PTE address refers to the storage address of PTE. TLB includes the mapping relationship between VPN and PPN. A PTE in PT corresponds to a table entry in TLB. Since the storage space of TLB is limited and the number of PTEs in PT is much larger than the number of entries in TLB, the size of physical memory that can be covered by the entries in TLB is limited, which may cause TLB misses during address conversion, and then walking through the page table when TLB misses will increase the memory access overhead.

[0077] Based on this, an embodiment of the present application provides a method for caching a memory page table. When a target virtual address does not hit the page table cache, based on the target virtual address, each page table entry located in the target cache line is obtained from the page table, and the target cache line is the cache line where the page table entry corresponding to the target virtual address is located. If there are at least two first page table entries that can be merged in the target cache line, the at least two first page table entries are merged into one first cache table entry, and the first cache table entry is stored in the page table cache. In this way, when translating the virtual addresses included in the virtual pages corresponding to the at least two first page table entries, the page table cache can be hit, thereby increasing the physical memory capacity covered by the page table cache, improving the hit rate of the page table cache, reducing page table walks, and thereby reducing the delay and overhead of memory access, and improving the performance of the computing device.

[0078] After introducing the terms and implementation environment involved in the embodiments of the present application, the memory page table caching method provided in the embodiments of the present application is explained in detail.

[0079] Figure 3 This is a flow chart of a memory page table caching method provided by an embodiment of the present application. The method is applied to a computing device, and specifically to an MMU included in a processor of the computing device. Please refer to Figure 3 , the method comprises the following steps.

[0080] Step 301: query the page table cache based on the target virtual address to determine whether the target virtual address hits the page table cache, where the page table cache is used to cache mapping relationships indicated by some page table entries in the page table.

[0081] The target virtual address includes the target virtual page number, which includes a string at the head, a string in the middle, and a string at the tail. The number of characters included in the string at the tail is related to the maximum number of page table entries that can be merged into a cache entry in the page table cache. For example, a cache entry can merge up to N page table entries, and N = 2 X , then the number of characters included in the string at the end is greater than or equal to X, N is an integer greater than or equal to 1, and X is an integer greater than or equal to 0. The number of characters included in the string in the middle is related to the maximum number of cache lines in the page table cache. For example, the page table cache can cache a maximum of M cache lines, each cache line includes at least one cache entry, and M = 2 Y , then the number of characters included in the middle string is equal to Y, M is an integer greater than or equal to 1, and Y is an integer greater than or equal to 0. The number of characters included in the head string is equal to the number of digits of the target virtual page number minus the number of digits of the middle string and the number of digits of the tail string. The number of characters in the head string, the number of characters in the middle string, and the number of characters in the tail string included in other subsequent virtual page numbers are the same as those described here and will not be repeated here.

[0082] In some embodiments, the string in the middle of the target virtual page number is used as the target table entry index, and the string at the head and the string at the tail of the target virtual page number are combined to obtain the target table entry tag. Based on the target table entry index and the target table entry tag, the page table cache is queried to determine whether the target virtual address hits the page table cache.

[0083] As an example, the page table cache includes multiple cache lines, each cache line includes at least one cache table entry, and each cache table entry includes a mapping relationship between a table entry tag, a merge flag, and a physical page number. Therefore, based on the target table entry index and the target table entry tag, the page table cache can be queried through the following steps (1)-(3) to determine whether the target virtual address hits the page table cache.

[0084] (1) Determine the cache line indicated by the target table entry index from the page table cache.

[0085] In some embodiments, the page table cache can store cache entries in a multi-line multi-channel (way) structure, where multiple lines of cache entries are stored in each channel, each line corresponds to an entry index, and cache entries in the same line in the multiple channels correspond to the same entry index, and cache entries in the same line in the multiple channels are located in the same cache line. The number of cache entries that can be cached by the page table cache is the product of the number of lines and the number of channels. For example, please refer to Figure 4 , the number of rows and channels of the page table cache are both 64. Figure 4 In the page table cache shown, a maximum of 64×64 cache entries can be stored. The cache entries in the same row in the 64 channels are located in the same cache row and correspond to the same entry index. Each cache entry includes a mapping relationship between an entry tag, a merge flag, and a physical page number. Figure 4 In the figure, way0-way63 schematically represent the 64 channels, set0-set63 schematically represent the table entry indexes of the 64 rows, Tag schematically represents the table entry tag, F schematically represents the merge flag, and PPN schematically represents the physical page number.

[0086] It should be noted that the page table cache may also include other numbers of rows or channels. For example, the page table cache may use a 64-row, 8-channel structure to store cache entries. This embodiment of the application does not limit this.

[0087] Since each row in the page table cache corresponds to an entry index, and the cache entries of the same row in the multiple channels are located in the same cache row, after determining the target entry index from the target virtual page number, the target entry index can be compared with the entry index corresponding to each row in the page table cache, and a row of cache entries in the page table cache whose entry index is the same as the target entry index is determined as each cache entry in the cache row indicated by the target entry index. That is, the cache row where a row of cache entries in the page table cache whose entry index is the same as the target entry index is located is the cache row indicated by the target entry index.

[0088] (2) For each cache entry in the cache row indicated by the target entry index, when the merge flag in the cache entry is the first value, determine the i-th bit of the entry tag in the cache entry, where the i-th bit is the first bit in the entry tag from right to left that takes a value of 1. If the character string between the i+1th bit and the highest bit of the entry tag in the cache entry is the same as the character string between the i+1th bit and the highest bit of the target entry tag, then determine that the cache entry is a cache entry that hits the target virtual address, that is, the target virtual address hits the page table cache.

[0089] If the character string between the i+1th bit and the highest bit of the entry tag in the cache entry is different from the character string between the i+1th bit and the highest bit of the target entry tag, it is determined that the cache entry is not a cache entry that hits the target virtual address, and then the same method is used to determine whether other cache entries are hit by the target virtual address. If other cache entries are not hit by the target virtual address, it is determined that the target virtual address does not hit the page table cache.

[0090] For a merge flag in a cache entry, the merge flag indicates whether the cache entry is a merge entry, that is, whether the cache entry is an entry obtained by merging at least two page table entries. When the merge flag is a first value, it indicates that the cache entry is a merge entry, that is, the cache entry is obtained by merging at least two page table entries. At this time, the entry tag included in the cache table entry is a combination of the character strings at the head and tail of the virtual page number in the page table entry, that is, the position of the first bit with a value of 1 from right to left in the entry tag included in the cache table entry is related to the number of page table entries participating in the merge (please refer to the following description for details), and the character string between the i+1th bit and the highest bit in the entry tag has not changed. Moreover, since the virtual page numbers corresponding to the page table entries participating in the merge are continuous, the left bits in the virtual page numbers of the page table entries participating in the merge are the same. Therefore, the character string between the i+1th bit and the highest bit of the entry tag in the cache table entry can be compared with the character string between the i+1th bit and the highest bit of the target table entry tag to determine whether the cache table entry is a cache table entry that hits the target virtual address.

[0091] It should be noted that the value of the first numerical value is predetermined, and the value of the first numerical value can be 0 or 1. For example, the value of the first numerical value is 0, that is, when the merge flag in a cache entry is 0, it indicates that the cache entry is a merge entry. The embodiment of the present application does not limit the value of the first numerical value.

[0092] (3) When the merge flag in the cache entry is the second value, if the entry tag in the cache entry is the same as the target entry tag, the cache entry is determined to be a cache entry that hits the target virtual address, that is, the target virtual address hits the page table cache.

[0093] If the entry tag in the cache entry is different from the target entry tag, it is determined that the cache entry is not a cache entry hit by the target virtual address. Then, the same method is used to determine whether other cache entries are hit by the target virtual address. If none of the other cache entries are hit by the target virtual address, it is determined that the target virtual address does not hit the page table cache.

[0094] Based on the above description, the merge flag indicates whether the cache entry is a merged entry. When the merge flag in the cache entry is the second value, it indicates that the cache entry is an unmerged entry, that is, the cache entry is not obtained by merging at least two page table entries, and the cache entry corresponds to a page table entry in the page table. At this time, the entry tag in the cache entry is directly obtained by combining the head and tail character strings of the virtual page number in the page table entry without transformation, so the entry tag in the cache entry can be compared with the target entry tag to determine whether the cache entry is a cache entry that hits the target virtual address.

[0095] It should be noted that the value of the second numerical value is predetermined, and the value of the second numerical value can be 0 or 1. For example, the value of the second numerical value is 1, that is, when the merge flag in a cache entry is 1, it indicates that the cache entry is an unmerged entry. The embodiment of the present application does not limit the value of the second numerical value.

[0096] In the above method, based on the value of the merge flag in the cache table entry, the number of bits involved in the comparison in the target table entry tag and the table entry tag included in the cache table entry is determined, which can ensure that the table entry tag is correctly matched when the cache table entry is a merged table entry, avoid misjudgment of the matching result due to the merged page table entry, and thus ensure the accuracy of the match.

[0097] Below through Figure 5 The above process is illustrated with an example. Figure 5 , the target virtual address includes X0 to X7, where Xi represents 4 bits, that is, 4 binary digits, namely Xi3, Xi2, Xi1 and Xi0. Therefore, the number of bits of the target virtual address is 32 bits, of which the number of bits of the virtual page number is 20 bits and the number of bits of the virtual page offset is 12 bits. The page table cache includes 64 (i.e. 2 6 ) cache lines, each of which includes 64 cache entries. The entry indexes of the 64 cache lines are set0-set63, and the number of bits of the string in the middle is 6. Each cache entry can merge up to 64 (i.e., 2 6 ) page table entries, the number of bits of the string at the end is greater than or equal to 6. Figure 5 In the example, the number of the tail character string is 6. Thus, the number of the head character string is 20-6-6=8.

[0098] Then, extract the first 8 characters {X6 X7} and the last 6 characters {X3 X41 X40} of the target virtual page number in the target virtual address to obtain 14 characters, and use these 14 characters to form the target entry tag {T13…T6 T5 T4 T3 T2 T1T0}, and extract the middle 6 characters {X5 X43 X42} of the target virtual page number. Determine the cache line whose entry index is the same as these 6 characters {X5 X43 X42} from the page table cache. Assuming that the entry index set4 is the same as these 6 characters {X5 X43 X42}, compare the entry tags of each cache entry in the cache line indicated by set4 with the target entry tag. Taking the cache entry in way1 as an example, assuming that the entry tag in the cache entry is {B13…B6 B5…B0}, the merge flag in the cache entry is 0, and B5 in {B13…B6 B5…B0} is the first bit with a value of 1 from right to left, then {T13…T6 T5} is compared with {B13…B6 B5}. If the two are the same, it is determined that the target virtual address hits the cache entry, that is, the target virtual address hits the page table cache. Assuming that the merge flag in the cache entry is 1, {T13…T6 T5 T4 T3 T2T1 T0} is compared with {B13…B6 B5…B0}. If the two are the same, it is determined that the target virtual address hits the cache entry, that is, the target virtual address hits the page table cache.

[0099] Step 302: If the target virtual address does not hit the page table cache, then based on the target virtual address, each page table entry located in the target cache line is obtained from the page table, the target cache line is the cache line where the target page table entry is located, and the target page table entry is the page table entry corresponding to the target virtual address.

[0100] Based on the above description, the page table cache is used to cache the mapping relationship indicated by some page table entries in the page table, so the target virtual address may hit the page table cache or may not hit the page table cache. In the case where the target virtual address does not hit the page table cache, the page table entries in the page table are obtained by walking the page table. In an embodiment of the present application, the page table entries of a cache line are obtained by walking the page table, so that the page table entries that can be merged in this cache line are merged and stored in the page table cache, so that when performing address translation, the hit rate of the page table cache can be improved and the number of page table walks can be reduced.

[0101] In some embodiments, each page table entry in the page table includes a mapping relationship between a virtual page number and a physical page number. At this time, based on the target virtual address, the implementation process of obtaining each page table entry located in the target cache line from the page table includes: based on the target virtual page number in the target virtual address, querying the target page table entry from the page table, the target page table entry is the page table entry corresponding to the target virtual page number, and based on the storage location of the target page table entry, obtaining each page table entry in the target cache line from the page table.

[0102] The memory storing the page table includes multiple cache lines, each cache line includes multiple page table entries, and each page table entry includes a mapping relationship between a virtual page number and a physical page number, so the target page table entry is determined based on the target virtual page number. After that, the storage location of the target page table entry is determined, and the target cache line can be determined, thereby obtaining each page table entry in the target cache line.

[0103] In other embodiments, if the target virtual address hits the page table cache, the target physical address corresponding to the target virtual address is determined based on the page table cache. For example, based on the cache entry hit by the target virtual address in the page table cache, the target physical page number corresponding to the target virtual page number is determined, and the target physical page number is combined with the target virtual page offset included in the target virtual address to obtain the target physical address.

[0104] The implementation process of determining the target physical page number corresponding to the target virtual page number based on the cache entry hit by the target virtual address in the page table cache includes the following two cases:

[0105] In the first case, the merge flag included in the cache entry hit by the target virtual address is a first value. At this time, the target physical page number is determined based on the target virtual page number included in the target virtual address, and the entry tag and physical page number in the cache entry hit by the target virtual address.

[0106] When the merge flag included in the cache table entry that hits the target virtual address is the first value, it indicates that the hit cache table entry is a merged table entry, and the physical page number in the hit cache table entry is different from the target physical page number. Therefore, it is necessary to transform the target virtual page number included in the target virtual address, and the entry tag and physical page number in the cache table entry that hits the target virtual address to determine the target physical page number.

[0107] Since the physical page number in the cache entry hit by the target virtual address is the minimum physical page number of at least two page table entries participating in the merge, the entry tag in the cache entry that hits is determined based on the virtual page number corresponding to the minimum physical page number (please refer to the description of the merging process later). Therefore, based on the target virtual page number included in the target virtual address, and the entry tag and physical page number in the cache entry that hits the target virtual address, the implementation process of determining the target physical page number includes: determining the number of pages between the minimum virtual page number and the target virtual page number in at least two page table entries participating in the merge based on the entry tag in the cache entry that hits the target virtual address and the target virtual page number, and determining the target physical page number based on the number of pages between the minimum virtual page number and the target virtual page number and the minimum physical page number.

[0108] Among them, the character string between the i+1th bit and the highest bit in the entry tag included in the hit cache entry is determined as the character string between the i+1th bit and the highest bit in the reference tag, the ith bit is the first bit from right to left in the entry tag with a value of 1, and the values ​​of each bit in the character string between the ith bit and the lowest bit in the reference tag are set to 0. The character string at the head and the character string at the tail of the target virtual page number are combined to obtain the target entry tag, and the difference between the target entry tag and the reference tag is determined as the number of pages between the minimum virtual page number and the target virtual page number. The number of pages in the interval is multiplied by the size of the physical page and then added to the minimum physical page number to obtain the target physical page number.

[0109] Since the virtual page numbers corresponding to the page table entries participating in the merge are continuous, the bits on the left side of the virtual page numbers of the page table entries participating in the merge are the same, and the i-th bit is related to the number of page table entries participating in the merge, the reference tag determined according to the above method can indicate the virtual page where the page table entries participating in the merge are located, and the target table entry tag can indicate the virtual page where the target virtual address is located, and the difference between the target table entry tag and the reference tag is the number of pages between the minimum virtual page number and the target virtual page number.

[0110] The implementation process of determining the reference tag can be expressed by the following formula (1). The implementation process of determining the target physical page number can be expressed by the following formula (2). Based on the target physical page number, the implementation process of determining the target physical address can be expressed by the following formula (3).

[0111] tag2[n:i+1]=vtag[n:i+1], tag2[i:0]=0 (1)

[0112] VPN=PPN+Page Size×(tag1-tag2) (2)

[0113] PA=PPN+Page Size×(tag1-tag2)+VA Offset (3)

[0114] In the above formula (1), tag2[n:i+1] is the string between the i+1th bit and the highest bit in the reference tag, n is the highest bit, vtag[n:i+1] is the string between the i+1th bit and the highest bit in the entry tag included in the hit cache entry, and tag2[i:0] is the string between the i-th bit and the lowest bit in the reference tag. In the above formula (2), VPN is the target physical page number, PPN is the minimum physical page number, that is, the physical page number in the hit cache entry, Page Size is the size of the physical page, tag1 is the target entry tag, and tag2 is the reference tag. In the above formula (3), VA Offset is the target virtual page offset, and the meanings of other letters are the same as in formula (2).

[0115] In the second case, the merge flag bit included in the cache entry hit by the target virtual address is the second value, and the physical page number in the cache entry hit is directly determined as the target physical page number.

[0116] When the merge flag included in the cache table entry that hits the target virtual address is the second value, it indicates that the hit cache table entry is an unmerged table entry, and the physical page number in the hit cache table entry is the same as the target physical page number, so the physical page number in the hit cache table entry is directly determined as the target physical page number.

[0117] Step 303: If there are at least two first page table entries that can be merged in the target cache line, merge the at least two first page table entries into a first cache table entry, store the first cache table entry in the page table cache, and the at least two first page table entries include the target page table entry.

[0118] After the target virtual address misses the page table cache, and each page table entry located in the target cache line is obtained from the page table based on the target virtual address, it can be determined whether there is a page table entry in the target cache line whose virtual page number is continuous with the virtual page number in the target page table entry, and whose physical page number is continuous with the physical page number in the target page table entry. If so, these continuous page table entries are determined as at least two first page table entries that can be merged. That is, the virtual page numbers included in the at least two first page table entries are continuous, and the physical page numbers included in the at least two first page table entries are also continuous. Next, the above step 303 will be introduced in the following steps (1)-(2).

[0119] (1) The at least two first page table entries are merged into a first cache table entry.

[0120] In some embodiments, each first page table entry includes a virtual page number and a physical page number, and the first cache table entry includes a first table entry tag, a first merge flag, and a first physical page number. At this time, based on the minimum virtual page number among the virtual page numbers included in the at least two first page table entries, the first table entry tag is determined, the first merge flag is set to a first value, the first value indicates that the first cache table entry is a merge table entry, and the first physical page number is set to the physical page number included in the first page table entry corresponding to the minimum virtual page number.

[0121] The implementation process of determining the first table item label based on the minimum virtual page number among the virtual page numbers included in the at least two first page table entries includes: setting the rightmost bit position of the minimum virtual page number to 1 to obtain a reference virtual page number, combining the character string located at the head and the character string located at the tail in the reference virtual page number to obtain a reference table item label, determining a first shift number based on the number of the at least two first page table entries, and shifting the value of the rightmost bit in the reference table item label to the left according to the first shift number to obtain the first table item label.

[0122] The implementation process of determining the first shift number based on the number of the at least two first page table entries can be expressed by the following formula (4).

[0123] H=log2C (4)

[0124] In the above formula (4), H is the first shift number, and C is the number of the at least two first page table entries involved in the merge.

[0125] According to the first shift number, when the value of the rightmost bit in the benchmark table item label is shifted left by H-1 bits, the values ​​of the 1st to H-1th bits from right to left in the benchmark table item label are all set to 0 to obtain the first table item label.

[0126] It should be noted that, since the virtual page numbers of the at least two first page table entries participating in the merger are continuous, the character strings located in the header of the at least two first page table entries are the same. After the above transformation, the virtual page numbers included in the at least two first page table entries participating in the merger all correspond to the same table item label, so the table item label generated in the above manner can indicate at least two page table entries in the page table. That is, the first table item label can indicate the at least two first page table entries in the page table.

[0127] (2) The first cache entry is stored in the page table cache.

[0128] In some embodiments, it is determined whether there is at least one cache table entry included in the page table cache and if the at least one cache table entry exists in the page table cache, the first cache table entry is used to overwrite one of the at least one cache table entry, and the other cache table entries in the at least one cache table entry that are not overwritten are invalidated or deleted.

[0129] At least one cache table entry in the page table cache that is included by the first cache table entry means: the virtual page number of the at least one cache table entry is within the range of the virtual page numbers of the at least two first page table entries, and the physical page number of the at least one cache table entry is within the range of the physical page numbers of the at least two first page table entries. In other words, the virtual page numbers of the at least two first page table entries constitute a virtual page number range, and the physical page numbers of the at least two first page table entries constitute a physical page number range. If the virtual page number indicated by a cache table entry in the page table cache is within the virtual page number range, and the physical page number indicated by the cache table entry is within the physical page number range, it is determined that the cache table entry is included by the first cache table entry, otherwise, it is determined that the cache table entry is not included by the first cache table entry.

[0130] As an example, the i-th bit in the first table entry tag is determined, and the i-th bit is the first bit in the first table entry tag whose value is 1. For a cache table entry in the page table cache, if the character string between the i+1th bit and the highest bit in the table entry tag included in the cache table entry is the same as the character string between the i+1th bit and the highest bit in the first table entry tag, it is determined that the cache table entry is included in the first cache table entry, otherwise, it is determined that the cache table entry is not included in the first cache table entry.

[0131] If there is at least one cache entry in the page table cache that is included in the first cache entry, the first cache entry is used to overwrite one of the at least one cache entry, and the other cache entries that are not overwritten in the at least one cache entry are invalidated or deleted, so that the same page table entry can be avoided from being cached repeatedly, saving the page table cache. If there is at least one cache entry in the page table cache that is included in the first cache entry, the first cache entry is inserted according to the elimination strategy of the page table cache, and the embodiment of the present application does not limit the elimination strategy.

[0132] Since the at least two first page table entries include the target page table entry, after the at least two first page table entries are merged into one cache table entry and stored in the page table cache, when performing address translation subsequently, not only can the target virtual address be translated directly by querying the page table cache, but other virtual addresses covered by the at least two first page table entries can also be translated, thereby increasing the physical memory capacity covered by the page table cache, improving the hit rate of the page table cache, reducing page table walks, and thereby reducing the delay and overhead of memory access.

[0133] The above steps (1)-(2) are the case where the target cache line includes at least two first page table entries that can be merged. In actual applications, there may be other cases in the target cache line, which will be introduced below.

[0134] In the first case, there are other cache entries in the page table cache that can be merged with the first cache entry, such as the third cache entry. At this time, the first cache entry can be further merged with the third cache entry, thereby further reducing the occupancy of the page table cache and increasing the physical memory capacity covered by the page table cache.

[0135] In the second case, there are at least two second page table entries in the target cache line. In this case, the at least two second page table entries can be merged and stored. That is, if there are at least two second page table entries that can be merged in the target cache line, the at least two second page table entries are merged into a second cache table entry, and the second cache table entry is stored in the page table cache. The at least two second page table entries are page table entries other than the at least two first page table entries.

[0136] In some embodiments, whether to merge the at least two second page table entries and store them in the page table cache can be determined according to the cache policy. That is, when the cache policy indicates that the at least two second page table entries can be merged and stored, the at least two second page table entries are merged and stored in the page table cache, and when the cache policy indicates that the at least two second page table entries cannot be merged and stored, the at least two second page table entries are not merged. Of course, the at least two second page table entries can also be directly stored in other caches.

[0137] Among them, the method of merging the at least two second page table entries into a second cache table entry and storing the second cache table entry in the page table cache is similar to the processing method of the at least two first page table entries mentioned above. Please refer to the above description for the detailed implementation process, which will not be repeated here.

[0138] In some embodiments, the virtual page numbers included in the at least two first page table entries are continuous and the physical page numbers are also continuous, and the virtual page numbers included in the at least two second page table entries are also continuous; moreover, the virtual page numbers included in the at least two first page table entries are discontinuous with the virtual page numbers included in the at least two second page table entries, and / or the physical page numbers included in the at least two first page table entries are discontinuous with the physical page numbers included in the at least two second page table entries.

[0139] In the third case, there is no page table entry that can be merged in the target cache line. In this case, the target table entry can be directly cached separately in the page table cache. That is, if there is no page table entry that can be merged in the target cache line, the target table entry tag is determined based on the target virtual page number in the target virtual address, and the target cache table entry is stored in the page table cache. The target cache table entry includes the target table entry tag, the target merge flag bit and the target physical page number. The target merge flag bit indicates that the target cache table entry is an unmerged table entry, and the target physical page number is the physical page number included in the page table entry corresponding to the target virtual address.

[0140] It should be noted that whether other entries in the target cache line are cached can be determined based on the cache policy, and the embodiments of the present application do not limit this.

[0141] The method of determining the target entry tag based on the target virtual page number in the target virtual address can be referred to the above description and will not be repeated here. The target merge flag bit can be set to a second value, thereby indicating that the target cache entry is an unmerged entry.

[0142] The above describes the content of caching the page table entry in the target cache line to the page table cache. In the scenario where the method is applied to memory access, after obtaining the target page table entry in step 303, the physical page number in the target page table entry can also be used as the target physical page number, and the target physical page number is combined with the target virtual page offset included in the target virtual address to obtain the target physical address.

[0143] Below Figure 6 Taking the example of merging page table entries into cache table entries and storing the cache table entries in the page table cache, the following example illustrates the process. Figure 6 As shown, the page table entries involved in the merge are PTE1-PTE4, and the computing device supports the merge of two page table entries and the merge of four page table entries, which are introduced below.

[0144] Take supporting the merge of two page table entries as an example. For PTE1 and PTE2 in the page table entries involved in the merge, the entry tag extracted from the virtual page number included in PTE1 is XXXXXXX0000, and the entry tag extracted from the virtual page number included in PTE2 is XXXXXXX0001. The physical page numbers in PTE1 and PTE2 are PPN0 and PPN1, respectively. According to the above method, the entry tag in the cache entry after the two page table entries are merged is XXXXXXX0001, the merge flag in the cache entry is 0, and the physical page number in the cache entry is PPN0. Similarly, for PTE3 and PTE4, according to the above method, the entry tag in the cache entry after the two page table entries are merged is XXXXXXX0011, the merge flag is 0, and the physical page number is PPN2.

[0145] Take the example of supporting the merging of four page table entries. For PTE1-PTE4, the entry tags extracted from the virtual page numbers included in PTE1-PTE4 are XXXXXXX0000, XXXXXXX0001, XXXXXXX0010, and XXXXXXX0011, respectively, and the physical page numbers in PTE1-PTE4 are PPN0, PPN1, PPN2, and PPN3, respectively. At this time, PTE1 and PTE2 can be merged to obtain a cache entry, PTE3 and PTE4 can be merged to obtain another cache entry, and then these two cache entries can be merged to obtain the final cache entry and stored in the page table cache. Among them, the entry tags in the two cache entries obtained after the two-by-two merging of these four page table entries are XXXXXXX0001 and XXXXXXX0011, respectively. According to the above method, the entry tag in the cache entry finally obtained is determined to be XXXXXXX0010.

[0146] Of course, PTE1-PTE4 can also be merged at once, such as Figure 6 As shown, the entry tag in the cache entry merged according to the above method is XXXXXXX0010, the merge flag is 0, and the physical page number is PPN0.

[0147] In the above page table cache method, by merging page table entries, the number of page table entries that can be cached by the page table cache can be increased, and the number of pages covered by the page table cache can be increased, thereby improving the hit rate of the page table cache. Figure 6 As shown in the figure, when PTE is cached in the page table cache without merging, one cache entry can only cover one physical page. When four PTEs are merged into one cache entry, one cache entry can cover two physical pages. When four PTEs are merged into one cache entry, one cache entry can cover four physical pages. It can be seen that this method of merging caches can effectively increase the number of pages covered by the page table cache, thereby improving the hit rate of the page table cache query entries.

[0148] It should be noted that the above Figure 6 The example in which the computing device supports merging two page table entries and four page table entries is used for explanation. In some embodiments, the computing device may also support merging of other numbers of page table entries, which is not limited in the embodiments of the present application. Figure 6 Tag schematically represents an entry tag, F schematically represents a merge flag, and PPN schematically represents a physical page number.

[0149] To sum up, in the method provided in the embodiment of the present application, a cache entry in the page table cache corresponds to at least one page table entry, which can increase the physical memory capacity covered by the cache entries in the page table cache, thereby improving the hit rate of the page table cache, reducing page table walks, and further reducing the latency and overhead of memory access; in addition, when matching the target entry tag with the entry tag in the cache entry, the number of bits involved in the comparison in the target entry tag and the entry tag of the cache entry is determined based on the value of the merge flag bit in the cache entry, which can ensure that the target entry is implemented when the cache entry is a merged entry. The correct matching of tags and cache entries avoids misjudgment of matching results due to merging page table entries, thereby ensuring the accuracy of matching; further, part of the character string in the target virtual page number in the target virtual address is used as the target table entry tag, and the remaining character string is used as the table entry index, so as to first lock the cache line corresponding to the target virtual page number, and then match the target table entry tag with each cache table entry in the cache line respectively, without having to match the target table entry tag with all cache table entries in the page table cache, which can improve the matching efficiency, thereby improving the efficiency of determining the physical address and reducing latency.

[0150] The above describes the caching method of the memory page table provided by the embodiment of the present application. In some embodiments, the page table entries in the page table may change, for example, the physical page number in the page table entry is modified, or the state of the page table entry changes (the virtual page corresponding to the page table entry is swapped in or out), resulting in the previously merged page table entry not being able to accurately indicate the mapping relationship between the virtual page number and the physical page number. The computing device refreshes the page table and the page table cache according to the changed page table entry. If the changed page table entry is a page table entry involved in the merge, the computing device deletes the cache entry corresponding to the page table entry, or sets the cache entry corresponding to the page table entry to invalid, and re-merges the page table entries in the page table.

[0151] Among them, the process of refreshing the page table cache based on the changed page table entry by the computing device includes: if any page table entry in the page table is changed, and the merge flag in the cache entry corresponding to the changed page table entry indicates that the cache entry is a merged entry, then the cache entry corresponding to the changed page table entry is deleted from the page table cache; if any page table entry in the page table is changed, and the merge flag in the cache entry corresponding to the changed page table entry indicates that the cache entry is an unmerged entry, then based on the virtual page number and physical page number corresponding to the changed page table entry, the cache entry corresponding to the changed page table entry is updated. In some embodiments, when the changed page table entry is an entry participating in the merge, the computing device sets the cache entry corresponding to the changed page table entry in the page table cache to invalid.

[0152] In the above method, after the page table entry is changed, the page table and the page table cache are refreshed based on the changed page table entry to ensure the consistency of the cache entry in the page table cache with the page table entry in the page table, thereby ensuring the accuracy of the determined physical address.

[0153] Figure 7 is a schematic diagram of a memory page table cache device provided in an embodiment of the present application. The device can be implemented by software, hardware, or a combination of both to form part or all of a computing device. The computing device can be Figure 1 See the equipment shown. Figure 7 The device includes: a page table cache query module 701, a page table entry acquisition module 702 and a merge cache module 703.

[0154] The page table cache query module 701 is used to query the page table cache based on the target virtual address to determine whether the target virtual address hits the page table cache. The page table cache is used to cache the mapping relationship indicated by some page table entries in the page table. For the detailed implementation process, please refer to the relevant description in the above step 301, which will not be repeated here.

[0155] The page table entry acquisition module 702 is used to obtain each page table entry located in the target cache line from the page table based on the target virtual address if the target virtual address does not hit the page table cache. The target cache line is the cache line where the target page table entry is located, and the target page table entry is the page table entry corresponding to the target virtual address. For the detailed implementation process, please refer to the relevant description in the above step 302, which will not be repeated here.

[0156] The merge cache module 703 is used to merge the at least two first page table entries into a first cache table entry if there are at least two first page table entries that can be merged in the target cache line, and store the first cache table entry in the page table cache, wherein the at least two first page table entries include the target page table entry. For the detailed implementation process, please refer to the relevant description in the above step 303, which will not be repeated here.

[0157] Optionally, each page table entry in the page table includes a mapping relationship between a virtual page number and a physical page number;

[0158] The page table entry acquisition module 702 is specifically used for:

[0159] Based on the target virtual page number in the target virtual address, query the target page table entry from the page table, the target page table entry being the page table entry corresponding to the target virtual page number;

[0160] Based on the storage location of the target page table entry, each page table entry in the target cache line is obtained from the page table.

[0161] Optionally, each first page table entry includes a mapping relationship between a virtual page number and a physical page number, and the first cache table entry includes a first table entry tag, a first merge flag bit, and a first physical page number;

[0162] The merge cache module 703 is specifically used for:

[0163] Determine a first entry tag based on a minimum virtual page number among virtual page numbers included in at least two first page table entries;

[0164] Setting a first merge flag bit to a first value, the first value indicating that the first cache entry is a merge entry;

[0165] The first physical page number is set to be the physical page number included in the first page table entry corresponding to the minimum virtual page number.

[0166] Optionally, the merge cache module 703 is specifically used for:

[0167] Set the rightmost bit of the minimum virtual page number to 1 to obtain the reference virtual page number;

[0168] Combine the character string at the head and the character string at the tail of the reference virtual page number to obtain a reference table entry label;

[0169] determining a first shift amount based on the number of at least two first page table entries;

[0170] According to the first shift number, the value of the rightmost bit in the reference entry tag is shifted left to obtain the first entry tag.

[0171] Optionally, the merge cache module 703 is specifically used for:

[0172] Determining whether there is at least one cache entry included by the first cache entry in the page table cache;

[0173] If there is at least one cache entry in the page table cache, a first cache entry is used to overwrite one of the at least one cache entry, and other cache entries in the at least one cache entry that are not overwritten are invalidated or deleted.

[0174] Optionally, the merge cache module 703 is further used for:

[0175] If there are at least two second page table entries that can be merged in the target cache line, the at least two second page table entries are merged into a second cache table entry, and the second cache table entry is stored in the page table cache, and the at least two second page table entries are page table entries other than the at least two first page table entries.

[0176] Optionally, at least two first page table entries include continuous virtual page numbers and continuous physical page numbers, and at least two second page table entries include continuous virtual page numbers and continuous physical page numbers;

[0177] The virtual page numbers included in the at least two first page table entries are not continuous with the virtual page numbers included in the at least two second page table entries, and / or the physical page numbers included in the at least two first page table entries are not continuous with the physical page numbers included in the at least two second page table entries.

[0178] Optionally, the device further comprises:

[0179] A table entry determination module, configured to determine a target table entry tag based on a target virtual page number in a target virtual address if no page table entry capable of being merged exists in a target cache line;

[0180] The table entry cache module is used to store the target cache table entry into the page table cache. The target cache table entry includes a target table entry tag, a target merge flag and a target physical page number. The target merge flag indicates that the target cache table entry is an unmerged table entry. The target physical page number is the physical page number included in the page table entry corresponding to the target virtual address.

[0181] In an embodiment of the present application, a cache entry in the page table cache corresponds to at least one page table entry, which can increase the physical memory capacity covered by the cache entries in the page table cache, thereby improving the hit rate of the page table cache, reducing page table walks, and further reducing the latency and overhead of memory access; in addition, when matching the target entry tag with the entry tag in the cache entry, the number of bits involved in the comparison in the target entry tag and the entry tag of the cache entry is determined based on the value of the merge flag bit in the cache entry, which can ensure that the target entry tag and the cache entry are matched when the cache entry is a merged entry. Correct matching of table entries avoids misjudgment of matching results due to merging page table entries, thereby ensuring the accuracy of matching; further, part of the character string in the target virtual page number in the target virtual address is used as the target table entry label, and the remaining character string is used as the table entry index, so as to first lock the cache line corresponding to the target virtual page number, and then match the target table entry label with each cache table entry in the cache line respectively, without having to match the target table entry label with all cache table entries in the page table cache, which can improve the matching efficiency, thereby improving the efficiency of determining the physical address and reducing latency.

[0182] It should be noted that: the cache device for storing page tables provided in the above embodiment only uses the division of the above functional modules as an example when caching the page tables. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the cache device for storing page tables provided in the above embodiment and the cache method embodiment for storing page tables belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0183] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital versatile disc (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)). It is worth noting that the computer-readable storage medium mentioned in the embodiment of the present application may be a non-volatile storage medium, in other words, a non-transient storage medium.

[0184] It should be understood that the "multiple" mentioned herein refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate the clear description of the technical solution of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish between the same items or similar items with basically the same functions and effects. Those skilled in the art can understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not limit them to be necessarily different.

[0185] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in the embodiments of the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with relevant laws, regulations and standards of relevant countries and regions.

[0186] The above-mentioned embodiments are provided for the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory page table cache method, characterized in that: The method comprises: Querying a page table cache based on a target virtual address to determine whether the target virtual address hits the page table cache, wherein the page table cache is used to cache mapping relationships indicated by some page table entries in a page table; If the target virtual address does not hit the page table cache, then based on the target virtual address, obtaining each page table entry located in a target cache line from the page table, the target cache line being the cache line where the target page table entry is located, and the target page table entry being the page table entry corresponding to the target virtual address; If there are at least two first page table entries that can be merged in the target cache line, the at least two first page table entries are merged into a first cache entry, and the first cache entry is stored in the page table cache, wherein the at least two first page table entries include the target page table entry.

2. The method according to claim 1, characterized in that Each of the page table entries in the page table includes a mapping relationship between a virtual page number and a physical page number; The acquiring, based on the target virtual address, each page table entry located at the target cache line from the page table comprises: Based on the target virtual page number in the target virtual address, query the target page table entry from the page table, the target page table entry being the page table entry corresponding to the target virtual page number; Based on the storage location of the target page table entry, each page table entry in the target cache line is obtained from the page table.

3. The method according to claim 1, characterized in that Each of the first page table entries includes a mapping relationship between a virtual page number and a physical page number, and the first cache table entry includes a first table entry tag, a first merge flag bit, and a first physical page number; The merging of the at least two first page table entries into a first cache table entry comprises: Determining the first entry tag based on the smallest virtual page number among the virtual page numbers included in the at least two first page table entries; Setting the first merge flag to a first value, wherein the first value indicates that the first cache entry is a merge entry; The first physical page number is set to be the physical page number included in the first page table entry corresponding to the minimum virtual page number.

4. The method according to claim 3, characterized in that The determining the first entry tag based on the minimum virtual page number among the virtual page numbers included in the at least two first page table entries comprises: Set the rightmost bit of the minimum virtual page number to 1 to obtain a reference virtual page number; Combining the character string at the head and the character string at the tail of the reference virtual page number to obtain a reference table entry label; Determining a first shift amount based on the number of the at least two first page table entries; The value of the rightmost bit in the reference entry tag is shifted left according to the first shift amount to obtain the first entry tag.

5. The method according to claim 1, characterized in that The storing the first cache entry into the page table cache includes: Determining whether there is at least one cache entry included in the first cache entry in the page table cache; If the at least one cache entry exists in the page table cache, the first cache entry is used to overwrite one of the at least one cache entry, and other cache entries in the at least one cache entry that are not overwritten are invalidated or deleted.

6. The method according to claim 1, characterized in that The method further comprises: If there are at least two second page table entries that can be merged in the target cache row, the at least two second page table entries are merged into a second cache table entry, and the second cache table entry is stored in the page table cache, and the at least two second page table entries are page table entries other than the at least two first page table entries.

7. The method according to claim 6, characterized in that The at least two first page table entries include continuous virtual page numbers and continuous physical page numbers, and the at least two second page table entries include continuous virtual page numbers and continuous physical page numbers; The virtual page numbers included in the at least two first page table entries are discontinuous with the virtual page numbers included in the at least two second page table entries, and / or the physical page numbers included in the at least two first page table entries are discontinuous with the physical page numbers included in the at least two second page table entries.

8. The method according to claim 1, characterized in that The method further comprises: If there is no page table entry that can be merged in the target cache line, determining a target table entry tag based on a target virtual page number in the target virtual address; The target cache entry is stored in the page table cache, wherein the target cache entry includes the target entry tag, a target merge flag and a target physical page number, wherein the target merge flag indicates that the target cache entry is an unmerged entry, and the target physical page number is the physical page number included in the page table entry corresponding to the target virtual address.

9. A cache device for a memory page table, characterized in that: The device comprises: A page table cache query module, used to query the page table cache based on the target virtual address to determine whether the target virtual address hits the page table cache, the page table cache is used to cache the mapping relationship indicated by some page table entries in the page table; A page table entry acquisition module, configured to acquire, if the target virtual address does not hit the page table cache, each page table entry located in a target cache line from the page table based on the target virtual address, the target cache line being the cache line where the target page table entry is located, and the target page table entry being the page table entry corresponding to the target virtual address; A merge cache module is used to merge the at least two first page table entries that can be merged into a first cache table entry if there are at least two first page table entries that can be merged in the target cache line, and store the first cache table entry in the page table cache, wherein the at least two first page table entries include the target page table entry.

10. The device according to claim 9, characterized in that Each of the page table entries in the page table includes a mapping relationship between a virtual page number and a physical page number; The page table entry acquisition module is specifically used for: Based on the target virtual page number in the target virtual address, query the target page table entry from the page table, the target page table entry being the page table entry corresponding to the target virtual page number; Based on the storage location of the target page table entry, each page table entry in the target cache line is obtained from the page table.

11. The device according to claim 9, characterized in that Each of the first page table entries includes a mapping relationship between a virtual page number and a physical page number, and the first cache table entry includes a first table entry tag, a first merge flag bit, and a first physical page number; The merge cache module is specifically used for: Determining the first entry tag based on the smallest virtual page number among the virtual page numbers included in the at least two first page table entries; Setting the first merge flag to a first value, wherein the first value indicates that the first cache entry is a merge entry; The first physical page number is set to be the physical page number included in the first page table entry corresponding to the minimum virtual page number.

12. The device according to claim 11, characterized in that The merge cache module is specifically used for: Set the rightmost bit of the minimum virtual page number to 1 to obtain a reference virtual page number; Combining the character string at the head and the character string at the tail of the reference virtual page number to obtain a reference table entry label; Determining a first shift amount based on the number of the at least two first page table entries; The value of the rightmost bit in the reference entry tag is shifted left according to the first shift amount to obtain the first entry tag.

13. The device according to claim 9, characterized in that The merge cache module is specifically used for: Determining whether there is at least one cache entry included in the first cache entry in the page table cache; If the at least one cache entry exists in the page table cache, the first cache entry is used to overwrite one of the at least one cache entry, and other cache entries in the at least one cache entry that are not overwritten are invalidated or deleted.

14. The device according to claim 9, characterized in that The merge cache module is also used for: If there are at least two second page table entries that can be merged in the target cache row, the at least two second page table entries are merged into a second cache table entry, and the second cache table entry is stored in the page table cache, and the at least two second page table entries are page table entries other than the at least two first page table entries.

15. The device according to claim 14, characterized in that The at least two first page table entries include continuous virtual page numbers and continuous physical page numbers, and the at least two second page table entries include continuous virtual page numbers and continuous physical page numbers; The virtual page numbers included in the at least two first page table entries are discontinuous with the virtual page numbers included in the at least two second page table entries, and / or the physical page numbers included in the at least two first page table entries are discontinuous with the physical page numbers included in the at least two second page table entries.

16. The device according to claim 9, characterized in that The device also includes: A table entry determination module, configured to determine a target table entry tag based on a target virtual page number in the target virtual address if no page table entry capable of being merged exists in the target cache line; A table entry cache module is used to store a target cache table entry into the page table cache, wherein the target cache table entry includes the target table entry tag, a target merge flag and a target physical page number, wherein the target merge flag indicates that the target cache table entry is an unmerged table entry, and the target physical page number is the physical page number included in the page table entry corresponding to the target virtual address.

17. A computing device, characterized in that The computing device includes a processor and a memory; The processor is configured to execute instructions stored in the memory, so that the computing device performs the method according to any one of claims 1 to 8.

18. A computer-readable storage medium, characterized in that: The storage medium stores instructions, and when the instructions are executed on the computer, the computer is enabled to execute the method according to any one of claims 1 to 8.

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