DMA controller, chip, root complex and endpoint device

Abstract

The invention discloses a DMA controller, a chip, a root complex and endpoint equipment, and belongs to the field of communication. The DMA controller provided by the invention is applied to RC or EP. The DMA controller comprises an acquisition module and a control module, the acquisition module is used for acquiring DMA control information from a target processor, the DMA control information comprises information of a target memory, and the information of the target memory is used for indicating a storage position of a description character linked list; the acquisition module is further used for determining a target memory according to the DMA control information and acquiring description character information in the description character linked list from the target memory, and the target memory comprises an RC memory or an EP memory; and the control module is used for transmitting data between the RC memory and the EP memory according to the description character information in the description character linked list. The DMA controller can be used for RC and also can be used for EP, reusability is achieved, and the problem that in the related technology, the application scene of the DMA controller is single is solved.

Description

Technical Field

[0001] The present application belongs to the field of communications, and specifically relates to a DMA controller, a chip, a root complex and an endpoint device. Background Art

[0002] In the field of communications, communication devices such as 5G and 4G all support the RC (Root Complex) mode (master mode) and EP (End Point) mode (slave mode) of the PCIe (Peripheral Component Interconnect Express) high-speed interface. In the RC mode, the communication device can be used as a master device to connect to an external expansion device, and in the EP mode, the communication device can be used as a slave device to connect to a host computer.

[0003] In the related art, in RC mode, the communication device can be used as a master device to use a DMA (Direct Memory Access) controller to transmit data to improve the data transmission rate between the communication device and the external expansion device. Alternatively, in EP mode, the communication device can be used as a slave device to use another DMA controller to transmit data to improve the data transmission rate between the communication device and the host computer.

[0004] However, since the existing DMA controller cannot be used in a communication device that supports multiple modes (for example, supporting both the RC mode and the EP mode), the related art has the problem of a single application scenario of the DMA controller. Summary of the invention

[0005] The embodiments of the present application provide a DMA controller, a chip, a root complex, and an endpoint device, which can solve the problem of a single application scenario of the DMA controller in the related art.

[0006] In a first aspect, an embodiment of the present application provides a DMA controller, the DMA controller is applied to a root complex RC or an endpoint device EP, the DMA controller includes: an acquisition module and a control module;

[0007] The acquisition module is used to acquire DMA control information from a target processor, wherein the DMA control information includes information of a target memory, and the information of the target memory is used to indicate a storage location of a description character linked list;

[0008] The acquisition module is further used to determine a target memory according to the DMA control information, and acquire description character information in a description character linked list from the target memory, wherein the target memory includes an RC memory or an EP memory;

[0009] The control module is used for performing data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.

[0010] In a second aspect, an embodiment of the present application provides a chip, comprising: a processor, a memory and a DMA controller as described in the first aspect, wherein the processor is connected to the memory and the DMA controller respectively, and the memory is connected to the DMA controller.

[0011] In a third aspect, an embodiment of the present application provides a root complex, including: an RC processor, an RC memory, a DMA controller as described in the first aspect, and a first PCIe controller;

[0012] The RC processor is connected to the RC memory and the DMA controller respectively, the RC memory is connected to the DMA controller, and the DMA controller is connected to the first PCIe controller.

[0013] In a fourth aspect, an embodiment of the present application provides an endpoint device, including: an EP processor, an EP memory, a DMA controller as described in the first aspect, and a second PCIe controller;

[0014] The EP processor is connected to the EP memory and the DMA controller respectively, the EP memory is connected to the DMA controller, and the DMA controller is connected to the second PCIe controller.

[0015] In an embodiment of the present application, a DMA controller includes an acquisition module and a control module; the acquisition module is used to acquire DMA control information from a target processor, the DMA control information includes information of a target memory, and the information of the target memory is used to indicate the storage location of a description character list; the acquisition module is also used to determine the target memory according to the DMA control information, and acquire the description character information in the description character list from the target memory, the target memory includes an RC memory or an EP memory; the control module is used to transfer data between the RC memory and the EP memory according to the description character information in the description character list. In this way, the DMA controller can determine the storage location of the description character list according to the DMA control information from the target processor, and then the DMA controller can acquire the description character information by accessing the local memory or the peer memory according to the storage location of the description character list, and can switch the direction in which the DMA controller reads the description character information, so that the DMA controller can be used for both RC and EP, solving the problem of a single application scenario of the DMA controller in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1is a schematic structural diagram of a DMA controller provided in an embodiment of the present application;

[0017] Figure 2 is a schematic structural diagram of another DMA controller provided in an embodiment of the present application;

[0018] Figure 3 is a schematic structural diagram of another DMA controller provided in an embodiment of the present application;

[0019] Figure 4 is a schematic structural diagram of another DMA controller provided in an embodiment of the present application;

[0020] Figure 5 is a schematic diagram provided in an embodiment of the present application describing that a character linked list is stored in a non-continuous storage space of a target memory;

[0021] Figure 6 is a schematic structural diagram of a chip provided in an embodiment of the present application;

[0022] Figure 7 is a schematic diagram of data transmission between a root complex and an endpoint device provided in an embodiment of the present application;

[0023] Figure 8 This is a schematic diagram of another root complex and endpoint device performing data transmission provided in an embodiment of the present application.

[0024] Description of reference numerals:

[0025] 100 - DMA controller; 110 - acquisition module; 120 - control module; 1201 - parsing module; 1202 - data channel control module; 130 - status write-back module; 140 - interrupt reporting module. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0027] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0028] The applicant has noticed that in the related art, the existing DMA controller cannot be used in a communication device that supports multiple modes (for example, supporting both the RC mode and the EP mode), and there is a problem that the application scenario of the DMA controller is single.

[0029] Based on this, an embodiment of the present application provides a DMA controller, which can determine the storage location of the description character list based on the DMA control information from the target processor. Then, the DMA controller can obtain the description character information by accessing the local memory or the peer memory according to the storage location of the description character list. The direction in which the DMA controller reads the description character information can be switched, so that the DMA controller can be used for both RC and EP. Compared with the related art, the DMA controller is reusable, which solves the problem of the single application scenario of the DMA controller in the related art.

[0030] The DMA controller, chip, root complex and endpoint device provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0031] Figure 1 It is a schematic structural diagram of a DMA controller provided in an embodiment of the present application.

[0032] like Figure 1 As shown, the DMA controller 100 provided in the embodiment of the present application is applied to RC or EP and may include: an acquisition module 110 and a control module 120;

[0033] The acquisition module 110 is used to acquire DMA control information from a target processor, wherein the DMA control information includes information of a target memory, and the information of the target memory is used to indicate a storage location of a description character linked list;

[0034] The acquisition module 110 is further used to determine the target memory according to the DMA control information, and acquire the description character information in the description character linked list from the target memory, wherein the target memory includes an RC memory or an EP memory;

[0035] The control module 120 is used to perform data transmission between the RC memory and the EP memory according to the description character information in the description character chain table.

[0036] In the embodiment of the present application, the target processor may be an RC processor or an EP processor, and the present application does not impose any specific limitation.

[0037] For example, when the DMA controller is applied to RC, the target processor may be the RC processor, in which case the RC processor is a local processor, and the RC processor communicates with the DMA controller via the AXI bus, and the acquisition module of the DMA controller may acquire DMA control information from the RC processor via the AXI bus. Alternatively, when the DMA controller is applied to RC, the target processor may also be the EP processor, in which case the EP processor is a peer processor, and the EP processor communicates with the DMA controller via the PCIe bus, and the acquisition module of the DMA controller may acquire DMA control information from the EP processor via the PCIe bus.

[0038] For another example, when the DMA controller is applied to the EP, the target processor may be the RC processor, in which case the RC processor is the peer processor, and the RC processor communicates with the DMA controller via the PCIe bus, and the acquisition module of the DMA controller can obtain DMA control information from the RC processor via the PCIe bus. Alternatively, when the DMA controller is applied to the EP, the target processor may also be the EP processor, in which case the EP processor is the local processor, and the EP processor communicates with the DMA controller via the AXI bus, and the acquisition module of the DMA controller can obtain DMA control information from the EP processor via the AXI bus.

[0039] In an embodiment of the present application, the DMA control information may be configuration information pre-set by the target processor to control how the DMA controller works. For example, the DMA control information may include information of the target memory, and the information of the target memory is used to indicate the storage location of the description character list, and the target memory may be an RC memory or an EP memory. Among them, the description character list includes at least one description character information, and the description character information can be used to indicate the relevant control parameters of the DMA controller to carry data.

[0040] In practical applications, the DMA control information may also include DMA enable information, doorbell information, and other information used to instruct the DMA controller to start working, and this application does not make any specific restrictions here.

[0041] In the embodiment of the present application, when the DMA controller is applied to RC, the target memory may be an RC memory, in which case the RC memory is a local memory, the RC memory communicates with the DMA controller via an AXI bus, and the acquisition module of the DMA controller may acquire the description character information in the description character linked list from the RC memory via the AXI bus. Alternatively, when the DMA controller is applied to RC, the target memory may also be an EP memory, in which case the EP memory is a peer memory, the EP memory communicates with the DMA controller via a PCIe bus, and the acquisition module of the DMA controller may acquire the description character information in the description character linked list from the EP memory via the PCIe bus.

[0042] In the embodiment of the present application, when the DMA controller is applied to the EP, the target memory may be the RC memory, in which case the RC memory is the peer memory, the RC memory communicates with the DMA controller via the PCIe bus, and the acquisition module of the DMA controller may acquire the description character information in the description character linked list from the RC memory via the PCIe bus. Alternatively, when the DMA controller is applied to the EP, the target memory may also be the EP memory, in which case the EP memory is the local memory, the EP memory and the DMA controller may communicate via the AXI bus, and the acquisition module of the DMA controller may acquire the description character information in the description character linked list from the EP memory via the AXI bus.

[0043] It can be understood that the embodiment of the present application configures DMA control information for the DMA controller in advance through the target processor, and informs the DMA controller of the storage location of the description character list. Then, the DMA controller can obtain the description character information by accessing the local memory through the AXI link or accessing the peer memory through the PCIe link according to the storage location of the description character list. This improves the flexibility of the target processor in controlling the DMA controller, can switch the direction in which the DMA controller reads the description character information, and broadens the application scenarios of the DMA controller, so that the DMA controller can be used for both RC and EP.

[0044] In particular, for communication devices compatible with RC mode and EP mode, the related art requires the design of two different DMA controllers for communication devices in RC mode and EP mode, while the DMA controller provided in the embodiment of the present application can be used in both the RC mode and the EP mode of the communication device, and has reusability. Compared with the related art, it broadens the application scenarios of the DMA controller and reduces the cost of the DMA controller in the communication device, thereby solving the problem of the single application scenario of the DMA controller in the related art.

[0045] According to the DMA controller provided in the embodiment of the present application, the DMA controller includes an acquisition module and a control module; the acquisition module is used to acquire DMA control information from the target processor, the DMA control information includes information of the target memory, and the information of the target memory is used to indicate the storage location of the description character list; the acquisition module is also used to determine the target memory according to the DMA control information, and acquire the description character information in the description character list from the target memory, the target memory includes an RC memory or an EP memory; the control module is used to transfer data between the RC memory and the EP memory according to the description character information in the description character list. In this way, the DMA controller can determine the storage location of the description character list according to the DMA control information from the target processor, and then the DMA controller can acquire the description character information by accessing the local memory or accessing the peer memory according to the storage location of the description character list, and can switch the direction in which the DMA controller reads the description character information, so that the DMA controller can be used for both RC and EP, solving the problem of a single application scenario of the DMA controller in the related art.

[0046] Figure 2 It is a schematic structural diagram of another DMA controller provided in an embodiment of the present application.

[0047] In a specific embodiment, Figure 2 As shown, in the DMA controller 100 provided in the embodiment of the present application,

[0048] The control module 120 may include a parsing module 1201 and a data channel control module 1202;

[0049] The parsing module 1201 is used to extract the description character information, convert the description character information into data transport information in a target instruction format, and transmit the data transport information to the data channel control module;

[0050] The data channel control module 1202 is used to perform data transmission between the RC memory and the EP memory according to the data handling information.

[0051] The data channel control module 1202 may be a data channel controller, and the target instruction format may be an instruction required by the data channel controller. For example, when the amount of information describing the character information is relatively large, the parsing module 1201 may decompose the describing character information, extract the information required by the data channel controller from the describing character information, and convert it into the data handling information required by the data channel controller, so that the data channel controller can perform data transmission between the RC memory and the EP memory according to the data handling information.

[0052] For example, in an embodiment of the present application, the description character information may include at least one of a data description character, a state description character, and a link connection description character.

[0053] Among them, the data description character can be used to store the source address, target address, data block length, etc. of the DMA transferred data.

[0054] Among them, the status description character can be used to store the DMA execution result, and is physically stored in the same location as the corresponding data description character (ie, it covers the original data description character). When the designated processor finishes reading the status description character, this storage space can be reclaimed.

[0055] The chain connection description characters can be used to connect the description characters stored in discrete storage spaces, so as to realize non-continuous storage of the description characters in the storage space.

[0056] The description character information extracted by the parsing module 1201 is a data description character, which may include source address information of the data to be transferred, destination address information of the data to be transferred, and data volume information of the data to be transferred;

[0057] The parsing module can be used to extract data description characters in the description character information, convert the source address information of the data to be transferred, the destination address information of the data to be transferred and the data volume information of the data to be transferred in the data description characters into data transfer information in the target instruction format, and transmit the data transfer information to the data channel control module.

[0058] For example, the following table 1 is a schematic data structure diagram of a data description character:

[0059]

[0060] Table 1

[0061] The data description characters may include 6 double words (DW, Double Word), and the size of each double word is 32 bits.

[0062] Among them, the "DAR Low" field in the first double word and the "DAR High" field in the second double word can represent the destination address information of the data to be transferred.

[0063] Among them, the "SAR Low" field in the third double word and the "SAR High" field in the fourth double word can represent the source address information of the data to be transferred.

[0064] The "Transfer Size" field in the fifth double word may indicate the data volume information of the data to be transferred.

[0065] The sixth double word is divided into 7 fields, among which the "Stop" field can indicate the order of this data description character in the description character list. For example, if the "Stop" field is "0", it means that this data description character is not the last data description character in the description character list. If the "Stop" field is "1", it means that this data description character is the last data description character in the description character list, and after executing this data description character, it is necessary to report the DMA completion interrupt information to the specified processor.

[0066] The "Reserve" field may indicate that this field is a reserved field.

[0067] The "LLP" field may indicate the type of the data description character. For example, if the "LLP" field is "1", it may indicate that the type of the description character is a link description character, and if the "LLP" field is "0", it may indicate that the type of the description character is a data description character or a status description character.

[0068] The "LIE" field may indicate the interrupt reporting direction. For example, if the "LIE" field is "1", it means that the interrupt information needs to be reported to the local processor, and if the "LIE" field is "0", it means that the interrupt information does not need to be reported to the local processor.

[0069] The "RIE" field may also indicate the interrupt reporting direction. For example, if the "RIE" field is "1", it means that the interrupt information needs to be reported to the peer processor, and if the "RIE" field is "0", it means that the interrupt information does not need to be reported to the peer processor.

[0070] The "OWN" field can indicate whether the description character has been executed. For example, if the "OWN" field is "1", it means it has not been executed, and if it is "0", it means it has been executed. Generally, the "OWN" field in the data description character is "1", and the "OWN" field in the status description character is "0".

[0071] In this way, taking the structure of the data description characters shown in Table 1 as an example, the parsing module can be used to extract the data description characters in the description character information, extract the information in the "SAR Low" field, the "SAR High" field, the "DAR Low" field, the "DAR High" field and the "Transfer Size" field in the data description characters, and convert them into data handling information in the target instruction format, and transmit the data handling information to the data channel control module, so that the data channel control module can perform data transmission between the RC memory and the EP memory according to the data handling information.

[0072] Figure 3 It is a schematic structural diagram of another DMA controller provided in an embodiment of the present application.

[0073] In a specific embodiment, Figure 3 As shown, in the DMA controller 100 provided in the embodiment of the present application, the data channel control module 1201 is also used to generate a DMA execution result after data is transmitted between the RC memory and the EP memory; the DMA execution result includes status information reflecting that the DMA controller transmits the data to be transferred;

[0074] For example, the DMA execution result may indicate that the DMA controller has successfully transmitted the data to be transferred, or may indicate that the DMA controller has failed to transmit the data to be transferred, or may indicate the type of failure of the DMA controller to transmit the data to be transferred, and so on. The present application does not limit the specific content of the DMA execution result.

[0075] like Figure 3 As shown, the DMA controller 100 provided in the embodiment of the present application further includes a status write-back module 130;

[0076] The status write-back module 130 is used to obtain the DMA execution result from the data channel control module, and generate a status description character corresponding to the data description character according to the DMA execution result;

[0077] The status write-back module 130 is further configured to transmit the status description characters to a target memory, so that the target memory stores the status description characters in a manner of overwriting the data description characters.

[0078] For example, the following table 2 is a schematic data structure diagram of a status description character:

[0079]

[0080] Table 2

[0081] Compared with the data description characters shown in Table 1, the status description characters shown in Table 2 are different in that:

[0082] Two fields are redefined in the "Reserve" field of bits 6-31 of the sixth double word: a "SEC" field and an "Error Type" field.

[0083] Among them, the "SEC" field and the "Error Type" field are used to indicate the DMA execution result.

[0084] The "SEC" field is used to indicate whether the DMA controller successfully transfers the data to be transferred. For example, "SEC" is "1" for successful execution, and "SEC" is "0" for failed execution.

[0085] Among them, the "Error Type" field is used to indicate the failure type of the DMA controller's failure to transmit the data to be moved. This application does not limit the specific failure type.

[0086] In this way, taking the structure of the status description character shown in Table 2 as an example, in the process of the status write-back module 130 generating a status description character corresponding to the data description character, the status write-back module 130 can write the "OWN" field to "0", indicating that this data description character has been executed, and write corresponding content in the "SEC" field and the "Error Type" field according to the DMA execution result.

[0087] In another specific embodiment, when all data description characters in the description character chain list have been executed, the DMA controller may also report DMA completion interrupt information to a designated processor, so that the designated processor obtains the status description character from the target memory and determines the DMA execution result according to the status description character. The following is an example:

[0088] In the embodiment of the present application, the description character chain list includes a target data description character, the target data description character is the last data description character in the description character chain list, and the target data description character includes configuration information for indicating an interrupt reporting direction.

[0089] For example, taking the structure of the data description character shown in Table 1 as an example, the "Stop" field of the target data description character is "1", indicating that the target data description character is the last data description character in the description character linked list. The configuration information for indicating the interrupt reporting direction contained in the target data description character can be stored in the "LIE" field and / or the "RIE" field.

[0090] like Figure 4 As shown, the DMA controller 100 provided in the embodiment of the present application may further include: an interrupt control module 140;

[0091] The interrupt control module 140 can be used to determine the designated processor according to the configuration information indicating the interrupt reporting direction in the target data description character, and report the DMA completion interrupt information to the designated processor, so that the designated processor obtains the status description character from the target memory and determines the DMA execution result according to the status description character.

[0092] The configuration information for indicating the interrupt reporting direction includes: first configuration information and / or second configuration information; the first configuration information is used to indicate that the designated processor includes a local processor; the second configuration information is used to indicate that the designated processor includes a peer processor.

[0093] Taking the structure of the data description character shown in Table 1 as an example, the first configuration information can be stored in the "LIE" field, and the second configuration information can be stored in the "RIE" field. For example, the "LIE" field is "1" to indicate that the DMA completion interrupt information is reported to the local memory. Alternatively, the "RIE" field is "1" to indicate that the DMA completion interrupt information is reported to the peer memory. Alternatively, the "LIE" field and the "RIE" field can both be "1", indicating that the DMA completion interrupt information is reported to the local memory and the peer memory.

[0094] Wherein, in the case where the DMA controller is applied to the RC, the first configuration information is used to indicate that the designated processor includes the RC processor, and the second configuration information is used to indicate that the designated processor includes the EP processor;

[0095] Wherein, in the case where the DMA controller is applied to the EP, the first configuration information is used to indicate that the designated processor includes the EP processor, and the second configuration information is used to indicate that the designated processor includes the RC processor.

[0096] In the embodiments of the present application, the designated processor may be an RC processor, an EP processor, or both an RC processor and an EP processor, and the present application does not impose any specific limitation thereto.

[0097] The designated processor and the target processor may be the same processor or different processors, and this application does not impose any specific limitation.

[0098] For example, when the DMA controller is applied to RC, the "LIE" field of the data description character is "1", indicating that the specified processor can be an RC processor. In this case, the RC processor is a local processor, and the RC processor and the DMA controller communicate through the AXI bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor through the AXI bus, so that the RC processor obtains the status description character from the target memory and determines the DMA execution result based on the status description character.

[0099] Alternatively, when the DMA controller is applied to RC, the "RIE" field of the data description character is "1", indicating that the specified processor can be an EP processor. In this case, the EP processor is the peer processor, and the EP processor and the DMA controller communicate through the PCIe bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the EP processor through the PCIe bus, so that the EP processor obtains the status description character from the target memory and determines the DMA execution result based on the status description character.

[0100] Alternatively, in the case where the DMA controller is applied to RC, the "LIE" field and the "RIE" field of the data description character are both "1", indicating that the specified processor can be an RC processor and an EP processor. In this case, the RC processor is a local processor, and the EP processor is a peer processor. The RC processor communicates with the DMA controller through the AXI bus, and the EP processor communicates with the DMA controller through the PCIe bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor through the AXI bus, and report the DMA completion interrupt information to the EP processor through the PCIe bus, so that the RC processor and the EP processor can obtain the status description character from the target memory and determine the DMA execution result based on the status description character.

[0101] For another example, when the DMA controller is applied to EP, the "RIE" field of the data description character is "1", and the specified processor can be an RC processor. In this case, the RC processor is the peer processor, and the RC processor and the DMA controller communicate through the PCIe bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor through the PCIe bus, so that the RC processor obtains the status description character from the target memory and determines the DMA execution result based on the status description character.

[0102] Alternatively, in the case where the DMA controller is applied to the EP, the "LIE" field of the data description character is "1", indicating that the specified processor can be the EP processor. In this case, the EP processor is a local processor, and the EP processor communicates with the DMA controller through the AXI bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the EP processor through the AXI bus, so that the EP processor obtains the status description character from the target memory and determines the DMA execution result based on the status description character.

[0103] Alternatively, in the case where the DMA controller is applied to the EP, the "RIE" field and the "LIE" field of the data description character are both "1", indicating that the specified processor can be the RC processor and the EP processor. In this case, the RC processor is the peer processor, the EP processor is the local processor, the RC processor and the DMA controller communicate through the PCIe bus, and the EP processor and the DMA controller communicate through the AXI bus. The interrupt control module 140 of the DMA controller can report the DMA completion interrupt information to the RC processor through the PCIe bus, and report the DMA completion interrupt information to the EP processor through the AXI bus, so that the RC processor and the EP processor can obtain the status description character from the target memory and determine the DMA execution result according to the status description character.

[0104] In this way, the DMA controller is configured in advance with the first configuration information and / or the second configuration information in the data description character to report the DMA completion interrupt information, and the DMA controller is informed to report the DMA completion interrupt information to the local processor and / or the peer processor. Furthermore, the DMA controller can report the DMA completion interrupt information to the local controller through the AXI link or report the DMA completion interrupt information to the peer controller through the PCIe link according to the first configuration information and / or the second configuration information in the data description character, thereby improving the flexibility of the DMA controller and being able to switch the direction in which the DMA controller reports the DMA completion interrupt information.

[0105] For example, taking the structure of the data description character shown in Table 1 as an example, the "RIE" field and the "LIE" field in the data description character obtained by the DMA controller indicate whether the DMA completion interrupt information needs to be sent to the peer processor or the local processor. After parsing the data description character, the DMA controller can directly report the DMA completion interrupt information to the peer processor and / or the local processor. In particular, in the case where the DMA completion interrupt information needs to be reported to the peer processor, the DMA controller directly reports the DMA interrupt message to the peer processor through the PCIe link, and the local processor does not need to participate in the forwarding during the period.

[0106] In addition, for communication devices compatible with RC mode and EP mode, the DMA controller can dynamically control the direction of interrupt reporting in RC mode and EP mode, so that the DMA controller can be used in both RC mode and EP mode, broadening the application scenarios of the DMA controller.

[0107] In this way, the DMA controller provided in the embodiment of the present application can be used in communication devices compatible with EP mode and RC mode, and the reporting direction of DMA completion interrupt information can also be directly controlled through the "RIE" field and "LIE" field in the data description character, which has higher robustness.

[0108] In practical applications, when the description character list is long and the continuous space of the target memory is insufficient, the embodiment of the present application can store the description character list non-continuously in the target memory. When the description character list is to be physically stored non-continuously, the physical address of the next data description character can be pointed to by linking the description characters. When the storage space of the target memory is discrete and the description character list is long, the DMA controller is guaranteed to work normally. The following example illustrates.

[0109] In a specific embodiment, the description character linked list includes a plurality of description character information, and the plurality of description character information is non-continuously stored in a plurality of storage spaces of the target memory;

[0110] The plurality of description character information includes: link connection description characters stored in a first storage space of the target storage, and data description characters stored in a second storage space of the target storage; the second storage space is a storage space discrete from the first storage space.

[0111] In the embodiment of the present application, the link connection description character includes a target pointer, and the target pointer is used to indicate the physical address of the data description character stored in the second storage space of the target memory.

[0112] by Figure 5 Taking the target memory shown in the figure as an example, multiple description character information in the description character linked list is non-continuously stored in the first storage space, the second storage space and the third storage space, and the first storage space, the second storage space and the third storage space are all discrete storage spaces. The chain connection description character 1 is stored in the first storage space of the target memory, and the data description character 4 is stored in the second storage space of the target memory. The chain connection description character 1 includes a target pointer for indicating the physical address of the data description character 4.

[0113] certainly, Figure 5 The target memory shown is only an example, and the present application does not limit the number of discrete storage spaces of the target memory, the number of data description characters stored in each storage space, and the number of link connection description characters.

[0114] In this way, the embodiment of the present application connects the data description characters stored in discrete storage space by chaining description characters, thereby realizing non-continuous storage of description character information in the storage space, and realizing non-continuous storage of description character linked lists when the description character linked list is long and the continuous space of the target memory is insufficient.

[0115] The following describes in detail the content of the chain connection description characters in the description character chain table in combination with the data structure of the chain connection description characters. For example, Table 3 is a schematic data structure diagram of the chain connection description characters:

[0116]

[0117] Table 3

[0118] The link description characters may include 6 double words (DW, Double Word), and the size of each double word is 32 bits.

[0119] Among them, the first double word, the second double word and the third double word are "Reserve" fields, indicating that these fields are reserved fields.

[0120] Among them, the "Next Transfer List Pointer Address Low" field in the fourth double word and the "Next Transfer List Pointer Address High" field in the fifth double word can represent the target pointer, which is used to indicate the physical address of the next data description character stored in the discrete storage space.

[0121] The sixth double word is divided into three fields, wherein the "LLP" field can indicate the type of this data description character. For example, "LLP" field being "1" can indicate that the type of this description character is a link connection description character. Two "Reserve" fields can indicate that this field is a reserved field.

[0122] In this way, Figure 5 Taking the target memory shown as an example, the "Next Transfer List Pointer Address Low" field and the "Next Transfer List Pointer Address High" field in the chain connection description character 1 are used to indicate the physical address of the data description character 4; the data description character stored in the first storage space (for example, data description character 3) is connected with the data description character stored in the second storage space (for example, data description character 4) to realize the non-continuous storage of the description character information in the storage space, and realize the non-continuous storage of the description character chain list when the continuous space of the target memory is insufficient when the description character chain list is long.

[0123] Furthermore, in the DMA controller 100 provided in the embodiment of the present application, the acquisition module 100 can be specifically used to obtain the link connection description character from the target memory according to the information of the target memory in the DMA control information, and obtain the data description character stored in the second storage space of the target memory according to the target pointer contained in the link connection description character.

[0124] For example, Figure 5 Taking the target memory shown as an example, the acquisition module 100 can obtain the link connection description character 1 from the target memory according to the information of the target memory in the DMA control information, and then obtain the data description character 4 stored in the second storage space according to the target pointer included in the link connection description character 1.

[0125] In this way, the embodiment of the present application indicates the physical address of the next data description character stored in the discrete storage space through the target pointer contained in the chain-connected description character. Then, the DMA controller can obtain the description character information in the discrete storage space according to the target pointer, and ensure the normal operation of the DMA controller when the description character linked list is stored non-continuously in the target memory.

[0126] Based on the same concept as the DMA controller provided in the embodiment of the present application, the embodiment of the present application also provides a chip.

[0127] Figure 6 It is a schematic structural diagram of a chip provided in an embodiment of the present application.

[0128] like Figure 6 As shown, an embodiment of the present application also provides a chip, including a processor, a memory and a DMA controller provided by any of the above embodiments, wherein the processor is connected to the memory and the DMA controller respectively, and the memory is connected to the DMA controller.

[0129] Among them, the chips provided in the embodiments of the present application may include 4G chips, 5G chips, etc., and the present application does not specifically limit the chip type.

[0130] The chip provided in the embodiment of the present application can implement each process implemented by the above-mentioned DMA controller and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0131] Based on the same concept as the DMA controller provided in the embodiment of the present application, the embodiment of the present application also provides a root complex.

[0132] like Figure 7 As shown, an embodiment of the present application further provides a root complex, which may include an RC processor, an RC memory, a DMA controller provided by any of the above embodiments, and a first PCIe controller;

[0133] The RC processor is connected to the RC memory and the DMA controller respectively, the RC memory is connected to the DMA controller, and the DMA controller is connected to the first PCIe controller.

[0134] In the embodiments of the present application, Figure 7 As shown, the process of DMA data transfer by the root complex may include:

[0135] ①The RC processor stores the description character list in the RC memory;

[0136] ②RC processor sends DMA control information to DMA controller;

[0137] ③ The acquisition module of the DMA controller acquires the description character information in the description character list from the RC memory according to the DMA control information;

[0138] ④The parsing module of the DMA controller extracts the data description characters and converts them into data transfer information in the target instruction format;

[0139] ⑤The parsing module of the DMA controller transmits the data transfer information to the data channel control module of the DMA controller;

[0140] ⑥ The data channel control module of the DMA controller transfers data between the RC memory and the EP memory according to the data handling information, and generates the DMA execution result;

[0141] ⑦ The status write-back module of the DMA controller obtains the DMA execution result, and generates a status description character corresponding to the data description character according to the DMA execution result; and transmits the status description character to the RC memory, so that the RC memory stores the status description character in a manner of overwriting the data description character;

[0142] ⑧The interrupt control module of the DMA controller can determine the RC processor according to the configuration information used to indicate the interrupt reporting direction in the data description character, and report the DMA completion interrupt information to the RC processor;

[0143] ⑨The RC processor obtains the status description character from the RC memory and determines the DMA execution result based on the status description character.

[0144] In the embodiment of the present application, in the above steps ① and ②, in addition to the RC processor, the DMA controller can also be controlled by the EP processor, and the present application does not impose any restrictions on this.

[0145] In the embodiment of the present application, in addition to the RC memory, the description character linked list can also be stored in the EP memory, and the present application does not impose any limitation on this.

[0146] In the above step ⑥, the data channel control module of the DMA controller can access the RC memory through the AXI bus and access the EP memory through the PCIe bus to complete the data transfer between the RC memory and the EP memory, and save the DMA execution results during the data transfer process.

[0147] In the above step ⑦, after the data channel control module completes the data transfer of a data description character, it sends the DMA execution result to the status write-back module, and the status write-back module is responsible for writing the DMA execution result back to the storage space corresponding to the original data description character.

[0148] In the above step ⑧, if the data description character being executed is the last data description character in the description character list (i.e., the Stop field = 1), the interrupt control module of the DMA controller will interrupt the DMA controller according to the values ​​of the "RIE" field and the "LIE" field in the data description character ( Figure 7 The DMA controller works in RC mode, the designated processor is the RC processor, RIE=0, LIE=1), and determines whether to send the DMA completion interrupt information to the local processor (ie, the RC processor).

[0149] Of course, in the embodiment of the present application, in addition to sending the DMA completion interrupt information to the local processor, the DMA completion interrupt information can also be sent to the peer processor (i.e., the EP processor). For example, by writing a value to the terminal register of the EP through the RC processor, the DMA completion interrupt information is generated and reported to the EP processor. Of course, the present application can also use other methods to send the DMA completion interrupt information to the peer processor, and the present application does not make specific restrictions here.

[0150] The root complex provided in the embodiment of the present application can implement each process implemented by the above-mentioned DMA controller and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0151] Based on the same concept as the DMA controller provided in the embodiment of the present application, the embodiment of the present application also provides an endpoint device.

[0152] like Figure 8 As shown, an embodiment of the present application further provides an endpoint device, which may include an EP processor, an EP memory, a DMA controller provided by any of the above embodiments, and a second PCIe controller;

[0153] The EP processor is connected to the EP memory and the DMA controller respectively, the EP memory is connected to the DMA controller, and the DMA controller is connected to the second PCIe controller.

[0154] In the embodiments of the present application, Figure 8 As shown, the process of DMA data transmission by the endpoint device may include:

[0155] ① The RC processor stores the description character list in the EP memory through the PCIe bus;

[0156] ②The RC processor sends DMA control information to the DMA controller through the PCIe bus;

[0157] ③ The acquisition module of the DMA controller acquires the description character information in the description character list from the EP memory according to the DMA control information;

[0158] ④The parsing module of the DMA controller extracts the data description characters and converts them into data transfer information in the target instruction format;

[0159] ⑤The parsing module of the DMA controller transmits the data transfer information to the data channel control module of the DMA controller;

[0160] ⑥ The data channel control module of the DMA controller transfers data between the RC memory and the EP memory according to the data handling information, and generates the DMA execution result;

[0161] ⑦ The status write-back module of the DMA controller obtains the DMA execution result, and generates a status description character corresponding to the data description character according to the DMA execution result; and transmits the status description character to the EP memory, so that the EP memory stores the status description character in a manner of overwriting the data description character;

[0162] ⑧The interrupt control module of the DMA controller can determine the RC processor according to the configuration information used to indicate the interrupt reporting direction in the data description character, and report the DMA completion interrupt information to the RC processor through the PCIe bus;

[0163] ⑨The RC processor obtains the status description character from the EP memory through the PCIe bus and determines the DMA execution result according to the status description character.

[0164] In the embodiment of the present application, in the above steps ① and ②, in addition to the RC processor, the DMA controller can also be controlled by the EP processor, and the present application does not impose any restrictions on this.

[0165] In the embodiment of the present application, in addition to the EP memory, the description character linked list can also be stored in the RC memory, and the present application does not impose any limitation on this.

[0166] In the above step ⑥, the data channel control module of the DMA controller can access the EP memory through the AXI bus and access the RC memory through the PCIe bus to complete the data transfer between the RC memory and the EP memory, and save the DMA execution results during the data transfer process.

[0167] In the above step ⑦, after the data channel control module completes the data transfer of a data description character, it sends the DMA execution result to the status write-back module, and the status write-back module is responsible for writing the DMA execution result back to the storage space corresponding to the original data description character.

[0168] In the above step ⑧, if the data description character being executed is the last data description character in the description character list (i.e., the Stop field = 1), the interrupt control module of the DMA controller will interrupt the DMA controller according to the values ​​of the "RIE" field and the "LIE" field in the data description character ( Figure 7 The DMA controller works in EP mode, the designated processor is the RC processor, RIE=1, LIE=0), and it is determined that the DMA completion interrupt information is sent to the opposite processor (i.e., the RC processor). Specifically, any one of the three interrupt sending modes defined in the PCIe protocol, legacy, MSI, and MSI-X, can be selected to send the DMA completion interrupt information. This application does not make any specific restrictions here.

[0169] Of course, in the embodiment of the present application, in addition to sending the DMA completion interrupt information to the peer processor, the DMA completion interrupt information can also be sent to the local processor, and the present application does not make any specific restrictions here.

[0170] The endpoint device provided in the embodiment of the present application can implement each process implemented by the above-mentioned DMA controller and can achieve the same technical effect. To avoid repetition, it will not be described here.

[0171] In this way, the DMA controller provided in the embodiment of the present application can determine the storage location of the description character list according to the DMA control information from the RC processor in the RC mode and the EP mode, and then the DMA controller can obtain the description character information by accessing the local memory or the peer memory according to the storage location of the description character list, and can switch the direction in which the DMA controller reads the description character information, so that the DMA controller can be used for both RC and EP. Compared with the related art, the DMA controller is reusable, which solves the problem of the single application scenario of the DMA controller in the related art, and reduces the cost of the DMA controller for communication devices compatible with the RC mode and the EP mode.

[0172] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0173] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0174] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A DMA controller, characterized in that: The DMA controller is applied to the root complex RC or the endpoint device EP, and the DMA controller includes: an acquisition module and a control module; The acquisition module is used to acquire DMA control information from a target processor, wherein the DMA control information includes information of a target memory, and the information of the target memory is used to indicate a storage location of a description character linked list; The acquisition module is further used to determine a target memory according to the DMA control information, and acquire description character information in a description character linked list from the target memory, wherein the target memory includes an RC memory or an EP memory; The control module is used for performing data transmission between the RC memory and the EP memory according to the description character information in the description character linked list.

2. The DMA controller according to claim 1, characterized in that: The control module includes a parsing module and a data channel control module; The parsing module is used to extract the description character information, convert the description character information into data handling information in a target instruction format, and transmit the data handling information to the data channel control module; The data channel control module is used to perform data transmission between the RC memory and the EP memory according to the data handling information.

3. The DMA controller according to claim 2, characterized in that: The descriptive character information includes data descriptive characters, and the data descriptive characters include source address information of the data to be transferred, destination address information of the data to be transferred, and data volume information of the data to be transferred; The parsing module is used to extract data description characters from the description character information, convert the source address information of the data to be transferred, the destination address information of the data to be transferred and the data volume information of the data to be transferred in the data description characters into data transfer information in a target instruction format, and transmit the data transfer information to the data channel control module.

4. The DMA controller according to claim 3, characterized in that: The data channel control module is also used to generate a DMA execution result after data is transmitted between the RC memory and the EP memory; the DMA execution result includes status information reflecting that the DMA controller transmits the data to be transferred; The DMA controller also includes a status write-back module; The state write-back module is used to obtain the DMA execution result from the data channel control module, and generate a state description character corresponding to the data description character according to the DMA execution result; The status write-back module is further used to transmit the status description character to the target memory, so that the target memory stores the status description character in a manner of overwriting the data description character.

5. The DMA controller according to claim 4, characterized in that: The description character chain list includes a target data description character, the target data description character is the last data description character in the description character chain list, and the target data description character includes configuration information for indicating an interrupt reporting direction; The DMA controller also includes: an interrupt control module; The interrupt control module is used to determine the designated processor according to the configuration information indicating the interrupt reporting direction in the target data description character, and report the DMA completion interrupt information to the designated processor, so that the designated processor obtains the status description character from the target memory and determines the DMA execution result according to the status description character.

6. The DMA controller according to claim 5, characterized in that: The configuration information for indicating the interrupt reporting direction includes: first configuration information and / or second configuration information; the first configuration information is used to indicate that the designated processor includes a local processor; the second configuration information is used to indicate that the designated processor includes a peer processor; In the case where the DMA controller is applied to RC, the first configuration information is used to indicate that the designated processor includes an RC processor, and the second configuration information is used to indicate that the designated processor includes an EP processor; In the case where the DMA controller is applied to the EP, the first configuration information is used to indicate that the designated processor includes an EP processor, and the second configuration information is used to indicate that the designated processor includes an RC processor.

7. The DMA controller according to any one of claims 1 to 6, characterized in that: The description character linked list includes a plurality of description character information, and the plurality of description character information is non-continuously stored in a plurality of storage spaces of the target memory; The plurality of description character information includes: link connection description characters stored in a first storage space of the target storage, and data description characters stored in a second storage space of the target storage; the second storage space is a storage space discrete from the first storage space; The link connection description character includes a target pointer, and the target pointer is used to indicate the physical address of the data description character stored in the second storage space of the target memory.

8. The DMA controller according to claim 7, characterized in that: The acquisition module is specifically used to acquire the link connection description character from the target memory according to the information of the target memory in the DMA control information, and acquire the data description character stored in the second storage space of the target memory according to the target pointer contained in the link connection description character.

9. A chip, characterized in that: The method comprises a processor, a memory and a DMA controller as described in any one of claims 1 to 8, wherein the processor is connected to the memory and the DMA controller respectively, and the memory is connected to the DMA controller.

10. A root complex, characterized in that: comprising an RC processor, an RC memory, a DMA controller as claimed in any one of claims 1 to 8, and a first PCIe controller; The RC processor is connected to the RC memory and the DMA controller respectively, the RC memory is connected to the DMA controller, and the DMA controller is connected to the first PCIe controller.

11. An endpoint device, characterized in that: comprising an EP processor, an EP memory, a DMA controller as claimed in any one of claims 1 to 8, and a second PCIe controller; The EP processor is connected to the EP memory and the DMA controller respectively, the EP memory is connected to the DMA controller, and the DMA controller is connected to the second PCIe controller.

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