A quantum computer benchmarking system, test method

Abstract

The application provides a quantum computer benchmarking system for evaluating the performance of a quantum computer, comprising: a virtual quantum computer for storing quantum computer information to be tested; a test set generation module for constructing an initial test circuit set based on the quantum computer information to be tested stored by the virtual quantum computer; a test set preprocessing module for compiling the circuits in the initial test circuit set to obtain a target test circuit set; an execution module for transmitting the target test circuit set to the quantum computer to be tested through a quantum computer interface arranged thereon to execute each circuit in the target test circuit set, and transmitting the execution result of each circuit to an evaluation module; and the evaluation module for evaluating the performance of the quantum computer to be tested.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of quantum computing, in particular, to benchmarking technology in the field of quantum computing, and more particularly to a quantum computer benchmarking system and method. BACKGROUND

[0002] With the rapid development of quantum computing technology, benchmarking as a key technology to measure the performance of quantum processors occupies a core position in the field of quantum computing. Quantum computers, with their unique parallel computing capabilities and computing potential beyond traditional computers, have become a powerful tool for solving large-scale optimization problems, cryptography problems and physical problems. However, how to accurately and comprehensively evaluate the performance of quantum computers is a key challenge in the practical and industrialization process of quantum computing technology.

[0003] Existing quantum computing benchmarking methods are diverse, but each has certain limitations. For example, quantum gate set tomography (GST) can provide in-depth performance analysis, but its requirements for experimental scale and post-processing are extremely strict, making it difficult to achieve efficient and scalable benchmarking. Random benchmark (RB) testing, on the other hand, is favored for its scalability, but is mainly limited to Clifford gate sets and cannot fully reflect the characteristics of general gate sets for quantum computing.

[0004] In order to overcome the limitations of the above benchmarking, researchers have proposed evaluation indicators such as quantum volume (QV) and circuits per layer operations per second (CLOPS) to evaluate the performance of quantum computers by taking into account multiple key factors such as the number of qubits, quantum lifetime, and gate fidelity. Not only that, some application-oriented systems have also proposed evaluation methods from the perspective of application, which intuitively reflect the performance of quantum computers by providing a single indicator and score.

[0005] Although the existing benchmarking method can evaluate the performance of the quantum computer, there are still two deficiencies. On the one hand: the test set in the existing benchmarking method needs complex preprocessing to adapt to the running environment of the quantum computer, and the circuit in the test set after complex preprocessing may affect the running efficiency of the quantum computer. The current benchmarking method generally uses fully random circuits and classical quantum algorithm circuits as the main components of the test set to evaluate the performance of the quantum computer. Among them, the random circuits in the test set are used to aggregate test results from random distribution to obtain overall evaluation of the performance of the quantum computer. However, such general random circuits are not always directly applicable to the running environment of the quantum computer, and often need to go through a series of complex preprocessing steps to adapt to the running environment of the quantum computer, and the random circuits after complex preprocessing steps may affect the running efficiency of the quantum computer, thereby reducing the performance of the quantum computer. On the other hand: the existing benchmarking method fails to comprehensively evaluate the performance of the quantum computer. Benchmarking should comprehensively consider multiple key dimensions of evaluation indicators to ensure comprehensive and in-depth evaluation of the quantum computer, and the existing benchmarking method often can only evaluate part of the work performance of the quantum computer by focusing on specific evaluation indicators, and fails to comprehensively evaluate the performance of the quantum computer. For example, the quantum volume (Quantum Volume, QV) is generally used as an evaluation indicator to evaluate the ability and maturity of the quantum computer. For example, the circuits per second (Circuits per Second, CPS) is used to measure the number of circuit layers that the quantum computer can execute in unit time to evaluate the computing ability and efficiency of the quantum computer.

[0006] In summary, although the existing benchmarking method can evaluate the performance of the quantum computer, there are still two deficiencies. On the one hand: the test set needs complex preprocessing steps to adapt to the running environment of the quantum computer, and the random circuits after complex preprocessing steps may affect the running efficiency of the quantum computer. On the other hand: the existing benchmarking method fails to comprehensively evaluate the performance of the quantum computer.

[0007] It should be noted that the background art is only used to introduce related information of the present application, so as to help understand the technical solutions of the present application, but does not mean that the related information must be prior art. In the absence of evidence that the related information has been disclosed before the filing date of the present application, the related information should not be regarded as prior art. SUMMARY

[0008] Therefore, the purpose of the present application is to overcome the defects of the prior art, and to provide a quantum computer benchmarking system and a quantum computer benchmarking method.

[0009] The object of the present application is achieved by the following technical solutions.

[0010] According to a first aspect of the present application, a quantum computer benchmarking system is provided, the system comprising: a virtual quantum computer configured to store quantum computer to be tested information; a test set generation module configured to construct an initial test circuit set based on the quantum computer to be tested information stored by the virtual quantum computer, wherein the initial test circuit set comprises an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit; a test set preprocessing module configured to preprocess the circuits in the initial test circuit set to obtain a target test circuit set, wherein preprocessing the circuits in the initial test circuit set comprises mirroring the initial random physical machine circuit and the initial special benchmark circuit, combining the mirrored results of the initial random physical machine circuit with the initial random physical machine circuit to obtain a target random physical machine circuit, and combining the mirrored results of the initial special benchmark circuit with the initial special benchmark circuit to obtain a target special benchmark circuit, and preprocessing the circuits in the initial test circuit set further comprises optimizing, mapping and quantum gate converting the initial quantum algorithm circuit to compile the quantum algorithm circuit into a target circuit conforming to an execution environment of the quantum computer to be tested; the target random physical machine circuit, the target special benchmark circuit and the target circuit constitute the target test circuit set; an execution module configured to transmit the target test circuit set to the quantum computer to be tested through a quantum computer interface arranged thereon to execute each circuit in the target test circuit set, and transmit the execution results of each circuit to an evaluation module; and the evaluation module configured to evaluate the quantum computer to be tested in terms of hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serialism, entanglement and execution fidelity of different circuits according to the execution results of each circuit, and evaluate the performance of the quantum computer to be tested in a preset manner.

[0011] In some embodiments of the present application, the special benchmark circuit comprises a highly parallelized circuit, a highly serialized circuit and a highly entangled circuit, wherein the ratio of the number of quantum gates to the depth and width of the circuit in the highly parallelized circuit is less than or equal to a preset proportion; the ratio of the two-bit quantum gates on the critical path to the total two-bit quantum gates in the highly serialized circuit is less than or equal to a preset proportion, and the critical path refers to the path with the longest dependent operation span from the input to the output of the circuit; and the proportion of the interaction of all quantum gates and two-bit quantum gates in the highly entangled circuit is less than or equal to a preset proportion.

[0012] Preferably, the preset proportion is 1.

[0013] In some embodiments of the present application, the hierarchical ratio is calculated in the following manner:

[0014]

[0015] wherein LR represents a hierarchy ratio of the circuit, n d represents a depth of the circuit, n q represents a number of qubits of the circuit, and max(LRs) represents a maximum ratio of the depth and the number of qubits in the target test circuit set;

[0016] The quantum gate density GD is calculated as follows:

[0017]

[0018] wherein GD represents a quantum gate density of the circuit, n1 represents a number of single-bit gates of the circuit, and n2 represents a number of double-bit gates of the circuit;

[0019] The cumulative fidelity CF is calculated as follows:

[0020]

[0021] wherein CF represents a cumulative fidelity of the circuit, f1 represents an average single-bit gate fidelity of the quantum computer to be tested, f2 represents an average double-bit gate fidelity of the quantum computer to be tested, n g represents a total number of quantum gates of the circuit.

[0022] In some embodiments of the present application, the parallelism Par is calculated as follows:

[0023]

[0024] wherein Par represents a parallelism of the circuit;

[0025] The serialism Ser is calculated as follows:

[0026]

[0027] wherein Ser represents a serialism of the circuit, n2' represents a number of double-bit gates on a target bit of the circuit, and the target bit represents a highest degree of coincidence of a double-bit gate control bit and a target bit on the bit of the circuit.

[0028] The entanglement Ent is calculated as follows:

[0029]

[0030] wherein,

[0031]

[0032] wherein Ent represents an entanglement of the circuit, C i represents a clustering coefficient of an i-th node represented by a qubit in an undirected graph composed of the circuit, T irepresents the number of edges between the neighbor nodes of the i-th node represented by the quantum bit in the undirected graph composed of the circuit, k i represents the number of edges directly connected to the i-th node represented by the quantum bit in the undirected graph composed of the circuit.

[0033] In some embodiments of the present application, the execution fidelity is calculated in the following manner: the probability that the actual execution result of each circuit after being repeatedly executed multiple times on the quantum computer to be tested is consistent with the predicted result is calculated, and the probability is taken as the execution fidelity of each circuit.

[0034] In some embodiments of the present application, the preset method is to perform evaluation processing on each circuit in the following manner: the average value of the hierarchical ratio, quantum gate density and cumulative fidelity of the circuit is calculated, and the average value is mapped to obtain a basic score of the circuit greater than or equal to a preset threshold; the average value of the parallelism, serial degree and entanglement degree of the circuit is calculated, and the average value is mapped to obtain a difficulty coefficient of the circuit located in a preset numerical interval; the basic score, difficulty coefficient and execution fidelity of the circuit are multiplied to obtain an evaluation score of the circuit, and the evaluation score represents the performance of the circuit executed by the quantum computer to be tested.

[0035] According to a second aspect of the present application, a quantum computer benchmarking method for evaluating the working performance of a quantum computer is provided, and the method comprises the following steps: S1, obtaining a quantum computer to be tested and information thereof; S2, performing benchmarking on the quantum computer to be tested by using the system according to the first aspect of the present application according to the information of the quantum computer to be tested to evaluate the working performance of the quantum computer to be tested.

[0036] Compared with the prior art, the present application has the following advantages: (1) the circuit is preprocessed by mirroring to make the preprocessed circuit output a unique error-free solution, so that the preprocessed circuit does not affect the running efficiency of the quantum computer; (2) a special benchmark circuit is constructed to evaluate the performance of the quantum computer executing highly parallelized, highly serialized and highly entangled circuits, so that the benchmarking of the quantum computer is more comprehensive; (3) the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serial degree, entanglement degree and execution fidelity are taken as evaluation indexes to comprehensively evaluate the performance of the quantum computer, so that the evaluation result of the quantum computer is more accurate and reliable. BRIEF DESCRIPTION OF DRAWINGS

[0037] The embodiments of the present application will be further described below with reference to the accompanying drawings, in which:

[0038] Figure 1 FIG. 1 is a structural schematic diagram of a quantum computer benchmarking system according to an embodiment of the present application;

[0039] Figure 2An example schematic diagram of an evaluation score of a circuit according to an embodiment of the present application;

[0040] Figure 3 An example schematic diagram of an evaluation index of a circuit according to an embodiment of the present application;

[0041] Figure 4 An example schematic diagram of an evaluation score of a random physical machine circuit according to an embodiment of the present application;

[0042] Figure 5 An example schematic diagram of a flow of a quantum computer benchmarking method according to an embodiment of the present application;

[0043] Figure 6 An example schematic diagram of a flow of a quantum computer benchmarking method according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the objects, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely intended to explain the present application and should not be used to limit the present application.

[0045] As mentioned in the background section, although the existing benchmarking method can evaluate the performance of a quantum computer, there are still two deficiencies. On the one hand, the test set needs complex preprocessing steps to adapt to the running environment of the quantum computer, and the circuit in the test set after complex preprocessing may affect the running efficiency of the quantum computer. On the other hand, the existing benchmarking method fails to comprehensively evaluate the performance of the quantum computer.

[0046] In order to solve the defects of the prior art, the inventors analyzed the prior art and found that the circuit in the test set cannot fix the number and size of solutions, and in order to meet the execution environment of quantum computing, preprocessing is needed, which results in that the results of the circuit are not "pure", thereby affecting the running efficiency of the quantum computer. In order to make up for this defect, the inventors propose that the circuit can be preprocessed by mirroring to make the preprocessed circuit output unique error-free solutions, thereby making the preprocessed circuit not affect the running efficiency of the quantum computer. Further, in order to comprehensively evaluate the performance of the quantum computer, the inventors propose that a special benchmark circuit can be constructed to analyze the ability of the quantum computer when executing a specific task. Furthermore, the inventors propose that the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serial degree, entanglement degree and execution fidelity obtained after the quantum computer executes the circuit are used as evaluation indexes to comprehensively evaluate the performance of the quantum computer. Based on this, the inventors propose a benchmark test system, which includes a test set generation module, a test set preprocessing module, an execution module and an evaluation module. The initial test circuit set is generated by the test set generation module, the initial test circuit set is preprocessed by the test set preprocessing module to obtain the target test circuit set, the circuits in the target test circuit set are executed by the execution module, and the working performance of the quantum computer is evaluated by the evaluation module according to the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serial degree, entanglement degree and execution fidelity obtained by the execution module.

[0047] In summary, as Figure 1As shown, the present application provides a quantum computer benchmarking system for evaluating the performance of a quantum computer, which comprises: a virtual quantum computer for storing quantum computer information to be tested; a test set generation module for constructing an initial test circuit set based on the quantum computer information to be tested stored by the virtual quantum computer, wherein the initial test circuit set comprises an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit; a test set preprocessing module for preprocessing the circuits in the initial test circuit set to obtain a target test circuit set, wherein preprocessing the circuits in the initial test circuit set comprises mirroring the initial random physical machine circuit and the initial special benchmark circuit, combining the mirrored results of the initial random physical machine circuit with the initial random physical machine circuit to obtain a target random physical machine circuit, and combining the mirrored results of the initial special benchmark circuit with the initial special benchmark circuit to obtain a target special benchmark circuit, and preprocessing the circuits in the initial test circuit set further comprises optimizing, mapping and quantum gate converting the initial quantum algorithm circuit to compile the quantum algorithm circuit into a target circuit conforming to the execution environment of the quantum computer to be tested; the target random physical machine circuit, the target special benchmark circuit and the target circuit constitute the target test circuit set; an execution module for transmitting the target test circuit set to the quantum computer to be tested through the quantum computer interface arranged thereon to execute each circuit in the target test circuit set, and transmitting the execution results of each circuit to an evaluation module; and the evaluation module evaluates the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serial degree, entanglement degree and execution fidelity of the quantum computer to be tested in executing different circuits according to the execution results of each circuit, so as to evaluate the performance of the quantum computer to be tested in a preset method.

[0048] In order to better understand the present application, the various components of the benchmarking system will be described in detail below in combination with specific embodiments.

[0049] I. Virtual quantum computer

[0050] When the benchmarking system is built, a virtual quantum computer needs to be constructed by the class Virtual Quantum Machine to store quantum computer information to be tested, so as to generate a test set based thereon to evaluate the working performance of the quantum computer to be tested. Among them, the virtual quantum computer stores information such as the number of bits of the quantum computer to be tested, the physical topology, the quantum gate instruction set, the single-bit quantum gate fidelity and the double-bit quantum gate fidelity.

[0051] II. Test set generation module

[0052] The test set generation module is configured to construct an initial test circuit set based on the information of the quantum computer to be tested stored in the virtual quantum computer. In order to comprehensively evaluate the working performance of the quantum computer to be tested, the initial test circuit set constructed includes an initial random physical machine circuit, an initial special benchmark circuit and an initial quantum algorithm circuit. The following will introduce these different test circuits respectively.

[0053] The initial random physical machine circuit is a multi-level circuit set with a scale not exceeding the number of physical machine bits, which is constructed based on the information stored in the virtual quantum computer. The proportion of two-bit quantum gates and single-bit quantum gates in the circuit set is different, and the circuit set completely meets the operation standard of the quantum computer to be tested. The initial random physical machine circuit does not need to be compiled twice, which realizes more pure and direct testing of the ability of the quantum computer to execute complex circuits. It should be noted that the proportion of two-bit quantum gates and single-bit quantum gates in the initial random physical machine circuit is set according to actual testing requirements, and the present application does not make special limitations. It should also be noted that the initial random physical machine circuit constructed by the present application is different from the existing random gate set circuit. The initial random physical machine circuit constructed by the present application is a circuit constructed based on the information stored in the quantum virtual machine, which meets the operation condition of the quantum computer to be tested, and will output a unique error-free solution after preprocessing. The existing random gate set circuit cannot meet the condition of direct operation of the quantum computer, and needs to be preprocessed, i.e. processing the gate set that cannot be operated and the "error" topology structure, which will increase unnecessary time consumption and also lose the characteristic of simulating random distribution of the quantum computer.

[0054] The initial special benchmark circuit is based on the number of bits of the quantum computer to be tested, the quantum gate instruction set, and part of the sub-topology of the physical topology, and generates a highly parallelized, highly serialized, and highly entangled circuit. Among them, the highly parallelized circuit is defined as the ability to test the hardware processing pressure of the quantum computer by concentrating a large number of operations in a smaller depth, so as to add the largest proportion of two-bit gates in each layer of the circuit as much as possible during circuit design, and add single-bit gates on the spare bit positions of each layer of the circuit, so that each layer of the circuit has as few spare bit positions as possible. Based on this, the ratio of the number of quantum gates to the depth width (parallelism) in the highly parallelized circuit is less than or equal to 1, and in the actual design process, the ratio range is usually kept around the ratio 1, such as between 0.8-1. The highly serialized circuit is defined as the two-bit gates in the circuit being on the critical path, which can shorten the running time of the circuit during operation, so as to make the control bits or target bits of the two-bit gates on the target bits with the largest concentrated bit positions in the topology of the quantum computer to be tested as the target bits, and make the ratio of the two-bit gates on the critical path to the total two-bit gates (critical depth of the circuit) less than or equal to 1. In the actual design process, the ratio range is usually kept around the ratio 1, such as between 0.8-1, wherein the critical path refers to the longest dependent operation span path from the input to the output of the circuit. The highly entangled circuit is defined as the two-bit gates in the circuit interacting to a large value, so as to randomly select a bit position as idle, and the remaining bit positions are all entangled together through two-bit gates, so that the ratio of the interaction of all gates in the circuit with two-bit gates (entanglement ratio) is less than or equal to 1. In the actual design process, the ratio range is usually kept around the ratio 1, such as between 0.8-1. It should be noted that the initial special benchmark circuit is different from the initial random physical machine circuit, and the quantum gate positions in the initial special benchmark circuit need to follow certain rules. These rules are specially designed to test the performance of the quantum computer in handling specific situations, in order to comprehensively evaluate the working performance of the quantum computer. It should also be noted that the highly parallelized circuit is designed because parallel operations can cause pressure on the quantum hardware in the quantum computer, at which time the related noise events are called "cross talk" (cross talk is usually caused by simultaneously executed gates), and cross talk can reduce the working performance of the quantum computer. Based on this, the highly parallelized circuit is constructed to analyze to what extent the quantum computer is susceptible to cross talk.It should be noted that the highly serialized circuit is designed because the coherence time of the quantum bit stored is limited, and this limitation plus the cumulative gate error will cause the fidelity of the circuit to be executed to be reduced, so the quantum circuit must shorten the duration as much as possible, based on which the present application proposes the shortest duration of the quantum circuit, and takes the longest dependent operation span of the circuit input to output on the critical path as the shortest duration, by shortening the execution time of the circuit on the hardware, to test the processing result of the hardware on such circuit. It should be noted that the highly entangled circuit is designed because entanglement is a key feature of quantum computing, which gives quantum computing great advantages and is an effective performance indicator of quantum computers. Entanglement can display quantum advantage computing tasks, such as Shor factorization, long-distance transmission, super-dense coding and quantum encryption protocols. Based on this, the ability of the hardware to process highly entangled states is tested by calculating the proportion of two-qubit interactions in all gate operations.

[0055] The initial quantum algorithm circuit is a circuit generated based on an algorithm in the existing algorithm library. The existing algorithm library includes algorithms such as adder, multiplier, divider, variational quantum algorithm (vqe), maxcut, quantum neural network (qnn), quantum walk, satisfiability problem (cnf), Grover algorithm (grover), quantum Fourier transform (qft), quantum phase estimation (qpe), etc. These algorithms can be converted into circuits through QASM files, and the converted circuits can reflect the performance and ability of the quantum computer when executing a specific algorithm, and each algorithm converted circuit has a fixed solution.

[0056] III. Test set preprocessing module

[0057] The test set preprocessing module is used to preprocess the circuits in the initial test circuit set to obtain the target test circuit set. How to preprocess the initial random physical machine circuit, the initial special benchmark circuit and the initial quantum algorithm circuit in the initial test circuit set is described in detail below.

[0058] For the initial random physical machine circuit and the initial special benchmark circuit, the preprocessing process is to mirror the initial random physical machine circuit and the initial special benchmark circuit, and to combine the mirror result of the initial random physical machine circuit with the initial random physical machine circuit to obtain a target random physical machine circuit, and to combine the mirror result of the initial special benchmark circuit with the initial special benchmark circuit to obtain a target special benchmark circuit. It should be noted that the target random physical machine circuit and the target special benchmark circuit obtained by preprocessing are mirror circuits. The mirror circuit is a kind of general quality benchmark. By connecting the circuit with its reverse mirror copy, a unique and easy-to-calculate bit string is generated, which helps to ensure that the quality and performance of the circuit meet the evaluation standard.

[0059] For the initial quantum algorithm circuit, in order to ensure that it can meet the execution environment of the quantum computer, preprocessing is required to optimize, map and quantum gate transform the initial quantum algorithm circuit. In the optimization process, one or more existing optimization algorithms are used to optimize the initial quantum algorithm circuit, such as quantum gate merging and other operations to reduce the number of circuit gates and circuit depth; in the mapping process, the existing mapping algorithm is used to map the initial quantum algorithm circuit, and the mapping algorithm can use sabre quantum bit mapping algorithm or circuit mapping algorithm based on Monte Carlo tree search; in the quantum gate transformation process, the quantum instruction set conversion algorithm is used to transform the initial quantum algorithm circuit. It should be noted that during preprocessing, the initial quantum algorithm circuit is processed in the order of optimization-mapping-transformation-optimization. It should be noted that since the algorithm circuit can reflect the performance and ability of the quantum computer when executing a specific algorithm, and each algorithm has a fixed solution, there is no need to convert the initial quantum algorithm circuit into a mirror circuit, only preprocessing is required to make the preprocessed circuit fully adaptable and directly executable on the quantum computer.

[0060] It should be noted that in order to facilitate data reading after the circuit is executed, a measurement gate can also be added at the end of the initial random physical machine circuit, the initial special benchmark circuit and the initial quantum algorithm circuit according to actual needs. The measurement gate can convert the state of the quantum bit into a classical bit, which is convenient for understanding and reading the execution result of the quantum computer after executing the circuit, and is conducive to more accurately evaluating the performance of the quantum computer and the accuracy and reliability of the evaluation result.

[0061] Four, execution module

[0062] The execution module is used to transmit the target test circuit set to the quantum computer to be tested through the quantum computer interface arranged thereon to execute each circuit in the target test circuit set. It should be noted that the input of the quantum computer interface is the circuit, and the output is the amplitude result.

[0063] It should be noted that before transmitting the circuits in the target test circuit set to the quantum computer to be tested through the quantum computer interface, each circuit in the target test circuit set needs to be packaged, and a data structure named BenchCirData is created, which stores the detailed information of the circuit with the circuit name as the key. Moreover, after the circuit performs a task on the quantum computer, the simulation result is also stored in the corresponding BenchCirData data structure. In this way, all circuits and their corresponding simulation results can be organized and saved in order, which is convenient for subsequent analysis and processing.

[0064] It should also be noted that when the circuits in the target test circuit set are executed multiple times, there may be "redundancy". For example, when a quantum computer executes a large-scale circuit, if the fidelity test result is failed (in the absence of errors, the quantum computer will output a unique and easily calculated bit string after executing the circuit, and the first bit of the bit string is the fidelity value, and the fidelity is 0 when the test result is failed), this execution will be meaningless. In order to avoid unnecessary resource consumption, the present application designs an intermediate review mechanism, which will monitor in real time during the execution of the circuit. If the fidelity test result is failed in three consecutive executions, the mechanism will automatically suspend the execution of the subsequent circuit. Although the execution of the subsequent circuit is suspended, the evaluation module will still analyze the execution result of the circuit that has been executed. As can be seen, the intermediate review mechanism not only improves the efficiency of circuit execution and avoids the repetition of invalid experiments, but also ensures the rigor of the circuit execution process and the reliability of the result, thereby more accurately evaluating the performance of the quantum computer and improving the overall quality of the evaluation process.

[0065] Five, evaluation module

[0066] The evaluation module is configured to evaluate the layer ratio, quantum gate density, cumulative fidelity, parallelism, serialism, entanglement, and execution fidelity of each circuit according to the execution result of the quantum computer to be tested, so as to evaluate the performance of the quantum computer to be tested according to a preset method. According to an embodiment of the present application, the preset method is to evaluate each circuit in the following manner: calculating the average of the layer ratio, quantum gate density, and cumulative fidelity of the circuit, and performing mapping processing on the average to obtain a basic score of the circuit that is greater than or equal to a preset threshold; calculating the average of the parallelism, serialism, and entanglement of the circuit, and performing mapping processing on the average to obtain a difficulty coefficient of the circuit that is located in a preset numerical interval; multiplying the basic score, difficulty coefficient, and execution fidelity of the circuit to obtain an evaluation score of the circuit, and the evaluation score represents the performance of the quantum computer to be tested in executing the circuit. It should be noted that the preset threshold and the preset numerical interval are set according to actual needs, for example, the preset threshold can be set to 50, and the preset numerical interval can be set to 1-2, and the present application does not specially limit them.

[0067] It should be noted that the evaluation module outputs a comprehensive quantitative evaluation result by comprehensively considering the basic score, difficulty coefficient, and execution fidelity to evaluate the working performance of the quantum computer. The basic score evaluates the performance of the quantum computer in executing the circuit; the difficulty coefficient evaluates the complexity of the circuit executed by the quantum computer; and the execution fidelity evaluates the efficiency and accuracy of the quantum computer in actually executing the circuit.

[0068] The basic score evaluates the performance of the quantum computer in executing the circuit, which is determined by the layer ratio, quantum gate density, and cumulative fidelity of the circuit.

[0069] The layer ratio represents the comprehensive ratio of the number of qubits to the depth, wherein the size of the depth is determined by the distribution rule of the quantum gate on the qubit and the quantum gate density. The high or low of the layer ratio can indicate the complexity of the circuit, and can also evaluate the time and resources required by the quantum hardware on the quantum computer to be tested to execute the circuit. The layer ratio is calculated in the following manner:

[0070]

[0071] wherein LR represents the layer ratio of the circuit, n d represents the depth of the circuit, n q represents the number of qubits of the circuit, and max(LRs) represents the maximum ratio of the depth to the number of qubits in the target test circuit set.

[0072] The density of quantum gates focuses on the density of quantum gate operations in the entire computing process. The density of quantum gates can be used to evaluate the possible occupancy of the circuit when mapped to the quantum hardware on the quantum computer to be tested. The quantum gate density is the product of the single-bit and double-bit gates (n1, n2) and the corresponding weights and the number of quantum bits (n q ) and depth (n d ) is calculated by multiplying the product of, which is specifically expressed as follows:

[0073]

[0074] Where GD represents the quantum gate density of the circuit, n1 represents the number of single-bit gates of the circuit, and n2 represents the number of two-bit gates of the circuit;

[0075] Cumulative fidelity, the fidelity of the single-bit and two-bit gates of a quantum computer is an important indicator in the field of quantum computing, which directly reflects the performance and reliability of the quantum computer. The bit gate fidelity of a quantum computer indicates the similarity between the quantum bit and the ideal output state after the gate operation. Among them, the cumulative fidelity is obtained by adding the product of the average single-bit gate fidelity (f1) of the quantum computer to be tested and the number of single-bit gates in the circuit (n1) and the average two-bit gate fidelity (f2) and the number of two-bit gates in the circuit (n2) to obtain the average total fidelity, and then adding the average total fidelity to the total number of quantum gates (n g ) is roughly mapped to the standard circular curve in the (0, 1) interval and is calculated as follows:

[0076]

[0077] Where CF represents the cumulative fidelity of the circuit, f1 represents the average single-bit gate fidelity of the quantum computer to be tested, f2 represents the average two-bit gate fidelity of the quantum computer to be tested, and n g Represents the total number of quantum gates in the circuit.

[0078] The calculated layer ratio, quantum gate density and cumulative fidelity of each circuit are averaged and then linearly integrated to map the mean value in the range of 0 to 1 to a score above 50 points. The mapped score is used as the basic score to evaluate the performance of the quantum computer executing the corresponding circuit.

[0079] The difficulty coefficient measures the complexity of the circuit executed by the quantum computer, which is determined by the circuit's parallelism, seriality, and entanglement.

[0080] Parallelism reflects the degree of parallel operation in quantum computing, which reveals the distribution of quantum gate operations among qubits in the circuit. A higher parallel rate means an increase in the number of quantum gate operations that can be performed simultaneously, which will improve the efficiency and speed of computation; at the same time, it will also increase the complexity and processing difficulty of the circuit. Among them, the parallelism is calculated by comparing the ratio between the number of qubits (n q ), the number of gates (n g ) and the depth (n d ), which is specifically expressed as follows:

[0081]

[0082] Where Par represents the parallelism of the circuit.

[0083] Serial degree reflects the degree of serial operation in quantum computing. A higher serial rate means that more gate operations in the circuit are executed sequentially, which may limit the speed and efficiency of computation. Among them, the serial degree is calculated by calculating the proportion of the number of quantum gates on the highest coincidence bit to the total number of quantum gates, which is specifically expressed as follows:

[0084]

[0085] Where Ser represents the serial degree of the circuit, and n2' represents the number of double-bit gates on the target bit in the circuit. The target bit represents the highest degree of coincidence between the double-bit gate control bit and the target bit in the circuit.

[0086] Entanglement degree measures the distribution of entangled states in the circuit. When calculating the entanglement degree, first, the connections of each bit and each double-bit gate in the circuit are combined into an undirected graph, and the depth of each double-bit gate when inserted into the circuit is taken as the weight of the corresponding edge to obtain a weighted undirected graph (the smaller the depth when inserted, the higher the entanglement depth of the circuit); Then, the tightness of the connection between the neighbor nodes of a node is measured by the weighted undirected graph, and the clustering coefficient of each node is calculated. The clustering coefficient of each node is determined by the number of edges actually existing between the neighbors of the node and the number of edges directly connected to the node; Then, according to the weighted undirected graph and the clustering coefficient, the entanglement degree is calculated, and the specific process is represented as follows:

[0087]

[0088] Where,

[0089]

[0090] Where Ent represents the entanglement degree of the circuit, C i represents the clustering coefficient of the i-th node represented by the quantum bit in the undirected graph composed of the circuit, and T ik represents the number of edges between the neighbor nodes of the i-th node represented by the quantum bit in the undirected graph composed of the circuit. i k represents the number of edges directly connected to the i-th node represented by the quantum bit in the undirected graph composed of the circuit. It should be noted that in the weighted undirected graph composed of the connections of each bit, each two-bit gate of the circuit, if a node has only one critical point or no critical point (k i =0), the clustering coefficient of the node is 0, indicating that there is no edge connecting the neighbor nodes of the node, and when the clustering coefficient of the node is 1, it indicates that all neighbor nodes of the node are connected to each other, forming a complete subgraph. It should also be noted that in quantum physics, entanglement is usually related to the non-locality of a quantum system, and the clustering coefficient should be able to capture this non-locality and reflect the global correlation between quantum bits. For example, if the clustering coefficient can divide highly entangled quantum bits into the same cluster, the "purity" of the cluster can be used as a measure of entanglement.

[0091] The parallelism, seriality and entanglement of each circuit calculated are averaged and linearly synthesized to linearly map the average value to the numerical interval of 1 to 2, and the value after mapping is taken as the difficulty coefficient to determine the difficulty of the circuit executed by the quantum computer, and further evaluate the ability of the quantum computer to process complex circuits. It should be noted that when the difficulty coefficient is close to 1, it indicates that the circuit consumes too little resource in the execution of the quantum computer, and when the difficulty coefficient is close to 2, it indicates that the circuit consumes too much resource in the execution of the quantum computer.

[0092] The execution fidelity evaluates the efficiency and accuracy of the quantum computer in actually executing the circuit. According to an embodiment of the present application, the execution fidelity is calculated as follows: the probability that the actual execution result of each circuit after being repeatedly executed multiple times on the quantum computer to be tested is consistent with the predicted result is calculated, and the probability is taken as the execution fidelity of each circuit. Although the execution fidelity compares the consistency between the actual execution result and the predicted result, different ways are needed to calculate the probability that the actual execution result is consistent with the predicted result for different circuits.

[0093] For the target random physical machine circuit and the target special benchmark circuit, after the mirroring operation, the order and manner of quantum gate operation can be affected, so that the results of multiple executions still fall on the fixed point, and the probability result of this point is the execution fidelity of this type of circuit. For example, the execution result obtained after executing the target random physical machine circuit or the target special benchmark circuit on the quantum computer to be tested includes the results of 6 points (for example, [1, 2, 3, 4, 5, 6]), assuming that 500 times are executed, 450 times of results fall on the first point, and 50 times of results fall on the third point, and the probability of falling on the sum of the first point and the third point is considered as the execution fidelity of this type of circuit.

[0094] For the target quantum algorithm circuit, different algorithm circuits have different calculation methods. Among them, for the circuit constructed by the algorithm of the adder and the multiplier, after the circuit simulation, the result distribution of the algorithm will show that the probability amplitude of the target item is significantly higher than that of other items, and through measurement, the high probability result of the target item can be obtained. Assuming that an algorithm circuit is simulated 1000 times in a noise-free simulation environment, the result falls on the second point, which is the expected result. By comparing the expected result with the actual execution result obtained by simulating the quantum computer with noise, the fidelity value ranging from 0 to 1 is obtained, which is the execution fidelity of this type of circuit. For uncertain algorithm circuits, such as quantum Fourier transform algorithm circuits, after simulating this type of circuit, the results can be observed by measuring the quantum bits. Measurement will cause the quantum superposition state to collapse to a specific computational ground state, and the probability of observing each ground state is determined by the square of the amplitude of the ground state. Therefore, if the quantum bits after the quantum Fourier transform are measured multiple times, a probability distribution can be obtained, which reflects the amplitude size of different computational ground states. However, this distribution will be relatively scattered compared to other algorithm circuits, and it is not easy to locate the bit number in the case of a large number of bits. In order to be able to locate the bit number, a cross-entropy loss function is introduced to determine the difference between the probability distribution of this type of circuit after execution on a real quantum computer with noise and a full-amplitude simulator without noise. In quantum computing, cross-entropy can be used to measure the difference between two quantum states. The cross-entropy score is used as the execution fidelity of this type of circuit. For two probability distributions P and Q, the cross-entropy is defined as: H(P, Q) = -∑xP(x)logQ(x), where H(P, Q) is the cross-entropy between distributions P and Q, P(x) is the actual probability (true distribution), and Q(x) is the predicted probability (predicted distribution). The core idea of cross-entropy is to approximate the true distribution with the predicted distribution, and cross-entropy measures the difference between the true distribution and the actual distribution. If the two distributions are exactly the same, the cross-entropy is the smallest, which is zero. If the two distributions are very different, the cross-entropy will also be very large.

[0095] After the base score, the difficulty coefficient and the execution fidelity of each circuit are calculated, the base score, the difficulty coefficient and the execution fidelity of the circuit are multiplied to obtain the evaluation score of the circuit, and the greater the evaluation score indicates the better performance of the quantum computer in executing the circuit. It should be noted that the evaluation score integrates the base score, the difficulty coefficient and the execution fidelity, and can more accurately evaluate the performance of the quantum computer in executing the specific circuit.

[0096] In addition to the virtual quantum computer, the test set generation module, the test set preprocessing module, the execution module and the evaluation module, the quantum computer benchmark test system is also provided with a visual display module for converting the evaluation score of each circuit obtained by the evaluation module into a table, a text file, a radar chart, a column chart and the like. Among them, the table and the text file show the details in the benchmark test process, such as the category, the depth, the width, the base score, the difficulty coefficient and the execution fidelity of each circuit, which are used to record the information of each circuit in the execution process. The radar chart can be used to show the evaluation scores of different circuits and the hierarchical ratio LR, the quantum gate density GD, the cumulative fidelity CF, the parallel degree Par, the serial degree Ser and the entanglement degree Ent of different circuits, so that the user can intuitively understand the performance of the quantum computer in executing different circuits. Figure 2 The radar chart is an example to introduce the evaluation scores of each circuit shown in the chart, which includes three different circuits, one is a random physical machine circuit: random circuit; one is a special benchmark circuit: parallelized circuit, serialized circuit and entangled circuit; the other is a quantum algorithm circuit: adder circuit (adder circuit), qft circuit (quantum Fourier transform algorithm circuit), cnf circuit (conjunctive normal form solving algorithm circuit), qnn circuit (quantum neural network algorithm circuit), vqe circuit (variational quantum algorithm circuit) and quantum walk circuit (quantum random walk algorithm circuit). From the chart, it can be seen that the evaluation scores of the quantum algorithm circuits are much higher than those of the random physical machine circuits and the special benchmark circuits, which indicates that the quantum computer has better performance in executing the quantum algorithm circuits. Figure 2It can be seen that the evaluation score of the random circuit is 100, the evaluation score of the parallelized circuit is 130, the evaluation score of the serialized circuit is 125, the evaluation score of the entangled circuit is 88, the evaluation score of the adder circuit is 93, the evaluation score of the qft circuit is 63, the evaluation score of the cnf circuit is 104, the evaluation score of the qnn circuit is 87, the evaluation score of the vqe circuit is 124, and the evaluation score of the quantum walk circuit is 99. The evaluation score of the parallelized circuit is 130, indicating that the quantum computer has the best working performance when executing the circuit. The evaluation score of the qft circuit is 63, indicating that the quantum computer has the worst working performance when executing the circuit. Further, the radar chart is used to represent the hierarchical ratio LR, quantum gate density GD, cumulative fidelity CF, parallel degree Par, serial degree Ser, and entanglement degree Ent of each circuit represented by the radar chart. Figure 3 The radar chart is used to represent the hierarchical ratio LR, quantum gate density GD, cumulative fidelity CF, parallel degree Par, serial degree Ser, and entanglement degree Ent of each circuit represented by the radar chart. Figure 3 It can be seen that the quantum gate density and parallel degree of the parallelized circuit and the entangled circuit are higher; the hierarchical ratio and serial degree of the serialized circuit are higher; the quantum gate density and entanglement degree of the adder circuit are higher; the quantum gate density of the qft circuit is higher; the quantum gate density and serial degree of the cnf circuit are higher; the quantum gate density, parallel degree, and entanglement degree of the qnn circuit are higher; the quantum gate density of the vqe circuit is higher; and the quantum gate density and entanglement degree of the quantum walk circuit are higher. The bar chart can be used to represent the change of the evaluation score after the transformation of the quantum gate number in each circuit, so as to Figure 4 The bar chart of the random physical machine circuit is used to represent the content represented by the bar chart. Among them, Figure 4 The vertical coordinate is the evaluation score, and the horizontal coordinate is the quantum gate number. Figure 4 It can be seen that as the quantum gate number in the random physical machine circuit increases, the evaluation score shows a downward trend.

[0097] The quantum computer benchmark test system described in the foregoing embodiments can be used to perform benchmark tests to evaluate the working performance of the quantum computer. Based on this, as Figure 5As shown, the present application provides a quantum computer benchmarking method for evaluating the working performance of a computer, which comprises the following steps: S1, obtaining a quantum computer to be tested and information thereof; S2, performing benchmarking on the quantum computer to be tested by using a quantum computer benchmarking system according to the information of the quantum computer to be tested, so as to evaluate the working performance of the quantum computer to be tested. Figure 6 As shown, the benchmarking can be performed according to the following steps: first, obtaining a quantum computer to be tested and information thereof; then, storing the obtained information of the quantum computer to be tested into a virtual quantum computer of the system; then, constructing an initial test circuit set according to the stored information of the quantum computer to be tested by using a test set generation module of the system; then, pre-processing the circuits in the initial test circuit set to obtain a target test circuit set by using a test set preprocessing module of the system; then, transmitting the target test circuit set to the quantum computer to be tested by using a quantum computer interface arranged on an execution module of the system, so as to execute each circuit in the target test circuit set, and transmitting the execution result of each circuit to an evaluation module; then, evaluating the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serialism, entanglement and execution fidelity of the quantum computer to be tested in executing different circuits according to the execution result of each circuit by using the evaluation module, and evaluating the performance of the quantum computer to be tested according to a preset method; finally, displaying the evaluation result by using a visual display module of the system.

[0098] Compared with the prior art, the present application has the following advantages: (1) the circuits are pre-processed by mirroring, so that the pre-processed circuits can output unique error-free solutions, and thus the pre-processed circuits will not affect the running efficiency of the quantum computer; (2) special benchmark circuits are constructed to evaluate the performance of the quantum computer in executing highly parallelized, highly serialized and highly entangled circuits, so that the benchmarking of the quantum computer is more comprehensive; (3) the hierarchical ratio, quantum gate density, cumulative fidelity, parallelism, serialism, entanglement and execution fidelity are used as evaluation indexes to comprehensively evaluate the performance of the quantum computer, so that the evaluation result of the quantum computer is more accurate and reliable.

[0099] It should be noted that although the above describes the steps in a specific order, it does not mean that the steps must be performed in the above specific order, in fact, some of the steps can be performed concurrently or even in a changed order, as long as the required functions can be achieved.

[0100] The present application can be a system, a method and / or a computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions loaded thereon, which are used to enable a processor to implement various aspects of the present application.

[0101] A computer readable storage medium can be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, semiconductor, or any other suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves.

[0102] Having described above several embodiments, now will be described a number of modifications and alternatives. Such description is included to provide for a more complete understanding of the various embodiments and is not intended in any way to limit the scope of possibilities. Many modifications in addition to those described above can be made by one skilled in the relevant art without departing from the scope and spirit of the described embodiments. The scope of the various embodiments disclosed herein cover all technical equivalents that do not depart from the spirit or essential characteristics of the various embodiments. The embodiments illustratively disclosed herein can suitably be practiced in the absence of any element or elements not specifically disclosed herein.

Claims

1. A quantum computer benchmark system for evaluating the performance of a quantum computer, characterized in that: The system comprises: A virtual quantum computer, used to store quantum computer information to be tested; A test set generation module is used to construct an initial test circuit set based on the quantum computer information to be tested stored in the virtual quantum computer, wherein the initial test circuit set includes an initial random physical machine circuit, an initial special benchmark circuit, and an initial quantum algorithm circuit; a test set preprocessing module, configured to preprocess the circuits in the initial test circuit set to obtain a target test circuit set, wherein the preprocessing of the circuits in the initial test circuit set includes mirroring the initial random physical machine circuit and the initial special benchmark circuit and combining the mirror result of the initial random physical machine circuit with the initial random physical machine circuit to obtain a target random physical machine circuit, and combining the mirror result of the initial special benchmark circuit with the initial special benchmark circuit to obtain a target special benchmark circuit; and the preprocessing of the circuits in the initial test circuit set also includes optimizing, mapping, and quantum gate conversion processing the initial quantum algorithm circuit to compile the quantum algorithm circuit into a target circuit that conforms to the execution environment of the quantum computer to be tested; the target random physical machine circuit, the target special benchmark circuit, and the target circuit constitute the target test circuit set; an execution module, configured to transmit the target test circuit set to the quantum computer to be tested via a quantum computer interface provided thereon, so as to execute each circuit in the target test circuit set, and transmit the execution result of each circuit to the evaluation module; The evaluation module is used to evaluate the layering ratio, quantum gate density, cumulative fidelity, parallelism, seriality, entanglement and execution fidelity of the quantum computer to be tested in executing different circuits based on the execution results of each circuit, so as to evaluate the performance of the quantum computer to be tested according to a preset method.

2. The system according to claim 1, wherein: Special benchmark circuits include highly parallel circuits, highly serialized circuits, and highly entangled circuits, among which the ratios of the number of quantum gates in the highly parallelized circuits to the circuit depth and circuit width are all less than or equal to a preset ratio; the ratio of the two-bit quantum gates on the critical path in the highly serialized circuits to the total two-bit quantum gates is less than or equal to a preset ratio, and the critical path refers to the path from the circuit input to the output with the longest operation-dependent span in the circuit; and the ratio of the interactions between all quantum gates and the two-bit quantum gate in the highly entangled circuits is less than or equal to a preset ratio.

3. The system according to claim 2, characterized in that The preset ratio is 1.

4. The system according to claim 3, characterized in that The stratification ratio is calculated as follows: Among them, LR represents the layer ratio of the circuit, n d Indicates the depth of the circuit, n q represents the number of qubits in the circuit, and max(LRs) represents the maximum ratio of the depth to the number of qubits in the target test circuit. The quantum gate density is calculated as follows: Where GD represents the quantum gate density of the circuit, n1 represents the number of single-bit gates of the circuit, and n2 represents the number of two-bit gates of the circuit; The cumulative fidelity is calculated as follows: Where CF represents the cumulative fidelity of the circuit, f1 represents the average single-bit gate fidelity of the quantum computer to be tested, f2 represents the average two-bit gate fidelity of the quantum computer to be tested, and n g Represents the total number of quantum gates in the circuit.

5. The system according to claim 4, characterized in that The degree of parallelism is calculated as follows: Among them, Par represents the parallelism of the circuit; The serialization degree is calculated as follows: Where Ser represents the serial degree of the circuit, n2′ represents the number of two-bit gates on the target bit in the circuit, and the target bit represents the circuit where the degree of overlap between the two-bit gate control bit and the target bit is the highest. The entanglement is calculated as follows: in, Among them, Ent represents the entanglement of the circuit, C i represents the clustering coefficient of the i-th node represented by the quantum bit in the undirected graph composed of circuits, T i represents the number of edges between neighboring nodes of the ith node represented by the quantum bit in the undirected graph composed of circuits, k i Represents the number of edges directly connected to the i-th node represented by the quantum bit in the undirected graph composed of circuits.

6. The system according to claim 5, characterized in that Execution fidelity is calculated as follows: The probability that the actual execution result of each circuit is consistent with the predicted result after it is repeatedly executed multiple times on the quantum computer to be tested is calculated, and this probability is used as the execution fidelity of each circuit.

7. The system according to claim 6, characterized in that The preset method is to evaluate each circuit in the following manner: Calculating the mean of the layering ratio, quantum gate density, and cumulative fidelity of the circuit, and mapping the mean to obtain a basic score of the circuit that is greater than or equal to a preset threshold; Calculating the mean of the parallelism, seriality, and entanglement of the circuit, and mapping the mean to obtain the difficulty coefficient of the circuit within a preset numerical range; The circuit's evaluation score is obtained by multiplying the circuit's basic score, difficulty coefficient, and execution fidelity. The evaluation score represents the performance of the circuit executed by the quantum computer under test.

8. A quantum computer benchmarking method for evaluating the performance of a quantum computer, characterized in that: The method comprises: Step S1, obtaining the quantum computer to be tested and its information; Step S2: Based on the information of the quantum computer to be tested, a benchmark test is performed on the quantum computer to be tested using the system according to any one of claims 1 to 7 to evaluate the working performance of the quantum computer to be tested.

9. A computer-readable storage medium, characterized in that A computer program is stored thereon, and the computer program can be executed by a processor to implement the steps of the method according to claim 8.

10. An electronic device, characterized in that: include: one or more processors; and a memory, wherein the memory is configured to store executable instructions; The one or more processors are configured to implement the steps of the method of claim 8 by executing the executable instructions.

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