A timing controller, a display device and a method

Abstract

The present invention discloses a timing controller, a display device and a method. By collecting the rise time of a target differential signal received by a source driver and comparing the size relationship between the collected rise time and a preset time, the difference between the target differential signal received by the source driver and the target differential signal output by an output module can be determined. This difference can usually be considered to be caused by the loss generated by wire transmission, so the rise speed of the intermediate differential signal can be adjusted according to the difference to compensate for the difference caused by the loss of wire transmission, increase the signal-to-noise ratio of the target differential signal, so that the target differential signal received by the source driver meets the requirements, thereby improving the signal transmission quality and further improving the display effect.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a timing controller, a display device and a method. Background Art

[0002] The timing controller includes: a signal sending circuit and a differential signal generating circuit. The signal sending circuit includes: a reference module, a differential module and an output module. The reference module is connected to the differential module and the output module respectively. The reference module outputs a reference current to the differential module on the one hand, and outputs a reference voltage to the output module on the other hand. The differential module is also connected to the differential signal generating circuit and the output module respectively. The differential signal generating circuit can generate a source differential signal and output it to the differential module. The differential module is used to: adjust the input source differential signal in cooperation with the reference current to generate an intermediate differential signal and output it to the output module, so that when the output module generates a common-mode voltage based on the reference voltage, the intermediate differential signal is superimposed on the common-mode voltage to form a target differential signal and output it, thereby improving the signal-to-noise ratio of the target differential signal.

[0003] However, if the wire is too long, the target differential signal will be lost when transmitted in the wire, which will cause the quality of the target differential signal received by the source driver to be worse than the quality of the target differential signal output by the timing controller; when the source driver drives the display panel for display based on the target differential signal, it will cause the eye diagram to be poor or even closed, affecting the display effect. Summary of the invention

[0004] The embodiments of the present invention provide a timing controller, a display device and a method for improving the transmission quality of a target differential signal, thereby improving the display effect.

[0005] In a first aspect, an embodiment of the present invention provides a timing controller, comprising: a reference module, a differential module, an output module and a pre-emphasis de-emphasis module; the output module is connected to a receiving end of a source driver;

[0006] The reference module is connected to the differential module, the output module, and the pre-emphasis de-emphasis module respectively, and the reference module is used to: output a reference voltage to the output module, and output a reference current to the differential module and the pre-emphasis de-emphasis module respectively;

[0007] The pre-emphasis de-emphasis module is also connected to the receiving end of the differential module and the source driver respectively. The pre-emphasis de-emphasis module is used to: collect the rise time of the target differential signal received by the receiving end of the source driver, and adjust the rise speed of the intermediate differential signal output by the differential module based on the size relationship between the collected rise time and the preset time in cooperation with the reference current;

[0008] The differential module is also connected to the output module, and the differential module is used to: output an intermediate differential signal to the output module according to the input source differential signal, the reference current, and the adjusted rising speed;

[0009] The output module is used to output a target differential signal to the source driver according to a reference voltage and an intermediate differential signal.

[0010] In a second aspect, an embodiment of the present invention provides a method for processing pre-emphasis and de-emphasis, the method being implemented by a timing controller as described in the first aspect above, the method comprising:

[0011] The reference module outputs a reference voltage to the output module, and outputs a reference current to the differential module and the pre-emphasis de-emphasis module respectively;

[0012] The pre-emphasis and de-emphasis module collects the rise time of the target differential signal received by the receiving end of the source driver, and adjusts the rise speed of the intermediate differential signal output by the differential module based on the relationship between the collected rise time and the preset time in cooperation with the reference current;

[0013] The differential module outputs an intermediate differential signal to the output module according to the input source differential signal, the reference current, and the adjusted rising speed;

[0014] The output module outputs a target differential signal to the source driver according to the reference voltage and the intermediate differential signal.

[0015] In a third aspect, an embodiment of the present invention provides a display device, including: a source driver, and a timing controller as described in the first aspect above, wherein the timing controller is connected to the source driver.

[0016] The beneficial effects of the present invention are as follows:

[0017] A timing controller, a display device and a method provided by an embodiment of the present invention can determine the difference between the target differential signal received by the source driver and the target differential signal output by the output module by collecting the rise time of the target differential signal received by the source driver and comparing the size relationship between the collected rise time and the preset time. This difference can usually be considered to be caused by the loss generated by the wire transmission, so the rise speed of the intermediate differential signal can be adjusted according to the difference to compensate for the difference caused by the loss of the wire transmission, increase the signal-to-noise ratio of the target differential signal, so that the target differential signal received by the source driver meets the requirements, thereby improving the signal transmission quality and further improving the display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic diagram of the structure of a display device provided in an embodiment of the present invention;

[0019] Figure 2 It is a structural schematic diagram of a timing controller in the prior art;

[0020] Figure 3 A schematic diagram of the structure of a timing controller provided in an embodiment of the present invention;

[0021] Figure 4 A schematic diagram of the specific structure of the reference module and the differential module provided in the embodiment of the present invention;

[0022] Figure 5 A schematic diagram of the specific structure of the pre-emphasis and de-emphasis module provided in an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of the specific structure of a control unit provided in an embodiment of the present invention;

[0024] Figure 7 A schematic diagram of the specific structure of an output module provided in an embodiment of the present invention;

[0025] Figure 8 A schematic diagram of the structure of another timing controller provided in an embodiment of the present invention;

[0026] Fig. 9 A schematic diagram of the specific structure of the amplitude adjustment module provided in an embodiment of the present invention;

[0027] Fig.10 The present invention provides a flowchart of a method for processing pre-emphasis and de-emphasis in accordance with an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings to describe in detail the specific implementation of a timing controller, a display device and a method provided by an embodiment of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] First, before introducing the technical solution provided by the embodiment of the present invention, the following terms are explained.

[0030] 1. Eye diagram: A tool that graphically represents the waveform of a digital signal, reflecting the impact on the digital signal during the transmission process.

[0031] 2. Differential signal: The differential signal includes two signals with the same amplitude and opposite phase. These two signals are transmitted on two wires respectively.

[0032] In the current technology, see Figure 1As shown, the display device may include: a display panel, a source driver and a timing controller, the display panel is connected to the source driver, the source driver is connected to the timing controller through wires, and the timing controller outputs a target differential signal to the source driver through the wires.

[0033] See also Figure 2 As shown, the timing controller includes: a signal sending circuit and a differential signal generating circuit, the signal sending circuit includes: a reference module, a differential module and an output module, the reference module is connected to the differential module and the output module respectively, the reference module outputs a reference current to the differential module on the one hand, and outputs a reference voltage to the output module on the other hand; the differential module is also connected to the differential signal generating circuit and the output module respectively, the differential signal generating circuit can generate a source differential signal and output it to the differential module, the differential module is used to: with the cooperation of the reference current, adjust the input source differential signal to generate an intermediate differential signal and output it to the output module, so that when the output module generates a common-mode voltage based on the reference voltage, the intermediate differential signal is superimposed with the common-mode voltage to form a target differential signal and output it, thereby improving the signal-to-noise ratio of the target differential signal.

[0034] However, if the wire is too long, the target differential signal will be lost when transmitted in the wire, which will cause the quality of the target differential signal received by the source driver to be worse than the quality of the target differential signal output by the timing controller; when the source driver drives the display panel for display based on the target differential signal, it will cause the eye diagram to be poor or even closed, affecting the display effect.

[0035] Based on this, an embodiment of the present invention provides a timing controller, see Figure 3 As shown, the timing controller may include: a reference module 10, a differential module 20, an output module 30 and a pre-emphasis de-emphasis module 40; the output module 30 is connected to the receiving end m20 of the source driver m2;

[0036] The reference module 10 is connected to the differential module 20, the output module 30, and the pre-emphasis de-emphasis module 40 respectively. The reference module 10 is used to output a reference voltage (such as Figure 3 Vref shown in FIG), and outputs reference current (such as Vref shown in FIG) to the differential module 20 and the pre-emphasis de-emphasis module 40 respectively. Figure 3 Ip and In shown in );

[0037] The pre-emphasis de-emphasis module 40 is also connected to the differential module 20 and the receiving end m20 of the source driver m2 respectively. The pre-emphasis de-emphasis module 40 is used to collect the target differential signal (such as Figure 3The rise time of outP'+outN') shown in FIG is adjusted based on the relationship between the collected rise time and the preset time under the cooperation of the reference current, and the intermediate differential signal (such as outP'+outN') output by the differential module 20 is adjusted. Figure 3 The rising speed of outP+outN) shown in;

[0038] The differential module 20 is also connected to the output module 30. The differential module 20 is used to: Figure 3 inP+inN shown in ), the reference current, and the adjusted rising speed, output the intermediate differential signal to the output module 30; the output module 30 is used to: output the target differential signal to the source driver m2 according to the reference voltage and the intermediate differential signal.

[0039] In actual situations, the rise time of the target differential signal output by the output module 30 can be considered to be within the preset time; by collecting the rise time of the target differential signal received by the source driver m2 and comparing the size relationship between the collected rise time and the preset time, the difference between the target differential signal received by the source driver m2 and the target differential signal output by the output module 30 can be determined. This difference can usually be considered to be caused by the loss generated by the wire transmission, so the rise speed of the intermediate differential signal can be adjusted according to the difference to compensate for the difference caused by the loss of wire transmission, increase the signal-to-noise ratio of the target differential signal, so that the target differential signal received by the source driver m2 meets the requirements, thereby improving the signal transmission quality and further improving the display effect.

[0040] Among them, the preset time can be a fixed value determined based on actual experience, application scenarios and other factors, and the specific value is not specifically limited here.

[0041] It should be understood that, in the embodiment of the present invention, the adjustment of the rising speed of the intermediate differential signal usually occurs in the testing stage before the timing controller leaves the factory, and the rising speed of the intermediate differential signal will remain fixed and will not change after leaving the factory.

[0042] Optionally, combined Figure 3 As shown, the source differential signal can be provided by the differential signal generating circuit m3, and the timing controller can include: the differential signal generating circuit m3 and the signal transmitting circuit m1, the signal transmitting circuit m1 includes a reference module 10, a differential module 20, an output module 30 and a pre-emphasis de-emphasis module 40. In this way, the target differential signal sent by the timing controller can be compensated to improve the signal transmission quality.

[0043] Furthermore, the timing controller may further include a signal receiving circuit, which is not shown in the figure. A pre-emphasis and de-emphasis module 40 may also be added to the signal receiving circuit to compensate for the differential signal received by the timing controller, which is beneficial to improving the display effect of the display device.

[0044] The structure and function of each module will be introduced below.

[0045] 1. Benchmark module 10.

[0046] Alternatively, see Figure 4 As shown, the reference module 10 may include: a bandgap reference unit, a current source Iy, a tenth transistor P10, an eleventh transistor N11, and a twelfth transistor N12; the bandgap reference unit is connected to the output module 30 and the current source Iy respectively, the bandgap reference unit outputs a reference voltage Vref to the output module 30, and outputs an initial current Iref to the current source Iy; the current source Iy is also connected to the first electrode of the eleventh transistor N11, the control electrode of the eleventh transistor N11, the control electrode of the twelfth transistor N12, and the differential module 20, the second electrode of the eleventh transistor N11 and the second electrode of the twelfth transistor N12 are both connected to the second constant voltage signal terminal (i.e., the signal terminal providing VSS), the first electrode of the twelfth transistor N12 is respectively connected to the second electrode of the tenth transistor P10, the control electrode of the tenth transistor P10, and the differential module 20, and the first electrode of the tenth transistor P10 is connected to the first constant voltage signal terminal (i.e., the signal terminal providing VDD). Among them, the eleventh transistor N11 and the twelfth transistor N12 can both be N-type transistors, and the tenth transistor P10 is a P-type transistor, as shown in FIG. Figure 4 As shown; or, the eleventh transistor N11 and the twelfth transistor N12 can both be P-type transistors, and the tenth transistor P10 is an N-type transistor, which is not shown in the figure. In this case, the connection relationship between the tenth transistor P10, the eleventh transistor N11, and the twelfth transistor N12 can be adaptively adjusted according to the characteristics of the actual transistors, which is not limited here.

[0047] In this way, the current source Iy doubles the initial current Iref to obtain a×Iref, and a is a fixed value set according to actual needs; the eleventh transistor N11 and the twelfth transistor N12 are mirror images of each other, and after processing a×Iref, the first reference current In is obtained and output to the control electrode of the fifth transistor N5 of the differential module 20, so as to control the on and off of the fifth transistor N5; under the action of the tenth transistor P10 and the twelfth transistor N12, the second reference current Ip is formed and output to the control electrode of the fourth transistor P4 of the differential module 20, so as to control the on and off of the fourth transistor P4.

[0048] It should be understood that the reference currents mentioned in the above content include: a first reference current In and a second reference current Ip. These two reference currents act on the control electrodes of different transistors in the differential module 20, and act on the first adjustment unit and the second adjustment unit, respectively, so as to facilitate the generation of the target differential signal.

[0049] The specific structure of the bandgap reference unit may be other structures known to those skilled in the art that can realize its functions; and in specific implementation, the specific structure of the reference module 10 is not limited to Figure 4 The structure shown in the figure may also be other structures known to those skilled in the art that can achieve its functions, and is not limited here.

[0050] 2. Differential module 20.

[0051] Alternatively, if Figure 4 As shown, the differential module 20 may include: a fourth transistor P4 , a fifth transistor N5 and a differential processing unit 21 .

[0052] The first electrode of the fourth transistor P4 is connected to the first constant voltage signal end, the second electrode of the fourth transistor P4 is connected to the first end of the differential processing unit 21 and forms a first node x1, and the control electrode of the fourth transistor P4 is connected to the second output end of the differential module 20 for outputting the second reference current Ip; the first electrode of the fifth transistor N5 is connected to the second constant voltage signal end, the second electrode of the fifth transistor N5 is connected to the second end of the differential processing unit 21 and forms a second node x2, and the control electrode of the fifth transistor N5 is connected to the first output end of the differential module 20 for outputting the first reference current In; the first node x1 and the second node x2 are also connected to the pre-emphasis de-emphasis module 40; wherein the fourth transistor P4 and the fifth transistor N5 are of different types, for example, the fourth transistor P4 is a P-type transistor, the fifth transistor N5 is an N-type transistor, or the fourth transistor P4 is an N-type transistor, and the fifth transistor N5 is a P-type transistor; it can be specifically set according to actual needs and is not specifically limited here.

[0053] The third terminal x3 of the differential processing unit 21 is used to connect one of the two source signal terminals providing the source differential signal (eg Figure 4 The fourth terminal x4 of the differential processing unit 21 is used to connect the other signal terminal of the two source signal terminals (such as Figure 4The fifth terminal x5 and the sixth terminal x6 of the differential processing unit 21 are both connected to the output module 30; the differential processing unit 21 is used to: under the control of the source differential signal and the reference current, determine and output the intermediate differential signal according to the adjusted rising speed, the first constant voltage signal VDD provided by the first constant voltage signal terminal, and the second constant voltage signal VSS provided by the second constant voltage signal terminal.

[0054] Therefore, the potentials of the first node x1 and the second node x2 will affect the output intermediate differential signal. Moreover, by adjusting the rising speed of the intermediate differential signal, the intermediate differential signal can be compensated, and then the target differential signal can be compensated, thereby improving the transmission quality of the signal between the timing controller and the source driver m2.

[0055] Furthermore, if Figure 4 As shown, the differential processing unit 21 may include: a sixth transistor P6, a seventh transistor P7, an eighth transistor N8 and a ninth transistor N9; the control end of the sixth transistor P6 and the control end of the eighth transistor N8 are both connected to one of the signal ends (such as Figure 4 The control end of the seventh transistor P7 and the control end of the ninth transistor N9 are both connected to another signal end (as shown in Figure 4 ) is connected to the signal end of inP shown in ; the first pole of the sixth transistor P6 and the first pole of the seventh transistor P7 are both connected to the first node x1, and the second pole of the sixth transistor P6 and the second pole of the seventh transistor P7 are both connected to the output module 30; the first pole of the eighth transistor N8 and the first pole of the ninth transistor N9 are both connected to the output module 30, and the second pole of the eighth transistor N8 and the second pole of the ninth transistor N9 are both connected to the second node x2. Wherein, the sixth transistor P6 and the seventh transistor P7 are of the same type, such as both are P-type transistors, and the eighth transistor N8 and the ninth transistor N9 are of the same type, such as both are N-type transistors; or, the sixth transistor P6 and the seventh transistor P7 are both N-type transistors, and the eighth transistor N8 and the ninth transistor N9 are both P-type transistors, which can be set according to actual needs, and are not specifically limited here. In this way, through the setting of four transistors, the function of the differential processing unit 21 can be realized, so as to realize the conversion of the source differential signal into the intermediate differential signal and output it to the output module 30.

[0056] Of course, in specific implementation, the specific structure of the differential processing unit 21 is not limited to Figure 4 The structure shown in the figure may also be other structures known to those skilled in the art that can achieve its functions, and is not limited here.

[0057] 3. Pre-emphasis and de-emphasis module 40.

[0058] Optionally, the pre-emphasis and de-emphasis module 40 is specifically used to: collect the rise time of the target differential signal received by the receiving end m20 of the source driver m2, and determine the difference between the collected rise time and the preset time; when the collected rise time is greater than the preset time, turn on the pre-emphasis function, and increase the rise speed of the intermediate differential signal output by the differential module 20 according to the difference in cooperation with the reference current; when the collected rise time is less than the preset time, turn on the de-emphasis function, and reduce the rise speed of the intermediate differential signal output by the differential module 20 according to the difference in cooperation with the reference current. In this way, it can be determined whether to turn on the pre-emphasis function or the de-emphasis function according to the size relationship between the collected rise time and the preset time, thereby realizing the adjustment of the rise speed of the intermediate differential signal, which is conducive to realizing the compensation of the target differential signal.

[0059] In order to realize the function of the pre-emphasis de-emphasis module 40, see Figure 5 As shown, the pre-emphasis de-emphasis module 40 includes: a control unit 43, a plurality of first adjustment units 41 and a plurality of second adjustment units 42; the control unit 43 is respectively connected to the receiving end m20 of the source driver m2, the control end of each first adjustment unit 41, and the control end of each second adjustment unit 42; the first adjustment unit 41 is also respectively connected to the first constant voltage signal end, the second constant voltage signal end, the reference module 10, and the differential module 20; the second adjustment unit 42 is also respectively connected to the first constant voltage signal end, the second constant voltage signal end, the reference module 10, and the differential module 20; the control unit 43 is used to:

[0060] The rise time of the target differential signal received by the receiving end m20 of the source driver m2 is collected to determine the difference; when the collected rise time is greater than the preset time, the pre-emphasis function is turned on, and the first adjustment gear corresponding to the difference is determined, and according to the first adjustment gear, in cooperation with the reference current, the corresponding number of first adjustment units 41 are controlled to be turned on, and all the second adjustment units 42 are controlled to be turned on, so that the turned-on first adjustment unit 41 and the turned-on second adjustment unit 42 output the first constant voltage signal VDD provided by the first constant voltage signal end and the second constant voltage signal VSS provided by the second constant voltage signal end to the differential Module 20, increases the rising speed of the intermediate differential signal output by the differential module 20; when the collected rise time is less than the preset time, turns on the de-emphasis function, determines the second adjustment gear corresponding to the difference value, and controls the corresponding number of first adjustment units 41 to turn on and the corresponding number of second adjustment units 42 to turn on according to the second adjustment gear in cooperation with the reference current, so that the turned-on first adjustment units 41 and the turned-on second adjustment units 42 output the first constant voltage signal VDD and the second constant voltage signal VSS to the differential module 20, thereby reducing the rising speed of the intermediate differential signal output by the differential module 20.

[0061] Among them, the number of first adjustment units 41 and second adjustment units 42 can be set to be the same and one-to-one corresponding, and the connection relationship between the first adjustment unit 41 and the reference module 10, the differential module 20, and the control unit 43 can be basically similar to the connection relationship between the second adjustment unit 42 and the reference module 10, the differential module 20, and the control unit 43, so all the first adjustment units 41 can be regarded as one group of structures, and all the second adjustment units 42 can be regarded as another group of structures, and the setting methods of the two groups of structures are basically similar.

[0062] In this way, when the pre-emphasis function is turned on or started, all the second adjustment units 42 are turned on, and at least part of the first adjustment units 41 are turned on to increase the rising speed of the intermediate differential signal, and the degree of increase in the rising speed of the intermediate differential signal can be adjusted by controlling the number of the turned-on first adjustment units 41. For example, the more the number of turned-on first adjustment units 41, the faster the rising speed of the intermediate differential signal, and the fewer the number of turned-on first adjustment units 41, the slower the rising speed of the intermediate differential signal, so that the rising speed of the intermediate differential signal can be accurately adjusted based on the difference between the collected rise time and the preset time, so as to improve the efficiency of the adjustment, thereby improving the transmission quality of the target differential signal.

[0063] When the de-emphasis function is turned on or started, at least part of the first adjustment units 41 is turned on, wherein the number of the first adjustment units 41 and the second adjustment units 42 turned on can be set to: the number of the turned-on first adjustment units 41 is the same as the number of the unturned second adjustment units 42, or the number of the turned-on first adjustment units 41 is the same as the number of the turned-on second adjustment units 42. In this way, by adjusting the number of the turned-on first adjustment units 41 and the second adjustment units 42, the rise speed of the intermediate differential signal can be accurately adjusted based on the difference between the collected rise time and the preset time, so as to improve the adjustment efficiency and thus improve the transmission quality of the target differential signal.

[0064] Optionally, the control unit 43 may determine the adjustment gear position in the following ways:

[0065] The first method is automatic determination: for example, it is pre-configured to add a gear each time the adjustment is made, and the selection starts from the first gear; or the corresponding adjustment gear is determined according to the difference between the collected rise time and the preset time, and the corresponding relationship table of the gears. In this way, the automatic selection of the adjustment gear can be realized, and the intelligent design of the adjustment can be realized.

[0066] The second method is manual determination: for example, the staff determines the adjustment gear according to the difference between the collected rise time and the preset time and experience. In this way, when the automatic adjustment is abnormal, the manual determination method can be used to ensure the adjustment of the rise speed of the intermediate differential signal.

[0067] 3.1. Structure of the first regulating unit 41 and the second regulating unit 42.

[0068] Alternatively, see Figure 5 As shown, at least one of the first regulating unit 41 and the second regulating unit 42 includes a first circuit 40a and a second circuit 40b, wherein the first circuit 40a is respectively connected to the reference module 10, the control unit 43, the first node x1 in the differential module 20, and the first constant voltage signal terminal; the second circuit 40b is respectively connected to the reference module 10, the control unit 43, the second node x2 in the differential module 20, and the second constant voltage signal terminal; the first circuit 40a is used for: when it is turned on under the action of the control unit 43 and the reference current, transmitting the first constant voltage signal VDD to the first node x1; the second circuit 40b is used for: when it is turned on under the action of the control unit 43 and the reference current, transmitting the second constant voltage signal VSS to the second node x2; wherein the first node x1 and the second node x2 are two different nodes in the differential module 20, respectively.

[0069] That is to say, there are the following situations: the first adjustment unit 41 includes the first circuit 40a and the second circuit 40b, and the second adjustment unit 42 does not include the first circuit 40a and the second circuit 40b; or, the first adjustment unit 41 does not include the first circuit 40a and the second circuit 40b, and the second adjustment unit 42 includes the first circuit 40a and the second circuit 40b; or, the first adjustment unit 41 includes the first circuit 40a and the second circuit 40b, and the second adjustment unit 42 also includes the first circuit 40a and the second circuit 40b; the specific settings can be made according to the actual situation to meet the needs of different application scenarios and improve the flexibility of the design. Among them, the following contents are all based on Figure 5 The first regulating unit 41 and the second regulating unit 42 shown in the figure both include the first circuit 40a and the second circuit 40b for explanation.

[0070] By setting the above-mentioned first circuit 40a and second circuit 40b, it can be achieved that each first circuit 40a is arranged in parallel between the first constant voltage signal end and the first node x1, and each second circuit 40b is arranged in parallel between the second constant voltage signal end and the second node x2; taking the first adjustment unit 41 as an example, when multiple first adjustment units 41 are turned on, the first circuit 40a in these turned-on first adjustment units 41 can inject current into the first node x1 or absorb current, thereby adjusting the potential of the first node x1, and the second circuit 40b in these turned-on first adjustment units 41 can inject current into the second node x2 or absorb current, thereby adjusting the potential of the second node x2; based on the introduction of the differential module 20 in the above content, it can be known that the potential of the first node x1 and the second node x2 will affect the size of the output intermediate differential signal, so by adjusting the potential of the first node x1 and the second node x2, the rising speed of the output intermediate differential signal can be adjusted.

[0071] Further, see Figure 5 As shown, the first circuit 40a includes: a first switch V1 and a first transistor P1; the first switch V1 is respectively connected to the control electrode of the first transistor P1, the reference module 10, and the control unit 43; the first electrode of the first transistor P1 is connected to the first constant voltage signal end, and the second electrode of the first transistor P1 is connected to the first node x1; the second circuit 40b includes: a second switch V2 and a second transistor N2; the second switch V2 is respectively connected to the control electrode of the first transistor P1, the reference module 10, and the control unit 43; the first electrode of the second transistor N2 is connected to the second constant voltage signal end, and the second electrode of the second transistor N2 is connected to the second node x2; wherein the first transistor P1 and the second transistor N2 are of different types; for example, when the first constant voltage signal is greater than the second constant voltage signal, the first transistor P1 can be a P-type transistor, and the second transistor N2 can be an N-type transistor; or, when the first constant voltage signal is less than the second constant voltage signal, the first transistor P1 can be an N-type transistor, and the second transistor N2 can be a P-type transistor.

[0072] Moreover, both the first switch V1 and the second switch V2 can be implemented by CMOS transistors. Taking the first switch V1 as an example, the first switch V1 is composed of a PMOS transistor and an NMOS transistor. The signals input to the two control terminals of the first switch V1 are V1-ctrlP and V1-ctrlN respectively. The levels of V1-ctrlP and V1-ctrlN are opposite. V1-ctrlP is used to control the closing and opening of the PMOS transistor, and V1-ctrlN is used to control the closing and opening of the NMOS transistor. When V1-ctrlP is at a low level and V1-ctrlN is at a high level, the first switch V1 is closed. When V1-ctrlP is at a high level and V1-ctrlN is at a low level, the first switch V1 is opened. Therefore, by controlling the signals input to the two control terminals, the conduction states of the first switch V1 and the second switch V2 can be controlled. Of course, the first switch V1 and the second switch V2 may also be switches of other forms, such as PMOS transistor switches, NMOS transistors, etc., and the types of the first switch V1 and the second switch V2 may be the same or different, and the signals input to their control ends may be adaptively adjusted to meet the working needs of the first switch V1 and the second switch V2. The specific settings may be made according to actual needs and are not specifically limited here.

[0073] Optionally, the width-to-length ratios of the first channels in the first transistors P1 belonging to different first adjustment units 41 are different, and the width-to-length ratios of the second channels in the second transistors N2 belonging to different first adjustment units 41 are different; for example, Figure 5 Three first adjustment units 41 are shown in the figure, so the three first adjustment units 41 correspond to a total of three first transistors P1 and three second transistors N2, and the width-to-length ratios of the first channels of the three first transistors P1 are different, and the width-to-length ratios of the second channels of the three second transistors N2 are different. In this way, the adjustment capabilities of different first adjustment units 41 to the potentials of the first node x1 and the second node x2 can be different, and then a plurality of adjustment gears can be formed through the combination of multiple first adjustment units 41. When adjusting the rising speed of the intermediate differential signal, the corresponding adjustment gear can be selected according to the difference between the collected rising time and the preset time to achieve accurate and rapid adjustment. Of course, the width-to-length ratios of the first channels of the three first transistors P1 can also be the same, and the width-to-length ratios of the second channels of the three second transistors N2 can also be the same, which can simplify the structure of the timing controller, reduce the difficulty of production, and reduce the production cost.

[0074] Further, for the first channels in the first transistors P1 belonging to different first adjustment units 41: the width-to-length ratio of each first channel changes in proportion according to the arrangement direction of each first transistor P1; for the second channels in the second transistors N2 belonging to different first adjustment units 41: the width-to-length ratio of each second channel changes in proportion according to the arrangement direction of each second transistor N2. Figure 5 As shown in the figure, three first adjustment units 41 correspond to three first channels. From left to right, the width-to-length ratios of the three first channels are: 1 、b 2 、b 3 Therefore, the width-to-length ratio of two adjacent first channels differs by a constant b, wherein the constant b can be 2, 3, 4 or other values, which are not specifically limited here.

[0075] Similarly, the width-to-length ratio of the first channel in each first transistor P1 belonging to different second adjustment units 42 is different, and the width-to-length ratio of the second channel in each second transistor N2 belonging to different second adjustment units 42 is different. In this way, different second adjustment units 42 can have different adjustment capabilities for the potentials of the first node x1 and the second node x2, and then a plurality of adjustment gears can be formed through the combination of multiple second adjustment units 42. When adjusting the rising speed of the intermediate differential signal, the corresponding adjustment gear can be selected according to the difference between the collected rising time and the preset time to achieve accurate and rapid adjustment. Of course, the width-to-length ratio of the first channel of the three first transistors P1 can also be the same, and the width-to-length ratio of the second channel of the three second transistors N2 can also be the same, which can simplify the structure of the timing controller, reduce the difficulty of production, and reduce the production cost.

[0076] Further, for the first channels in the first transistors P1 belonging to different second adjustment units 42: according to the arrangement direction of the first transistors P1, the width-to-length ratio of the first channels changes in proportion; for the second channels in the second transistors N2 belonging to different second adjustment units 42: according to the arrangement direction of the second transistors N2, the width-to-length ratio of the second channels changes in proportion; for example, Figure 5 As shown in the figure, three second adjustment units 42 correspond to three first channels. From left to right, the width-to-length ratios of the three first channels are: c 1 、c 2 、c 3 Therefore, the width-to-length ratio of two adjacent first channels differs by a constant c, wherein the constant c can be 2, 3, 4 or other values, which are not specifically limited here.

[0077] In summary, no matter for the first adjustment unit 41 or the second adjustment unit 42, the width-to-length ratio of the corresponding first channels can be changed not only in equal proportion but also in non-equal proportion, and can be set according to actual needs to meet the needs of different application scenarios.

[0078] It should be understood that the setting of the width-to-length ratio of the first channel and the second channel can be applicable only to the first adjustment unit 41, or only to the second adjustment unit 42, or to the first adjustment unit 41 and the second adjustment unit 42. It can be set according to actual needs and is not specifically limited here.

[0079] In this way, by setting the width-to-length ratio of each first channel and the second channel, the ability of the first adjustment unit 41 and the second adjustment unit 42 to inject current or absorb current into the first node x1 and the second node x2 can be adjusted, thereby adjusting the degree of influence on the potential of the first node x1 and the second node x2, thereby achieving finer and more accurate adjustment, thereby further improving the transmission quality of the target differential signal.

[0080] 3.2. Structure of the control unit 43.

[0081] Alternatively, see Figure 6 As shown, the control unit 43 may include: a first processor 431 and a plurality of first processing circuits 432; the acquisition terminal D1 of the first processor 431 is connected to the receiving terminal m20 of the source driver m2, the function selection output terminal D2 of the first processor 431 is respectively connected to each first processing circuit 432, the first processor 431 has a plurality of first control signal output terminals D3, each first control signal output terminal D3 is correspondingly connected to each first processing circuit 432; each first processing circuit 432 is also respectively connected to one of the first adjustment units 41 and one of the second adjustment units 42, and different first adjustment units 41 are connected to different first processing circuits 432, and different second adjustment units 42 are connected to different first processing circuits 432. Among them, the acquisition terminal D1 is used to realize the acquisition of the rising speed of the target differential signal, the function selection output terminal D2 is used to output the first start signal or the second start signal, and the first control signal output terminal D3 is used to output the first control signal or the second control signal.

[0082] The first processor 431 is used to: collect the rise time of the target differential signal received by the receiving end m20 of the source driver m2 to determine the difference; when the collected rise time is greater than the preset time, output a first start signal for starting the pre-emphasis function to each first processing circuit 432; and determine the first adjustment gear, and according to the first adjustment gear, output a first control signal to the first processing circuit 432 corresponding to the first adjustment unit 41 to be turned on, so that the first processing circuit 432 controls the corresponding first adjustment unit 41 and the second adjustment unit 42 to be turned on based on the first control signal; when the collected rise time is less than the preset time, output a second start signal for starting the de-emphasis function to the first processing circuit 432; and determine the second adjustment gear, and according to the second adjustment gear, output a second control signal to the first processing circuit 432 corresponding to the first adjustment unit 41 to be turned on, so that the first processing circuit 432 controls the corresponding first adjustment unit 41 or the second adjustment unit 42 to be turned on based on the second control signal.

[0083] That is, the function selection output terminal D2 of the first processor 431 is connected to each first processing circuit 432, and when the function selection output terminal D2 is used to output the first start signal and the second start signal, each first processing circuit 432 can receive the first start signal or the second start signal, so that each first processing circuit 432 is in the state of the pre-emphasis function or the state of the de-emphasis function, thereby realizing unified control of the state of each first processing circuit 432 through the first processor 431. The first start signal can be a high level signal, and the second start signal can be a low level signal; or the first start signal can be a low level signal, and the second start signal can be a high level signal.

[0084] Moreover, a first adjustment unit 41 and a corresponding second adjustment unit 42 can be regarded as an adjustment group, so when the first adjustment unit 41 and the second adjustment unit 42 are set one by one, the number of the first adjustment units 41 is equal to the number of the adjustment groups, and each first processing circuit 432 is connected to the first switch V1 and the second switch V2 in an adjustment group. In other words, different first processing circuits 432 are connected to different adjustment groups; in this way, the first processor 431 can control whether the first switch V1 and the second switch V2 in the corresponding adjustment group are turned on through the first processing circuit 432, and then control the corresponding number of first adjustment units 41 and second adjustment units 42 to be turned on when starting the pre-emphasis function or starting the de-emphasis function, so that the corresponding first adjustment units 41 and the second adjustment units 42 are controlled separately through the first processor 431 and the first processing circuit 432, so as to achieve precise adjustment of the rising speed of the intermediate differential signal.

[0085] Further, see Figure 6As shown, the first processing circuit 432 may include: a first logic gate F0, a first inverter F1, a second inverter F2, a third inverter F3, and a fourth inverter F4; the first input end of the first logic gate F0 is connected to the function selection output end D2 of the first processor 431, the second input end of the first logic gate F0 is respectively connected to the output end of the first inverter F1 and the input end of the second inverter F2, and the output end of the first logic gate F0 is connected to the input end of the fourth inverter F4; the input end of the first inverter F1 is connected to the first control signal output end D3 of the first processor 431; the output end of the second inverter F2 is connected to the input end of the third inverter F3; the output end of the third inverter F3 is connected to the corresponding first adjustment unit 41; and the output end of the fourth inverter F4 is connected to the corresponding second adjustment unit 42.

[0086] Among them, when both the first switch V1 and the second switch V2 have two control terminals, the output terminal of the first logic gate F0 is also connected to one of the control terminals of the second switch V2, and the output terminal of the fourth inverter F4 is also connected to the other control terminal of the second switch V2, so when the output terminal of the first logic gate F0 outputs a low level and the output terminal of the fourth inverter F4 outputs a high level, the second switch V2 will be closed, otherwise the second switch V2 will be disconnected; or, when the output terminal of the first logic gate F0 outputs a high level and the output terminal of the fourth inverter F4 outputs a low level, the second switch V2 will be closed, otherwise the second switch V2 will be disconnected.

[0087] Similarly, the output end of the second inverter F2 is also connected to one of the control ends of the first switch V1, and the output end of the third inverter F3 is also connected to the other control end of the first switch V1. Therefore, when the output end of the second inverter F2 outputs a high level and the output end of the third inverter F3 outputs a low level, the first switch V1 will be closed, otherwise the first switch V1 will be disconnected; or, when the output end of the second inverter F2 outputs a low level and the output end of the third inverter F3 outputs a high level, the first switch V1 will be closed, otherwise the first switch V1 will be disconnected.

[0088] In this way, through the cooperation of the first logic gate F0 and the four inverters, it is possible to control whether the first switch V1 and the second switch V2 in the corresponding adjustment group are closed, thereby achieving the adjustment of the potential of the first node x1 and the second node x2.

[0089] Specifically, the first logic gate F0 can be a NOR gate or a NAND gate; when the first logic gate F0 is a NOR gate, the first start signal can be a high level signal, and the second start signal can be a low level signal, so that each adjustment group can be controlled; when the first logic gate F0 is a NAND gate, the first start signal can be a low level signal, and the second start signal can be a high level signal, so that each adjustment group can also be controlled.

[0090] 4. Output module 30.

[0091] Alternatively, see Figure 7 As shown, the output module 30 may include: an operational amplifier, a first resistor R1 and a second resistor R2, the first input terminal of the operational amplifier is connected to the reference module 10, the reference module 10 outputs a reference voltage to the first input terminal of the operational amplifier, the second input terminal of the operational amplifier is respectively connected to the output terminal of the operational amplifier, the connection node between the first resistor R1 and the second resistor R2 (i.e., the third node k3), the other end of the first resistor R1 is respectively connected to the fifth end of the differential module 20 and the output terminal of the source driver m2, and the other end of the second resistor R2 is respectively connected to the sixth end of the differential module 20 and the output terminal of the source driver m2. In this way, the voltage of the third node k3 is the common mode voltage output by the operational amplifier based on the reference voltage, and the common mode voltage is superimposed on the intermediate differential signal to form a target differential signal and output.

[0092] Of course, the specific structure of the output module 30 is not limited to Figure 7 As shown in , it can also be other structures that are well known to those skilled in the art and can achieve its functions, which are not specifically limited here.

[0093] 5. Amplitude adjustment module 50.

[0094] Alternatively, see Figure 8 As shown, the timing controller may further include an amplitude adjustment module 50, which is connected to the reference module 10; the amplitude adjustment module 50 is used to: in response to the adjustment instruction of the amplitude of the target differential signal, according to the amplitude of the target differential signal received by the receiving end m20 of the source driver m2 and the preset amplitude, adjust the reference current output by the reference module 10. The preset amplitude may be determined based on experience, application scenarios, and other factors, and the specific value is not specifically limited here.

[0095] When the amplitude of the collected target differential signal is less than the preset amplitude, it means that the loss of the target differential signal transmitted in the wire is large. At this time, it is necessary to increase the reference current, thereby increasing the amplitude of the intermediate differential signal, and finally increasing the amplitude of the output target differential signal. When the amplitude of the collected target differential signal is greater than the preset amplitude, it means that the output target differential signal is too large and needs to be reduced. At this time, it is necessary to reduce the reference current, thereby reducing the amplitude of the intermediate differential signal, and finally reducing the amplitude of the output target differential signal. Therefore, in an embodiment of the present invention, not only the rising speed of the intermediate differential signal can be adjusted, but also the amplitude of the reference current can be adjusted, and then the amplitude of the target differential signal can be adjusted, so that the transmission quality of the target differential signal can be further improved.

[0096] Specifically, see Fig. 9As shown, the amplitude adjustment module 50 includes: a second processor 51, a plurality of second processing circuits 52 and a plurality of amplitude adjustment units 53. The acquisition terminal D4 of the second processor 51 is connected to the receiving terminal m20 of the source driver m2, and the acquisition terminal D4 is used to collect the amplitude of the target differential signal received by the receiving terminal m20 of the source driver m2; the enable output terminal D5 of the second processor 51 is respectively connected to each second processing circuit 52, and the enable output terminal D5 is used to output an enable signal to each second processing circuit 52 to drive the second processing circuit 52 to start working; the second processor 51 has a plurality of The second control signal output terminal D6, each second control signal output terminal D6 is correspondingly connected to each second processing circuit 52; each second processing circuit 52 is correspondingly connected to each amplitude adjustment unit 53, so that the second control signal output terminal D6, the second processing circuit 52, and the amplitude adjustment unit 53 are all connected one by one; the amplitude adjustment unit 53 is also respectively connected to the second constant voltage signal terminal and the output terminal of the reference module 10; wherein the amplitude adjustment unit 53 is not associated with the adjustment group mentioned in the above content, so the setting number of the amplitude adjustment unit 53 and the setting number of the adjustment group can be the same or different;

[0097] The second processor 51 is used to: respond to the adjustment instruction, according to the amplitude of the target differential signal received by the receiving end m20 of the source driver m2 and the preset amplitude, control the corresponding number of amplitude adjustment units 53 to turn on through the second processing circuit 52, so that the turned-on amplitude adjustment units 53 transmit the second constant voltage signal VSS provided by the second constant voltage signal end to the output end of the reference module 10, and adjust the reference current output by the reference module 10.

[0098] So, combined Figure 4 In the structure of the differential module 20 in FIG. 1 , when a certain number of amplitude adjustment units 53 are turned on, these amplitude adjustment units 53 will transmit the second constant voltage signal VSS to the fourth node k4, thereby adjusting the second reference current Ip output by the reference module 10; since the second reference current Ip flows into the control electrode of the fourth transistor in the differential module 20, the change in the magnitude of the second reference current Ip can change the degree of opening of the fourth transistor, thereby changing the potential of the first node x1, and further changing the amplitude of the intermediate differential signal output by the differential module 20, thereby changing the amplitude of the target differential signal. Moreover, by controlling the corresponding number of amplitude adjustment units 53 to be turned on, the degree to which the reference current is adjusted can be selected, thereby achieving precise adjustment, thereby precisely adjusting the amplitude of the target differential signal.

[0099] It should be noted that, since the pre-emphasis de-emphasis module 40 can also adjust the potentials of the first node x1 and the second node x2, but the pre-emphasis de-emphasis module 40 directly acts on the first node x1 and the second node x2, the impact on the potentials of the first node x1 and the second node x2 is relatively small, and the impact on the amplitude of the intermediate differential signal is small, so it mainly affects the rising speed of the intermediate differential signal. The amplitude adjustment module 50 directly acts on the control electrode of the fourth transistor through the second reference current Ip, and then acts on the first node x1 and the second node x2. At this time, the impact on the potentials of the first node x1 and the second node x2 is relatively large, and the impact on the amplitude of the intermediate differential signal is large, so it mainly affects the amplitude of the intermediate differential signal.

[0100] Further, see Fig. 9 As shown, the reference module 10 includes a first output terminal and a second output terminal, the reference current includes a first reference current In and a second reference current Ip, the first output terminal is used to output the first reference current In, and the second output terminal is used to output the second reference current Ip;

[0101] The amplitude adjustment unit 53 includes: a third switch V3 and a third transistor N3, wherein the third switch V3 is connected to the control electrode of the third transistor N3, the second processing circuit 52, and the first output terminal respectively; the first electrode of the third transistor N3 is connected to the second constant voltage signal terminal, and the second electrode of the third transistor N3 is connected to the second output terminal (i.e., the fourth node k4). The configuration of the third switch V3 can be similar to that of the first switch V1, and will not be described in detail here.

[0102] In this way, when the third switch V3 is closed, the first reference current In can control the corresponding third transistor N3 to turn on, and transmit the second constant voltage signal VSS to the fourth node k4; therefore, by controlling each third switch V3, the number of third transistors N3 that are turned on can be controlled, and then the current injected into the fourth node k4 can be controlled, thereby adjusting the second reference current Ip.

[0103] The second processing circuit 52 may include: a second logic gate F6 and a fifth inverter F5; the first input end of the second logic gate F6 is connected to the enable output end D5 of the second processor 51, the second input end of the second logic gate F6 is connected to the second control signal output end D6 of the second processor 51, the output end of the second logic gate F6 is connected to the input end of the fifth inverter F5, and the output end of the fifth inverter F5 is connected to the amplitude adjustment unit 53. The output end of the second logic gate F6 is also connected to one of the two control ends of the third switch V3 (i.e. Fig. 9 The output terminal of the fifth inverter F5 is connected to the other control terminal of the two control terminals of the third switch V3 (i.e., the corresponding control terminal of swb1, wsb2 or swb3 shown in FIG. 1 ), and the output terminal of the fifth inverter F5 is connected to the other control terminal of the two control terminals of the third switch V3 (i.e., Fig. 9 In this way, it is possible to control whether the third switch V3 of the correspondingly connected amplitude adjustment unit 53 is closed, thereby controlling the magnitude of the current injected into the fourth node k4, thereby adjusting the second reference current Ip.

[0104] Combine the following Figure 4 , Figure 5 , Figure 6 , Figure 7 and Fig. 9 The structure shown in the figure describes the working process of the timing controller.

[0105] The reference module 10 outputs a reference voltage Vref to the output module 30 , and further outputs a second reference current Ip to a control electrode of the fourth transistor P4 in the differential module 20 , and outputs a first reference current In to a control electrode of the fifth transistor N5 in the differential module 20 .

[0106] When the amplitude adjustment module 50 is provided, it is assumed that the required amplitude adjustment is determined according to the difference between the amplitude of the target differential signal received by the receiving end m20 of the source driver m2 and the preset amplitude. Fig. 9 When the two amplitude adjustment units 53 on the left side are turned on, the second processor 51 sends a signal to the second processor 51 through the second processing circuit 52. Fig. 9 The third switch V3 in the leftmost amplitude adjustment unit 53 outputs signals sw1 and swb1, and sw1 is at a high level and swb1 is at a low level. At this time, the third switch V3 is closed, and the first reference current In is transmitted to the control electrode of the third transistor N3. The third transistor N3 is turned on, and the second constant voltage signal VSS is transmitted to the fourth node k4; and the second processor 51 sends the first reference current In to the control electrode of the third transistor N3 through the second processing circuit 52. Fig. 9 The third switch V3 in the second amplitude adjustment unit 53 on the left side outputs signals sw2 and swb2, and sw2 is high level and swb2 is low level. At this time, the third switch V3 is closed, and the first reference current In is transmitted to the control electrode of the third transistor N3. The third transistor N3 is turned on to transmit the second constant voltage signal VSS to the fourth node k4; in this way, the size of the second reference current Ip output by the reference module 10 is changed, and then the opening degree of the fourth transistor P4 in the differential module 20 is changed, thereby changing the potential of the first node x1 in the differential module 20 to adjust the amplitude of the intermediate differential signal output by the differential module 20.

[0107] If the rise time collected by the first processor 431 is greater than the preset time, it is determined that the pre-emphasis function needs to be turned on. At this time, the first processor 431 outputs a first start signal (such as a high-level signal) to the first input terminal of each first logic gate F0; at this time, no matter whether the first inverter F1 outputs a high level or a low level, the first logic gate F0 always outputs a low level, so the k21b, k22b, and k23b output by each first processing circuit 432 are all low levels, and the k21, k22, and k23 output by each first processing circuit 432 are all high levels, and then all the second adjustment units 42 are turned on.

[0108] Assume that the adjustment gear is determined based on the difference between the collected rise time and the preset time: Figure 5 The first adjustment unit 41 on the left side is turned on. At this time, the first processor 431 sends Figure 6 The input terminal of the first inverter F1 of the top first processing circuit 432 outputs a high level, and the input terminals of the first inverters F1 of the other first processing circuits 432 output a low level, then Figure 6 The top first processing circuit 432 outputs k11 at a high level and k11b at a low level, while the other first processing circuits 432 output k12 and k13 at low levels and output k12b and k13b at high levels; Figure 5 The first switch V1 and the second switch V2 in the first regulating unit 41 on the far left are closed, controlling the connected first transistor P1 and the second transistor N2 to be turned on, transmitting the first constant voltage signal VDD to the first node x1, and transmitting the second constant voltage signal VSS to the second node x2, so as to increase the rising speed of the intermediate differential signal output by the differential module 20.

[0109] If the rise time collected by the first processor 431 is less than the preset time, it is determined that the de-emphasis function needs to be enabled, and the first processor 431 outputs a second start signal (such as a low level signal) to the first input terminal of each first logic gate F0.

[0110] Assume that the adjustment gear is determined based on the difference between the collected rise time and the preset time: Figure 5 The first adjustment unit 41 on the right side is turned on. At this time, the first processor 431 sends Figure 6 The input terminal of the first inverter F1 of the bottom first processing circuit 432 outputs a high level, and the input terminals of the first inverters F1 of other first processing circuits 432 output a low level, then Figure 6 The k13 output by the bottom first processing circuit 432 is high level, and the k13b output is low level, while the k12 and k11 output by the other first processing circuits 432 are both low level, and the k12b and k11b output are both high level; at this time Figure 5The first switch V1 and the second switch V2 in the first regulating unit 41 on the right are closed, controlling the connected first transistor P1 and the second transistor N2 to be turned on, transmitting the first constant voltage signal VDD to the first node x1, and transmitting the second constant voltage signal VSS to the second node x2.

[0111] Furthermore, since the first processor 431 Figure 6 The input terminal of the first inverter F1 of the bottom first processing circuit 432 outputs a high level, and the input terminals of the first inverter F1 of other first processing circuits 432 output a low level. Figure 6 The first processing circuit 432 at the top and in the middle, the output terminal of the first logic gate F0 outputs a high level, and then k21b and k22b are both low levels, and k21 and k22 are both high levels, so Figure 5 The two second regulating units 42 on the left side are turned on, so that the first transistor P1 and the second transistor N2 in the two second regulating units 42 are turned on, the first constant voltage signal VDD is transmitted to the first node x1, and the second constant voltage signal VSS is transmitted to the second node x2; and for Figure 6 The output terminal of the first logic gate F0 of the bottom processing circuit 432 outputs a high level, and then k23b is all high level, and k23 is all low level, so Figure 5 The second regulating unit 42 on the far right is not turned on; under the action of the turned-on first regulating unit 41 and the turned-on second regulating unit 42, the rising speed of the intermediate differential signal output by the differential module 20 is reduced.

[0112] It should be understood that, in the timing controller described above, the number of the first adjustment unit 41, the second adjustment unit 42, the first processing circuit 432, the amplitude adjustment unit 53, and the second processing circuit 52 involved is not limited to Figure 5 , Figure 6 and Fig. 9 The number shown in the figure can be set according to actual conditions and is not specifically limited here.

[0113] Based on the same inventive concept, an embodiment of the present invention provides a pre-emphasis de-emphasis processing method, the implementation principle of the method is basically similar to the implementation principle of the aforementioned timing controller, and the specific implementation method of the method can refer to the specific embodiment of the aforementioned timing controller, and the repeated parts will not be repeated.

[0114] Specifically, an embodiment of the present invention provides a method for processing pre-emphasis and de-emphasis, such as Fig.10 As shown, it may include:

[0115] S1001, the reference module outputs a reference voltage to the output module, and outputs a reference current to the differential module and the pre-emphasis de-emphasis module respectively;

[0116] S1002, the pre-emphasis and de-emphasis modules collect the rise time of the target differential signal received by the receiving end of the source driver, and adjust the rise speed of the intermediate differential signal output by the differential module based on the relationship between the collected rise time and the preset time in cooperation with the reference current;

[0117] S1003, the differential module outputs an intermediate differential signal to the output module according to the input source differential signal, the reference current, and the adjusted rising speed;

[0118] S1004 . The output module outputs a target differential signal to the source driver according to the reference voltage and the intermediate differential signal.

[0119] Optionally, in cooperation with the reference current, based on the relationship between the collected rise time and the preset time, adjusting the rise speed of the intermediate differential signal output by the differential module specifically includes:

[0120] Collecting the rise time of the target differential signal received by the receiving end of the source driver, and determining the difference between the collected rise time and the preset time;

[0121] When the collected rise time is greater than the preset time, the pre-emphasis function is turned on, and with the cooperation of the reference current, the rise speed of the intermediate differential signal output by the differential module is increased according to the difference;

[0122] When the collected rise time is less than the preset time, the de-emphasis function is turned on, and with the cooperation of the reference current, the rise speed of the intermediate differential signal output by the differential module is reduced according to the difference.

[0123] Optionally, it also includes:

[0124] The timing controller also includes an amplitude adjustment module. When the amplitude adjustment module is connected to the reference module, when the reference module outputs a reference current, the amplitude adjustment module responds to an adjustment instruction of the amplitude of the target differential signal, and adjusts the reference current output by the reference module according to the amplitude of the target differential signal received by the receiving end of the source driver and a preset amplitude.

[0125] Based on the same inventive concept, an embodiment of the present invention provides a display device, which may include: a source driver, and a timing controller as described above, wherein the timing controller is connected to the source driver.

[0126] In specific implementation, the display device can be any product or component with display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The implementation of the display device can refer to the above-mentioned embodiment of the timing controller, and the repeated parts will not be repeated.

[0127] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A timing controller, characterized in that: include: Reference module, differential module, output module and pre-emphasis and de-emphasis module; The output module is connected to the receiving end of the source driver; The reference module is connected to the differential module, the output module, and the pre-emphasis de-emphasis module respectively, and the reference module is used to: output a reference voltage to the output module, and output a reference current to the differential module and the pre-emphasis de-emphasis module respectively; The pre-emphasis de-emphasis module is also connected to the differential module and the receiving end of the source driver respectively, and the pre-emphasis de-emphasis module is used to: collect the rise time of the target differential signal received by the receiving end of the source driver, and adjust the rise speed of the intermediate differential signal output by the differential module based on the size relationship between the collected rise time and the preset time in cooperation with the reference current; The differential module is also connected to the output module, and the differential module is used to: output an intermediate differential signal to the output module according to the input source differential signal, the reference current, and the adjusted rising speed; The output module is used to output a target differential signal to the source driver according to the reference voltage and the intermediate differential signal.

2. The timing controller according to claim 1, characterized in that: The pre-emphasis de-emphasis module is specifically used for: Collecting the rise time of the target differential signal received by the receiving end of the source driver, and determining the difference between the collected rise time and the preset time; When the collected rise time is greater than the preset time, the pre-emphasis function is turned on, and in cooperation with the reference current, the rise speed of the intermediate differential signal output by the differential module is increased according to the difference; When the collected rise time is less than the preset time, the de-emphasis function is turned on, and in cooperation with the reference current, the rise speed of the intermediate differential signal output by the differential module is reduced according to the difference.

3. The timing controller according to claim 2, characterized in that: The pre-emphasis de-emphasis module includes: a control unit, a plurality of first adjustment units and a plurality of second adjustment units; the control unit is respectively connected to the receiving end of the source driver, the control end of each of the first adjustment units, and the control end of each of the second adjustment units; the first adjustment unit is also respectively connected to the first constant voltage signal end, the second constant voltage signal end, the reference module, and the differential module; the second adjustment unit is also respectively connected to the first constant voltage signal end, the second constant voltage signal end, the reference module, and the differential module; the control unit is used to: Collecting the rise time of the target differential signal received by the receiving end of the source driver to determine the difference; When the collected rise time is greater than the preset time, the pre-emphasis function is turned on, and the first adjustment gear corresponding to the difference is determined, and according to the first adjustment gear, in cooperation with the reference current, a corresponding number of the first adjustment units are controlled to be turned on, and all the second adjustment units are controlled to be turned on, so that the turned-on first adjustment units and the turned-on second adjustment units output the first constant voltage signal provided by the first constant voltage signal end and the second constant voltage signal provided by the second constant voltage signal end to the differential module, thereby increasing the rise speed of the intermediate differential signal output by the differential module.

4. The timing controller according to claim 2, characterized in that: The pre-emphasis de-emphasis module includes: a control unit, a plurality of first adjustment units and a plurality of second adjustment units; the control unit is respectively connected to the receiving end of the source driver, the control end of each of the first adjustment units, and the control end of each of the second adjustment units; the first adjustment unit is also respectively connected to the first constant voltage signal end, the second constant voltage signal end, the reference module, and the differential module; the second adjustment unit is also respectively connected to the first constant voltage signal end, the second constant voltage signal end, the reference module, and the differential module; the control unit is used to: Collecting the rise time of the target differential signal received by the receiving end of the source driver to determine the difference; When the collected rise time is less than the preset time, the de-emphasis function is turned on, and the second adjustment gear corresponding to the difference is determined. According to the second adjustment gear, in cooperation with the reference current, a corresponding number of the first adjustment units are controlled to be turned on, and a corresponding number of the second adjustment units are controlled to be turned on, so that the turned-on first adjustment units and the turned-on second adjustment units output the first constant voltage signal and the second constant voltage signal to the differential module, thereby reducing the rising speed of the intermediate differential signal output by the differential module.

5. The timing controller according to claim 3 or 4, characterized in that: At least one of the first regulating unit and the second regulating unit includes a first circuit and a second circuit, the first circuit is respectively connected to the reference module, the control unit, the first node in the differential module, and the first constant voltage signal end; the second circuit is respectively connected to the reference module, the control unit, the second node in the differential module, and the second constant voltage signal end; The first circuit is used to: transmit the first constant voltage signal to the first node when turned on by the control unit and the reference current; The second circuit is used to: transmit the second constant voltage signal to the second node when turned on by the control unit and the reference current; The first node and the second node are two different nodes in the differential module.

6. The timing controller according to claim 5, characterized in that: The first circuit includes: a first switch and a first transistor; the first switch is respectively connected to the control electrode of the first transistor, the reference module, and the control unit; the first electrode of the first transistor is connected to the first constant voltage signal terminal, and the second electrode of the first transistor is connected to the first node; The second circuit includes: a second switch and a second transistor; the second switch is respectively connected to the control electrode of the first transistor, the reference module, and the control unit; the first electrode of the second transistor is connected to the second constant voltage signal terminal, and the second electrode of the second transistor is connected to the second node; The first transistor and the second transistor are of different types.

7. The timing controller according to claim 6, characterized in that: The width-to-length ratios of the first channels in the first transistors belonging to different first regulating units are different, and the width-to-length ratios of the second channels in the second transistors belonging to different first regulating units are different; And / or, the width-to-length ratios of the first channels in the first transistors belonging to different second regulating units are different, and the width-to-length ratios of the second channels in the second transistors belonging to different second regulating units are different.

8. The timing controller according to claim 7, characterized in that: For the first channels in the first transistors belonging to different first regulating units: the width-to-length ratios of the first channels are proportionally changed according to the arrangement directions of the first transistors; for the second channels in the second transistors belonging to different first regulating units: the width-to-length ratios of the second channels are proportionally changed according to the arrangement directions of the second transistors; And / or, for the first channels in each of the first transistors belonging to different second adjustment units: the width-to-length ratio of each of the first channels changes proportionally according to the arrangement direction of each of the first transistors; for the second channels in each of the second transistors belonging to different second adjustment units: the width-to-length ratio of each of the second channels changes proportionally according to the arrangement direction of each of the second transistors.

9. The timing controller according to claim 3, characterized in that: The control unit includes: a first processor and a plurality of first processing circuits; The acquisition end of the first processor is connected to the receiving end of the source driver, the function selection output end of the first processor is respectively connected to each of the first processing circuits, the first processor has a plurality of first control signal output ends, and each of the first control signal output ends is correspondingly connected to each of the first processing circuits; each of the first processing circuits is also respectively connected to one of the first regulating units and one of the second regulating units, and different first regulating units are connected to different first processing circuits, and different second regulating units are connected to different first processing circuits; The first processor is used to: collect the rise time of the target differential signal received by the receiving end of the source driver to determine the difference; When the collected rise time is greater than the preset time, a first start signal for starting the pre-emphasis function is output to each first processing circuit; and the first adjustment gear is determined, and according to the first adjustment gear, a first control signal is output to the first processing circuit corresponding to the first adjustment unit to be turned on, so that the first processing circuit controls the corresponding first adjustment unit and the second adjustment unit to be turned on based on the first control signal.

10. The timing controller according to claim 4, characterized in that: The control unit includes: a first processor and a plurality of first processing circuits; The acquisition end of the first processor is connected to the receiving end of the source driver, the function selection output end of the first processor is respectively connected to each of the first processing circuits, the first processor has a plurality of first control signal output ends, and each of the first control signal output ends is correspondingly connected to each of the first processing circuits; each of the first processing circuits is also respectively connected to one of the first regulating units and one of the second regulating units, and different first regulating units are connected to different first processing circuits, and different second regulating units are connected to different first processing circuits; The first processor is used to: collect the rise time of the target differential signal received by the receiving end of the source driver to determine the difference; When the collected rise time is less than the preset time, a second start signal for starting the de-emphasis function is output to the first processing circuit; and the second adjustment gear is determined, and according to the second adjustment gear, a second control signal is output to the first processing circuit corresponding to the first adjustment unit to be turned on, so that the first processing circuit controls the corresponding first adjustment unit or the second adjustment unit to be turned on based on the second control signal.

11. The timing controller according to claim 9 or 10, characterized in that: The first processing circuit includes: a first logic gate, a first inverter, a second inverter, a third inverter, and a fourth inverter; The first input end of the first logic gate is connected to the function selection output end of the first processor, the second input end of the first logic gate is respectively connected to the output end of the first inverter and the input end of the second inverter, and the output end of the first logic gate is connected to the input end of the fourth inverter; The input terminal of the first inverter is connected to the first control signal output terminal of the first processor; The output terminal of the second inverter is connected to the input terminal of the third inverter; The output end of the third inverter is connected to the corresponding first regulating unit; An output terminal of the fourth inverter is connected to the corresponding second regulating unit.

12. The timing controller according to claim 1, characterized in that: The timing controller further comprises an amplitude adjustment module, and the amplitude adjustment module is connected to the reference module; The amplitude adjustment module is used to: in response to an adjustment instruction of the amplitude of the target differential signal, adjust the reference current output by the reference module according to the amplitude of the target differential signal received by the receiving end of the source driver and a preset amplitude.

13. The timing controller according to claim 12, characterized in that: The amplitude adjustment module includes: a second processor, a plurality of second processing circuits and a plurality of amplitude adjustment units, the acquisition end of the second processor is connected to the receiving end of the source driver, the enable output end of the second processor is respectively connected to each of the second processing circuits, the second processor has a plurality of second control signal output ends, each of the second control signal output ends is correspondingly connected to each of the second processing circuits; each of the second processing circuits is correspondingly connected to each of the amplitude adjustment units; the amplitude adjustment units are also respectively connected to the second constant voltage signal end and the output end of the reference module; The second processor is used to: respond to the adjustment instruction, and according to the amplitude of the target differential signal received by the receiving end of the source driver and the preset amplitude, control the corresponding number of the amplitude adjustment units to turn on through the second processing circuit, so that the turned-on amplitude adjustment units transmit the second constant voltage signal provided by the second constant voltage signal end to the output end of the reference module, and adjust the reference current output by the reference module.

14. A method for processing pre-emphasis and de-emphasis, characterized in that: The method is implemented by using the timing controller according to any one of claims 1 to 13, and the method comprises: The reference module outputs a reference voltage to the output module, and outputs a reference current to the differential module and the pre-emphasis de-emphasis module respectively; The pre-emphasis and de-emphasis module collects the rise time of the target differential signal received by the receiving end of the source driver, and adjusts the rise speed of the intermediate differential signal output by the differential module based on the relationship between the collected rise time and the preset time in cooperation with the reference current; The differential module outputs an intermediate differential signal to the output module according to the input source differential signal, the reference current, and the adjusted rising speed; The output module outputs a target differential signal to the source driver according to the reference voltage and the intermediate differential signal.

15. A display device, characterized in that: include: A source driver, and a timing controller as claimed in any one of claims 1 to 13, wherein the timing controller is connected to the source driver.

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