A data transmission method and a transmission circuit for pulling a power line down to a ground line

Abstract

The present invention discloses a data transmission method and a transmission circuit for pulling a power line down to a ground line, including demodulating a waveform signal on a power supply VCC to obtain a demodulated signal; decoding the demodulated signal according to a clock signal to obtain a decoded signal, and obtaining a control instruction according to the decoded signal and an LED chip address, wherein the control instruction is used to control an LED. The present invention uses a power line to perform data transmission by pulling the power line down to the ground, and performs signal recognition on the length of a trigger level during the process of pulling the power line down to the ground or pulling it up from the ground, thereby realizing data output, and sending the data signal demodulated from the power line to a decoding module for protocol decoding, thereby realizing control of an LED driving unit; the system only needs two lines, a power line and a ground line, and does not need an additional signal line to realize control of an LED system, which is conducive to reducing costs, facilitating production and installation, enhancing product applicability, and is also conducive to chip integration of an LED driving circuit.

Description

Technical Field

[0001] The invention relates to LED driving, in particular to a data transmission method and a transmission circuit that pulls a power line down to a ground line. Background Art

[0002] With the rapid development of LED (Light Emitting Diode) lighting and display technology, LED drive control design and optimization have become the key links to improve product competitiveness and reduce costs. Traditional LED drive control systems usually rely on independent signal lines to transmit control data to achieve LED control, such as brightness adjustment, color change and dynamic display.

[0003] However, the use of additional signal lines significantly increases material costs and complicates system wiring, installation, and subsequent maintenance. At the same time, this control method is not suitable for scenarios with only two-wire products with power and ground wires. Summary of the invention

[0004] In order to solve the defects of the above-mentioned prior art, the present invention provides a data transmission method and a transmission circuit for pulling a power line down to a ground line, so as to solve the problems of increased cost, complicated wiring, installation and maintenance, and unsuitability for two-wire products caused by the current use of additional signals.

[0005] To achieve the above technical purpose, the present invention adopts the following technical solution: a data transmission method that pulls a power line down to a ground line, comprising:

[0006] Demodulate the waveform signal on the power supply VCC to obtain a demodulated signal;

[0007] The demodulated signal is decoded according to the clock signal to obtain a decoded signal, and a control instruction is obtained according to the decoded signal and the LED chip address, and the control instruction is used to control the LED.

[0008] Demodulating the waveform signal on the power supply VCC specifically includes the following sub-steps:

[0009] A first level signal and a second level signal are acquired according to the level state of the power supply VCC, and the first level signal is inverted to obtain a first reverse level signal, and the demodulated signal is obtained according to the first reverse level signal and the second level signal.

[0010] Define the power supply level as VPWR, the system ground level as VGND, and obtain the first start-up voltage VT41, the second start-up voltage VT42, the first trigger threshold V1, and the second trigger threshold V2;

[0011] The power supply VCC is divided into the conversion of the voltage of the power supply VCC from VGND to VPWR, and the conversion of the voltage of the power supply VCC from VPWR to VGND;

[0012] When the voltage of the power supply VCC is converted from VGND to VPWR, obtaining the first level signal specifically includes the following sub-steps: As the VCC voltage increases, when VT41 < VCC < V1, the first level signal is high level, and after inverting the first level signal, the first inverted level signal is low level. When V1 < VCC, the first level signal is low level, and the first inverted level is high level; Obtaining the second level signal specifically includes the following sub-steps: As the VCC voltage increases, when VT42 < VCC < V2, the second level signal is high level, and when V2 < VCC, the second level signal is low level;

[0013] When the voltage of the power supply VCC is converted from VPWR to VGND, obtaining the first level signal specifically includes the following sub-steps: As the VCC voltage decreases, when V1 < VCC < VPWR, the first level signal is low level, and the first inverted level is high level. When VT41 < VCC < V1, the first level signal is high level, and the first inverted level is low level; Obtaining the second level signal specifically includes the following sub-steps: As the VCC voltage decreases, when V2 < VCC < VPWR, the second level signal is low level, and when VT42 < VCC < V2, the second level signal is high level;

[0014] Wherein, when the first level signal is high level, the first inverted level signal is low level, and at this time the demodulation signal is low level; when the first level signal is low level, the first inverted level signal is high level, and at this time the high and low state of the demodulation signal depends on the second level signal;

[0015] When the second level signal is high level, at this time the high and low state of the demodulation signal depends on the first inverted level signal; when the second level signal is low level and the first inverted level signal is high level, at this time the demodulation signal is high level.

[0016] The first trigger threshold V1 is less than the second trigger threshold V2, that is, V1 < V2:

[0017] When the voltage of the power supply VCC is converted from VGND to VPWR, as the VCC voltage increases:

[0018] When VCC < V1, the first level signal is high level, the first inverted level signal is low level, and at this time the demodulation signal is low level;

[0019] When V1 < VCC < V2, the first level signal is at a low level, the first inverted level signal is at a high level, the second level signal is at a high level, and at this time the demodulation signal is at a low level;

[0020] When VCC > V2, the first level signal is at a low level, the first inverted level signal is at a high level, the second level signal is at a low level, and at this time the demodulation signal is at a high level;

[0021] When the voltage of the power supply VCC is converted from VPWR to VGND, as the VCC voltage decreases:

[0022] When V1 < VCC < V2, the first level signal is at a low level, the first inverted level signal is at a high level, the second level signal is at a high level, and at this time the demodulation signal is at a high level;

[0023] When VCC < V1, the first level signal is at a high level, the first inverted level signal is at a low level, and at this time the demodulation signal is at a low level.

[0024] Decoding the demodulation signal according to the clock signal specifically includes the following sub-steps:

[0025] Record the low level that appears in the demodulation signal as the P code;

[0026] Obtain the duration of the high level in the demodulation signal and record it as t. When t > Trst, record the high level corresponding to this time t as the reset code; record the first segment of high level with a duration less than the reset code time that appears after the reset code as the reference code, and record the time of this high level as Tref. When , record the high level corresponding to this time t as the 0 code; when

[0027] , record the high level corresponding to this time t as the 1 code; where n and m are natural numbers greater than 1, and m > n;

[0028] Obtain the sequence composed of 0 and 1 of each frame of data in the demodulation signal according to the reset code, reference code, 0 code, and 1 code, and use this sequence as the decoded signal;

[0029] Take the N data bits after the reference code in the sequence as the command code, and take the remaining data bits after the command code as the data code, where the data bits are 0 code or 1 code; obtain the control instruction according to the command code, data code, and LED chip address.

[0030] It further includes:

[0031] Determine the level state of the power supply VCC. When the power supply VCC is at a high level, control the power supply VCC as a working power supply and charge the digital power supply holding circuit. When the power supply VCC is at a low level, control the digital power supply holding circuit as a working power supply, and require that the time for the power supply VCC to be pulled down to the ground level is less than the time required for the voltage of the digital power supply holding circuit to drop to the threshold level.

[0032] A data transmission circuit in which a power line is pulled down to a ground line, comprising:

[0033] A power signal demodulation circuit, used for demodulating the waveform signal on the power supply VCC and outputting a demodulated signal, wherein the demodulated signal is sent to a data protocol decoding circuit;

[0034] A bandgap reference circuit, used for generating a reference voltage, wherein the reference voltage is sent to a voltage stabilizing circuit;

[0035] A digital power supply holding circuit is used to generate power required for the operation of the digital circuit. When the power line VCC is at a high level, the digital power supply holding circuit is charged. When the power line VCC is at a low level, the digital power supply holding circuit supplies power to the digital circuit.

[0036] The chip ID storage circuit is used to store the LED chip address of the LED driving circuit and send the address to the data protocol decoding circuit for use;

[0037] Voltage stabilization circuit, used to convert the power supply voltage into a stable voltage for internal use, and supply it to other circuits except the digital power supply;

[0038] The oscillator unit is used to generate a clock signal to provide a clock beat for the entire digital circuit operation;

[0039] The data protocol decoding circuit is used to decode the demodulated signal to obtain the control instruction of the LED control system according to the clock signal and the LED chip address;

[0040] A logic control circuit, used for generating corresponding display data according to the decoding instruction;

[0041] The display data control circuit is used to convert the display data into grayscale duty data for controlling the brightness of the LED lamp. The grayscale duty data is sent to the LED driving circuit for driving the LED.

[0042] The power signal demodulation circuit comprises:

[0043] A first level trigger module, used for outputting a first level signal;

[0044] A second level trigger module, used for outputting a second level signal;

[0045] The inverter INV2 is used to invert the first level signal to obtain a first reverse level signal;

[0046] A trigger, used for obtaining a demodulated signal according to the first reverse level signal and the second level signal;

[0047] Among them, the output of the first level trigger module is connected to the input terminal of the inverter INV2, and the output of the inverter INV2 is connected to the R terminal of the RS trigger, which is used to clear the output terminal Q of the RS trigger so that it outputs a low level, and the output of the second level trigger module is connected to the S terminal of the RS trigger, which is used to set the output terminal Q of the RS trigger so that it outputs a high level.

[0048] The first level trigger module includes: a pull-up resistor R1, a transistor T1, a transistor T2, a transistor T3, a transistor T4 and an inverter INV1;

[0049] One end of the pull-up resistor R1 is connected to the power line, and the other end is connected to the drain end of the transistor T1. The gate end of the transistor T1 is connected to the power line, and the source end is connected to the gate and drain of the transistor T2, so that the transistor T2 forms an equivalent diode through the diode connection method of the transistor. The source end of the transistor T2 is grounded, and the gate ends of the transistors T3 and T4 are connected, and then connected to the drain end of the transistor T1 and one end of the pull-up resistor R1. The drains of the transistors T3 and T4 are connected, and the sources are connected to the power supply and the ground respectively, forming an inverter structure, and the output of the inverter is connected to the input end of the inverter INV1, and the output end of the inverter INV1 is used as the output of the first level trigger module;

[0050] The internal components and topological connection relationship of the second level trigger module are the same as those of the first level trigger module.

[0051] The RS trigger includes: the RS trigger includes an input NAND gate NAND1, an input NAND gate NAND2, and an inverter INV3;

[0052] An input terminal S of the input NAND gate NAND1 is connected to the output terminal of the second level trigger module, and the other terminal thereof is connected to the output terminal of the input NAND gate NAND2; an input terminal R of the input NAND gate NAND2 is connected to the output terminal of the inverter INV2, and the other terminal thereof is connected to the output terminal of the input NAND gate NAND1; an input terminal of the inverter INV3 is connected to the output terminal of the input NAND gate NAND2, and its output is used as the output of the power signal demodulation circuit.

[0053] In summary, the present invention has achieved the following technical effects:

[0054] The present invention utilizes a power line to transmit data by pulling the power line down to the ground, and performs signal recognition on the length of the trigger level in the process of pulling the power line down to the ground or pulling it up from the ground, thereby realizing data output, and sending the data signal demodulated by the power line to a decoding module for protocol decoding, thereby realizing control of the LED driving unit; the system only needs two lines, a power line and a ground line, and does not need an additional signal line to realize control of the LED system, which is conducive to reducing costs, facilitating production and installation, enhancing product applicability, and is also conducive to chip integration of the LED driving circuit;

[0055] The present invention reduces costs: by reducing or eliminating the reliance on separate signal lines, material costs can be significantly reduced because additional cables and connectors are no longer required.

[0056] The present invention simplifies system wiring: avoids complicated system wiring work, and makes the production process of the LED drive control system simpler and faster.

[0057] The present invention is convenient for installation and maintenance: system components are reduced, the complexity of installation is reduced, and later maintenance and troubleshooting are also convenient.

[0058] The present invention has wide adaptability: it is suitable for two-wire product scenarios with only a power line and a ground line, thereby enhancing the applicability and flexibility of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] FIG1 is a schematic diagram of a circuit functional module of the present invention;

[0060] Figure 2 is a schematic diagram of a power signal demodulation circuit;

[0061] Figure 3 is a schematic diagram of a digital power supply holding circuit;

[0062] Figure 4 is a diagram showing the definition of the code pattern during data transmission;

[0063] Figure 5 shows the code structure and timing diagram of a frame of data. DETAILED DESCRIPTION

[0064] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0065] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

[0066] In order to make the purpose, technical scheme and advantages of the present invention clearer, the device proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings adopt a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structure, proportion, size, etc. illustrated by the accompanying drawings of this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effect that the present invention can produce and the purpose that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.

[0067] Example:

[0068] A data transmission method for pulling a power line down to a ground line, and a data transmission circuit for pulling the power line down to a ground line, pull the power line down to the ground for data transmission, thereby realizing data transmission of a two-wire product and saving the cost of redundant wires and redundant signals.

[0069] In order to better describe a data transmission method in which a power line is pulled down to a ground line, a data transmission circuit in which a power line is pulled down to a ground line is first described in detail:

[0070] A data transmission circuit in which the power line is pulled low to the ground line, such as Figure 1 As shown, including:

[0071] (1) A power signal demodulation circuit, used to demodulate the waveform signal on the power supply VCC and output a demodulated signal, and the demodulated signal is sent to a data protocol decoding circuit;

[0072] (2) a bandgap reference circuit for generating a reference voltage, wherein the reference voltage is sent to a voltage stabilization circuit;

[0073] (3) a digital power supply holding circuit, which is used to generate power required for the operation of the digital circuit. When the power line VCC is at a high level, the digital power supply holding circuit is charged. When the power line VCC is at a low level, the digital power supply holding circuit supplies power to the digital circuit.

[0074] (4) Chip ID storage circuit, used to store the LED chip address of the LED driving circuit and send the address to the data protocol decoding circuit for use;

[0075] (5) Voltage stabilization circuit, used to convert the power supply voltage into a stable voltage for internal use and supply it to other circuits except the digital power supply;

[0076] (6) Oscillator unit, used to generate clock signals and provide clock beats for the entire digital circuit operation;

[0077] (7) A data protocol decoding circuit is used to decode the demodulated signal to obtain the control instruction of the LED control system according to the clock signal and the LED chip address; the data protocol decoding circuit decodes the input demodulated signal according to the clock signal provided by the oscillator, and decides whether to execute the instruction in the data frame according to the decoded information and the ID provided by the chip ID storage circuit;

[0078] (8) a logic control circuit, used to generate corresponding display data according to the decoding instruction;

[0079] (9) A display data control circuit, used to convert the display data into grayscale duty data for controlling the brightness of the LED lamp. The grayscale duty data is sent to the LED driving circuit for driving the LED.

[0080] Furthermore, the power signal demodulation circuit is to generate a demodulated signal, such as Figure 2 As shown, including:

[0081] A first level trigger module, used for outputting a first level signal;

[0082] A second level trigger module, used for outputting a second level signal;

[0083] The inverter INV2 is used to invert the first level signal to obtain a first reverse level signal;

[0084] A trigger, used for obtaining a demodulated signal according to the first reverse level signal and the second level signal;

[0085] Among them, the output of the first level trigger module is connected to the input terminal of the inverter INV2, and the output of the inverter INV2 is connected to the R terminal of the RS trigger, which is used to clear the output terminal Q of the RS trigger so that it outputs a low level, and the output of the second level trigger module is connected to the S terminal of the RS trigger, which is used to set the output terminal Q of the RS trigger so that it outputs a high level.

[0086] Furthermore, the first level trigger module includes: a pull-up resistor R1, a transistor T1, a transistor T2, a transistor T3, a transistor T4 and an inverter INV1; one end of the pull-up resistor R1 is connected to a power line, and the other end is connected to a drain end of the transistor T1, the gate end of the transistor T1 is connected to the power line, and the source end is connected to the gate and drain of the transistor T2, so that the transistor T2 forms an equivalent diode through the diode connection of the transistor, the source end of the transistor T2 is grounded, the gate ends of the transistors T3 and T4 are connected, and then connected to the drain end of the transistor T1 and one end of the pull-up resistor R1, the drains of the transistors T3 and T4 are connected, and the sources are respectively connected to the power supply and the ground, forming an inverter structure, and the output of the inverter is connected to the input end of the inverter INV1, and the output end of the inverter INV1 is used as the output of the first level trigger module;

[0087] The internal components and topological connection relationship of the second level trigger module are the same as those of the first level trigger module.

[0088] Therefore, the output states of the two level-triggered modules are determined by the level state of the power supply VCC. In other words, the states of the two level-triggered modules are triggered by the level state of the power supply VCC.

[0089] The RS trigger includes: the RS trigger includes an input NAND gate NAND1, an input NAND gate NAND2, and an inverter INV3;

[0090] An input terminal S of the input NAND gate NAND1 is connected to the output terminal of the second level trigger module, and the other terminal thereof is connected to the output terminal of the input NAND gate NAND2; an input terminal R of the input NAND gate NAND2 is connected to the output terminal of the inverter INV2, and the other terminal thereof is connected to the output terminal of the input NAND gate NAND1; an input terminal of the inverter INV3 is connected to the output terminal of the input NAND gate NAND2, and its output is used as the output of the power signal demodulation circuit.

[0091] A data transmission method in which a power line is pulled down to a ground line, comprising:

[0092] Demodulate the waveform signal on the power supply VCC to obtain a demodulated signal;

[0093] The demodulated signal is decoded according to the clock signal to obtain a decoded signal, and a control instruction is obtained according to the decoded signal and the LED chip address, and the control instruction is used to control the LED.

[0094] The demodulation of the waveform signal on the power supply VCC specifically includes the following sub-steps:

[0095] Obtain a first level signal and a second level signal according to the level state of the power supply VCC, invert the first level signal to obtain a first inverted level signal, and obtain the demodulation signal according to the first inverted level signal and the second level signal.

[0096] Define the power supply level as VPWR and the system ground level as VGND, and obtain a first turn-on voltage VT41, a second turn-on voltage VT42, a first trigger threshold V1, and a second trigger threshold V2; wherein, the first turn-on voltage VT41 and the second turn-on voltage VT42 are respectively the turn-on voltages of the transistor T4 of two level trigger modules, and the first trigger threshold V1 and the second trigger threshold V2 are respectively the trigger thresholds of two level trigger modules.

[0097] Since the power supply VCC needs to be rapidly converted between VPWR and VGND during data transmission, therefore, the power supply VCC is divided into the conversion of the voltage of the power supply VCC from VGND to VPWR, and the conversion of the voltage of the power supply VCC from VPWR to VGND;

[0098] When the voltage of the power supply VCC is converted from VGND to VPWR, the specific steps for obtaining the first level signal include the following sub-steps: as the VCC voltage increases, when VT41 < VCC < V1, the first level signal is high level, and after inverting the first level signal, the first inverted level signal is low level, when V1 < VCC, the first level signal is low level, and the first inverted level is high level; the specific steps for obtaining the second level signal include the following sub-steps: as the VCC voltage increases, when VT42 < VCC < V2, the second level signal is high level, when V2 < VCC, the second level signal is low level;

[0099] When the voltage of the power supply VCC is converted from VPWR to VGND, the specific steps for obtaining the first level signal include the following sub-steps: as the VCC voltage decreases, when V1 < VCC < VPWR, the first level signal is low level, and the first inverted level is high level, when VT41 < VCC < V1, the first level signal is high level, and the first inverted level is low level; the specific steps for obtaining the second level signal include the following sub-steps: as the VCC voltage decreases, when V2 < VCC < VPWR, the second level signal is low level, when VT42 < VCC < V2, the second level signal is high level;

[0100] Wherein, when the first level signal is high level, the first inverted level signal is low level, and at this time the demodulation signal is low level; when the first level signal is low level, the first inverted level signal is high level, and at this time the high and low state of the demodulation signal depends on the second level signal;

[0101] When the second - level signal is at a high level, the high - low state of the demodulation signal at this time depends on the first reverse - level signal; when the second - level signal is at a low level and the first reverse - level signal is at a high level, the demodulation signal is at a high level at this time.

[0102] The first trigger threshold V1 is less than the second trigger threshold V2, that is, V1 < V2:

[0103] When the voltage of the power supply VCC is converted from VGND to VPWR, as the VCC voltage increases:

[0104] When VCC < V1, the first - level signal is at a high level, the first reverse - level signal is at a low level, and the demodulation signal is at a low level at this time;

[0105] When V1 < VCC < V2, the first - level signal is at a low level, the first reverse - level signal is at a high level, the second - level signal is at a high level, and the demodulation signal is at a low level at this time;

[0106] When VCC > V2, the first - level signal is at a low level, the first reverse - level signal is at a high level, the second - level signal is at a low level, and the demodulation signal is at a high level at this time;

[0107] When the voltage of the power supply VCC is converted from VPWR to VGND, as the VCC voltage decreases:

[0108] When V1 < VCC < V2, the first - level signal is at a low level, the first reverse - level signal is at a high level, the second - level signal is at a high level, and the demodulation signal is at a high level at this time;

[0109] When VCC < V1, the first - level signal is at a high level, the first reverse - level signal is at a low level, and the demodulation signal is at a low level at this time.

[0110] The detailed process is as follows:

[0111] Taking the first - level trigger module as an example, for the convenience of describing the working principle of the level - trigger module, the trigger threshold of the level - trigger module is VT, and the VT can be regarded as the sum of the turn - on voltages VT1 and VT2 of the transistors T1 and T2 in the level - trigger module, that is, VT = VT1 + VT2.

[0112] When the voltage of the power supply VCC converts from VGND to VPWR, as the VCC voltage rises and exceeds the turn-on voltage VT4 of the transistor T4 but is less than the trigger level VT, that is, VT4 < VCC < VT. Due to the pull-up effect of R1, the transistor T3 is turned off and T4 is turned on. Therefore, the input end of INV1 is at a low level. After one-level inversion, the output of the level trigger module is at a high level.

[0113] Further, when the VCC voltage continues to rise and exceeds VT until it reaches VPWR, that is, VCC > VT, the transistors T1 and T2 are turned on, resulting in a relatively low level at the gate inputs of T3 and T4, which causes T3 to be turned on. Furthermore, the input of the inverter is at a high level. After one-level inversion, the output of the level trigger module is at a low level.

[0114] It should be emphasized that when designing the chip, the size of the T3 transistor should be larger than that of the T4 transistor, so that when VCC > VT, the T3 transistor has a relatively larger driving ability than the T4 transistor, thereby making the input end of INV1 at a high level.

[0115] When the voltage of the power supply VCC converts from VPWR to VGND, as the VCC voltage drops but is higher than the trigger level VT, that is, VT < VCC < VPWR. Since the transistors T1 and T2 are turned on, the node N1 outputs a relatively low level. And because the transistor T3 has a relatively larger driving ability than T4, the node N3 outputs a relatively high level. After one-level inversion, the output of the level trigger module remains at a low level.

[0116] Further, when the VCC voltage continues to drop, is lower than VT but higher than VT4, that is, VT4 < VCC < VT, the transistors T1 and T2 are turned off. Due to the pull-up effect of R1, T3 is turned off and T4 is activated, making N3 output a relatively high level. After one-level inversion, the output of the level trigger module is at a low level.

[0117] It should be emphasized that to achieve the above effects, during the chip design process, the sizes of the above transistors and resistors need to be reasonably selected.

[0118] The working process of the above level trigger module can be summarized into a conclusion: during the conversion process of the power supply VCC between the power supply level VPWR and the ground level VGND, when it is lower than the trigger level VT, the level trigger module outputs high; when it is higher than the trigger level VT, the level trigger module outputs low.

[0119] It should be noted that the trigger level thresholds of the first level trigger module and the second level trigger module are different.

[0120] Preferably, the trigger level of the first level trigger module is less than that of the second level trigger module. Let the trigger level threshold of the first level trigger module be V1, and the trigger level threshold of the second level trigger module be V2, then V1 < V2.

[0121] Further, the first level trigger module is connected to the reset terminal of the RS flip-flop after being inverted by the inverter INV2. Its working process is as follows:

[0122] When the first level trigger module outputs a high level, after being inverted once, the clear terminal R of the flip-flop is at a low level. Therefore, the output terminal Q of the flip-flop outputs a low level. When the first level trigger module outputs a low level, after being inverted once, the clear terminal R of the flip-flop is at a high level. Therefore, the output state of the output terminal Q of the flip-flop depends on the S terminal. It can be understood that when the level trigger 1 outputs a low level, it has no effect on the output of the flip-flop.

[0123] When the second level trigger module outputs a high level, the set terminal S of the flip-flop is at a high level. Therefore, the output state of the output terminal Q of the flip-flop depends on the R terminal. It can be understood that when the level trigger 2 outputs a high level, it has no effect on the output of the flip-flop. When the second level trigger module outputs a low level, the set terminal S of the flip-flop is at a low level. And at this time, the R terminal of the flip-flop is also at a high level. At this time, the output terminal Q of the flip-flop outputs a high level. It can be understood that when the level trigger 2 outputs a low level and the R terminal of the flip-flop is at a high level, the flip-flop outputs a high level.

[0124] Combining the working principles of the level trigger module and the flip-flop, the working process of the power signal demodulation circuit during the conversion of the power supply VCC between the power supply level VPWR and the ground level VGND is described in detail below.

[0125] When VCC converts from VGND to VPWR, the process is as follows:

[0126] Specifically, when VCC < V1, the first level trigger module outputs a high level, which is at a low level after being inverted once. At this time, the R terminal of the flip-flop is at a low level, so that the Q terminal outputs a low level. Then the output of the power signal demodulation circuit is at a low level at this time.

[0127] Further, as the VCC level crosses V1 and is less than V2, that is, V1 < VCC < V2. At this time, the first level trigger module outputs a low level, and the output after being inverted once is at a high level. At this time, the R terminal of the flip-flop is at a high level, and the output state of the flip-flop depends on the S terminal. Since VCC < V2, the second level trigger module outputs a high level, so the S terminal is at a high level, and the Q terminal of the flip-flop continues to maintain a low level state, that is, the output of the power signal demodulation circuit continues to maintain a low level.

[0128] Further, when VCC > V2, the second level trigger module outputs a low level at this time, so the S terminal is at a low level. Obviously, the R terminal is at a high level at this time. Therefore, the output terminal Q of the flip-flop is set to a high level, and the output state of the power signal demodulation circuit becomes a high level at this time.

[0129] Conversely, when VCC is converted from VPWR to VGND, the process is as follows:

[0130] Specifically, when the VCC level is lower than V2 and higher than V1, that is, V1 < VCC < V2, the second level trigger module outputs a high level at this time, so the S terminal is at a high level. Obviously, the R terminal is at a high level at this time. Therefore, the output terminal Q of the flip-flop maintains the original high level state, that is, the output state of the power signal demodulation circuit maintains a high level at this time.

[0131] Further, when VCC < V1, the first level trigger module outputs a high level, which becomes a low level after one-stage inversion. At this time, the R terminal of the flip-flop is at a low level, so that the Q terminal outputs a low level, and the output of the power signal demodulation circuit is converted to a low level at this time.

[0132] In summary, the working process of the power signal demodulation circuit is summarized as the following conclusion:

[0133] During the conversion of the power supply VCC between the power supply level VPWR and the ground level VGND, when the power supply VCC is converted from VGND to VPWR and when VCC > V2, the power signal demodulation circuit outputs a high level; conversely, when the power supply VCC is converted from VPWR to VGND and when VCC < V1, the power signal demodulation circuit outputs a low level.

[0134] Decoding the demodulation signal according to the clock signal specifically includes the following sub-steps:

[0135] Record the low level that appears in the demodulation signal as the P code;

[0136] Obtain the duration of the high level in the demodulation signal and record it as t. When t > Trst, record the high level corresponding to this time t as the reset code; record the first segment of high level with a duration less than the reset code time that appears after the reset code as the reference code, and record the time of this high level as Tref; when , record the high level corresponding to this time t as the 0 code; when

[0137] , record the high level corresponding to this time t as the 1 code; where n and m are natural numbers greater than 1, and m > n;

[0138] Obtain the sequence composed of 0 and 1 of each frame of data in the demodulation signal according to the reset code, reference code, 0 code, and 1 code, and use this sequence as the decoded signal;

[0139] The N data bits after the reference code in the sequence are used as command codes, and the remaining data bits after the command code are used as data codes, wherein the data bits are 0 codes or 1 codes; the control instruction is obtained according to the command code and the data code.

[0140] The chip receives the decoded data and obtains the command code in the decoded data. At the same time, the chip intercepts the data code in the decoded data according to its own address. The command code and the data code together constitute the control instruction of the chip, and the chip performs the corresponding operation according to the control instruction.

[0141] The method further includes: converting the control instruction into display data, and converting the display data into grayscale duty data recognizable by the LED, wherein the grayscale duty data is used to drive the LED.

[0142] The detailed process is as follows: Figure 4 As shown:

[0143] When the demodulated signal is at a low level for a period of time, the low level during this period is defined as P code, and the low level time is defined as Tp. At the same time, the duration of the high level in the demodulated signal is defined as t.

[0144] Furthermore, it is stipulated that when t>Trst, the code type is defined as a reset code.

[0145] Furthermore, the high level between two P codes is defined as 1 code, 0 code, and reference code. In order to distinguish the above code types, the high level after the first P code that is less than the reset code time is defined as the reference code, and the time is defined as Tref.

[0146] Furthermore, in order to distinguish code 0 from code 1, we define the high level time of code 0 as T0 and the high level time of code 1 as T1, and satisfy T1=n*T0, Tref=m*T0, where n and m are natural numbers greater than 1, and m>n. Obviously, when is defined as 0 code, when

[0147] is defined as 1 code.

[0148] Furthermore, by defining the data pattern, the data protocol decoding circuit can identify "0" or "1" of the demodulated signal, and thus can identify the sequence of "0" and "1" in the entire demodulated signal.

[0149] Specifically, Figure 5 As shown, a frame of data can be defined as including a reset code RST, a reference code REF, a command code CMD, and data codes D0, D1...D MThe command code and data code may be composed of N data bits, where N is a natural number not equal to 0. The data bit is the 0 code or 1 code. Preferably, N=8, and a command code or data code contains 8 data bits. At this point, the data decoding protocol decoding circuit can complete the decoding of the demodulated signal according to the above data frame structure and the definition of the data code type, and then combine the decoded data with the chip ID to decide whether to execute the corresponding instruction.

[0150] Furthermore, if a corresponding instruction needs to be executed, the corresponding instruction and data are sent to the logic control circuit, and the logic control circuit generates corresponding display data through logic operations.

[0151] Furthermore, the corresponding display data is sent to a display data control circuit, which converts the display data into grayscale duty data that can be recognized by the LED.

[0152] Furthermore, the grayscale duty data is sent to the LED driving circuit to drive the corresponding power tube to achieve control of the color, brightness, mode, etc. of the LED.

[0153] In the above control process, the power supply VCC will be pulled down to ground, so the circuit powered by VCC will stop working. However, in order to ensure that the digital circuit continues to work when the power supply is powered off, a digital power supply holding circuit is required to maintain the required power supply.

[0154] Therefore, it also includes:

[0155] Determine the level state of the power supply VCC. When the power supply VCC is at a high level, control the power supply VCC as a working power supply and charge the digital power supply holding circuit. When the power supply VCC is at a low level, control the digital power supply holding circuit as a working power supply, and require that the time for the power supply VCC to be pulled down to the ground level is less than the time required for the voltage of the digital power supply holding circuit to drop to the threshold level.

[0156] Specifically, the digital power supply holding circuit is used to generate the power required for the operation of the digital circuit. When the power line VCC is high, the digital power supply holding circuit is charged. When the power line VCC is low, the digital power supply holding circuit supplies power to the digital circuit, and the power supply voltage decreases with time. To ensure that the digital circuit can work reliably, the low level time when the power supply VCC is pulled down to the ground line is ensured to be less than the time required for the voltage of the digital power supply holding circuit to drop to a certain threshold level.

[0157] Specifically, Figure 3As shown, the digital power supply holding circuit includes a diode and an energy storage capacitor. The anode of the diode is connected to the power supply VCC, the cathode of the diode is connected to one end of the energy storage capacitor, and the other end of the energy storage capacitor is grounded. The diode is a unidirectional conductive element. When the power supply VCC is raised, the energy storage capacitor will be charged through the diode. When the power supply VCC is pulled down to the ground line, the unidirectional conductivity of the diode can effectively prevent the energy storage capacitor from discharging the power supply VCC in reverse, thereby realizing that the digital power supply holding circuit powers the digital circuit during the period when the power supply VCC is pulled down to the ground.

[0158] It should be emphasized that the time for the power supply VCC to be pulled down to ground cannot exceed the time required for the energy storage capacitor to discharge to a certain level.

[0159] Optionally, for easy integration inside the chip, the diode can be replaced by the following method: short-circuit the emitter and base of the NPN transistor or PNP transistor and then connect it to the power supply VCC, connect the collector to the energy storage capacitor, and the other end of the energy storage capacitor is grounded.

[0160] Optionally, for the convenience of integration inside the chip, the diode can be replaced by another method: short-circuit the gate and source of the NMOS tube or PMOS tube and then connect it to the power supply VCC, connect the drain end to the energy storage capacitor, and the other end of the energy storage capacitor is grounded.

[0161] Optionally, in order to facilitate integration inside the chip, the energy storage capacitor can be replaced by another method: short-circuit the drain and source of the NMOS tube and then connect them to the ground, and connect the gate end to the cathode of the diode to form a MOS capacitor.

[0162] The present invention also provides an LED driving circuit, which converts the LED brightness duty cycle signal into a corresponding current to realize driving control of the LED.

[0163] Specifically, the LED driving circuit integrates multiple LED driving ports, each of which can be connected to LEDs of different colors. The circuit receives signals from the display data control circuit to achieve precise control of LED color changes and brightness.

[0164] Specifically, the display data control circuit first parses the brightness and enable commands of each port of the chip in the decoded instructions, and then converts these commands into the high and low levels and driving current signals required to drive the LED. In this system, the high level signal is set to activate the LED (that is, the LED is on), while the low level signal turns the LED off. By adjusting the state of each drive port, the on and off state of the LED on each port can be flexibly controlled.

[0165] Furthermore, the brightness adjustment of the LED is achieved by adjusting the proportion of high-level signals at the drive port within a cycle: when the proportion of high-level signals is high, the LED presents high brightness; otherwise, the brightness is low. In addition, the brightness of the LED can also be finely adjusted by directly controlling the current on the drive port. This adjustment process depends on the setting of the instruction current parameters inside the chip. The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are within the scope of the technical solution of the present invention.

Claims

1. A data transmission method in which a power line is pulled down to a ground line, characterized in that: including demodulating the waveform signal on the power supply VCC to obtain a demodulated signal; decoding the demodulated signal according to a clock signal to obtain a decoded signal, and obtaining a control instruction according to the decoded signal and the LED chip address, where the control instruction is used to control the LED; Specifically, demodulating the waveform signal on the power supply VCC includes the following sub-steps: obtaining a first level signal and a second level signal according to the level state of the power supply VCC, inverting the first level signal to obtain a first inverted level signal, and obtaining the demodulated signal according to the first inverted level signal and the second level signal; defining the power supply level as VPWR, the system ground level as VGND, and obtaining a first turn-on voltage VT41, a second turn-on voltage VT42, a first trigger threshold V1, and a second trigger threshold V2; dividing the power supply VCC into a conversion of the voltage of the power supply VCC from VGND to VPWR and a conversion of the voltage of the power supply VCC from VPWR to VGND; When the voltage of the power supply VCC is converted from VGND to VPWR, specifically obtaining the first level signal includes the following sub-steps: as the VCC voltage increases, when VT41 < VCC < V1, the first level signal is high level, and inverting the first level signal to obtain a first inverted level signal that is low level, when V1 < VCC, the first level signal is low level, and obtaining a first inverted level that is high level; specifically obtaining the second level signal includes the following sub-steps: as the VCC voltage increases, when VT42 < VCC < V2, the second level signal is high level, and when V2 < VCC, the second level signal is low level; When the voltage of the power supply VCC is converted from VPWR to VGND, specifically obtaining the first level signal includes the following sub-steps: as the VCC voltage decreases, when V1 < VCC < VPWR, the first level signal is low level, and obtaining a first inverted level that is high level, when VT41 < VCC < V1, the first level signal is high level, and obtaining a first inverted level that is low level; specifically obtaining the second level signal includes the following sub-steps: as the VCC voltage decreases, when V2 < VCC < VPWR, the second level signal is low level, and when VT42 < VCC < V2, the second level signal is high level; wherein, when the first level signal is high level, the first inverted level signal is low level, and at this time the demodulated signal is low level; when the first level signal is low level, the first inverted level signal is high level, and at this time the high-low state of the demodulated signal depends on the second level signal; when the second level signal is high level, at this time the high-low state of the demodulated signal depends on the first inverted level signal; when the second level signal is low level and the first inverted level signal is high level, at this time the demodulated signal is high level.

2. A data transmission method according to claim 1, wherein: The first trigger threshold V1 is less than the second trigger threshold V2, that is, V1 < V2: When the voltage of the power supply VCC is converted from VGND to VPWR, as the VCC voltage increases: When VCC < V1, the first level signal is at a high level and the first inverted level signal is at a low level. At this time, the demodulation signal is at a low level; When V1 < VCC < V2, the first level signal is at a low level, the first inverted level signal is at a high level, and the second level signal is at a high level. At this time, the demodulation signal is at a low level; When VCC > V2, the first level signal is at a low level, the first inverted level signal is at a high level, and the second level signal is at a low level. At this time, the demodulation signal is at a high level; When the voltage of the power supply VCC converts from VPWR to VGND, as the VCC voltage decreases: When V1 < VCC < V2, the first level signal is at a low level, the first inverted level signal is at a high level, and the second level signal is at a high level. At this time, the demodulation signal is at a high level; When VCC < V1, the first level signal is at a high level, the first inverted level signal is at a low level. At this time, the demodulation signal is at a low level.

3. The data transmission method according to claim 2, wherein: Decoding the demodulation signal according to the clock signal specifically includes the following sub-steps: Denote the low level that appears in the demodulation signal as the P code; Obtain the duration of the high level in the demodulation signal and denote it as t. When t > Trst, denote the high level corresponding to this time t as the reset code; The first high level that appears after the reset code and lasts less than the reset code time is recorded as a reference code, and the time of the high level is recorded as Tref; When , the high level corresponding to the time t is recorded as 0 code; when When t is 0, the high level corresponding to the time t is recorded as code 1; wherein n, m are natural numbers greater than 1, and m>n; Obtain the sequence composed of 0 and 1 of each frame of data in the demodulation signal according to the reset code, reference code, 0 code, and 1 code, and use this sequence as the decoded signal; Take the N data bits after the reference code in the sequence as the command code, and take the remaining data bits after the command code as the data code, where the data bit is either the 0 code or the 1 code; obtain the control instruction according to the command code and the data code.

4. The data transmission method according to claim 1, wherein: It further includes: Judge the level state of the power supply VCC. When the power supply VCC is at a high level, control the power supply VCC as the working power supply and charge the digital power holding circuit; when the power supply VCC is at a low level, control the digital power holding circuit as the working power supply, and require the time for the control power supply VCC to be pulled down to the ground level to be less than the time required for the voltage of the digital power holding circuit to drop to the threshold level.

5. A data transmission circuit in which a power line is pulled down to a ground line, characterized in that: Applied to a data transmission method for pulling a power line down to the ground as described in any one of claims 1 - 4, including: A power signal demodulation circuit for demodulating the waveform signal on the power supply VCC and outputting a demodulation signal, and the demodulation signal is sent to the data protocol decoding circuit; A bandgap reference circuit for generating a reference voltage, and the reference voltage is sent to the voltage regulation circuit; A digital power holding circuit for generating the power supply required for the operation of the digital circuit. When the power line VCC is at a high level, it will charge the digital power holding circuit. When the power line VCC is at a low level, the digital power holding circuit supplies power to the digital circuit; A chip ID storage circuit for storing the LED chip address of the LED driving circuit and sending this address to the data protocol decoding circuit for use; A voltage regulation circuit for converting the power supply voltage into a stable voltage available for internal use and supplying it to other circuits except the digital power supply; The oscillator unit is used to generate a clock signal to provide a clock beat for the entire digital circuit operation; The data protocol decoding circuit is used to decode the demodulated signal to obtain the control instruction of the LED control system according to the clock signal and the LED chip address; A logic control circuit, used for generating corresponding display data according to the decoding instruction; The display data control circuit is used to convert the display data into grayscale duty data for controlling the brightness of the LED lamp. The grayscale duty data is sent to the LED driving circuit for driving the LED.

6. The data transmission circuit according to claim 5, wherein the power line is pulled down to the ground line, characterized in that: The power signal demodulation circuit comprises: A first level trigger module, used for outputting a first level signal; A second level trigger module, used for outputting a second level signal; The inverter INV2 is used to invert the first level signal to obtain a first reverse level signal; A trigger, used for obtaining a demodulated signal according to the first reverse level signal and the second level signal; Among them, the output of the first level trigger module is connected to the input terminal of the inverter INV2, and the output of the inverter INV2 is connected to the R terminal of the RS trigger, which is used to clear the output terminal Q of the RS trigger so that it outputs a low level, and the output of the second level trigger module is connected to the S terminal of the RS trigger, which is used to set the output terminal Q of the RS trigger so that it outputs a high level.

7. A data transmission circuit according to claim 6, wherein the power line is pulled down to the ground line, characterized in that: The first level trigger module includes: a pull-up resistor R1, a transistor T1, a transistor T2, a transistor T3, a transistor T4 and an inverter INV1; One end of the pull-up resistor R1 is connected to the power line, and the other end is connected to the drain end of the transistor T1. The gate end of the transistor T1 is connected to the power line, and the source end is connected to the gate and drain of the transistor T2, so that the transistor T2 forms an equivalent diode through the diode connection method of the transistor. The source end of the transistor T2 is grounded, and the gate ends of the transistors T3 and T4 are connected, and then connected to the drain end of the transistor T1 and one end of the pull-up resistor R1. The drains of the transistors T3 and T4 are connected, and the sources are connected to the power supply and the ground respectively, forming an inverter structure, and the output of the inverter is connected to the input end of the inverter INV1, and the output end of the inverter INV1 is used as the output of the first level trigger module; The internal components and topological connection relationship of the second level trigger module are the same as those of the first level trigger module.

8. The data transmission circuit according to claim 6, wherein the power line is pulled down to the ground line, characterized in that: The RS trigger includes: the RS trigger includes an input NAND gate NAND1, an input NAND gate NAND2, and an inverter INV3; An input terminal S of the input NAND gate NAND1 is connected to the output terminal of the second level trigger module, and the other terminal thereof is connected to the output terminal of the input NAND gate NAND2; an input terminal R of the input NAND gate NAND2 is connected to the output terminal of the inverter INV2, and the other terminal thereof is connected to the output terminal of the input NAND gate NAND1; an input terminal of the inverter INV3 is connected to the output terminal of the input NAND gate NAND2, and its output is used as the output of the power signal demodulation circuit.

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