Data processing in memory systems

Abstract

A method for a memory system is disclosed. The memory system can include a memory controller and a memory device. The method can include receiving data including bits and to be written to the memory device, counting a first number of bits corresponding to a first state and a second number of bits corresponding to a second state, and performing a flipping operation in response to the second number of bits being greater than the first number of bits.

Description

TECHNICAL FIELD

[0001] The present application relates to data processing techniques in memory systems. BACKGROUND

[0002] Storage class memory (SCM) can be employed as a new tier of memory / storage between dynamic random-access memory (DRAM) and NAND flash storage in a computer memory hierarchy. SCM provides fast non-volatile memory for a processor that is slightly slower than DRAM but significantly faster than NAND flash storage. The capacity of SCM is on the scale of a NAND flash drive and can be addressed at byte granularity. Technologies such as phase change memory (PCM), resistive random-access memory (ReRAN), magnetic random-access memory (MRAM), carbon nanotube random-access memory, etc. can be employed in SCM. SUMMARY

[0003] Aspects of the present disclosure provide a method for a memory system. The memory system can include a memory controller and a memory device. The method can include receiving data to be written into the memory device, the memory device including memory cells each having a first state and a second state, the data including bits each of which corresponds to one of the first state and the second state; counting a first number of bits of the received data that correspond to the first state and a second number of bits of the received data that correspond to the second state; determining whether to perform a first flipping operation on the received data based on the second number of bits that correspond to the second state and the first number of bits that correspond to the first state; in response to a difference between the second number of bits that correspond to the second state and the first number of bits that correspond to the first state being greater than a threshold value, performing the first flipping operation to flip bits in the received data; and storing the received data having the flipped bits to the memory device.

[0004] In embodiments, the method can further include storing the received data to the storage device without flipping bits in the received data in response to: the second number of bits corresponding to the second state being not greater than the first number of bits corresponding to the first state, or a difference between the second number of bits corresponding to the second state and the first number of bits corresponding to the first state being less than a threshold value.

[0005] In embodiments, the method can further include generating a flip flag indicating whether the first flipping operation has been performed on the received data, and storing the flip flag to the storage device. In examples, the method can further include reading the received data with flipped bits and the flip flag from the storage device, the flip flag indicating whether the first flipping operation has been performed on the received data, determining whether to perform a second flipping operation on the received data with flipped bits based on the flip flag indicating whether the first flipping operation has been performed on the received data, and performing the second flipping operation to flip bits in the received data that were previously flipped in response to the flip flag indicating that the first flipping operation has been performed on the received data.

[0006] In examples, storing the received data with flipped bits to the storage device includes encoding the received data with flipped bits to generate error correction code (ECC) parity information, and storing the ECC parity information to the storage device. In examples, reading the received data with flipped bits from the storage device includes reading the ECC parity information from the storage device, and recovering the received data with flipped bits based on the ECC parity information.

[0007] In embodiments, the storage device is a phase change memory (PCM) device, and the first state and the second state of the storage cells of the storage device correspond to crystalline and amorphous states of the PCM device, respectively. In embodiments, the storage device is one of: resistive random access memory, magnetic random access memory, carbon nanotube random access memory, and dynamic random access memory.

[0008] Aspects of the present disclosure also provide a memory system, comprising: a memory device; and a memory controller comprising circuitry. The circuitry can be configured to: receive, at the memory controller, data to be written into the memory device, the memory device comprising memory cells each having a first state and a second state, the data comprising bits each of which corresponds to one of the first state and the second state; count a first number of bits in the received data that correspond to the first state and a second number of bits that correspond to the second state; determine, based on the second number of bits that correspond to the second state and the first number of bits that correspond to the first state, whether to perform a first flipping operation on the received data; in response to a difference between the second number of bits that correspond to the second state and the first number of bits that correspond to the first state being greater than a threshold value, perform the first flipping operation to flip bits in the received data; and store the received data with the flipped bits to the memory device.

[0009] Aspects of the present disclosure provide a non-transitory computer-readable medium storing instructions. The instructions, when executed by a processing device, cause the processing device to perform the above-described method of a memory system. BRIEF DESCRIPTION OF DRAWINGS

[0010] Aspects of the present disclosure can be understood more readily by reference to the following detailed description when taken in connection with the accompanying drawings. Note that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features can be increased or decreased for the sake of clarity of discussion.

[0011] Figure 1 A block diagram of a computer system 100 having a memory device is shown in accordance with some aspects of the present disclosure.

[0012] Figure 2 An example of a PCM device 200 is shown in accordance with embodiments of the present disclosure.

[0013] Figure 3 Temperature curves 301-303 of reset, set, and read operations in a PCM cell are shown.

[0014] Figure 4 A schematic diagram of a storage information distribution of a storage cell is shown in accordance with embodiments of the present disclosure.

[0015] Figure 5A A schematic diagram of a codeword 500A is shown in accordance with embodiments of the present disclosure.

[0016] Figure 5B An example of a layout of spare data 502 is shown in accordance with embodiments of the present disclosure.

[0017] Figure 6A flowchart illustrating a data processing procedure 600 is shown in accordance with embodiments of the present disclosure.

[0018] Figure 7 Another flowchart illustrating a data processing procedure 700 is shown in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0019] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Other configurations and arrangements can be employed without departing from the scope of the disclosure. Moreover, the disclosure is applicable to other applications as well. The functions and structures described in this disclosure can be combined, adjusted, and modified in ways that are not specifically described in the present disclosure, so that these combinations, adjustments, and modifications are within the scope of the present disclosure.

[0020] Generally, terminology can be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, can be used to describe any feature, structure, or characteristic in the singular or can be used to describe combinations of features, structures or characteristics, in the plural, as

[0021] Figure 1 A block diagram illustrating a computer system 100 with a memory device is shown in accordance with some aspects of the present disclosure. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device with a memory device. As shown, the system 100 includes a memory device 102, a processor 104, and a bus 106. Figure 1As shown in the middle, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), such as an application processor (AP). The host 108 can be configured to send data to or receive data from the memory device 104. The memory device 104 can be any memory device disclosed in the present disclosure.

[0022] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations (write operations). The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to handle error correction codes (ECC) with respect to data read from or written to the memory device 104. Any other suitable functions can also be performed by the memory controller 106.

[0023] The memory controller 106 can communicate with external devices (e.g., the host 108) in accordance with a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of a variety of interface protocols (e.g., a USB protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a firewire protocol, etc.).

[0024] In some embodiments, the memory system 102 does not include the memory controller 106, and the host 108 is directly coupled to the memory device 104. The memory controller 106 can be located in the host 108. Alternatively, the host 108 can also not include the memory controller 106, but can be configured to perform functions similar to those performed by the memory controller 106, as described above or below.

[0025] In various embodiments, the memory device 104 can be based on various memory technologies. In some embodiments, the memory device 104 employs storage class memory (SCM) technology. Examples of SCM technology include phase change memory (PCM), resistive random access memory (ReRAM), magnetic random access memory (MRAM), carbon nanotube random access memory, etc.

[0026] PCM is based on phase change materials. Such materials can exist in two different phases: an amorphous phase and a crystalline phase. The amorphous phase has a higher resistivity than the crystalline phase. Thus, the two phases can represent two different memory states for a single-level cell (SLC). By appropriate optical or electrical heating, the amorphous phase can be set to the crystalline phase, or the crystalline phase can be reset to the amorphous phase. In some examples, some phase change materials can be controlled to change between more than two states with different levels of electrical resistance. Thus, multiple-level cells (MLCs) can be implemented. Examples of phase change materials can include GeSbTe (GST), N-doped GST, GaSbGe, GeBiTe, physical vapor deposition (PVD) GST, GeTe / SbTe, etc. In some embodiments, phase change chalcogenides are used for PCM.

[0027] ReRAM utilizes a physical phenomenon of resistance switching. For example, a dielectric object can experience a change in resistance across its terminals when subjected to a current or electric field. Switching from a high resistance state to a low resistance state is a set operation, while switching from a low resistance state to a high resistance state is a reset operation. In some examples, a cell of ReRAM (called a memristor) can have a metal-insulator-metal structure.

[0028] MRAM can use magnetic charge to store data. For example, a MRAM cell can include two magnetic elements stacked on top of each other. One magnetic element has a fixed magnetic polarity, while the other magnetic element has a switchable (programmable) polarity. Depending on the switchable polarity, the MRAM cell can exhibit parallel magnetic moments of the magnetic elements (with a low resistance) or anti-parallel magnetic moments of the magnetic elements (with a high resistance). The resistance of the cell can be measured by flowing a current through a write line to induce a magnetic field across the cell.

[0029] Carbon nanotube random access memory is based on the location of carbon nanotubes deposited on a chip-like substrate. For example, in a two-terminal cell, a crossing nanotube between two electrodes can be either in contact or slightly separated. The resistance of a nanotube in contact is lower, while the resistance of a nanotube that is separated is higher. A suitable voltage can be applied to the two terminals to cause the cell to switch between a low resistance state and a high resistance state.

[0030] The memory device 104 can include one or more arrays of memory cells. In some embodiments, the memory cells of the array of memory cells can be SLCs, each SLC having two possible memory states and thus can store one bit of data. For example, a first memory state of “0” can correspond to a first range of resistances and a second memory state of “1” can correspond to a second range of resistances. In some embodiments, the memory cells of the memory array can be MLCs capable of storing more than a single bit of data in more than two memory states. For example, a MLC can store two bits per cell (also referred to as a double-level cell (DLC)), three bits per cell (also referred to as a triple-level cell (TLC)), or four bits per cell (also referred to as a quad-level cell (QLC)).

[0031] In some embodiments, the memory device 104 is a dynamic random access memory (DRAM). In an example, the memory cells of such a DRAM can be made of a capacitor and a transistor. The capacitor can be charged or discharged. These two states can represent the two values of a bit, 0 and 1. A memory refresh circuit can be configured to periodically rewrite the data in the capacitor.

[0032] According to aspects of the present disclosure, the memory controller 106 can be configured to perform data processing to convert data from an original form to a target form before writing the data to the memory device 104. The target form is more friendly to the memory device 104 compared to the original form of the data. For example, the memory device 104 employs PCM technology. The memory cells in the memory device 104 use an amorphous phase to represent a binary digit (bit) of 0 and a crystalline phase to represent a binary digit (bit) of 1. Writing a digit of 0 involves more reset operations, while writing a digit of 1 involves more set operations. According to the present disclosure, a reset operation exerts a stronger current and high temperature on the phase change material in the memory cell, thus having a greater negative impact on the endurance of the memory cell compared to a set operation, and also consumes more power. Therefore, a sequence of digits to be written to the memory device 104 preferably includes more 1s than 0s.

[0033] To improve endurance of the storage cells and save power, the memory controller 106 can be configured to investigate the number of Is and Os in a sequence of digits (or bits) in the data. In some embodiments, when the number of 0 bits is greater than the number of 1 bits, the memory controller 106 can employ an inverter to flip the bits in the sequence. For example, as a result of the flipping or inverting operation, a 0 bit becomes a 1 bit and a 1 bit becomes a 0 bit. The resulting sequence will include more 1 bits than 0 bits. Writing such a sequence will result in fewer reset operations (which transform the crystalline phase to the amorphous phase) than writing the original sequence.

[0034] A flip flag can be generated and stored in the memory device 104 along with the corresponding data segment. The flip flag can indicate whether a bit flipping operation has been applied to the corresponding data. When the data segment is read, the associated flip flag can also be retrieved from the memory device 104. The memory controller 106 can determine, based on the value of the flip flag, whether to perform an inverse transformation on the corresponding data to obtain the original data.

[0035] While PCM is used in some examples to explain the data transformation scheme, the inventive concepts of the present disclosure are not limited to any particular memory technology. Various memory technologies can employ different materials, device structures, or operating principles, and corresponding memory devices can have different properties. The data transformation scheme disclosed herein can be employed whenever a memory device exhibits a preference for a particular bit pattern (0 or 1) in the data, e.g., the percentage of 0 bits and 1 bits, and the preference can be motivated by various possible reasons such as saving power, improving endurance, or any other reason.

[0036] Figure 2 An example of a PCM device 200 is shown in accordance with an embodiment of the present disclosure. The PCM device 200 can be in communication with a memory controller (e.g., the memory controller 106) via a channel bus. The PCM device 200 can include a plurality of memory cells 202, a write driver 204, a read driver 206, and a sense amplifier 208. Figure 1The PCM device 200 is in communication with a memory controller (e.g., the memory controller 106 in FIG. 1). Data and addresses can be transmitted between the PCM device 200 and the memory controller. The PCM device 200 includes a die having a set of memory banks 202. Each memory bank 202 includes a memory array 204 (also referred to as a memory cell array) having memory cells arranged in rows and columns. The memory array 204 can be partitioned into a plurality of memory subarrays 208 for efficient wiring and low power consumption. In some embodiments, each or at least one of the memory cells includes a PCM cell. As described above, a PCM cell can be programmed to a set state or a reset state to store data. Each memory cell is connected to a bit line 210 and a word line 212. Each memory bank 202 includes a data buffer / sense amplifier 214, a column decoder / bit line driver 216, and a row decoder / word line driver 218. In some examples, additional peripheral circuitry (not shown in FIG. 2) can also be included. Figure 2

[0037] The data buffer / sense amplifier 214 can be configured to read data from and program (write) data to the memory cell array 204 according to control signals from the memory controller (e.g., the memory controller 106 in FIG. 1). In one example, the data buffer / sense amplifier 214 can store a codeword of program data (write data) to be programmed into the memory cell array 204. In another example, the data buffer / sense amplifier 214 can perform a program verify operation to ensure that data has been correctly programmed into selected memory cells coupled to a selected word line 212. In yet another example, the data buffer / sense amplifier 214 can also sense a low power signal from the bit line 210 representing a data bit stored in a memory cell and amplify a small voltage swing to an identifiable logic level in a read operation. Figure 1

[0038] The column decoder / bit line driver 216 can be connected to the memory cell array 204 via the bit lines and select / driver one or more bit lines to perform operations on memory cells coupled to the selected bit line. The row decoder / word line driver 218 can be connected to the memory cell array 204 via the word lines and select / driver one or more word lines to perform operations on memory cells coupled to the selected word line.

[0039] Figure 3 ​​Temperature curves 301-303 show reset, set, and read operations in a PCM cell. For example, a PCM cell is used to store information based on a large resistivity contrast between a high-resistance amorphous state and a low-resistance crystalline state of a phase change material. Electrical pulses can be used to program (set or reset) and read a PCM cell. The electrical pulses can generate Joule heat to induce phase transformation in the phase change material during a reset or set operation.

[0040] To reset a PCM cell to an amorphous phase, a large current pulse can be applied to a program region for a short time (e.g., 50 ns or less). The program region can be melted and then rapidly quenched. Temperature curve 301 corresponds to this reset operation. As shown, the peak portion of temperature curve 301 is above the melting temperature. This high temperature can negatively affect the endurance of the PCM cell. In an example, frequently applying a high temperature can change the properties of the phase change material, thereby reducing or eliminating the resistivity contrast between the amorphous state and the crystalline state.

[0041] To set a PCM cell to a crystalline phase, a moderate current pulse can be applied for a longer time to anneal the program region compared to the reset operation. Temperature curve 302 corresponds to this set operation. As shown, the corresponding temperature can be above the crystallization temperature and below the melting temperature. Compared to the reset operation, the operating temperature in the set operation is lower, and thus can have less negative impact on the endurance of the PCM cell. Also, the power consumption in the set operation can be less than in the reset operation. The data pattern transformation techniques disclosed herein can reduce the number of reset operations in the programming operations of a PCM-based memory device. Thus, the data pattern transformation techniques have the advantages of improving the endurance and saving power of the corresponding memory device.

[0042] To read the state of a PCM cell, a small electrical bias is applied to measure the resistance without disturbing the phase change material in the program region. Temperature curve 303 corresponds to this read operation.

[0043] Figure 4 A diagram shows the storage information distribution of a storage cell according to an embodiment of the disclosure. The horizontal axis represents the electrical parameter value (e.g., resistance value) of the memory state of the corresponding storage cell. The vertical axis represents the number of storage cells corresponding to different electrical parameter values. The storage cell can belong to a memory device 104 based on various memory technologies. For example, the storage cell can belong to a memory device of SCM.

[0044] The storage cell can have at least two memory states corresponding to bit 1 and bit 0, as Figure 4The distribution 401 represents a distribution of storage information of storage cells in the memory state of bit 1. The distribution 402 represents a distribution of storage information of storage cells in the memory state of bit 0. On average, the storage cells in the memory state of bit 0 have greater electrical parameter values than the storage cells in the memory state of bit 1. A portion of the storage cells of bit 0 have smaller electrical parameter values than a portion of the storage cells of bit 1.

[0045] Figure 5A A schematic diagram of a codeword 500A is shown in accordance with an embodiment of the disclosure. The codeword 500A includes a first portion (M pages of user data 501) and a second portion (N pages of spare data 502). The codeword 500A can be generated by a data processing process. For example, in Figure 1 In an example, the memory controller 106 can receive data from the host 108 to be written to the memory device 104. The memory controller 106 can then process the data prior to the programming operation. Various processing operations can be performed for various purposes during the data processing process. For example, an error correction code (ECC) encoding process can be performed to generate ECC parity information. For example, a compression process can be performed to compress the data. For example, the data can be reshaped to another form to reduce read latency. For example, the data can be remapped to a particular storage region for wear leveling purposes. For example, a cyclic redundancy check (CRC) code can be generated for error detection.

[0046] The data received from the host 108 can be a portion of the M pages of user data 501. Alternatively, a transformed copy of the received data can be a portion of the M pages of user data. Information related to or generated by the various processing operations described above can be generated and included in the N pages of spare data 502. The M pages of user data 501 and the N pages of spare data 502 are associated with each other and written to the memory device 104. During a read process, the memory controller 106 can process the user data 501 based on the spare data 502 to output the data in the original form.

[0047] Figure 5B An example of a layout of the spare data 502 is shown in accordance with an embodiment of the disclosure. The spare data 502 can include ECC parity information 504. The remaining portion of the spare data 502 can be used to store various metadata, CRC, etc.

[0048] In some embodiments, the data transformation schemes disclosed herein are used to process data to be programmed to a memory device 104 in Figure 1 or Figure 2The memory controller 106 can flip bits in the data when the number of 0 bits in the received data is greater than the number of 1 bits. The memory controller 106 can determine not to perform the flipping operation when the number of 0 bits is not greater than the number of 1 bits, or the number of 0 bits is greater than the number of 1 bits but the difference is not greater than a threshold. Thus, a flip flag can be generated to indicate whether a flipping operation is performed on the data.

[0049] In some embodiments, the memory controller 106 can flip bits in the data when the number of 0 bits in the received data is greater than the number of 1 bits by a difference that is greater than a threshold. Thus, a flip flag can be generated to indicate that a flipping operation is performed on the data.

[0050] In the above embodiments, the data to be programmed to the memory device 104 can be part of the user data 501, either in the original form or in the transformed form, depending on whether a flipping operation has been performed or not. The flip flag can be part of the spare data 502. During a read operation, the memory controller 106 can efficiently determine whether to perform a flipping operation to recover the data or to skip a padding operation based on the flip flag obtained from the spare data 502.

[0051] Figure 6 A flowchart of a data processing procedure 600 is shown in accordance with an embodiment of the present disclosure. The procedure 600 can be performed by the memory controller 106 in the memory system 102 in the example. Figure 1 The procedure 600 can start from S601 and proceed to S610.

[0052] At S610, the number of 1 bits and 0 bits in the data to be stored is counted. For example, the memory controller 106 can receive original data from the host 108. The memory controller 106 can count the number of digits 1 and the number of digits 0 in the original data. For example, the memory controller 106 can be configured with a counter. The counter can be implemented with appropriate hardware, software (firmware), or a combination thereof. In an example, instead of counting the bits in the original data from the host 108, the memory controller 106 can count the bits in the data resulting from a previous processing operation. For example, the original data is transformed (e.g., reshaped, compressed, etc.) into another form. The data transformation procedure 600 can be performed on the transformed data.

[0053] At S620, it is determined whether the number of 0 bits is greater than the number of 1 bits based on the result of S610. When the number of 0 bits is greater than the number of 1 bits, the procedure 600 proceeds to S630. Otherwise, the procedure 600 proceeds to S650.

[0054] In some embodiments, at S620, a predefined threshold is used to control the flow of the process 600. Specifically, it is determined whether the number of 0 bits is greater than the number of 1 bits, and whether the difference between the number of 0 bits and the number of 1 bits is greater than a threshold. If so, the process 600 proceeds to S630. Otherwise, the process 600 proceeds to S650. For example, the bit flipping operation can cause delay and increase power consumption. If the difference between the number of 0 bits and the number of 1 bits is less than the threshold, the benefit of inverting the bits can not be worth the cost of the bit flipping operation. Thus, performing the flipping operation can be skipped.

[0055] At S630, the bits in the data can be flipped. In some embodiments, all bits in the data can be flipped. In some embodiments, a portion of the bits are flipped. For example, the bits at specific locations in the data are flipped. The resulting data can be included in the user data. In embodiments, the user data can then go through an ECC process by the ECC encoder to generate ECC parity information. The ECC parity information can be included in the spare data. The user data and the spare data can be later stored in the memory device 104. In some embodiments, the memory controller 106 can be configured with an inverter to perform the flipping operation. The inverter can be implemented with appropriate hardware, software (firmware), or a combination thereof.

[0056] At S640, a flip flag is set. For example, the flip flag uses one bit to indicate that the flipping operation has been performed. In an example, the value of the flip flag is set to 1 to indicate that the flipping operation has been performed. The flip flag can be included in the spare data and stored in the memory device 104. The process 600 can proceed to S699 and terminate at S699.

[0057] At S650, a flip flag is set. For example, the flip flag uses one bit to indicate that the flipping operation has not been performed. In an example, the value of the flip flag is set to 0 to indicate that the flipping operation has not been performed. Similarly, the flip flag can be included in the spare data and stored in the memory device 104. The process 600 can proceed to S699 and terminate at S699. In some examples, the flip flag uses bit 0 to indicate that the flipping operation has been performed, and bit 1 to indicate that the flipping operation has not been performed.

[0058] Figure 7 Another flow diagram of a data processing process 700 is shown in accordance with embodiments of the present disclosure. The process 700 can be performed by the memory controller 106 in the memory system 102 in the example. Figure 1 The process 700 can start from S701 and proceed to S710.

[0059] At S710, the data read from the memory device 104 can be successfully decoded by performing an ECC decoding process by the ECC decoder. For example, a codeword (e.g., codeword 500A) can be read from the memory device 104. The codeword can include a user data portion and a spare data portion. The spare data can include ECC parity information. The ECC decoder can recover the user data based on the ECC parity information and the user data.

[0060] At S720, it can be determined whether a flip operation has been performed on the user data based on a value of a flip flag. For example, the flip flag can be a portion of the spare data obtained at S710. In some embodiments, if the flip flag has a bit value of 1, it can be determined that a flip operation has been performed. If the flip flag has a bit value of 0, it can be determined that a flip operation has not been performed. When a flip operation has been performed, the process 700 proceeds to S730. Otherwise, the process 700 proceeds to S740.

[0061] At S730, bits in the recovered user data obtained at S710 can be flipped at an inverter to obtain inverted data. In cases where the inverted data is the original data received from the host 108, the inverted data can be transferred to the host 108. In cases where the inverted data is a transformed form from the original data, further operations (e.g., decompression, inverse operations of previous shaping operations, etc.) can be performed to obtain the original data received from the host 108.

[0062] At S740, the original data obtained at S730 or included in the user data at S710 can be transferred to a system memory (e.g., a read buffer) of the host 108. The process 700 can proceed to S799 and terminate at S799.

[0063] A memory controller in a memory system can be configured to perform various functions in accordance with one or more embodiments or examples described herein. The memory controller can include a general purpose processor or specially designed circuitry to implement various functions, components, or processes described in various embodiments herein. For example, the memory controller can include processing circuitry configured to perform the functions and processes described herein, with or without software. In various examples, the processing circuitry can be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), a digital enhanced circuit, or comparable device or combination thereof.

[0064] In some other examples, the processing circuitry can be a central processing unit (CPU) configured to execute program instructions to perform various functions and processes described herein. For example, the memory controller can include a memory configured to store program instructions. Upon execution of the program instructions, the processing circuitry can perform the functions and processes. The memory can also store other programs or data, e.g., an operating system, application programs, etc. The memory can include a non-transitory storage medium, e.g., read-only memory (ROM), random-access memory (RAM), flash memory, solid-state memory, etc.

[0065] The processes and functions described herein can be implemented as a computer program that, when executed by one or more processors, can cause the one or more processors to perform the corresponding processes and functions. The computer program can be stored or distributed on suitable media, e.g., optical storage media or solid-state storage media provided with or part of other hardware. The computer program can also be distributed in other forms, e.g., via a network or other wired or wireless telecommunications systems. For example, the computer program can be obtained and loaded into a device, including by physical media or distributed systems, including, e.g., from a server connected to the Internet.

[0066] A computer program can be accessed from the computer-readable medium providing program instructions for use by, or in connection with, a computer or any instruction execution system. The computer-readable medium can include any means that can store, communicate, propagate, or transport the computer program for use by or in connection with the instruction execution system, apparatus, or device. The computer-readable medium can be a magnetic, optical, electronic, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. The computer-readable medium can include a computer-readable non-transitory storage medium, such as a semiconductor or solid state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a magnetic disk, and an optical disk, and the like. The computer-readable non-transitory storage medium can include all types of computer-readable media, including magnetic storage media, optical storage media, flash memory media, and solid state storage media.

[0067] While aspects of the present disclosure have been described and illustrated with reference to the exemplary embodiments, the examples are intended to illustrate techniques that can be employed by those of skill in the art and are not intended to limit the scope of the disclosure. Changes can be made in the implementations and details of the examples without departing from the scope of the claims as described below.

Claims

1. A method for a memory system including a storage device, the method comprising: Receive data to be written into the storage device, the storage device including storage cells, each storage cell having a first state and a second state, the data including bits, each bit corresponding to one of the first state and the second state; Count the number of the first bit corresponding to the first state and the number of the second bit corresponding to the second state in the received data; In response to the fact that the number of the second bits of the bit corresponding to the second state is greater than the number of the first bits of the bit corresponding to the first state, a first flip operation is performed to flip the bits in the received data; as well as The received data with flipped bits is stored in the storage device.

2. The method according to claim 1, further comprising: In response to a difference greater than a threshold between the number of the second bits of the bit corresponding to the second state and the number of the first bits of the bit corresponding to the first state, the first flip operation is performed to flip the bits in the received data.

3. The method according to claim 1, further comprising: In response to the following, the received data is stored in the storage device without flipping the bits in the received data: The number of the second bits corresponding to the second state is not greater than the number of the first bits corresponding to the first state, or The difference between the number of the second bits of the bit corresponding to the second state and the number of the first bits of the bit corresponding to the first state is less than a threshold.

4. The method according to claim 1, further comprising: Generate a flip flag indicating whether the first flip operation has been performed on the received data; as well as The flip flag is stored in the storage device.

5. The method according to claim 4, further comprising: Read the received data having the flip bit and the flip flag from the storage device, the flip flag indicating whether the first flip operation has been performed on the received data; Based on the flip flag indicating whether the first flip operation has been performed on the received data, determine whether to perform a second flip operation on the received data having the flipped bit; as well as In response to the flip flag indicating that the first flip operation has been performed on the received data, the second flip operation is performed to flip the previously flipped bits in the received data.

6. The method according to claim 5, wherein, Storing the received data having the flipped bits into the storage device includes: The received data having the flipped bits is encoded to generate error correction code (ECC) parity check information; and The ECC parity information is stored in the storage device.

7. The method according to claim 6, wherein, Reading the received data having the flipped bits from the storage device includes: Read the ECC parity information from the storage device; and The received data with the flipped bits is recovered based on the ECC parity information.

8. The method according to claim 1, wherein, The storage device is a phase change memory (PCM) device, and the first state and the second state of the storage cells of the storage device correspond to the crystalline state and the amorphous state of the PCM device, respectively.

9. A memory system, comprising: Storage device, the storage device including storage units, and A memory controller, comprising a circuit system configured to: Receive data to be written into the storage device, each storage cell having a first state and a second state, the data including bits, each bit corresponding to one of the first state and the second state; Count the number of the first bit corresponding to the first state and the number of the second bit corresponding to the second state in the received data; In response to the fact that the number of the second bits of the bit corresponding to the second state is greater than the number of the first bits of the bit corresponding to the first state, a first flip operation is performed to flip the bits in the received data; as well as The received data with flipped bits is stored in the storage device.

10. The memory system according to claim 9, wherein, The circuit system is also configured to: In response to a difference greater than a threshold between the number of the second bits of the bit corresponding to the second state and the number of the first bits of the bit corresponding to the first state, the first flip operation is performed to flip the bits in the received data.

11. The memory system according to claim 9, wherein, The circuit system is also configured to: In response to the following, the received data is stored in the storage device without flipping the bits in the received data: The number of the second bits corresponding to the second state is not greater than the number of the first bits corresponding to the first state, or The difference between the number of the second bits of the bit corresponding to the second state and the number of the first bits of the bit corresponding to the first state is less than a threshold.

12. The memory system according to claim 9, wherein, The circuit system is also configured to: Generate a flip flag indicating whether the first flip operation has been performed on the received data; and The flip flag is stored in the storage device.

13. The memory system according to claim 12, wherein, The circuit system is also configured to: Read the received data having the flip bit and the flip flag from the storage device, the flip flag indicating whether the first flip operation has been performed on the received data; Based on the flip flag indicating whether the first flip operation has been performed on the received data, determine whether to perform a second flip operation on the received data having the flipped bit; as well as In response to the flip flag indicating that the first flip operation has been performed on the received data, the second flip operation is performed to flip the previously flipped bits in the received data.

14. The memory system according to claim 13, wherein, The circuit system is also configured to: The received data having the flipped bits is encoded to generate error correction code (ECC) parity check information; and The ECC parity information is stored in the storage device.

15. The memory system according to claim 14, wherein, The circuit system is also configured to: Read the ECC parity information from the storage device; and The received data with the flipped bits is recovered based on the ECC parity information.

16. The memory system according to claim 9, wherein, The storage device is a phase change memory (PCM) device, and the first state and the second state of the storage cells of the storage device correspond to the crystalline state and the amorphous state of the PCM device, respectively.

17. A non-transitory computer-readable medium storing instructions, which, when executed by a processing device, cause the processing device to perform a method for a memory system, comprising: Receive data to be written into a storage device of the memory system, the storage device including storage cells, each storage cell having a first state and a second state, the data including bits, each bit corresponding to one of the first state and the second state; Count the number of the first bit corresponding to the first state and the number of the second bit corresponding to the second state in the received data; In response to the fact that the number of the second bits of the bit corresponding to the second state is greater than the number of the first bits of the bit corresponding to the first state, a first flip operation is performed to flip the bits in the received data; as well as The received data with flipped bits is stored in the storage device.

18. The non-transitory computer-readable medium according to claim 17, wherein, The method further includes: In response to the following, the received data is stored in the storage device without flipping the bits in the received data: The number of the second bits corresponding to the second state is not greater than the number of the first bits corresponding to the first state, or The difference between the number of the second bits of the bit corresponding to the second state and the number of the first bits of the bit corresponding to the first state is less than a threshold.

19. The non-transitory computer-readable medium according to claim 17, wherein, The method further includes: Generate a flip flag indicating whether the first flip operation has been performed on the received data; and The flip flag is stored in the storage device.

20. The non-transitory computer-readable medium according to claim 19, wherein, The method further includes: Read the received data having the flip bit and the flip flag from the storage device, the flip flag indicating whether the first flip operation has been performed on the received data; Based on the flip flag indicating whether the first flip operation has been performed on the received data, determine whether to perform a second flip operation on the received data having the flipped bits; and In response to the flip flag indicating that the first flip operation has been performed on the received data, the second flip operation is performed to flip the previously flipped bits in the received data.

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