Method for measuring layering height of ground integrated circuit product

Abstract

The invention discloses a method for measuring the layering height of an integrated circuit product after grinding, and belongs to the technical field of integrated circuits, and the method comprises the steps: providing a chip, scanning a sample by using SAT, presenting the overall morphology of the chip through an imaging picture, drawing a central position, punching a heat dissipation cover at the central position of the chip through a drilling machine, heating the FCBGA sample, and measuring the layering height of the FCBGA sample. Two probes of a displacement sensor are perpendicular to a chip, a first probe is pricked on the surface of the chip, a second probe is pricked on a heat dissipation cover at the edge of a hole, the other ends of the probes are connected with displacement sensor equipment, the displacement sensor equipment is started, a heating table is controlled to heat the FCBGA sample to different temperatures, and the real-time temperature of the FCBGA sample is detected through a thermodetector. The temperature and displacement of the sample are recorded, the displacement difference, namely the layering height between the heat dissipation cover and the chip, is calculated through displacement data of the sensor, the data are sorted to obtain the relation between the temperature and the layering height between the chip and the heat dissipation cover, the sample is ground, and whether the layering height is matched with the displacement difference generated when the LVDT is cooled to the room temperature or not is obtained through measurement.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a method for measuring the layer height of an integrated circuit product after grinding. Background Art

[0002] In FCBGA devices, the heat dissipation function is particularly important. The lower side of the heat dissipation cover is connected to the chip through thermal conductive glue to guide the heat dissipation of the chip. The contact area between the three directly affects the heat dissipation effect of the entire chip. In practical applications, due to the different thermal expansion systems of the chip and the heat dissipation cover, internal stress is easily generated under the condition of thermal expansion and contraction. If these stresses are mismatched, it will cause delamination between the heat dissipation cover and the chip, which will reduce the heat dissipation function of the entire chip. The current method is: perform a temperature test on the sample, wait for the sample to cool to room temperature, and use SAT scanning to determine whether there is delamination between the lid and the chip. If delamination occurs, locate the delamination position through SAT, and measure the delamination height by grinding method for the delamination position. However, this method can only obtain the delamination of the sample during the heating process and the delamination height at room temperature. In fact, the delamination height will change with the change of temperature. If it is possible to understand at which temperature stage the sample delaminates and obtain the corresponding relationship between temperature and delamination degree, measures can be taken to reduce the probability of delamination. Summary of the invention

[0003] In view of the above situation, in order to overcome the defects of the prior art, the present invention proposes a method for measuring the layer height of an integrated circuit product after grinding.

[0004] In order to achieve the above object, the following technical solution is adopted: The present invention provides a method for measuring the layer height of an integrated circuit product after grinding, comprising the following steps:

[0005] Provide chips;

[0006] Use SAT to scan the sample. When the focus position is focused on the chip surface, select the chip position waveform on the waveform diagram, and present the overall morphology of the chip through the imaging diagram;

[0007] Draw the center position of the chip based on the surface imaging of the chip;

[0008] Place the heat dissipation cover of the FCBGA sample facing upwards, and punch a hole in the heat dissipation cover at the center of the chip;

[0009] Place the FCBGA sample with the heat dissipation cover facing upward on a heating platform for heating;

[0010] Place the two probes of the displacement sensor perpendicular to the chip, with the first probe inserted into the chip surface and the second probe inserted into the heat dissipation cover at the edge of the hole;

[0011] Connect the other end of the probe to the displacement sensor device, start the displacement sensor device, control the heating stage to heat to different temperatures, and use the thermometer to detect the real-time temperature of the FCBGA sample;

[0012] Record the sample temperature and displacement, and calculate the displacement difference, i.e. the layer height between the heat sink and the chip, through the sensor displacement data;

[0013] Organize the data to find the relationship between temperature and the layer height between the chip and the heat sink;

[0014] The sample that has been tested by LVDT is ground and measured to see whether the layer height is consistent with the displacement difference when the LVDT is cooled to room temperature.

[0015] Furthermore, the FCBGA sample includes from top to bottom:

[0016] Heat dissipation cover, used to protect the chip and provide physical protection and moisture protection;

[0017] Thermally conductive adhesive is used to improve the heat conduction efficiency between the chip and the heat dissipation cover and reduce the temperature of the chip during operation;

[0018] The chip is the integrated circuit chip itself in the FCBGA package, which has circuits and functional logic;

[0019] Filling material, a material filled between the chip and the packaging substrate, used to enhance the bonding between the chip and the substrate;

[0020] The packaging substrate is the underlying structure used to support and connect the chip. It is composed of multiple layers of materials and can achieve electrical connection and signal transmission.

[0021] Furthermore, a 50 Hz probe was selected when scanning the sample using SAT.

[0022] Furthermore, when using a drilling machine, select a drill bit with a diameter of 1.5 mm.

[0023] Furthermore, when drilling holes in the heat dissipation cover, the drilling depth needs to be controlled to prevent the chip from being hit.

[0024] Furthermore, the first probe needs to just touch the chip surface, and the second probe needs to be inserted into the outermost edge of the hole.

[0025] The beneficial effects of the present invention are:

[0026] (1) The present invention obtains the layer height between the heat dissipation cover and the chip at different temperatures through the displacement difference of the displacement sensor, which can verify the influence of temperature on the heat dissipation cover, thermal conductive adhesive and chip, and provides a method for material research.

[0027] (2) The layer height measured by the displacement sensor can improve the accuracy of layer height measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The overall morphology of the chip obtained by SAT scanning imaging;

[0029] Figure 2 To measure the center position of the chip using a ruler and a marker;

[0030] Figure 3 This is the structural diagram of the FCBGA sample after drilling by a drilling machine;

[0031] Figure 4 This is the structural diagram of the FCBGA sample when it is heated;

[0032] Figure 5 A structural diagram showing the connection between the first probe, the second probe and the FCBGA sample;

[0033] Figure 6 It is a graph showing the relationship between temperature and the layer height between the chip and the heat sink;

[0034] Figure 7 This is a magnified view of the polished part of the sample after the LVDT test.

[0035] Legend: 1. Chip surface; 2. Center position; 3. Heat sink cover; 4. Thermal adhesive; 5. Chip; 6. Filling material; 7. Package substrate; 8. Hole; 9. Heating platform; 10. First probe; 11. Second probe.

[0036] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0038] Unless otherwise defined, all professional and scientific terms used herein have the same meanings as those familiar to those skilled in the art. In addition, any methods and materials similar or equivalent to those described herein may be applied to the present invention. The preferred implementation methods and materials described herein are for demonstration purposes only and are not intended to limit the content of this application.

[0039] The experimental methods in the following examples are conventional methods unless otherwise specified, and the experimental materials used in the following examples are purchased from commercial channels unless otherwise specified.

[0040] Example

[0041] The method for measuring the delamination height of an integrated circuit product after grinding comprises the following steps:

[0042] Providing a chip, wherein the chip is made of silicon;

[0043] Use SAT to scan the sample, adjust SAT to C-SCAN mode, select a 50Hz probe, focus on the chip surface, select the chip position waveform on the waveform graph, and the imaging graph shows the following: Figure 1 The overall morphology of the chip shown;

[0044] According to the surface imaging of the chip, use a ruler to measure and use a marker to draw the center position of the chip, such as Figure 2 As shown;

[0045] Place the heat dissipation cover of the FCBGA sample facing upwards, and drill a hole on the heat dissipation cover at the center of the chip using a drill. Use a drill bit with a diameter of 1.5 mm. When drilling, control the drilling depth to prevent hitting the chip.

[0046] The structure of the FCBGA sample after punching is as follows Figure 3 As shown;

[0047] The FCBGA sample includes from top to bottom:

[0048] Heat dissipation cover, used to protect the chip and provide physical protection and moisture protection;

[0049] Thermally conductive adhesive is used to improve the heat conduction efficiency between the chip and the heat dissipation cover and reduce the temperature of the chip during operation;

[0050] The chip is the integrated circuit chip itself in the FCBGA package, which has circuits and functional logic;

[0051] Filling material, a material filled between the chip and the packaging substrate, used to enhance the bonding between the chip and the substrate;

[0052] The packaging substrate is used to support and connect the underlying structure of the chip. It is composed of multiple layers of materials and can achieve electrical connection and signal transmission;

[0053] like Figure 4 As shown, the heat dissipation cover of the FCBGA sample is placed on a heating platform for heating;

[0054] like Figure 5As shown, place the two probes of the displacement sensor perpendicular to the chip, with the first probe inserted on the chip surface and the second probe inserted on the heat dissipation cover at the edge of the hole. Note that the first probe should just touch the chip surface and the second probe should be inserted at the edge of the hole.

[0055] Connect the other end of the probe to the displacement sensor device, start the displacement sensor device, control the heating stage to heat to different temperatures, and use the thermometer to detect the real-time temperature of the FCBGA sample;

[0056] Record the sample temperature and displacement, and calculate the displacement difference, i.e. the layer height between the heat sink and the chip, through the sensor displacement data;

[0057] By sorting the data, we can find the relationship between temperature and the layer height between the chip and the heat sink cover, such as Figure 6 As shown;

[0058] The sample that has been tested by LVDT is ground and the layer height is measured to see if it matches the displacement difference when the LVDT is cooled to room temperature. The test results are as follows: Figure 7 As shown in the figure, it can be seen that the layer height coincides with the displacement difference of the LVDT when it drops to room temperature.

[0059] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

[0060] The present invention and its implementation methods are described above, which is not restrictive. The drawings are only one of the implementation methods of the present invention, and the actual application is not limited thereto. In short, if ordinary technicians in the field are inspired by it and design methods and embodiments similar to the technical solution without creativity without departing from the purpose of the invention, they should all fall within the protection scope of the present invention.

Claims

1. A method for measuring the layer height of an integrated circuit product after grinding, characterized in that: The following steps are involved: Provide chips; Use SAT to scan the sample. When the focus position is focused on the chip surface, select the chip position waveform on the waveform diagram, and present the overall morphology of the chip through the imaging diagram; Draw the center position of the chip based on the surface imaging of the chip; Place the heat dissipation cover of the FCBGA sample facing upwards, and punch a hole in the heat dissipation cover at the center of the chip; Place the FCBGA sample with the heat dissipation cover facing upward on a heating platform for heating; Place the two probes of the displacement sensor perpendicular to the chip, with the first probe inserted into the chip surface and the second probe inserted into the heat dissipation cover at the edge of the hole; Connect the other end of the probe to the displacement sensor device, start the displacement sensor device, control the heating stage to heat to different temperatures, and use the thermometer to detect the real-time temperature of the FCBGA sample; Record the sample temperature and displacement, and calculate the displacement difference, i.e. the layer height between the heat sink and the chip, through the sensor displacement data; Organize the data to find the relationship between temperature and the layer height between the chip and the heat sink; The sample that has been tested by LVDT is ground and measured to see whether the layer height is consistent with the displacement difference when the LVDT is cooled to room temperature.

2. The method for measuring the delamination height of an integrated circuit product after grinding according to claim 1, characterized in that: The FCBGA sample includes from top to bottom: Heat dissipation cover, used to protect the chip and provide physical protection and moisture protection; Thermally conductive adhesive is used to improve the heat conduction efficiency between the chip and the heat dissipation cover and reduce the temperature of the chip during operation; The chip is the integrated circuit chip itself in the FCBGA package, which has circuits and functional logic; Filling material, a material filled between the chip and the packaging substrate, used to enhance the bonding between the chip and the substrate; The packaging substrate is the underlying structure used to support and connect the chip. It is composed of multiple layers of materials and can achieve electrical connection and signal transmission.

3. The method for measuring the delamination height of an integrated circuit product after grinding according to claim 1, characterized in that: Select a 50 Hz probe when scanning the sample using SAT.

4. The method for measuring the delamination height of an integrated circuit product after grinding according to claim 1, characterized in that: When using a drill, choose a drill bit with a diameter of 1.5 mm.

5. The method for measuring the delamination height of an integrated circuit product after grinding according to claim 1, characterized in that: When drilling holes on the heat sink, the drilling depth must be controlled to prevent the chip from being hit.

6. The method for measuring the delamination height of an integrated circuit product after grinding according to claim 1, characterized in that: The first probe needs to just touch the chip surface, and the second probe needs to be inserted into the edge of the hole.

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