Integrated circuit device including backside power

Abstract

Integrated circuit devices and methods of forming the same are provided. The integrated circuit device may include a transistor including a first source / drain region and a second source / drain region spaced apart from each other in a horizontal direction; a backside power distribution network structure (BSPDNS); a substrate between the first and second source / drain regions and the BSPDNS; a back contact in the substrate and overlapped by the first source / drain region; a spacer in the substrate and overlapped by the second source / drain region; and a cavity in the substrate between the backside contact and the spacer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of integrated circuit devices, and more particularly, to integrated circuit devices including a back side power distribution network structure (BSPDNS). Background Art

[0002] Various structures of integrated circuit devices and methods of forming the same have been proposed to increase the integration density of the integrated circuit devices. In particular, integrated circuit devices including components formed in a substrate or on the back side of a substrate have been proposed to simplify the middle of line (MOL) portion and / or back end of line (BEOL) portion of device manufacturing. Summary of the invention

[0003] According to some embodiments, an integrated circuit device may include: a transistor including a first source / drain region and a second source / drain region spaced apart from each other in a horizontal direction; a back side power distribution network structure (BSPDNS); a substrate between the first source / drain region and the second source / drain region and the BSPDNS; a back side contact in the substrate and overlapped by the first source / drain region; a placeholder in the substrate and overlapped by the second source / drain region; and a cavity in the substrate between the back side contact and the placeholder.

[0004] According to some embodiments, an integrated circuit device may include: a transistor including a channel region and a source / drain region contacting a side surface of the channel region; a back side power distribution network structure (BSPDNS); a substrate between the source / drain region and the BSPDNS; a back side contact in the substrate and between the source / drain region and the BSPDNS; and a cavity in the substrate and overlapped by the channel region.

[0005] According to some embodiments, a method of forming an integrated circuit device may include: forming a first source / drain region and a second source / drain region on a preliminary substrate and forming a first preliminary placeholder and a second preliminary placeholder in the preliminary substrate, wherein the first source / drain region and the second source / drain region overlap with the first preliminary placeholder and the second preliminary placeholder, respectively; replacing the preliminary substrate with a substrate, wherein the substrate includes a cavity between the first preliminary placeholder and the second preliminary placeholder; forming an opening in the substrate by removing the first preliminary placeholder; forming a back side contact in the opening; and forming a back side power distribution network structure (BSPDNS) on the back side contact, wherein the back side contact is electrically connected to the BSPDNS and the first source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a layout diagram of an integrated circuit device according to some embodiments.

[0007] Figure 2A , Figure 2Band Figure 2C According to some embodiments, Figure 1 2 is a cross-sectional view of the integrated circuit device taken along lines XX′, Y1-Y1′ and Y2-Y2′.

[0008] Figure 3 is a flow chart of a method of forming an integrated circuit device according to some embodiments.

[0009] Figures 4 to 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B and Fig. 11C is a cross-sectional view illustrating a method of forming an integrated circuit device according to some embodiments.

[0010] Fig.12 is a layout diagram of an integrated circuit device according to some embodiments.

[0011] Fig.13A , Fig. 13B and Fig. 13C According to some embodiments, Fig.12 2 is a cross-sectional view of the integrated circuit device taken along lines XX′, Y1-Y1′ and Y2-Y2′. DETAILED DESCRIPTION

[0012] The integrated circuit device may include (multiple) back contacts and (multiple) placeholders (also referred to as (multiple) dummy placeholders or (multiple) dummy contacts). Each of the (multiple) back contacts and (multiple) placeholders may include at least a portion provided in a substrate. The (multiple) back contacts and (multiple) placeholders may be formed by forming (multiple) preliminary placeholders and then replacing the first group of (multiple) preliminary placeholders with (multiple) back contacts, respectively. In some embodiments, the second group of those (multiple) preliminary placeholders may not be replaced by (multiple) back contacts and remain in the integrated circuit device after forming the BSPDNS. In some embodiments, the (multiple) back contacts and (multiple) placeholders may include (multiple) conductive materials and / or (multiple) semiconductor materials, and there is a parasitic capacitance between two of the (multiple) back contacts and (multiple) placeholders that are adjacent to each other. The parasitic capacitance may cause resistance-capacitance (RC) delay, thereby degrading the performance of the integrated circuit device. This parasitic capacitance can be reduced or eliminated by two methods: (1) forming preliminary placeholders (multiple) only at locations where back contact (multiple) needs to be formed (i.e., a first group of preliminary placeholders (multiple)); or (2) removing some of the already formed preliminary placeholders (i.e., a second group of preliminary placeholders (multiple)). However, both methods involve additional processes (e.g., a photolithography process and / or an etching process).

[0013] According to some embodiments, a cavity may be formed in the substrate between adjacent two of the placeholders and the back contact(s), thereby reducing the parasitic capacitance therebetween without the additional process described above. Thus, resistance-capacitance (RC) delay may be reduced, and the performance of the integrated circuit device may be improved.

[0014] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0015] Figure 1 is a layout diagram of an integrated circuit device 100 according to some embodiments. Figure 2A , Figure 2B and Figure 2C According to some embodiments, Figure 1 1 is a cross-sectional view of the integrated circuit device 100 taken along the lines XX', Y1-Y1' and Y2-Y2'. Figure 1 , Figure 2A , Figure 2B and Figure 2C, the integrated circuit device 100 may include a substrate 212 (also referred to as a back insulating layer) and a transistor structure TS (also referred to as a transistor) on the substrate 212. A lower surface 211 of the substrate 212 may extend in a first direction X (also referred to as a first horizontal direction) and a second direction Y (also referred to as a second horizontal direction). The first direction X and the second direction Y may be parallel to the lower surface 211 of the substrate 212. In some embodiments, the first direction X may be perpendicular to the second direction Y.

[0016] In some embodiments, the substrate 212 may include or may be (multiple) insulating materials, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride and / or low-k materials. Low-k materials may include, for example, fluorine-doped silicon oxide, organic silicate glass, carbon-doped oxide, porous silicon dioxide, porous organic silicate glass, spin-on organic polymer dielectrics and / or spin-on silicon-based polymer dielectrics. In some other embodiments, the substrate 212 may include or may be (multiple) semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and / or InP. For example, the substrate 212 may be (multiple) insulating layers, a bulk substrate (e.g., a bulk silicon wafer) and / or a semiconductor on insulator (SOI) substrate. The thickness of the substrate 212 in the third direction Z (also referred to as the vertical direction) may be in the range of 50nm to 100nm. In some embodiments, the third direction Z may be perpendicular to the first direction X. The third direction Z may be perpendicular to the lower surface 211 of the substrate 212.

[0017] The substrate 212 may include portions separated from each other by trench isolation layers 232. The trench isolation layers 232 may include insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k materials). The substrate 212 may include an upper portion 215 and a lower portion 217. The upper portion 215 of the substrate 212 may be between the transistor structure TS and the lower portion 217 of the substrate 212. The upper portion 215 and the lower portion 217 of the substrate 212 may include the same (multiple) materials, so the interface therebetween may not be obvious. For ease of illustration, Figure 2A and Figure 2B The dashed line in indicates the interface between the upper portion 215 and the lower portion 217 of the substrate 212 .

[0018] Each transistor structure TS may include a gate electrode 104 and a channel region 202. In some embodiments, each transistor structure TS may include a plurality of channel regions 202 stacked in the third direction Z, and the channel regions 202 may be spaced apart from each other in the third direction Z. Each of the transistor structures TS may also include a gate insulator 204. The channel region 202 may extend through the gate electrode 104 in the first direction X, and the gate insulator 204 may be provided between the gate electrode 104 and the channel region 202. The gate insulator 204 may contact the gate electrode 104 and the channel region 202, and may separate the gate electrode 104 from the channel region 202.

[0019] Each of the transistor structures TS may also include a pair of source / drain regions 102 (e.g., a first source / drain region 102a and a second source / drain region 102b or a third source / drain region 102c and a fourth source / drain region 102d) that may be spaced apart from each other in the first direction X. A gate electrode 104 (e.g., a first gate electrode 104a) may be provided between the pair of source / drain regions 102. The pair of source / drain regions 102 may contact opposite side surfaces of the channel region 202, respectively, as shown in FIG. Figure 2A Opposite side surfaces of the channel region 202 may be spaced apart from each other in the first direction X.

[0020] The channel region 202 may include (multiple) semiconductor materials (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the channel region 202 may be a nanosheet, which may have a thickness in a range of 1 nanometer (nm) to 100 nm in a third direction Z, or may be a nanowire, which may have a circular cross-section with a diameter in a range of 1 nm to 100 nm. Although not shown, in some embodiments, the channel region 202 may be shaped as a fin. When the channel region 202 is a nanosheet or a nanowire, the gate electrode 104 may surround the channel region 202 on four sides. When the channel region 202 has a fin shape, the gate electrode 104 may surround the channel region 202 on two, three, or four sides.

[0021] Each of the source / drain regions 102 (e.g., the first to fourth source / drain regions 102a, 102b, 102c, and 102d) may include a semiconductor layer (e.g., a silicon (Si) layer and / or a silicon germanium (SiGe) layer), and may further include a dopant in the semiconductor layer. In some embodiments, each of the source / drain regions 102 may include a metal layer including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru).

[0022] The gate insulator 204 may include a single layer or multiple layers (eg, a silicon oxide layer and / or a high-k material layer). For example, the high-k material layer may include Al 2 O 3 , HfO 2 、ZrO 2 、HfZrO 4 、TiO 2 Sc 2 O 3 , Y 2 O 3 ,La 2 O 3 、Lu 2 O 3 , Nb 2 O 5 and / or 2 O 5 .

[0023] The integrated circuit device 100 may include a plurality of gate electrodes 104 (e.g., a first gate electrode 104a, a second gate electrode 104b, and a third gate electrode 104c) extending in a second direction Y and spaced apart from each other in a first direction X. As used herein, "element A extends in direction X" (or similar language) may mean that element A extends longitudinally in direction X. Each of the gate electrodes 104 together with a corresponding gate insulator 204 may constitute a gate structure. Each gate electrode 104 may include a single layer or multiple layers. In some embodiments, each gate electrode 104 may include a metal layer containing, for example, W, Al, Cu, Mo, Co, and / or Ru, and may additionally include (multiple) work function layers (e.g., TiN layer, TaN layer, TiAl layer, TiC layer, TiAlC layer, TiAlN layer, and / or WN layer). In some embodiments, each of the gate electrodes 104 may include the same (multiple) materials. (Multiple) work function layers may be provided between the metal layer and the gate insulator 204. In some embodiments, a work function layer can separate the metal layer from the gate insulator 204 .

[0024] In some embodiments, the transistor structure TS may be a three-dimensional (3D) field effect transistor (FET), such as a multi-bridge channel FET (MBCFET). In some embodiments, the transistor structure TS may have a structure different from that shown. For example, the transistor structure TS may be a gate all around FET (GAAFET) or a fin FET (FinFET) including a single channel region.

[0025] An insulating spacer 206 (also referred to as a gate spacer or an internal gate spacer) may be provided between the gate electrode 104 and the source / drain region 102 to separate the gate electrode 104 from the source / drain region 102. The insulating spacer 206 may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k material. The channel region 202 may extend through the insulating spacer 206 to contact the source / drain region 102 (e.g., the first source / drain region 102a and the second source / drain region 102b and / or the third source / drain region 102c and the fourth source / drain region 102d) on opposite sides of the gate electrode 104 (e.g., the first gate electrode 104a) in the first direction X.

[0026] The first interlayer 210 may be provided on the upper surface 213 of the substrate 212. In some embodiments, the first interlayer 210 may extend between the substrate 212 and the transistor structure TS, and may contact the upper surface 213 of the substrate 212 and the transistor structure TS.

[0027] The second interlayer 208 may be provided on the first interlayer 210 and the substrate 212, and the transistor structure TS may be provided in the second interlayer 208. In particular, the source / drain region 102, the gate electrode 104, the channel region 202, and the gate insulator 204 may be provided in the second interlayer 208. Although the second interlayer 208 is shown as a single layer, in some embodiments, the second interlayer 208 may include multiple layers. The lower surface of the second interlayer 208 may contact the upper surface of the trench isolation layer 232. For example, the first interlayer 210 and the second interlayer 208 may each include (multiple) insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k material).

[0028] Source / drain contacts 106 (also referred to as front contacts) may be provided in the second interlayer 208 on the second, third, and fourth source / drain regions 102b, 102c, and 102d, respectively. The source / drain contacts 106 may contact the upper surfaces of the second, third, and fourth source / drain regions 102b, 102c, and 102d, respectively. The source / drain contacts 106 may electrically connect the second, third, and fourth source / drain regions 102b, 102c, and 102d to conductive elements (e.g., conductive lines or conductive via plugs) of a back-end process (BEOL) structure 224 formed by a back-end process (BEOL) portion of device fabrication. The source / drain contacts 106 may include a metal layer containing, for example, W, Al, Cu, Mo, Co, and / or Ru. As used herein, the "lower surface" of an element may refer to a surface facing the substrate 212, and the "upper surface" refers to a surface opposite to its lower surface. In addition, as used herein, the "lower portion" refers to a portion closer to the substrate 212 than the "upper portion" and therefore between its upper portion and the substrate 212.

[0029] The gate contacts 108 may be provided in the second interlayer 208 on the gate electrodes 104. The gate contacts 108 may respectively contact the upper surfaces of the gate electrodes 104. The gate contacts 108 may electrically connect the gate electrodes 104 to conductive elements (e.g., conductive lines or conductive via plugs) of the BEOL structures 224. The gate contacts 108 may include a metal layer including, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0030] In some embodiments, each of the gate electrodes 104 may include portions spaced apart from each other in the second direction Y, and the cutting layer 110 may separate those portions of the gate electrodes 104 from each other. The cutting layer 110 may extend in the first direction X to separate portions of each of the gate electrodes 104 from each other. For example, the first gate electrode 104a may include a first portion between the first source / drain region 102a and the second source / drain region 102b and a second portion between the third source / drain region 102c and the fourth source / drain region 102d, and the cutting layer 110 may be between the first portion and the second portion of the first gate electrode 104a. A portion of the cutting layer 110 may be in the trench isolation layer 232. The cutting layer 110 may include (multiple) insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k material). In some embodiments, the cutting layer 110 may be omitted.

[0031] The BEOL structure 224 may include a BEOL insulating layer, conductive lines (e.g., metal conductive lines) provided in the BEOL insulating layer and stacked in the third direction Z, and conductive via plugs (e.g., metal via plugs), each of which may electrically connect two conductive lines spaced apart from each other in the third direction Z. The BEOL insulating layer may include, for example, silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k material.

[0032] The integrated circuit device 100 may further include a back contact 218 electrically connected to the first source / drain region 102a. The back contact 218 may include a portion in the substrate 212. In some embodiments, the back contact 218 (e.g., the entire back contact 218) may be in the upper portion 215 of the substrate 212. In some embodiments, the back contact 218 may extend in the substrate 212 in a third direction Z. The back contact 218 may be overlapped by the first source / drain region 102a in the third direction Z. As used herein, "element A overlaps element B in direction Z" (or similar language) means that there is at least one line extending in direction Z and intersecting both elements A and B. The back contact 218 may include a metal layer including, for example, W, Al, Cu, Mo, Co and / or Ru.

[0033] A conductive layer 222 may be provided between the back contact 218 and the first source / drain region 102a. The conductive layer 222 may be provided in the first interlayer 210. For example, the lower surface and the upper surface of the conductive layer 222 may be coplanar with the lower surface and the upper surface of the first interlayer 210, respectively. In some embodiments, the conductive layer 222 may include a metal silicide layer (e.g., tungsten silicide, aluminum silicide, or copper silicide) or a metal nitride layer (e.g., titanium nitride, tantalum nitride, or tungsten nitride). The conductive layer 222 may contact the lower surface of the source / drain region 102 and the upper surface of the back contact 218. In some embodiments, the conductive layer 222 may not be provided, and the back contact 218 may directly contact the lower surface of the first source / drain region 102a.

[0034] A conductive plug 220 may be provided between the back contact 218 and a back power distribution network structure (BSPDNS) 230, which will be described below. The conductive plug 220 may contact a lower surface of the back contact 218 and an upper surface of the BSPDNS 230 (e.g., an upper surface of a back power rail 226). The conductive plug 220 may be in the substrate 212 (e.g., in the lower portion 217 of the substrate 212). The conductive plug 220 may include a metal layer including, for example, W, Al, Cu, Mo, Co, and / or Ru. The conductive layer 222, the back contact 218, and the conductive plug 220 may electrically connect the first source / drain region 102a to a conductive element of the BSPDNS 230 (e.g., a back power rail 226). The back contact 218 may be between the first source / drain region 102a and the BSPDNS 230 in the third direction Z. The back contact 218 may be electrically connected to the first source / drain region 102a and the BSPDNS 230.

[0035] In some embodiments, the back contact 218 and the conductive plug 220 may include the same material. For example, the back contact 218 and the conductive plug 220 may have an integrated unitary structure and may be monolithic. The "integrated unitary structure" herein may mean a structure formed by the same process or the same series of processes, wherein there are no structurally or visually separated sub-parts. The conductive layer 222, the back contact 218, and the conductive plug 220 may be collectively referred to as a back contact structure.

[0036] BSPDNS 230 may be provided on the lower surface of the conductive plug 220 and the lower surface of the back contact 218. BSPDNS 230 may contact the lower surface of the conductive plug 220 and the lower surface of the substrate 212 (e.g., the lower surface of the lower portion 217 of the substrate 212). BSPDNS 230 may include a back insulator 228 and a back power rail 226 provided in the back insulator 228. The back power rail 226 may contact the lower surface of the conductive plug 220 and may be electrically connected to the conductive plug 220. The substrate 212 may be between a pair of source / drain regions 102 (e.g., the first source / drain region 102a and the second source / drain region 102b) and the BSPDNS 230.

[0037] The back power rail 226 can be electrically connected to a power source having a predetermined voltage (e.g., a drain voltage or a source voltage). For example, the BSPDNS230 may include a power delivery network. The power delivery network may include a wiring network for delivering a power source (e.g., a drain and / or source voltage) to the back power rail 226. The first source / drain region 102a may be electrically connected to the power source through the conductive layer 222, the back contact 218, the conductive plug 220, and the back power rail 226. The back contact 218 may be electrically connected to the back power rail 226 and the first source / drain region 102a. The back contact 218 may be located between the back power rail 226 and the first source / drain region 102a in the third direction Z. As used herein, the back power rail 226 refers to a conductive element included in the BSPDNS230. For example, the back power rail 226 may be a power rail, a conductive path plug, or a conductive line included in the BSPDNS230. Back side power rail 226 may include a metal layer including, for example, W, Al, Cu, Mo, Co, and / or Ru.

[0038] In some embodiments, each of the source / drain contacts 106 and the gate contact 108 may include a Co layer and / or a W layer, and each of the back contact 218 and the back power rail 226 may include a Cu layer. In some embodiments, a barrier layer may be provided on a surface of each of the source / drain contacts 106, the gate contact 108, the back contact 218, and the back power rail 226. The barrier layer may include, for example, a metal nitride layer(s) (e.g., a TiN layer and / or a TaN layer).

[0039] For ease of explanation, FIG. 2A to FIG. 2C BSPDNS230 is shown to include a back power rail 226 and a back insulator 228, but it should be understood that BSPDNS230 may include one or more conductive layers (e.g., metal layers) stacked in a third direction Z that provide back power delivery to the transistor structure TS. The conductive layers may be included in the insulating layers, respectively, and conductive via plugs (e.g., metal via plugs) may electrically connect the conductive layers to each other in the third direction Z. For example, although the back insulator 228 is shown as a single layer, in some embodiments, the back insulator 228 may include multiple layers stacked on the lower surface 211 of the substrate 212. The conductive layer may include one or more conductive lines (e.g., metal wires). In some embodiments, an intermediate structure may be provided between the substrate 212 and the BSPDNS230, and the substrate 212 may be separated from the BSPDNS230. The BSPDNS 230 may improve the power delivery efficiency in the integrated circuit device 100, reduce the area used for power delivery in the integrated circuit device 100, and / or improve the voltage drop (i.e., IR drop) in the integrated circuit device 100.

[0040] The integrated circuit device 100 may further include a placeholder 216 in the substrate 212 (e.g., in the upper portion 215 of the substrate 212). The second source / drain region 102b, the third source / drain region 102c, and the fourth source / drain region 102d may be respectively on the placeholder 216. For example, the corresponding source / drain regions in the source / drain region 102 electrically connected to the source / drain contact 106 may be respectively on the placeholder 216. The second source / drain region 102b, the third source / drain region 102c, and the fourth source / drain region 102d may overlap with the placeholder 216 in the third direction Z, respectively.

[0041] A conductive layer 222 may be between each of the placeholders 216 and a corresponding one of the second source / drain region 102b, the third source / drain region 102c, and the fourth source / drain region 102d in the first interlayer 210. In some embodiments, the conductive layer 222 may be omitted, and the placeholders 216 may directly contact the second source / drain region 102b, the third source / drain region 102c, and the fourth source / drain region 102d, respectively.

[0042] Still refer to Figure 2A and Figure 2C , the second source / drain region 102b may be on the first placeholder 216a, and the third source / drain region 102c may be on the second placeholder 216b. That is, the second source / drain region 102b may overlap with the first placeholder 216a in the third direction Z, and the third source / drain region 102c may overlap with the second placeholder 216b in the third direction Z. Although not shown, the fourth source / drain region 102d may also overlap with one of the placeholders 216 in the third direction Z. The first placeholder 216a may be adjacent to the back contact 218 in the first direction X. The trench isolation layer 232 may be on the opposite side surfaces of the placeholder 216 in the second direction Y.

[0043] The substrate 212 (e.g., the lower portion 217 of the substrate 212) may be between the placeholder 216 and the BSPDNS 230, and may separate the placeholder 216 from the BSPDNS 230. The thickness of each of the placeholders 216 in the third direction Z may be equal to the thickness of the back contact 218 in the third direction Z. For example, the thickness of the first placeholder 216a in the third direction Z may be equal to the thickness of the back contact 218 in the third direction Z. The upper surface and the lower surface of each of the placeholders 216 may be coplanar with the upper surface and the lower surface of the back contact 218, respectively. For example, the upper surface and the lower surface of the first placeholder 216a may be coplanar with the upper surface and the lower surface of the back contact 218, respectively. The lower surface of the back contact 218 and the corresponding lower surface of the placeholder 216 may be spaced an equal distance from the upper surface 213 of the substrate 212 in the third direction Z. For example, the lower surface of the back contact 218 and the lower surface of the first placeholder 216 a may be spaced apart from the upper surface 213 of the substrate 212 in the third direction Z by an equal distance.

[0044] The placeholder 216 may include a different material than the back contact 218 and / or the substrate 212. The placeholder 216 may include, for example, a semiconductor material (e.g., Si or SiGe) and / or an insulating material (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or a low-k material).

[0045] The integrated circuit device 100 may further include a cavity 214 in the substrate 212 (e.g., in the upper portion 215 of the substrate 212). The cavity 214 may be arranged in the first direction X. Each of the cavities 214 may have a symmetrical circular shape. However, the present disclosure is not limited thereto, and each of the cavities 214 may have an elliptical shape. For example, each of the cavities 214 may include opposite side surfaces (e.g., convex side surfaces) that are curved outward. Each of the cavities 214 may be symmetrical with respect to a center line that passes through its center in the first direction X and extends in the third direction Z, such as Figure 2A In some embodiments, each of the cavities 214 may also be symmetrical with respect to a center line passing through its center in the second direction Y and extending in the third direction Z, as shown in FIG. Figure 2B shown.

[0046] The cavities 214 may be respectively between portions of the substrate 212 overlapped by the source / drain regions 102 in the third direction Z. In other words, the cavities 214 may be respectively overlapped by the channel regions 202 in the third direction Z. The cavities 214 may be respectively overlapped by the gate electrodes 104 in the third direction Z. The respective lower surfaces of the cavities 214 may be spaced apart from the lower surface 211 of the substrate 212 by an equal distance in the third direction Z. It should be understood that the cavities 214 may be, for example, any void or cavity, and may be a gap filled with air (e.g., an air gap), a gap filled with one or more inert gases (e.g., an inert gas gap), a gap defining a vacuum (e.g., a vacuum gap), etc.

[0047] refer to Figure 2A , adjacent cavities in the cavity 214 may be spaced apart from each other in the first direction X, and the first placeholder 216a or the back contact 218 is therebetween. The first cavity 214a may be between the back contact 218 and the first placeholder 216a in the first direction X. The first cavity 214a may be overlapped by the channel region 202 (also referred to as the first channel region) that electrically connects the first source / drain region 102a and the second source / drain region 102b to each other in the third direction Z. The first cavity 214a may be overlapped by the first gate electrode 104a in the third direction Z. The center of the first cavity 214a in the first direction X and the center of the first channel region 202 in the first direction X may be aligned in the third direction Z. The first cavity 214a may be spaced apart from the back contact 218 and the first placeholder 216a by an equal distance in the first direction X. For example, the center of the first cavity 214a in the first direction X may be equidistant from the center of the back contact 218 in the first direction X and the center of the first placeholder 216a in the first direction X. The first cavity 214 a may be spaced apart from the cavity 214 adjacent thereto in the first direction X by an equal distance. For example, the first gate electrode 104 a , the first and second source / drain regions 102 a and 102 b , the first channel region 202 , and the gate insulator 204 separating the first channel region 202 from the first gate electrode 104 a may constitute a first transistor structure TS.

[0048] refer to Figure 1 and Figure 2B, the cavities 214 may also be spaced apart from each other in the second direction Y and the trench isolation layer 232 therebetween. For example, the first cavity 214a may be spaced apart from the second cavity 214b in the second direction Y and the trench isolation layer 232 therebetween. The cutting layer 110 may also be between the first cavity 214a and the second cavity 214b in the second direction Y. The center of the first cavity 214a in the second direction Y may be aligned with the center of the first channel region 202 in the second direction Y in the third direction Z. The second cavity 214b may be overlapped by the channel region 202 (also referred to as the second channel region) that electrically connects the third source / drain region 102c and the fourth source / drain region 102d to each other. For example, the first gate electrode 104a, the third source / drain region 102c and the fourth source / drain region 102d, the second channel region 202, and the gate insulator 204 that separates the second channel region 202 from the first gate electrode 104a may constitute a second transistor structure TS. The second transistor structure TS may be spaced apart from the first transistor structure TS in the second direction Y. The cutting layer 110 may be between the first transistor structure TS and the second transistor structure TS.

[0049] Since the back contact 218 and the first placeholder 216a are close to each other, parasitic capacitance may exist between the back contact 218 and the first placeholder 216a, which may reduce the performance of the integrated circuit device 100. In some embodiments, the substrate 212 may include an insulating material, and the first placeholder 216a may include a semiconductor material, which may further increase the parasitic capacitance between the back contact 218 and the first placeholder 216a. For example, when conductive or semiconductive electrical components are close to each other and have different potentials, parasitic capacitance may exist between the electrical components. The first cavity 214a between the back contact 218 and the first placeholder 216a in the substrate 212 can reduce or eliminate the parasitic capacitance. Therefore, the resistance-capacitance (RC) delay can be reduced, and the performance of the integrated circuit device 100 can be improved.

[0050] Figure 3 is a flow chart of a method of forming an integrated circuit device (eg, integrated circuit device 100 ) according to some embodiments. Figures 4 to 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B and Fig. 11C is a cross-sectional view illustrating a method of forming an integrated circuit device (eg, integrated circuit device 100 ) according to some embodiments. Figures 4 to 9 , Fig. 10A and Fig.11A is corresponding to Figure 1 The cross-sectional view of the line X-X', Fig. 10B and Fig. 11Bis corresponding to Figure 1 A cross-sectional view of the line Y1-Y1', and Fig. 10C and Fig. 11C is corresponding to Figure 1 Cross-sectional view along line Y2-Y2'.

[0051] refer to Figure 4 , a first interlayer 210 may be formed on a preliminary substrate 410. A preliminary transistor structure PTS may be formed on the first interlayer 210 and the preliminary substrate 410. Each of the preliminary transistor structures PTS may include a channel region 202 and a sacrificial gate layer 402. In some embodiments, each of the preliminary transistor structures PTS may include a plurality of channel regions 202 and a plurality of portions of the sacrificial gate layer 402 alternately stacked with the channel regions 202, such as Figure 4 As shown, insulating spacers 206 may be formed on side surfaces of the sacrificial gate layer 402 .

[0052] The preliminary substrate 410 may include one or more semiconductor materials, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC and / or InP, or may include an insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride and / or a low-k material. In some embodiments, the preliminary substrate 410 may be a bulk substrate (e.g., a bulk silicon substrate) or a semiconductor on insulator (SOI) substrate. For example, the preliminary substrate 410 may be a silicon wafer or may be an insulating layer. The preliminary substrate 410 may include an etch stop layer 412, and the etch stop layer 412 may include, for example, SiN, SiBCN, SiOCN, SiBN, SiCN, SiO and / or SiON.

[0053] The sacrificial gate layer 402 may include a material having an etching selectivity relative to the channel region 202. The sacrificial gate layer 402 may include, for example, a semiconductor material(s) (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some embodiments, the sacrificial gate layer 402 may include a SiGe layer.

[0054] In some embodiments, the gate liner 404 may be formed on the side surface of the insulating spacer 206. The gate liner 404 may include, for example, a layer containing nitrogen (e.g., SiN, SiON, SiBCN, SiOCN, SiBN, and / or SiCN), and may have a thickness in the range of, for example, 1 nm to 5 nm (e.g., about 1 nm or 2 nm).

[0055] The upper surface of the preliminary substrate 410 may be etched to form a first opening 406 and a second opening 408 in the preliminary substrate 410. The first opening 406 and the second opening 408 may be formed by a self-aligned etching process using the preliminary transistor structure PTS, the insulating spacer 206, and the gate liner 404 as an etching mask. For example, a portion of the preliminary substrate 410 where holes for source / drain regions to be formed later overlap in the third direction Z may be etched to form the first opening 406 and the second opening 408 in the preliminary substrate 410. In some embodiments, the first opening 406 and the second opening 408 may be formed in the first interlayer 210 and the preliminary substrate 410. The first opening 406 and the second opening 408 may not completely extend through the preliminary substrate 410 in the third direction Z. For example, the lower surfaces of the first opening 406 and the second opening 408 may be spaced apart from the etching stop layer 412 in the third direction Z, and a portion of the preliminary substrate 410 is between the lower surfaces of the first opening 406 and the second opening 408 and the etching stop layer 412.

[0056] During the self-aligned etching process, a mask layer may be formed on the preliminary transistor structure PTS. The mask layer may include, for example, an inorganic material (e.g., SiN, SiBCN, SiOCN, SiBN, SiCN, SiON, and / or a spin-on glass material). The self-aligned etching process may include a dry etching process and / or a wet etching process.

[0057] refer to Figure 3 and Figure 5 , a first preliminary placeholder 502 and a second preliminary placeholder 504 may be formed in the first opening 406 and the second opening 408 of the preliminary substrate 410, respectively (block 302). In some embodiments, the first preliminary placeholder 502 and the second preliminary placeholder 504 may be formed by performing an epitaxial growth process using the preliminary substrate 410 as a seed layer. Specifically, the first preliminary placeholder 502 and the second preliminary placeholder 504 may be grown from the preliminary substrate 410 by the epitaxial growth process. In some embodiments, the first preliminary placeholder 502 and the second preliminary placeholder 504 may be formed by performing a deposition process and then etching the first preliminary placeholder 502 and the second preliminary placeholder 504 to the upper surface of the preliminary substrate 410. In some embodiments, the first opening 406 and the second opening 408 may not be formed, and the first preliminary placeholder 502 and the second preliminary placeholder 504 may be formed by adding impurities to the preliminary substrate 410 using a doping process.

[0058] The first preliminary placeholder 502 and the second preliminary placeholder 504 may include, for example, a semiconductor material and / or an insulating material (e.g., SiGe, SiN, or SiBCN). In some embodiments, the first preliminary placeholder 502 and the second preliminary placeholder 504 may include a SiGe layer including about 25 at% germanium (e.g., from 15 at% to 25 at%). When the source / drain region to be formed later includes a SiGe layer, the germanium concentration of the source / drain region may be higher than the germanium concentration of the SiGe layer of the first preliminary placeholder 502 and the second preliminary placeholder 504. For example, the germanium concentration of the source / drain region may be about 55 at% (e.g., from 40 at% to 70 at%). The first preliminary placeholder 502 and the second preliminary placeholder 504 may be self-aligned with the preliminary transistor structure PTS. The upper surfaces of the first preliminary placeholder 502 and the second preliminary placeholder 504 may be coplanar with the upper surface of the preliminary substrate 410. The thickness of the first preliminary placeholder 502 in the third direction Z may be equal to the thickness of the second preliminary placeholder 504 in the third direction Z. Lower surfaces of the first and second preliminary placeholders 502 and 504 may be spaced an equal distance in the third direction Z from the upper surface of the preliminary substrate 410 .

[0059] refer to Figure 3 and Figure 6 , a first source / drain region 102a and a second source / drain region 102b may be formed on the preliminary substrate 410 (block 304). Although not specifically shown, a third source / drain region 102c and a fourth source / drain region 102d may also be formed on the preliminary substrate 410. The source / drain region 102 may be formed by performing an epitaxial growth process using the channel region 202 as a seed layer. Specifically, the source / drain region 102 may be grown from opposite side surfaces of the channel region 202 by an epitaxial growth process. Before forming the source / drain region 102, a conductive layer 222 may be formed in the first interlayer 210 on the first preliminary placeholder 502 and the second preliminary placeholder 504.

[0060] The gate liner 404 may be removed, and the sacrificial gate layer 402 may be removed and replaced with the gate electrode 104 and the gate insulator 204. Thus, a transistor structure TS including a pair of source / drain regions 102, a gate electrode 104, a channel region 202, and a gate insulator 204 may be formed.

[0061] A second interlayer 208, source / drain contacts 106, and gate contact 108 may also be formed. A BEOL structure 224 may be formed on the second interlayer 208, source / drain contacts 106, and gate contact 108.

[0062] refer to Figure 7, a portion of the preliminary substrate 410 below the etch stop layer 412 may be removed. In some embodiments, Figure 6 The structure shown in FIG. 4 may be turned over (i.e., flipped), and the portion of the preliminary substrate 410 may be removed. For example, (multiple) processes (e.g., a grinding process, a wet etching process, a dry etching process, and / or a chemical mechanical polishing (CMP) process) may be performed to remove the portion of the preliminary substrate 410 until the etch stop layer 412 is exposed. Although not shown, the structure shown in FIG. 4 may be turned over (i.e., flipped), and the portion of the preliminary substrate 410 may be removed. Figure 6 4 and bonding the carrier wafer to the BEOL structure 224 before removing the portion of the preliminary substrate 410 .

[0063] refer to Figure 3 , Figure 8 and Fig. 9 , the preliminary substrate 410 may be replaced with the substrate 212 (block 306). Figure 8 , the preliminary substrate 410 and the etch stop layer 412 may be removed. For example, (multiple) processes (e.g., a grinding process, a wet etching process, a dry etching process, and / or a chemical mechanical polishing (CMP) process) may be performed to remove the preliminary substrate 410 and the etch stop layer 412. The first interlayer 210 and the first preliminary placeholder 502 and the second preliminary placeholder 504 may be exposed by removing the preliminary substrate 410. The first preliminary placeholder 502 and the second preliminary placeholder 504 may include a material different from the preliminary substrate 410, and thus may have an etching selectivity relative to the preliminary substrate 410. Therefore, the preliminary substrate 410 and the etch stop layer 412 may be selectively removed without removing the first preliminary placeholder 502 and the second preliminary placeholder 504. In some embodiments, the first preliminary placeholder 502 and the second preliminary placeholder 504 may include SiGe, and the preliminary substrate 410 may include Si. However, the present disclosure is not limited thereto, and the first and second preliminary placeholders 502 and 504 and the preliminary substrate 410 may include other different materials having etching selectivity with respect to each other.

[0064] refer to Fig. 9 , a substrate 212 may be formed on the first preliminary placeholder 502 and the second preliminary placeholder 504 and the first interlayer 210. The substrate 212 may be formed by performing a non-conformal deposition process on the first preliminary placeholder 502 and the second preliminary placeholder 504. The non-conformal deposition process may include forming the substrate 212 to include a cavity 214 therein. For example, the non-conformal deposition process may include non-conformally depositing the substrate 212 so that the cavity 214 is formed therein. In other words, the cavity 214 may be formed while performing the non-conformal deposition process to form the substrate 212.

[0065] Adjacent cavities among the cavities 214 may be spaced apart from each other in the first direction X, with one of the first preliminary placeholder 502 or the second preliminary placeholder 504 therebetween. The first cavity 214a may be between the first preliminary placeholder 502 and the second preliminary placeholder 504. The first cavity 214a may be overlapped by the first channel region 202 that electrically connects the first source / drain region 102a and the second source / drain region 102b to each other in the third direction Z. The first cavity 214a may be overlapped by the first gate electrode 104a in the third direction Z. The first cavity 214a may be spaced apart from the first preliminary placeholder 502 and the second preliminary placeholder 504 by an equal distance in the first direction X. For example, the center of the first cavity 214a in the first direction X may be equidistant from the respective centers of the first preliminary placeholder 502 and the second preliminary placeholder 504 in the first direction X.

[0066] The cavity 214 may be formed to have a symmetrical circular shape during the non-conformal deposition process. However, the present disclosure is not limited thereto, and each of the cavities 214 may have an elliptical shape. For example, each of the cavities 214 may be symmetrical with respect to a center line passing through its center in the first direction X and extending in the third direction Z. Each of the cavities 214 may include opposite side surfaces (e.g., convex side surfaces) that are curved outward.

[0067] Forming the cavity 214 during the non-conformal deposition process can reduce the cost and / or the number of manufacturing steps for forming the cavity 214. The result of the non-conformal deposition process can be that the cavity 214 has a symmetrical circular shape. The shape of the cavity 214 and / or the position of the cavity 214 (e.g., the spacing of the cavity 214 relative to the first preliminary placeholder 502 and the second preliminary placeholder 504) can help further reduce or eliminate the parasitic capacitance between the placeholder 216 (e.g., the first placeholder 216a) and the back contact 218 to be described later.

[0068] refer to Fig. 10A , Fig. 10B and Fig. 10C , the lower portion of the substrate 212 and the lower portions of the first preliminary placeholder 502 and the second preliminary placeholder 504 may be removed. As a result, the upper portion 215 of the substrate 212 and the first placeholder 216a may be formed. The lower portion of the substrate 212 and the lower portions of the first preliminary placeholder 502 and the second preliminary placeholder 504 may be removed by (multiple) processes (e.g., a grinding process, a wet etching process, a dry etching process, and / or a chemical mechanical polishing (CMP) process). The (multiple) processes may remove the lower portion of the substrate 212 and the lower portions of the first preliminary placeholder 502 and the second preliminary placeholder 504 until the trench isolation layer 232 is exposed. That is, the trench isolation layer 232 may serve as an etching stop for the (multiple) processes for removing the lower portion of the substrate 212 and the lower portions of the first preliminary placeholder 502 and the second preliminary placeholder 504.

[0069] refer to Figure 3 , Fig. 10A , Fig. 10B and Fig. 10C , an opening 1010 may be formed in the substrate 212 by removing the first preliminary placeholder 502 (block 308). The first preliminary placeholder 502 may be removed after its lower portion is removed. For example, an etching process (e.g., a wet etching process and / or a dry etching process) may be used to remove the first preliminary placeholder 502. The substrate 212 and the trench isolation layer 232 may include a material different from the first preliminary placeholder 502, and thus may have an etching selectivity relative to the first preliminary placeholder 502. Therefore, the first preliminary placeholder 502 may be selectively removed without removing the substrate 212 and the trench isolation layer 232. In some embodiments, the substrate 212 and the trench isolation layer 232 may include (multiple) insulating materials (e.g., silicon oxide, silicon oxynitride, silicon nitride, silicon carbon nitride, silicon boron nitride, and / or low-k material), and the first preliminary placeholder 502 may include SiGe. However, the present disclosure is not limited thereto, and the first preliminary placeholder 502 and the substrate 212 and the trench isolation layer 232 may include other different materials having an etching selectivity with respect to each other.

[0070] refer to Figure 3 , Fig.11A , Fig. 11B and Fig. 11C , a back contact 218 may be formed in the opening 1010 (block 310). The first cavity 214a may be between the back contact 218 and the first placeholder 216a in the first direction X. The thickness of the back contact 218 in the third direction Z may be equal to the thickness of the first placeholder 216a in the third direction Z. The conductive plug 220 may be formed on a lower surface of the back contact 218 and may contact the lower surface of the back contact 218. The lower portion 217 of the substrate 212 may be formed by a deposition process. The lower portion 217 of the substrate 212 may include the same (multiple) materials as the upper portion 215 of the substrate 212. The lower portion 217 of the substrate 212 may be formed on a lower surface of the placeholder 216 (e.g., a lower surface of the first placeholder 216a and the second placeholder 216b).

[0071] Return to reference Figure 2A , Figure 2B and Figure 2C as well as Figure 3, a BSPDNS 230 may be formed on the back contact 218 (block 312). The back contact 218 may be electrically connected to the BSPDNS 230 and the first source / drain region 102a. The back contact 218 may be between the BSPDNS 230 and the first source / drain region 102a in the third direction Z. The BSPDNS 230 may contact the lower surface of the conductive plug 220 and may be electrically connected to the conductive plug 220. The BSPDNS 230 may include a back insulator 228 and a back power rail 226 provided in the back insulator 228. The BSPDNS 230 may include a power delivery network for delivering a power source (e.g., a drain and / or source voltage) to the back power rail 226. The first source / drain region 102a may be electrically connected to a power source through the conductive layer 222, the back contact 218, the conductive plug 220, and the back power rail 226.

[0072] By forming the first cavity 214a in the substrate 212 between the back contact 218 and the first placeholder 216a, parasitic capacitance between the back contact 218 and the first placeholder 216a can be reduced or eliminated. Therefore, resistance-capacitance (RC) delay can be reduced and the performance of the integrated circuit device 100 can be improved.

[0073] Fig.12 is a layout diagram of an integrated circuit device 1200 according to some embodiments. Fig.13A , Fig. 13B and Fig. 13C According to some embodiments, Fig.12 1 is a cross-sectional view of the integrated circuit device 1200 taken along lines XX′, Y1 -Y1′, and Y2 -Y2′.

[0074] refer to Fig.12 , Fig.13A , Fig. 13B and Fig. 13C , the integrated circuit device 1200 may be similar to the reference Figure 1 , Figure 2A , Figure 2B and Figure 2C1 and 12. The integrated circuit device 1200 is described in detail, and thus repeated descriptions of similar elements will be omitted. Unlike the integrated circuit device 100, the integrated circuit device 1200 may include back contacts 218 electrically connected to the second source / drain region 102b, the third source / drain region 102c, and the fourth source / drain region 102d, respectively, in addition to the first source / drain region 102a. That is, the second source / drain region 102b, the third source / drain region 102c, and the fourth source / drain region 102d may be electrically connected to the back contacts 218, respectively, and may not be electrically connected to the source / drain contact 106. The integrated circuit device 1200 may not include the placeholder 216. The back contacts 218 may be electrically connected to the first to fourth source / drain regions 102a, 102b, 102c, and 102d, respectively, and the BSPDNS 230 (e.g., the back power rail 226). The back insulator 228 may provide insulation between power (eg, source voltage and / or drain voltage) delivered to a pair of source / drain regions 102 (eg, first source / drain region 102a and second source / drain region 102b) respectively through the back power rail 226 .

[0075] The first cavity 214a may be between the back contacts 218 electrically connected to the first source / drain region 102a and the second source / drain region 102b, respectively, in the first direction X. The center of the first cavity 214a in the first direction X may be equidistant from the center of the back contact 218 electrically connected to the first source / drain region 102a and the center of the back contact 218 electrically connected to the second source / drain region 102b in the first direction X. In other words, the first cavity 214a may be equally spaced apart from the back contact 218 electrically connected to the first source / drain region 102a and the back contact 218 electrically connected to the second source / drain region 102b in the first direction X.

[0076] It should be understood that the integrated circuit device 1200 may be implemented similarly to the reference Figures 4 to 9 , Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B and Fig. 11C For example, the back contact 218 of the integrated circuit device 1200 electrically connected to the second source / drain region 102b can be formed in the same manner as in the reference Fig. 10A , Fig. 10B , Fig. 10C , Fig.11A , Fig. 11B and Fig. 11CIn particular, the backside contact 218 of the integrated circuit device 1200 electrically connected to the second source / drain region 102 b can be formed by removing the second preliminary placeholder 504 to form an opening in the substrate 212 and forming the backside contact 218 in the opening.

[0077] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. On the contrary, these example embodiments are provided to make the present disclosure thorough and complete, and to convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0078] Example embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of idealized embodiments and intermediate structures of example embodiments. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, the embodiments herein should not be construed as limited to the specific shapes shown herein, but may include shape deviations, for example, caused by manufacturing. Although an element is shown as a single layer in the drawings, the element may include multiple layers.

[0079] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0080] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or groups thereof.

[0081] It should be understood that when an element is referred to as being "coupled," "connected," or "responsive to" another element or "on another element," it may be directly coupled, connected, or responsive to another element or on another element, or there may be intervening elements. Conversely, when an element is referred to as being "directly coupled," "directly connected," or "directly responsive to" another element or "directly on" another element, there are no intervening elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (for example, when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0082] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teaching of this embodiment, the first element may be referred to as the second element.

[0083] For ease of description, spatially relative terms, such as "below", "below", "lower", "above", "upper", etc., may be used herein to describe the relationship between one element or feature as shown in the figure and another one or more elements or features. It should be understood that in addition to the orientation shown in the figure, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "below" or "below" other elements or features will be oriented as "above" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein can be interpreted accordingly.

[0084] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It should be understood that literally describing and illustrating every combination and sub-combination of these embodiments would be overly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and sub-combinations of the embodiments described herein and the manner and process of making and using them, and should support claims to any such combination or sub-combination.

[0085] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope is to be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. An integrated circuit device, include: a transistor including a first source / drain region and a second source / drain region spaced apart from each other in a horizontal direction; Backside power distribution network structure (BSPDNS); a substrate, between the first source / drain region and the second source / drain region and the back power distribution network structure; a back contact in said substrate and overlapped by said first source / drain region; a placeholder in the substrate and overlapped by the second source / drain region; as well as A cavity is provided in the substrate between the back contact and the placeholder.

2. The integrated circuit device of claim 1 , wherein the transistor further comprises a channel region between the first source / drain region and the second source / drain region, and The channel region overlaps the cavity. 3 . The integrated circuit device according to claim 2 , wherein a center of the channel region in the horizontal direction and a center of the cavity in the horizontal direction are aligned in a vertical direction. 4 . The integrated circuit device of claim 1 , wherein a center of the cavity in the horizontal direction is equidistant from a center of the back contact in the horizontal direction and a center of the placeholder in the horizontal direction. 5 . The integrated circuit device according to claim 1 , wherein the cavity is symmetrical with respect to a center line passing through a center thereof in the horizontal direction and extending in a vertical direction. 6 . The integrated circuit device of claim 1 , wherein a thickness of the backside contact in a vertical direction is equal to a thickness of the placeholder in the vertical direction. 7 . The integrated circuit device of claim 1 , wherein a lower surface of the backside contact and a lower surface of the placeholder are spaced an equal distance apart from an upper surface of the substrate in a vertical direction.

8. The integrated circuit device according to claim 1, further comprising: include: an insulating layer on the substrate, wherein the first source / drain region and the second source / drain region are in the insulating layer; as well as A source / drain contact is in the insulating layer and electrically connected to the second source / drain region.

9. The integrated circuit device of claim 1, wherein the placeholder comprises a different material than the backside contact.

10. The integrated circuit device of claim 1, wherein the back side contact is electrically connected to a conductive element of the back side power distribution network structure and the first source / drain region.

11. The integrated circuit device of claim 1, wherein the cavity comprises opposite side surfaces that are curved outwardly.

12. The integrated circuit device of claim 1, wherein the transistor is a first transistor including a first channel region, the horizontal direction is a first horizontal direction, and the cavity is a first cavity, The first channel region overlaps the first cavity, and The integrated circuit device further include: a second transistor including a second channel region, wherein the second transistor is spaced apart from the first transistor in a second horizontal direction perpendicular to the first horizontal direction; as well as A second cavity is in the substrate and spaced apart from the first cavity, wherein the second channel region overlaps the second cavity.

13. An integrated circuit device, include: A transistor including a channel region and a source / drain region contacting a side surface of the channel region; Backside power distribution network structure (BSPDNS); a substrate between the source / drain regions and the backside power distribution network structure; a back contact in the substrate and between the source / drain regions and the back power distribution network structure; as well as A cavity is in the substrate and overlapped by the channel region.

14. The integrated circuit device according to claim 13, wherein the side surface of the channel region is one of opposite side surfaces of the channel region spaced apart from each other in a horizontal direction, and The cavity is symmetrical with respect to a center line passing through its center in the horizontal direction and extending in the vertical direction.

15. The integrated circuit device according to claim 13, wherein the side surface of the channel region is a first side surface, the channel region further includes a second side surface opposite to the first side surface, and the first side surface and the second side surface are spaced apart from each other in a horizontal direction, The source / drain region is a first source / drain region contacting the first side surface of the channel region, and the transistor further includes a second source / drain region contacting the second side surface of the channel region, The integrated circuit device further includes a placeholder in the substrate and overlapped by the second source / drain region, and The cavity is between the back contact and the placeholder.

16. The integrated circuit device according to claim 13, wherein the side surface of the channel region is a first side surface, the channel region further includes a second side surface opposite to the first side surface, and the first side surface and the second side surface are spaced apart from each other in a horizontal direction, The transistor further includes a second source / drain region contacting the second side surface of the channel region, The integrated circuit device further includes a placeholder in the substrate and overlapped by the second source / drain region, and The center of the cavity in the horizontal direction is equidistant from the center of the back contact in the horizontal direction and the center of the placeholder in the horizontal direction.

17. A method of forming an integrated circuit device, the method include: forming a first source / drain region and a second source / drain region on a preliminary substrate and forming a first preliminary placeholder and a second preliminary placeholder in the preliminary substrate, wherein the first source / drain region and the second source / drain region overlap the first preliminary placeholder and the second preliminary placeholder, respectively; replacing the preliminary substrate with a substrate, wherein the substrate includes a cavity between the first preliminary placeholder and the second preliminary placeholder; forming an opening in the substrate by removing the first preliminary placeholder; forming a back contact in the opening; as well as A back side power distribution network structure (BSPDNS) is formed on the back side contact, wherein the back side contact is electrically connected to the back side power distribution network structure and the first source / drain region. 18 . The method of claim 17 , wherein replacing the preliminary substrate with the substrate comprises performing a non-conformal deposition process on the first preliminary placeholder and the second preliminary placeholder, and forming the cavity while performing the non-conformal deposition process.

19. The method according to claim 17, wherein the first source / drain region and the second source / drain region are spaced apart from each other in a horizontal direction, and The cavity is symmetrical with respect to a center line passing through its center in the horizontal direction and extending in the vertical direction. 20 . The method of claim 17 , wherein the first preliminary placeholder and the second preliminary placeholder include a material different from the substrate.

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