Flow table offloading system, method, device and cluster

Abstract

The present application provides a flow table unloading system, method, device and cluster. The system includes: a host, which is used to unload the tunnel encapsulation table to the unloading hardware; the unloading hardware includes multiple storage libraries, each storage library includes one or more storage units, the storage unit is used to store the tunnel encapsulation table, the first storage library is used to store the first tunnel encapsulation table, the second storage library is used to store the second tunnel encapsulation table, the second tunnel encapsulation table is copied according to the first tunnel encapsulation table, and is used to select, when receiving the first original message, read the first tunnel encapsulation table from the first storage library, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, or select to read the second tunnel encapsulation table from the second storage library, encapsulate the first original message according to the second tunnel encapsulation table to obtain the second tunnel message. The above scheme can effectively improve the processing efficiency of the original message.

Description

Technical Field

[0001] The present application relates to the field of data communications, and in particular to a flow table offloading system, method, device, and cluster. Background Art

[0002] With the development of cloud computing networks, the amount of data that needs to be forwarded is increasing. To reduce the burden on the host, data forwarding can be offloaded to the offload hardware. After data forwarding is offloaded to the offload hardware, the data packets are directly forwarded according to the flow table entries stored in the offload hardware without the host's involvement, thereby effectively saving the host's resources. When a large number of data packets need to be processed quickly in the network, the ability to quickly and accurately read the flow table entries to determine how the data packets are processed is key to reducing network pressure. If the flow table entry reading efficiency is low, it will cause delays and packet loss during the data packet processing process, affecting the network's real-time performance, throughput, and overall performance, and may even cause network congestion and performance bottlenecks. Summary of the Invention

[0003] The present application provides a flow table unloading system, method, device and cluster, which can effectively improve the processing efficiency of original messages.

[0004] In a first aspect, a flow table offloading system is provided, comprising:

[0005] Host, used to offload the tunnel encapsulation table to the offload hardware;

[0006] The offloading hardware includes multiple storage libraries, each storage library includes one or more storage units, and the storage units are used to store tunnel encapsulation tables, wherein the first storage library is used to store the first tunnel encapsulation table, and the second storage library is used to store the second tunnel encapsulation table, and the second tunnel encapsulation table is copied according to the first tunnel encapsulation table. The hardware is used to, when receiving a first original message, select to read the first tunnel encapsulation table from the first storage library, encapsulate the first original message according to the first tunnel encapsulation table to obtain a first tunnel message, or select to read the second tunnel encapsulation table from the second storage library, and encapsulate the first original message according to the second tunnel encapsulation table to obtain a second tunnel message.

[0007] In some possible designs, the unloading hardware is used to select to read the first tunnel encapsulation table from the first storage repository, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, and at the same time select to read the second tunnel encapsulation table from the second storage repository, encapsulate the second original message according to the second tunnel encapsulation table to obtain the second tunnel message.

[0008] In the above solution, the same tunnel encapsulation table can be set in different storage repositories, and the tunnel encapsulation tables in different storage repositories can be read at the same time. If different original messages use the same tunnel encapsulation table, the tunnel encapsulation tables in different storage repositories can be used respectively, thereby improving processing efficiency.

[0009] In some possible designs, the first storage repository is used to store a hash table, the hash table including the first matching item and the first tunnel encapsulation table, and the second storage repository is used to store a result table, the result table including the second tunnel table;

[0010] The unloading hardware is used to select to read the first tunnel encapsulation table from the first storage library when the first original message received matches the first matching item, and encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, or select to read the second tunnel encapsulation table from the second storage library, and encapsulate the first original message according to the second tunnel encapsulation table to obtain the second tunnel message.

[0011] In some possible designs, the host is further used to copy the first tunnel encapsulation table to obtain a second tunnel encapsulation table, and send the first tunnel encapsulation table and the second tunnel encapsulation table to the offloading hardware.

[0012] In some possible designs, the host is further configured to send the first tunnel encapsulation table to the offload hardware;

[0013] The offloading hardware is further configured to copy the first tunnel encapsulation table to obtain a second tunnel encapsulation table.

[0014] In a second aspect, a flow table unloading method is provided, comprising:

[0015] Offload the tunnel encapsulation table to the offload hardware via the host;

[0016] Multiple storage libraries are provided through the offloading hardware, each storage library includes one or more storage units, and the storage units are used to store tunnel encapsulation tables, wherein the first storage library is used to store the first tunnel encapsulation table, and the second storage library is used to store the second tunnel encapsulation table, and the second tunnel encapsulation table is copied according to the first tunnel encapsulation table. When the first original message is received, the first tunnel encapsulation table is selected to be read from the first storage library, and the first original message is encapsulated according to the first tunnel encapsulation table to obtain the first tunnel message, or the second tunnel encapsulation table is selected to be read from the second storage library, and the first original message is encapsulated according to the second tunnel encapsulation table to obtain the second tunnel message.

[0017] In some possible designs, the offloading hardware selects to read the first tunnel encapsulation table from the first storage repository, encapsulates the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, and at the same time selects to read the second tunnel encapsulation table from the second storage repository, encapsulates the second original message according to the second tunnel encapsulation table to obtain the second tunnel message.

[0018] In some possible designs, the first storage repository is used to store a hash table, the hash table including the first matching item and the first tunnel encapsulation table, and the second storage repository is used to store a result table, the result table including the second tunnel table;

[0019] When the unloading hardware receives a first original message that matches the first matching item, it chooses to read the first tunnel encapsulation table from the first storage library, encapsulates the first original message according to the first tunnel encapsulation table to obtain a first tunnel message, or chooses to read the second tunnel encapsulation table from the second storage library, encapsulates the first original message according to the second tunnel encapsulation table to obtain a second tunnel message.

[0020] In a third aspect, a computing device is provided, comprising a flow table offloading system and a storage unit, wherein the flow table offloading system and the storage unit are capable of communicating with each other, and the flow table offloading system is a system as described in any one of the first aspects.

[0021] In a fourth aspect, a computing device cluster is provided, comprising a flow table offloading system and a storage unit, wherein the flow table offloading system and the storage unit are capable of communicating with each other, and the flow table offloading system is a system as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the background technology, the drawings required for use in the embodiments of the present invention or the background technology will be described below.

[0023] Figure 1 This is a structural diagram of a flow table unloading system provided by this application;

[0024] Figure 2 This is a schematic diagram of the structure of a memory provided by this application;

[0025] Figure 3 This is a schematic diagram of the structure of a random access memory provided by this application;

[0026] Figure 4 This is a structural diagram of a host provided by this application;

[0027] Figure 5 This is a structural diagram of a computing device provided by this application. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention in conjunction with the accompanying drawings. The terms used in the embodiments of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0029] See also Figure 1 , Figure 1 This is a structural diagram of a flow table unloading system provided by this application. Figure 1 As shown, the flow table offloading system includes offloading hardware 110 and a host 120 .

[0030] Offload hardware 110 can be memory. Memory uses double data rate (DDR) for data transmission. DDR is a synchronous dynamic random access memory (SDRAM) technology, with versions including DDR1, DDR2, DDR3, DDR4, and DDR5. DDR's primary feature is its high data transmission rate, which is achieved by transmitting data on both the rising and falling edges of each clock cycle.

[0031] Memory is typically used to store various running software in the operating system, input and output data, and information exchanged with external memory. To improve processor access speed, memory must have a high access speed. In traditional computer system architectures, dynamic random access memory (DRAM) is commonly used as memory. The processor can access memory at high speed through the memory controller, performing read and write operations on any storage location in memory.

[0032] like Figure 2 As shown, the memory may include one or more Dual-Inline-Memory-Modules (DIMMs) 10 . Figure 2 The diagram below uses two DIMMs 10 as an example. Generally, a DIMM can be considered as a memory stick entity. A memory stick has two sides. High-end memory sticks have memory chips on both sides. We call each side a Rank, which means a memory stick can have Rank 0 and Rank 1. Figure 2 As shown, a DIMM 10 may include one or more Ranks 111 . Each Rank 111 may include multiple Random Access Memory (RAM) 112 .

[0033] Data is stored in the memory, and data is stored in the storage cells in the random access memory 112. A storage cell refers to the smallest storage unit (cell) used to store data. Typically, a storage cell can store 1 bit of data. Of course, some storage cells can also implement multi-value storage. When the random access memory is DRAM, the storage cells in the DRAM (also called DRAM cells) are arranged and distributed in a matrix, which we call a memory bank or DRAM bank. In this way, the storage cells in a memory chip can be logically divided into multiple banks, and each bank can be regarded as a storage array composed of multiple storage cells. Each memory cell in the bank is identified by its row address and column address. The memory controller can locate any memory cell in the bank through the corresponding row and column decoders. The bank can also be simply referred to as a bank.

[0034] like Figure 3 As shown, a random access memory (RAM) comprising eight memory banks is used as an example. The RAM may include control and refresh circuitry, multiple memory banks (memory banks) 1121, a row address buffer, a column address buffer, a row decoder, and a column decoder. The control and refresh circuitry is used to control the refresh operation of the memory cells. Random access memory (e.g., DRAM) uses the amount of charge stored in capacitors to represent data 0 and 1 and is a volatile memory. Due to leakage in capacitors, they can only retain charge for a very short period of time. This leakage in capacitors causes charge drift, which can lead to errors in the stored data. Therefore, to store data, the control and refresh circuitry needs to automatically perform refresh operations to refresh and charge the memory cells storing data to prevent data loss.

[0035] During memory access, upon receiving a memory access request, the memory controller generates address and control signals based on the received memory access request and sends them to the DIMM to access the memory. Address signals may include row and column address signals, while control signals may include chip select (CS), write enable (WE), column access strobe (CAS), and row access strobe (RAS). These signals are received by the control and refresh circuitry. The row address signal is cached in a row address buffer, the column address signal is cached in a column address buffer, and the control signal is passed to the memory bank corresponding to the row address specified by the address signal.

[0036] The row address buffer is used to buffer row address signals sent by the memory controller. The column address buffer is used to buffer column address signals sent by the memory controller. The row decoder is connected to the row address buffer and multiple memory banks 1121, respectively, while the column decoder is connected to the column address buffer and multiple memory banks. The row decoder is used to decode the row address signals, and the column decoder is used to decode the column address signals, so that the corresponding storage cells in the memory banks 1121 can be located based on the decoded row and column address signals.

[0037] When a memory controller accesses DRAM, it first identifies the memory row corresponding to the data to be accessed and determines the memory bank to which the accessed memory row belongs. The memory controller then "opens" the corresponding memory bank and row. In some implementations, a memory row may also be referred to as a "page." A "page" is a logical concept; in this case, a page includes the memory cells of a memory row in DRAM. Typically, memory page sizes can include 512, 1024 (1K), 2048 (2K), 4098 (4K), 8196 (8K), 16392 (16K), or 32,768 (32K) bits of data.

[0038] Typically, during memory access, the storage row being accessed may be in one of three states: row hit, row idle, or row conflict. A row hit indicates that the storage row being accessed has been opened. This means that the data for the row has been loaded into the row buffer corresponding to the memory bank storing the row's data. Simply issuing a column access command can read data from or write data to the memory cells in that row. Column access commands can include read or write commands. A row idle indicates that the memory bank corresponding to the storage row being accessed is idle and unopened. Access to the row requires an "activate" command to open the row. This means that the data for the row must be loaded into the row buffer corresponding to the memory bank using an "activate" command before a column access command can be issued. A row conflict indicates that the currently open storage row is different from the storage row being accessed. In the case of rowconflict, the currently open storage row needs to be "closed" first, specifically by using the "precharge" command to write the data of the opened storage row back to the memory array, and then using the activate command to load the data of the row to be accessed into the corresponding row cache, and then send the column access command to access it. In an embodiment of the present invention, the above three states of the storage row to be accessed can be referred to as the row hit state of the storage row. "Storage row" can also be referred to as "row", and the storage row to be accessed can also be referred to as the target row.

[0039] As can be seen from the above description, during memory access, the different states of the row to be accessed will cause different access delays. In the row hit state, since the row to be accessed is already open, the memory controller can directly send a column access command. After sending the column access command, data can be read from or written to the memory. If the column access command is a read command, the read data is available after a delay. In the row idle state, since no rows in the memory bank are open, an "activate" command is required to open the row to be accessed before access can be made. Therefore, the memory controller must first send a row activate command, wait for the delay, and then send a column access command to access the open row. If the column access command is a read command, a delay is required before the read data is available. In the event of a row conflict, because the currently open row is not the row to be accessed, a pre-charge command must be sent to close the currently open row. After a delay, a row-activate command must be sent to open the row to be accessed. After another delay, a column-access command can be sent to access the row to be accessed. If the column-access command is a read command, a further delay is required after sending the column-access command to obtain the read data.

[0040] Each storage repository of the offload hardware 110 includes one or more storage units, each of which can be used to store a flow table entry.

[0041] The host 120 may be a central processing unit (CPU) or a processing core of a CPU. Figure 4 As shown, the host includes a memory address register 201, a memory data register 202, a program counter 203, an instruction register 204, an instruction decoder 205, an operation controller 207, a calculation unit 208, a general register group 209, an accumulator 210, a program status word register 211, a timing circuit 212, and a processor bus 220. The processor bus 220 can also be a data bus, a power bus, a control bus, or a status signal bus. In addition, the host is connected to the memory 240 via a DDR bus 230.

[0042] The host is configured to process instructions and data stored in memory 240. In some embodiments, instructions may include one or more instruction formats. The instruction format may indicate various fields (number of bits, bit positions, etc.) to specify the data processing operation to be performed and the operands on which the operation is to be performed. Some instruction formats may be further defined by instruction templates (or sub-formats).

[0043] In the host, the memory address register 201 is used to store the address of the memory 240 currently to be accessed by the host 120. The memory data register 202 is used to store the data and read or write instructions read or written from the address by the host 120, so as to compensate for the difference in operating speed between the processor and the memory.

[0044] The timing circuit 212 uses a fixed clock to provide a time reference for each component. The time it takes for the host 120 to execute an instruction is one instruction cycle. The program counter 203 stores the address of the next instruction. When instructions are executed sequentially, the program counter 203 automatically increments the byte count of each instruction after each instruction is fetched. When a branch instruction is encountered, the program counter 203 specifies the address of the next instruction using the address code field in the branch instruction. The instruction register 204 stores the currently executing instruction. An instruction consists of two fields: an operation code and an address code. The operation code is decoded by the instruction decoder 205 to generate the control voltage for the operation specified by the instruction. The operation controller 207 generates various operation control signals based on the control voltage signal output by the instruction decoder and the timing signals generated by the timing circuit 212, controlling the remaining components of the host to complete instruction fetching and execution.

[0045] A microinstruction is the smallest unit of instruction executed by a processor. An instruction can be a single microinstruction or composed of several microinstructions. Instructions composed of multiple microinstructions are called complex instructions. Various mechanisms can be used to decode complex instructions by the instruction decoder 205. Specific decoding mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLA), and microcode read-only memories (ROMs). In one embodiment, the steps of the microinstructions corresponding to complex instructions can be stored in the microcode ROM 206. During the decoding process, the instruction decoder 205 can query the microcode ROM 206 to obtain the opcode and address codes of the microinstructions that make up the complex instruction. It then decodes the opcode portion of the microinstructions in turn to generate the control voltages required by the microinstructions.

[0046] The operation controller 207 has multiple buffers that can send decoded instructions to their respective reservation stations for storage based on the type of instruction. After analyzing the status of the hardware circuits of the computing unit and the specific circumstances of whether each instruction can be executed in advance, the instructions that can be executed in advance are dispatched to the corresponding computing unit 208 for execution. During this period, the instruction stream is reordered to allow the instruction pipeline to proceed and be smoothly scheduled. For example, for integer calculation instructions, the operation controller 207 can use the integer reservation station to store the instructions and assign them to the integer computing unit for calculation; for floating-point calculation instructions, the operation controller 207 can use the floating-point reservation station to store the instructions and assign them to the floating-point computing unit for calculation.

[0047] The general register group 209 is used to store the data corresponding to the address code of the instruction. The calculation unit 208 is used to receive operation control signals from the operation controller 207 and perform calculations on the data stored in the general register group 209, including arithmetic operations (including basic operations such as addition, subtraction, multiplication, and additional operations) and logical operations (including shifts, logical tests, or comparisons between two values). Temporary variables generated during calculations are stored in the accumulator 210, and the generated status information is stored in the program status word register 211, such as the carry / borrow flag (C), overflow flag (O), zero flag (Z), negative flag (N), and sign flag (S). The program status word register is also used to store information such as interrupts and the operating status of the computing device, so that the host 120 can promptly understand the operating status of the machine and program.

[0048] The calculation unit 208 includes a variety of different circuit modules that can be used to execute different instructions. For example, the integer calculation unit 2081 and the floating-point calculation unit 2082 are used to perform arithmetic operations and logical operations on integers and floating-point numbers, respectively.

[0049] Host 120 is configured to offload the tunnel encapsulation table to offload hardware 110. The tunnel encapsulation table may include one or more of the following: a tunnel identifier (Tunnel ID), a source address (Source Address), a destination address (Destination Address), a tunnel source address (Tunnel Source Address), a tunnel destination address (Tunnel Destination Address), an encapsulation protocol type (Encapsulation Protocol Type), encapsulation header information, a time to live (TTL), quality of service (QoS) parameters, traffic classification or policy information, a tunnel status (Tunnel Status), a creation time (Creation Time), and an update time (Update Time). The tunnel identifier uniquely identifies a specific tunnel. The source address is the source IP address of the original packet. The destination address is the destination IP address of the original packet. The tunnel source address is the source IP address after tunnel encapsulation. The tunnel destination address is the destination IP address after tunnel encapsulation. The encapsulation protocol type can be, for example, Generic Routing Encapsulation (GRE), Internet Protocol Security (IPSec), or Virtual Extensible Local Area Network (VXLAN). The encapsulation header information can include one or more of the following: protocol version, flags, and checksum. In one possible embodiment, the host copies the first tunnel encapsulation table to obtain a second tunnel encapsulation table, and sends the first and second tunnel encapsulation tables to the offload hardware.

[0050] The offload hardware includes multiple repositories, each of which includes one or more storage units, each of which is used to store tunnel encapsulation tables. The first repository is used to store the first tunnel encapsulation table, and the second repository is used to store the second tunnel encapsulation table. The first repository and the second repository are different repositories. It will be understood that in the above example, only the first tunnel encapsulation table is copied into two copies and stored in the first and second repositories respectively. In actual applications, the first tunnel encapsulation table can be copied into multiple copies and stored in multiple repositories, and this is not specifically limited here. In one specific embodiment, the first repository is used to store a hash table, which includes a first matching item and the first tunnel encapsulation table. The second repository is used to store a result table, which includes the second tunnel encapsulation table. In another specific embodiment, the first repository is used to store a first result table, which includes the first tunnel encapsulation table. The second repository is used to store a second result table, which includes the second tunnel encapsulation table. The third repository is used to store a hash table, which includes the first matching item.

[0051] The unloading hardware is used to, upon receiving a first original message, select to read the first tunnel encapsulation table from the first storage repository, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, or select to read the second tunnel encapsulation table from the second storage repository, encapsulate the first original message according to the second tunnel encapsulation table to obtain the first tunnel message. In a specific embodiment, the unloading hardware is used to, upon receiving a first original message and the first original message matches a first matching item in a hash table in the first storage repository, select to read the first tunnel encapsulation table from the hash table in the first storage repository, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, or select to read the second tunnel encapsulation table from the result table in the second storage repository, encapsulate the first original message according to the second tunnel encapsulation table to obtain the second tunnel message. In a specific embodiment, the unloading hardware is used to, upon receiving a first original message and when the first original message matches the first matching item in the hash table in the third repository, select to read the first tunnel encapsulation table from the first result table in the first repository, and encapsulate the first original message according to the first tunnel encapsulation table to obtain a first tunnel message, or select to read the second tunnel encapsulation table from the second result table in the second repository, and encapsulate the first original message according to the second tunnel encapsulation table to obtain a second tunnel message.

[0052] Because the first tunnel encapsulation table and the second tunnel encapsulation table are identical, the offload hardware can freely choose which tunnel encapsulation table to use to encapsulate the original message. Therefore, when there are multiple original messages, the offload hardware can choose to read the first tunnel encapsulation table from the first storage repository and encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, while also choosing to read the second tunnel encapsulation table from the second storage repository and encapsulate the second original message according to the second tunnel encapsulation table to obtain the second tunnel message. It is not difficult to understand that when the multiple storage repositories of the offload hardware store multiple identical tunnel encapsulation tables, multiple original messages can be processed synchronously, thereby improving processing efficiency. Specifically, when there are multiple original messages, the offloading hardware may, if the first original message matches the first matching item in the hash table in the first repository, select to read the first tunnel encapsulation table from the hash table in the first repository, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, and at the same time, if the second original message matches the first matching item in the hash table in the first repository, read the second tunnel encapsulation table from the result table in the second repository, encapsulate the second original message according to the second tunnel encapsulation table to obtain the second tunnel message. Alternatively, when there are multiple original messages, the offloading hardware may, if the first original message matches the first matching item in the hash table in the third repository, select to read the first tunnel encapsulation table from the first result table in the first repository, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, and at the same time, if the second original message matches the first matching item in the hash table in the third repository, read the second tunnel encapsulation table from the second result table in the second repository, encapsulate the second original message according to the second tunnel encapsulation table to obtain the second tunnel message.

[0053] It can be understood that the above example is explained by taking the example that the host copies the first tunnel encapsulation table to obtain the second tunnel encapsulation table, and sends the first tunnel encapsulation table and the second tunnel encapsulation table to the offloading hardware. In actual applications, the host can also send the first tunnel encapsulation table to the offloading hardware, and the offloading hardware can copy the first tunnel encapsulation table to obtain the second tunnel encapsulation table.

[0054] See also Figure 5 , Figure 5 4 is a schematic diagram of a computing device provided by the present application. The computing device 400 includes: one or more processing units 410, a communication interface 420 and a storage unit 430.

[0055] The processing unit 410, the communication interface 420, and the storage unit 430 are interconnected via a bus 440. Optionally, the computing device 400 may further include an input / output interface 450, to which an input / output device is connected for receiving parameters set by the user, etc. The computing device 400 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiments of the present application; the processing unit 410 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiments of the present application. For example, the specific implementation of the various operations performed by the computing device 400 can refer to the specific details in the above-mentioned embodiments, such as the processing unit 410 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in the embodiments of the present application, the computing device 400 can be used to implement some or all of the functions of one or more components in the above-mentioned device embodiment. In addition, the communication interface 420 can be used specifically for the communication functions necessary to implement the functions of these devices and components, and the processing unit 410 can be used specifically for the processing functions necessary to implement the functions of these devices and components.

[0056] Figure 5 The computing device 400 may include one or more processing units 410, and the multiple processing units 410 may be connected in parallel, serially, serially, or in parallel or in any other manner to collaboratively provide processing capabilities, or the multiple processing units 410 may constitute a processor sequence or a processor array, or the multiple processing units 410 may be divided into a main processor and an auxiliary processor, or the multiple processing units 410 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 5 The computing device 400 shown, and the related structural and functional descriptions are exemplary and non-limiting. In some exemplary embodiments, the computing device 400 may include Figure 5 More or fewer components may be shown, some components may be combined, some components may be separated, or there may be a different arrangement of components.

[0057] The processing unit 410 can have various specific implementation forms. For example, the processing unit 410 can include a combination of one or more processors, such as a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU), although this is not specifically limited in the embodiments of the present application. The processing unit 410 can also be a single-core processor or a multi-core processor. The processing unit 410 can be a combination of a CPU and a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processing unit 410 can also be implemented solely using a logic device with built-in processing logic, such as an FPGA or a digital signal processor (DSP). The communication interface 420 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc. The wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0058] The memory unit 430 may be a non-volatile memory, such as a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory unit 430 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct RAM bus random access memory (DRRAM). The storage unit 430 can also be used to store program codes and data, so that the processing unit 410 can call the program codes stored in the storage unit 430 to execute part or all of the operation steps in the above method embodiment, or execute the corresponding functions in the above device embodiment. Figure 5 Show more or fewer components, or configure components differently.

[0059] The bus 440 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (UBus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 440 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 440 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 5 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0060] The present application also provides a system comprising multiple computing devices. The structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0061] The above embodiments can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part in the form of a computer program product. The computer program product comprises one or more computer instructions that, when loaded and executed on a computer, fully or partially perform the processes or functions described in accordance with the embodiments of the present invention. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one network site, computer, server, or data center to another network site, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that integrates one or more available media. The available media can be magnetic media (e.g., floppy disks, hard disks, magnetic tapes, etc.), optical media (e.g., DVDs, etc.), or semiconductor media (e.g., solid-state drives), etc. In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A flow table unloading system, characterized in that: include: Host, used to offload the tunnel encapsulation table to the offload hardware; The offloading hardware includes a plurality of storage libraries, each storage library includes one or more storage units, and the storage units are used to store tunnel encapsulation tables, wherein a first storage library is used to store a first tunnel encapsulation table, and a second storage library is used to store a second tunnel encapsulation table, wherein the second tunnel encapsulation table is copied based on the first tunnel encapsulation table, and is used to, upon receiving a first original message, select to read the first tunnel encapsulation table from the first storage library, encapsulate the first original message according to the first tunnel encapsulation table to obtain a first tunnel message, or select to read the second tunnel encapsulation table from the second storage library, and encapsulate the first original message according to the second tunnel encapsulation table to obtain a first tunnel message; The first storage repository is used to store a hash table, the hash table including a first matching item and a first tunnel encapsulation table; the second storage repository is used to store a result table, the result table including a second tunnel encapsulation table; The unloading hardware is used to select to read the first tunnel encapsulation table from the first storage library when the first original message received matches the first matching item, and encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, or select to read the second tunnel encapsulation table from the second storage library, and encapsulate the first original message according to the second tunnel encapsulation table to obtain the second tunnel message.

2. The system according to claim 1, wherein: The unloading hardware is used to select to read the first tunnel encapsulation table from the first storage library, encapsulate the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, and at the same time select to read the second tunnel encapsulation table from the second storage library, encapsulate the second original message according to the second tunnel encapsulation table to obtain the second tunnel message.

3. The system according to claim 1, wherein: The host is further configured to copy the first tunnel encapsulation table to obtain a second tunnel encapsulation table, and send the first tunnel encapsulation table and the second tunnel encapsulation table to the offloading hardware.

4. The system according to claim 1, wherein: The host is further configured to send the first tunnel encapsulation table to the offloading hardware; The offloading hardware is further configured to copy the first tunnel encapsulation table to obtain a second tunnel encapsulation table.

5. A flow table unloading method, characterized in that: include: Offload the tunnel encapsulation table to the offload hardware via the host; A plurality of storage libraries are provided by the offloading hardware, each storage library includes one or more storage units, and the storage units are used to store tunnel encapsulation tables, wherein a first storage library is used to store a first tunnel encapsulation table, and a second storage library is used to store a second tunnel encapsulation table, wherein the second tunnel encapsulation table is copied based on the first tunnel encapsulation table. When a first original message is received, the first tunnel encapsulation table is selected to be read from the first storage library, and the first original message is encapsulated according to the first tunnel encapsulation table to obtain a first tunnel message, or the second tunnel encapsulation table is selected to be read from the second storage library, and the first original message is encapsulated according to the second tunnel encapsulation table to obtain a second tunnel message; The first storage repository is used to store a hash table, the hash table including a first matching item and a first tunnel encapsulation table; the second storage repository is used to store a result table, the result table including a second tunnel table; When the unloading hardware receives a first original message that matches the first matching item, it chooses to read the first tunnel encapsulation table from the first storage library, encapsulates the first original message according to the first tunnel encapsulation table to obtain a first tunnel message, or chooses to read the second tunnel encapsulation table from the second storage library, encapsulates the first original message according to the second tunnel encapsulation table to obtain a second tunnel message.

6. The method according to claim 5, characterized in that The unloading hardware selects to read the first tunnel encapsulation table from the first storage library, encapsulates the first original message according to the first tunnel encapsulation table to obtain the first tunnel message, and at the same time selects to read the second tunnel encapsulation table from the second storage library, encapsulates the second original message according to the second tunnel encapsulation table to obtain the second tunnel message.

7. A computing device, characterized in that It includes a flow table offloading system and a storage unit, and the flow table offloading system and the storage unit can communicate with each other. The flow table offloading system is the system according to any one of claims 1 to 4.

8. A computing device cluster, characterized in that: It includes a flow table offloading system and a storage unit, and the flow table offloading system and the storage unit can communicate with each other. The flow table offloading system is the system according to any one of claims 1 to 4.

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