A high-speed dynamic vision sensor architecture based on column-level circuit sharing

Abstract

The present invention discloses a high-speed dynamic visual sensor architecture based on column-level circuit sharing, including a row driving circuit, a pixel array, a column-level shared event trigger circuit, and a readout system; the row driving circuit is used to provide row selection and switch timing signals for the pixel array, and at the same time provide data selection, reset and latch signals for the column-level shared event trigger circuit; the pixel array senses the external light intensity to realize photoelectric conversion, and outputs the voltage at the previous moment and the voltage at the current moment during row selection; the column-level shared event trigger circuit enters a reset state at the beginning of each row selection, first selects the voltage output by the sampled pixel array at the previous moment, then switches to an amplification state after the reset ends, inputs the voltage output by the sampled pixel array at the current moment, amplifies and compares this step voltage to generate an event, and stores the event information; the readout system is used to process the stored event information and output it to the outside.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, specifically to the field of dynamic perception when image information in a scene changes at high speed, and more specifically to a high-speed dynamic vision sensor architecture based on column-level circuit sharing. Background Art

[0002] Based on the characteristics of biological vision, people have abandoned the concept of "frame" and proposed a dynamic vision sensor (DVS). Compared with traditional complementary metal oxide semiconductor (CMOS) image sensors, the main feature of DVS is that it can realize continuous light intensity detection, logarithmically map the photocurrent and the output voltage of the light receiving level, significantly increase the photosensitivity dynamic range, and output a high-temporal-resolution event stream.

[0003] To meet time-domain sensitivity requirements, the classic DVS pixel structure incorporates a switched capacitor amplifier for precise voltage amplification. However, the 20-25 capacitance ratio restricts pixel size reduction. Research institutions at home and abroad have proposed methods such as sharing the switched capacitor gain with the pre-amplifier circuit, sharing the switched capacitor amplifier with pixel groups, and process improvements. Currently, back-illuminated and three-dimensional stacking processes are the most effective approach for reducing pixel size, but this results in a surge in wafer fabrication costs. Reducing DVS pixel size at low cost remains a pressing issue.

[0004] While reducing DVS pixel size also improves spatial resolution, using asynchronous readout technology based on Address-Event Representation (AER) in high-speed environments with rapidly increasing event information can lead to arbitration unfairness. Consequently, high-resolution DVS cameras have recently adopted synchronous readout technology. To cope with high-speed motion, the frame rate must be maximized, requiring extremely fast pixel response to changes in light intensity. Intra-pixel transmission delay is primarily determined by the DVS's logarithmic light receiving level and is inversely proportional to the photocurrent. Reducing this delay is a pressing issue. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the existing technology and propose a high-speed dynamic vision sensor architecture based on column-level circuit sharing. A photodiode structure with high photoelectric conversion efficiency is used at the pixel photosensor end to generate a larger photocurrent under the same light intensity, thereby achieving the purpose of reducing pixel delay. At the same time, a storage capacitor is introduced into the pixel circuit to realize the function of reading out the voltage at two moments in one row selection. The column level shares the switched capacitor amplifier and comparator circuit, which significantly reduces the pixel size.

[0006] The objectives of the present invention are achieved through the following technical solutions.

[0007] The present invention is based on a high-speed dynamic vision sensor architecture with column-level circuit sharing, comprising a row driver circuit, a pixel array, a column-level shared event trigger circuit, and a readout system. The row driver circuit is connected to the pixel array and the column-level shared event trigger circuit, respectively. The column-level shared event trigger circuit is also connected to the pixel array and the readout system, respectively.

[0008] The row drive circuit is used to provide row selection and switch timing signals for the pixel array, and at the same time provide data selection, reset and latch signals for the column-level shared event trigger circuit; the pixel array senses the external light intensity to achieve photoelectric conversion, and outputs the voltage at the previous moment and the voltage at the current moment during row selection; the column-level shared event trigger circuit enters the reset state at the beginning of each row selection, first selects the voltage output by the sampling pixel array at the previous moment, then switches to the amplification state after the reset ends, inputs the current moment voltage output by the sampling pixel array, amplifies and compares this step voltage to generate an event, and stores the event information; the readout system is used to process the stored event information and output it to the outside.

[0009] Furthermore, the pixel array is composed of M×N pixel units, each pixel unit in each row is connected to the row bus of the corresponding row in the row driving circuit, and each pixel unit in each column is connected to the input end of the corresponding column in the column-level shared event trigger circuit.

[0010] Furthermore, each of the pixel units is composed of a light receiving stage, a source follower, and a row selection circuit. The light receiving stage is composed of an NMOS tube No. 1, an NMOS tube No. 2, an NMOS tube No. 3, and a PMOS tube No. 1. The source follower is composed of an NMOS tube No. 4 and an NMOS tube No. 5. The row selection circuit is composed of a storage capacitor No. 1 NMOS switch, a transmission gate No. 2 NMOS switch, and a dummy switch. The transmission gate is composed of an NMOS tube No. 6 and a PMOS tube No. 2.

[0011] The source of the No. 1 NMOS tube and the gate of the No. 3 NMOS tube are both connected to the same photodiode, the source of the No. 3 NMOS tube is grounded, the drain and gate of the No. 1 NMOS tube are both connected to the source of the No. 2 NMOS tube, the drain of the No. 2 NMOS tube, the source of the No. 1 PMOS tube, and the drain of the No. 4 NMOS tube are all connected to the power supply, the gate of the No. 2 NMOS tube, the drain of the No. 3 NMOS tube, the drain of the No. 1 PMOS tube, and the gate of the No. 4 NMOS tube are all connected to the output node of the light receiving stage, the source of the No. 4 NMOS tube, the drain of the No. 5 NMOS tube, and the source of the No. 1 NMOS switch are connected. The drain of the No. 1 NMOS switch and the No. 2 NMOS switch are all connected to the source follower output node, the source of the No. 5 NMOS tube is grounded, the drain of the No. 1 NMOS switch is connected to the first input port of the corresponding column in the column-level shared event trigger circuit, the source of the No. 2 NMOS switch, the source and drain of the dummy switch, the source of the No. 6 NMOS tube, and the source of the No. 2 PMOS tube are all connected to the storage capacitor node, and the storage capacitor node is grounded via the storage capacitor, and the drain of the No. 6 NMOS tube and the drain of the No. 2 PMOS tube are both connected to the second input port of the corresponding column in the column-level shared event trigger circuit;

[0012] The gate of the No. 1 PMOS tube inputs a No. 1 bias voltage, the gate of the No. 5 NMOS tube inputs a No. 2 bias voltage, the gate of the No. 1 NMOS switch and the gate of the No. 6 NMOS tube both input the row selection signal of the corresponding row output by the row driving circuit, the gate of the No. 2 PMOS tube inputs the inverted signal of the row selection signal of the corresponding row output by the row driving circuit, the gate of the No. 2 NMOS switch inputs the switching timing signal of the corresponding row output by the row driving circuit, and the gate of the dummy switch inputs the inverted signal of the switching timing signal of the corresponding row output by the row driving circuit.

[0013] Furthermore, the photodiode adopts a "PINP" type photodiode structure, which is classified by doping regions into a p-substrate region, an intrinsic semiconductor region, an n+ injection region, and a surface p+ injection region. The p-substrate region and the intrinsic semiconductor region are both provided with grooves downward from the upper end surface. The p-substrate region, the intrinsic semiconductor region, and the n+ injection region are sequentially embedded from the outside to the inside, and the upper end surfaces of the intrinsic semiconductor region and the n+ injection region are flush. The surface p+ injection region is arranged on top of the intrinsic semiconductor region and the n+ injection region. The surface p+ injection region is flush with the upper end surface of the p-substrate region, and a through hole is provided in the middle of the surface p+ injection region. The p-substrate region and the surface p+ injection region are both grounded, and the n+ injection region is respectively connected to the source of the No. 1 NMOS tube and the gate of the No. 3 NMOS tube.

[0014] Furthermore, the column-level shared event trigger circuit is composed of N column-level shared event trigger units, each column-level shared event trigger unit is composed of a column data selector and an event trigger storage circuit, each of the column data selector input ends is connected to the output ends of each pixel unit of its corresponding column, each of the column data selector output ends corresponds to the event trigger storage circuit input end, and each of the event trigger storage circuit output ends is connected to the readout system.

[0015] Furthermore, each of the column data selectors is composed of a No. 1 transmission gate and a No. 2 transmission gate, the transmission gate is composed of a No. 7 NMOS transistor and a No. 3 PMOS transistor, and the No. 2 transmission gate is composed of a No. 8 NMOS transistor and a No. 4 PMOS transistor; each of the event-triggered storage circuits is composed of a switched capacitor amplifier, an event comparator, and an event latch, the switched capacitor amplifier is composed of a No. 1 amplifier, a No. 5 PMOS transistor, a No. 1 capacitor, and a No. 2 capacitor, the event comparator is composed of a No. 2 amplifier and a No. 3 amplifier, and the event latch is composed of an OFF latch unit and an ON latch unit;

[0016] The source of the seventh NMOS tube and the source of the third PMOS tube are both connected to the drain of the sixth NMOS tube and the drain of the second PMOS tube of each pixel unit in the corresponding column; the source of the eighth NMOS tube and the source of the fourth PMOS tube are both connected to the drain of the first NMOS switch of each pixel unit in the corresponding column; the gate of the seventh NMOS tube and the gate of the fourth PMOS tube are both input with the data selection signal provided by the row drive circuit; the gate of the third PMOS tube and the gate of the eighth NMOS tube are both input with the inverted signal of the data selection signal provided by the row drive circuit; the drain of the seventh NMOS tube, the drain of the third PMOS tube, the drain of the eighth NMOS tube, and the drain of the fourth PMOS tube are all connected to the negative input terminal of the first amplifier via the first capacitor;

[0017] The positive input terminal of the first amplifier inputs a third bias voltage, a second capacitor is connected between the negative input terminal and the output terminal of the first amplifier, the source and drain of the fifth PMOS transistor are respectively connected to the negative input terminal and the output terminal of the first amplifier, and the gate of the fifth PMOS transistor inputs a reset signal provided by the row drive circuit;

[0018] The negative phase input terminals of the second amplifier and the third amplifier are both connected to the output terminal of the first amplifier, the positive phase input terminals of the second amplifier and the third amplifier are respectively input with the fourth bias voltage and the fifth bias voltage, the output terminals of the second amplifier and the third amplifier are respectively connected to the input terminals of the OFF latch unit and the ON latch unit, the OFF latch unit and the ON latch unit are respectively input with the OFF latch signal and the ON latch signal, and the output terminals of the OFF latch unit and the ON latch unit are respectively connected to the same group of corresponding input ports in the readout system.

[0019] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0020] In response to the need for reduced DVS pixel latency and pixel size, this paper proposes a high-speed dynamic vision sensor architecture based on column-level circuit sharing. This architecture utilizes a photodiode structure with high photoelectric conversion efficiency and a column-level shared event trigger circuit. Compared to traditional event pixels, this new architecture generates a higher photocurrent at the photosensitive end of the pixel under the same light intensity, thereby reducing pixel latency without affecting other parameters. Furthermore, only a single storage capacitor is retained within the pixel, significantly reducing pixel size. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a diagram of the high-speed dynamic vision sensor architecture based on column-level circuit sharing in the present invention.

[0022] Figure 2 It is a schematic diagram of the structure of the "PINP" type photodiode with high photoelectric conversion efficiency in the present invention.

[0023] Figure 3 It is a schematic diagram of the principle of the pixel unit in the present invention.

[0024] Figure 4 This is a schematic diagram of the principle of the column-level shared event trigger circuit in the present invention.

[0025] Figure 5 This is a working timing diagram of the high-speed dynamic vision sensor based on column-level circuit sharing of the present invention. DETAILED DESCRIPTION

[0026] The present invention will be further described below in conjunction with the accompanying drawings.

[0027] Event-based dynamic vision sensors have the disadvantages of large single pixel size and high pixel transmission delay in low light conditions. To address the shortcomings of the existing technology, the present invention adopts a high-speed dynamic vision sensor architecture based on column-level circuit sharing, which significantly improves the photocurrent and reduces the capacitance area within the pixel, thereby achieving the purpose of reducing pixel delay and pixel size.

[0028] like Figure 1 As shown, the present invention is based on a high-speed dynamic vision sensor architecture with column-level circuit sharing, and is composed of a row driving circuit 1, a pixel array 2, a column-level shared event trigger circuit 3, and a readout system 4. The row driving circuit 1 is connected to the pixel array 2 and the column-level shared event trigger circuit 3, respectively, and the column-level shared event trigger circuit 3 is also connected to the pixel array 2 and the readout system 4, respectively.

[0029] The row driver circuit 1 is used to provide row selection and switch timing signals to the pixel array 2, enabling the pixel array to perform normal readout and refresh operations, and at the same time provides data selection, reset, and latch signals to the column-level shared event trigger circuit 3. The pixel array 2 senses the external light intensity to achieve photoelectric conversion and outputs two voltages during row selection: the voltage at the previous moment and the voltage at the current moment. The column-level shared event trigger circuit 3 performs periodic reset and amplification operations during each row selection. The order of transmission of the voltage at the previous moment and the voltage at the current moment is determined by the column data selector. First, at the beginning of each row selection, it enters the reset state and selects the voltage at the previous moment output by the sampled pixel array. Then, after the reset ends, it switches to the amplification state and inputs the current moment voltage output by the sampled pixel array 2. The subsequent circuit amplifies and compares this step voltage to generate an event and stores the event information, which can be stored in a latch. The readout system 4 is used to process the stored event information and output it to the outside, which can be implemented by a high-speed LVDS interface.

[0030] The pixel array 2 described above is composed of M×N pixel units, where M represents rows and N represents columns. Each pixel unit in each row is connected to the row bus of the corresponding row in the row driver circuit 1, and each pixel unit in each column is connected to the input terminal of the corresponding column in the column-level shared event trigger circuit 3. Preferably, the row driver circuit 1 has M groups of row buses, each of which includes two types of signal lines: the first type provides a switching timing signal and its inverted signal, and the second type provides a row select signal and its inverted signal. In actual circuit connection, each group of row buses can be designed to have four signal lines. The column-level shared event trigger circuit 3 has N groups of input terminals and N groups of output terminals, each group of input terminals includes two input ports, and each group of output terminals includes two output ports.

[0031] Figure 2 The present invention provides a two-dimensional cross-section of a "PINP" type photodiode structure with high photoelectric conversion efficiency, which is classified by doping region, including a p substrate region 51, an intrinsic semiconductor region 52, an n+ injection region 53, and a surface p+ injection region 54. The p substrate region 51 and the intrinsic semiconductor region 52 are both provided with grooves downward from the upper end surface, and the p substrate region 51, the intrinsic semiconductor region 52, and the n+ injection region 53 are sequentially embedded from the outside to the inside, and the upper end surfaces of the intrinsic semiconductor region 52 and the n+ injection region 53 are flush, and the surface p+ injection region 54 is provided on top of the intrinsic semiconductor region 52 and the n+ injection region 53. The surface p+ injection region 54 is flush with the upper end surface of the p substrate region 51, and a through hole is provided in the middle of the surface p+ injection region 54. The p substrate region 51 and the surface p+ injection region 54 are both grounded to GND, and the n+ injection region 53 is connected to Figure 3 V in PDThe photodiode is in a reverse biased state. When illuminated, the photovoltaic effect of the pn junction increases the width of the depletion region of the pn junction, generating a photocurrent flowing from the n-region to the p-region. When illuminated, the photodiode structure of the present invention depletes the entire intrinsic semiconductor region 52 and a portion of the surface p+ injection region 54, significantly expanding the depletion region width. This significantly increases photoelectric conversion efficiency. Furthermore, the surface p+ injection region 54 effectively suppresses dark current on the surface of the photodiode, thereby suppressing photodiode noise.

[0032] like Figure 3 As shown, each pixel unit is composed of a light receiving stage 6, a source follower 7, and a row selection circuit 8. The light receiving stage 6 is composed of a No. 1 NMOS transistor 61, a No. 2 NMOS transistor 62, a No. 3 NMOS transistor 63, and a No. 1 PMOS transistor 64. The basic working principle is that the No. 3 NMOS transistor 63 and the No. 1 PMOS transistor 64 form a common source amplifier, and the No. 1 NMOS transistor 61 and the No. 2 NMOS transistor 62 form a negative feedback to convert V PD The node voltage is clamped near a certain value. The source follower 7 is composed of the fourth NMOS tube 71 and the fifth NMOS tube 72. The basic principle is to filter out part of the noise of the light receiving stage 6 and play the role of low-pass filtering. The row selection circuit 8 is composed of a storage capacitor 81, an NMOS switch 82, a transmission gate 83, an NMOS switch 84, and a dummy switch 85. The basic principle is that it can output two moment voltages to the column level when the row selection timing arrives, and refresh the voltage of the storage capacitor 81 after the row selection is completed. The transmission gate 83 is composed of the sixth NMOS tube 8301 and the second PMOS tube 8302. The function of the transmission gate 83 is to suppress the voltage V at the previous moment of the row selection transmission. store The first NMOS switch 82, the second NMOS switch 84 and the dummy switch 85 can all be NMOS transistors. The function of the dummy switch 85 is to suppress the charge injection effect when the storage node is refreshed.

[0033] Specifically, the source of the first NMOS transistor 61 and the gate of the third NMOS transistor 63 are both connected to V PD Node, the V PD Node connected to Figure 2The n+ implantation region 53 of the photodiode shown in the figure adopts a "PINP" type photodiode structure. The source of the third NMOS tube 63 is grounded GND, the drain and gate of the first NMOS tube 61 are connected to the source of the second NMOS tube 62, the drain of the second NMOS tube 62, the source of the first PMOS tube 64, and the drain of the fourth NMOS tube 71 are all connected to the power supply VDD, the gate of the second NMOS tube 62, the drain of the third NMOS tube 63, the drain of the first PMOS tube 64, and the gate of the fourth NMOS tube 71 are all connected to the light receiving stage output node pr, the source of the fourth NMOS tube 71, the drain of the fifth NMOS tube 72, the source of the first NMOS switch 82, and the drain of the second NMOS tube 62 are all connected to the power supply VDD. The drains of the MOS switches 84 are all connected to the source follower output node sf. The source of the fifth NMOS transistor 72 is grounded to GND. The drain of the first NMOS switch 82 is connected to the first input port of the corresponding column in the column-level shared event trigger circuit 3. The source of the second NMOS switch 84, the source and drain of the dummy switch 85, the source of the sixth NMOS transistor 8301, and the source of the second PMOS transistor 8302 are all connected to the storage capacitor node store, and the storage capacitor node store is grounded to GND via the storage capacitor 81. The drain of the sixth NMOS transistor 8301 and the drain of the second PMOS transistor 8302 are both connected to the second input port of the corresponding column in the column-level shared event trigger circuit 3. The gate of the first PMOS transistor 64 inputs the first bias voltage V bpr The gate of the fifth NMOS tube 72 inputs the second bias voltage V bsf The gate of the first NMOS switch 82 and the gate of the sixth NMOS transistor 8301 are both input with the row selection signal V of the corresponding row output by the row driving circuit 1. sw The gate of the second PMOS tube 8302 inputs the inverted signal nV of the row selection signal of the corresponding row output by the row driver circuit 1 sw The gate of the second NMOS switch 84 inputs the switch timing signal V corresponding to the row output by the row driving circuit 1. fresh The gate of the dummy switch 85 inputs the inverted signal nV of the switch timing signal of the corresponding row output by the row driving circuit 1 fresh .

[0034] The column-level shared event trigger circuit 3 of the present invention is composed of N column-level shared event trigger units, such as Figure 4 As shown, each column-level shared event trigger unit is composed of a column data selector 9 and an event trigger storage circuit 10. Each input end of the column data selector 9 is connected to the output end of each pixel unit of its corresponding column, each output end of the column data selector 9 corresponds to the input end of the event trigger storage circuit 10, and each output end of the event trigger storage circuit 10 is connected to the readout system 4.

[0035] Each column data selector 9 is composed of a first transmission gate 91 and a second transmission gate 92. The transmission gate 91 is composed of a seventh NMOS transistor 9101 and a third PMOS transistor 9102. The second transmission gate 92 is composed of an eighth NMOS transistor 9201 and a fourth PMOS transistor 9202. Each event-triggered storage circuit 10 is composed of a switched capacitor amplifier 101, an event comparator 102, and an event latch 103. The switched capacitor amplifier 101 is composed of a first amplifier 1012, a fifth PMOS transistor 1011, a first capacitor C1, and a second capacitor C2. The event comparator 102 is composed of a second amplifier 1021 and a third amplifier 1022. The event latch 103 is composed of an OFF latch unit OFF Latch and an ON latch unit ON Latch.

[0036] The specific circuit connection of each column-level shared event trigger unit is as follows: the source of the seventh NMOS transistor 9101 and the source of the third PMOS transistor 9102 are both connected to the drain of the sixth NMOS transistor 8301 and the drain of the second PMOS transistor 8302 of each pixel unit in the corresponding column; the source of the eighth NMOS transistor 9201 and the source of the fourth PMOS transistor 9202 are both connected to the drain of the first NMOS switch 82 of each pixel unit in the corresponding column; the gate of the seventh NMOS transistor 9101 and the gate of the fourth PMOS transistor 9202 are both input with the data selection signal V provided by the row driver circuit 1 sel The gate of the third PMOS tube 9102 and the gate of the eighth NMOS tube 9201 are both input with the inverted signal nV of the data selection signal provided by the row driving circuit 1. sel The drain of the seventh NMOS tube 9101, the drain of the third PMOS tube 9102, the drain of the eighth NMOS tube 9201, and the drain of the fourth PMOS tube 9202 are all connected to the negative input terminal of the first amplifier 1012 through the first capacitor C1. The positive input terminal of the first amplifier 1012 inputs the third bias voltage V ref A second capacitor C2 is connected between the negative input terminal and the output terminal of the first amplifier 1012. The source and drain of the fifth PMOS tube 1011 are respectively connected to the negative input terminal and the output terminal of the first amplifier 1012. The gate of the fifth PMOS tube 1011 inputs the reset signal V provided by the row drive circuit 1. nrst The negative input terminals of the second amplifier 1021 and the third amplifier 1022 are connected to the output terminal of the first amplifier 1012, and the positive input terminals of the second amplifier 1021 and the third amplifier 1022 are respectively input with the fourth bias voltage V refh and bias voltage V reflThe output terminals of the second amplifier 1021 and the third amplifier 1022 are connected to the input terminals of the OFF latch unit OFF Latch and the ON latch unit ON Latch, respectively. The OFF latch unit OFF Latch and the ON latch unit ON Latch input the OFF latch signal V loff and ON latch signal V lon The output ends of the OFF latch unit OFF Latch and the ON latch unit ON Latch are respectively connected to the same corresponding group of input ports in the readout system 4.

[0037] The basic working principle of the column-level shared event trigger circuit 3 of the present invention is as follows: at the beginning of the row selection phase of a certain row of pixels, the switched capacitor amplifier 101 is reset. At this time, the first transmission gate 91 is turned on, so that the lower plate of the input capacitor of the switched capacitor amplifier 101 samples the voltage V2 at the previous moment. After a certain period of time, the reset is completed, the first transmission gate 91 is turned off, and the second transmission gate 92 is turned on. The lower plate of the input capacitor of the switched capacitor amplifier 101 samples the voltage V1 at the current moment. At this time, the event latch 103 is in a transparent state. This step voltage is judged by the switched capacitor amplifier 101 and the event comparator 102 to determine whether an event has occurred, and the result is stored in the event latch 103 for reference. Figure 1 The middle readout system 4 performs readout, after which the row selection of pixels in this row ends and the row selection of pixels in the next row begins. The column-level shared event trigger circuit 3 repeats the above-mentioned working process, so its working cycle is one row selection cycle.

[0038] Figure 5 The relevant working timing diagram of the pixel readout process of the i-th row and j-th column of the high-speed dynamic vision sensor of the present invention is given. The switching timing signal V fresh Set high, the second NMOS switch 84 is turned on, giving the storage capacitor 81 an initial value. At time t1, the switch timing signal V fresh Set to low, the high-speed dynamic vision sensor starts to work normally. Assume that the row selection signal V sw Set high, marking the pixels in row i entering the row selection stage, the voltage V store (i.e., the voltage of the storage capacitor node store) and the current voltage V sf (ie, the voltage of the source follower output node sf) is transmitted to the input terminal of the column data selector 9; the reset signal V nrst <j>Low active, the fifth PMOS tube 1011 is turned on, and the switched capacitor amplifier 101 enters the reset state; the data selection signal V sel <j>Set high, the column data selector 9 controls the first transmission gate 91 to be turned on, and the switched capacitor amplifier 101 inputs the capacitor lower plate to sample V2, i.e., V store At t3, the reset signal V nrst <j>Set to high level, the switched capacitor amplifier 101 enters the amplification state; ON latch signal V lon <j>and OFF latch signal V loff <j>Set high to make the event latch 103 transparent and receive the event information output by the event comparator 102 at any time. After a short time (nsec level) to t4, the data selection signal V sel <j>= low, the column data selector 9 controls the second transmission gate 92 to be turned on, and the switched capacitor amplifier 101 inputs the capacitor lower plate to sample the current voltage V1, i.e., V sf This step voltage is negatively amplified by the switched capacitor amplifier 101 according to the capacitance ratio, and is judged and generated by the event comparator 102 and stored in the event latch 103. At time t5, the row selection signal V sw Set low, the pixels in row i end the row selection phase; reset signal V nrst <j>Low active, the switched capacitor amplifier 101 re-enters the reset state; ON latch signal V lon <j>and OFF latch signal V loff <j>= is set low, so that the event latch 103 is in a latched state for subsequent reading by the readout system 4. Then after a short time (nsec level) to time t6, the switch timing signal V fresh The pixel in row i refreshes the voltage of the storage capacitor 81, and the process continues until time t7. The switching timing signal V fresh Set low to stop voltage refresh. After that, the pixels in this row wait for the next frame row selection phase and perform periodic work.

[0039] Although the functions and working processes of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the above-mentioned specific functions and working processes. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the purpose of the present invention and the claims, which are all protected by the present invention. < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j> < / j>

Claims

1. A high-speed dynamic vision sensor architecture based on column-level circuit sharing, characterized in that: The invention comprises a row driving circuit (1), a pixel array (2), a column-level shared event triggering circuit (3), and a readout system (4), wherein the row driving circuit (1) is connected to the pixel array (2) and the column-level shared event triggering circuit (3), respectively, and the column-level shared event triggering circuit (3) is also connected to the pixel array (2) and the readout system (4), respectively; The row drive circuit (1) is used to provide row selection and switch timing signals for the pixel array (2), and at the same time provide data selection, reset and latch signals for the column-level shared event trigger circuit (3); the pixel array (2) senses the external light intensity to realize photoelectric conversion, and outputs the voltage at the previous moment and the voltage at the current moment during the row selection period; the column-level shared event trigger circuit (3) enters a reset state at the beginning of each row selection, first selects the voltage at the previous moment output by the sampling pixel array, then switches to an amplification state after the reset ends, inputs the current moment voltage output by the sampling pixel array (2), amplifies and compares this step voltage to generate an event, and stores the event information; the readout system (4) is used to process the stored event information and output it to the outside; The pixel array (2) is composed of M×N pixel units, each pixel unit uses a photodiode to sense external light intensity to achieve photoelectric conversion, the photodiode adopts a "PINP" type photodiode structure, and is classified by doping region into a p substrate region (51), an intrinsic semiconductor region (52), an n+ injection region (53), and a surface p+ injection region (54), the p substrate region (51) and the intrinsic semiconductor region (52) are both provided with a groove from the upper end surface downward, and the p substrate region (51), the intrinsic semiconductor region (52), and the n+ injection region (53) are arranged from the outside to the inside. The upper end surfaces of the intrinsic semiconductor region (52) and the n+ injection region (53) are flush with each other, the surface p+ injection region (54) is arranged on top of the intrinsic semiconductor region (52) and the n+ injection region (53), the surface p+ injection region (54) is flush with the upper end surface of the p substrate region (51), and a through hole is opened in the middle of the surface p+ injection region (54); the p substrate region (51) and the surface p+ injection region (54) are both grounded (GND), and the n+ injection region 53 is respectively connected to the source of the first NMOS tube (61) and the gate of the third NMOS tube (63); The column-level shared event trigger circuit (3) is composed of N column-level shared event trigger units, each column-level shared event trigger unit is composed of a column data selector (9) and an event trigger storage circuit (10), each column data selector (9) is composed of a No. 1 transmission gate (91) and a No. 2 transmission gate (92), and each event trigger storage circuit (10) is composed of a switched capacitor amplifier (101), an event comparator (102), and an event latch (103).

2. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 1, characterized in that: Each pixel unit in each row of the pixel array (2) is connected to the row bus of the corresponding row in the row driving circuit (1), and each pixel unit in each column is connected to the input end of the corresponding column in the column-level shared event trigger circuit (3).

3. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 1, characterized in that: Each pixel unit is composed of a light receiving stage (6), a source follower (7), and a row selection circuit (8); the light receiving stage (6) is composed of a No. 1 NMOS tube (61), a No. 2 NMOS tube (62), a No. 3 NMOS tube (63), and a No. 1 PMOS tube (64); the source follower (7) is composed of a No. 4 NMOS tube (71) and a No. 5 NMOS tube (72); the row selection circuit (8) is composed of a storage capacitor (81), a No. 1 NMOS switch (82), a transmission gate (83), a No. 2 NMOS switch (84), and a dummy switch (85); the transmission gate (83) is composed of a No. 6 NMOS tube (8301) and a No. 2 PMOS tube (8302); The source of the No. 1 NMOS tube (61) and the gate of the No. 3 NMOS tube (63) are both connected to the same photodiode, the source of the No. 3 NMOS tube (63) is grounded (GND), the drain and gate of the No. 1 NMOS tube (61) are both connected to the source of the No. 2 NMOS tube (62), the drain of the No. 2 NMOS tube (62), the source of the No. 1 PMOS tube (64), and the drain of the No. 4 NMOS tube (71) are all connected to the power supply (VDD), the gate of the No. 2 NMOS tube (62), the drain of the No. 3 NMOS tube (63), the drain of the No. 1 PMOS tube (64), and the gate of the No. 4 NMOS tube (71) are all connected to the light receiving stage output node (pr), the source of the No. 4 NMOS tube (71), the drain of the No. 5 NMOS tube (72), the source of the No. 1 NMOS switch (82), the No. 2 NMOS tube (62) and the drain of the No. 1 PMOS tube (64) are all connected to the power supply (VDD), the gate of the No. 2 NMOS tube (62), the drain of the No. 3 NMOS tube (63), the drain of the No. 1 PMOS tube (64), and the gate of the No. 4 NMOS tube (71) are all connected to the light receiving stage output node (pr), the source of the No. 4 NMOS tube (71), the drain of the No. 5 NMOS tube (72), the source of the No. 1 NMOS switch (82), the No. 2 The drains of the NMOS switches (84) are all connected to the source follower output node (sf), the source of the fifth NMOS tube (72) is grounded (GND), the drain of the first NMOS switch (82) is connected to the first input port of the corresponding column in the column-level shared event trigger circuit (3), the source of the second NMOS switch (84), the source and drain of the dummy switch (85), the source of the sixth NMOS tube (8301), and the source of the second PMOS tube (8302) are all connected to the storage capacitor node (store), and the storage capacitor node (store) is grounded (GND) via the storage capacitor (81), and the drain of the sixth NMOS tube (8301) and the drain of the second PMOS tube (8302) are all connected to the second input port of the corresponding column in the column-level shared event trigger circuit (3); The gate of the No. 1 PMOS tube (64) inputs a No. 1 bias voltage (V bpr ), the gate of the fifth NMOS tube (72) inputs the second bias voltage (V bsf ), the gate of the No. 1 NMOS switch (82) and the gate of the No. 6 NMOS tube (8301) are both input with the row selection signal (V sw ), the gate of the second PMOS tube (8302) inputs the inverted signal (nV) of the row selection signal of the corresponding row output by the row drive circuit (1) sw ), the gate of the second NMOS switch (84) inputs the switch timing signal (V fresh ), the gate of the dummy switch (85) inputs the inverted signal (nV) of the switch timing signal of the corresponding row output by the row drive circuit (1) fresh ).

4. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 1, characterized in that: Each column data selector (9) input end is connected to the output end of each pixel unit of its corresponding column, each column data selector (9) output end corresponds to the input end of the event-triggered storage circuit (10), and each event-triggered storage circuit (10) output end is connected to the readout system (4).

5. The high-speed dynamic vision sensor architecture based on column-level circuit sharing according to claim 1, characterized in that: The transmission gate (91) is composed of a No. 7 NMOS tube (9101) and a No. 3 PMOS tube (9102); the No. 2 transmission gate (92) is composed of a No. 8 NMOS tube (9201) and a No. 4 PMOS tube (9202); the switched capacitor amplifier (101) is composed of a No. 1 amplifier (1012), a No. 5 PMOS tube (1011), a No. 1 capacitor (C1), and a No. 2 capacitor (C2); the event comparator (102) is composed of a No. 2 amplifier (1021) and a No. 3 amplifier (1022); and the event latch (103) is composed of an OFF latch unit (OFFLatch) and an ON latch unit (ONLatch); The source of the seventh NMOS tube (9101) and the source of the third PMOS tube (9102) are both connected to the drain of the sixth NMOS tube (8301) and the drain of the second PMOS tube (8302) of each pixel unit in the corresponding column. The source of the eighth NMOS tube (9201) and the source of the fourth PMOS tube (9202) are both connected to the drain of the first NMOS switch (82) of each pixel unit in the corresponding column. The gate of the seventh NMOS tube (9101) and the gate of the fourth PMOS tube (9202) are both input with the data selection signal (V) provided by the row drive circuit (1). sel ), the gate of the third PMOS tube (9102) and the gate of the eighth NMOS tube (9201) are both input with the inverted signal (nV) of the data selection signal provided by the row drive circuit (1) sel ), the drain of the seventh NMOS tube (9101), the drain of the third PMOS tube (9102), the drain of the eighth NMOS tube (9201), and the drain of the fourth PMOS tube (9202) are all connected to the negative input terminal of the first amplifier (1012) via the first capacitor (C1); The positive input terminal of the first amplifier (1012) inputs the third bias voltage (V ref ), a second capacitor (C2) is connected between the negative phase input terminal and the output terminal of the first amplifier (1012), the source and drain of the fifth PMOS tube (1011) are respectively connected to the negative phase input terminal and the output terminal of the first amplifier (1012), and the gate of the fifth PMOS tube (1011) inputs a reset signal (V nrst ); The negative phase input terminals of the second amplifier (1021) and the third amplifier (1022) are both connected to the output terminal of the first amplifier (1012), and the positive phase input terminals of the second amplifier (1021) and the third amplifier (1022) are respectively input with the fourth bias voltage (V refh ) and bias voltage No. 5 (V refl ), the output ends of the second amplifier (1021) and the third amplifier (1022) are respectively connected to the input ends of the OFF latch unit (OFF Latch) and the ON latch unit (ON Latch), and the OFF latch unit (OFF Latch) and the ON latch unit (ON Latch) are respectively input with the OFF latch signal (V loff ) and ON latch signal (V lon ), the output ends of the OFF latch unit (OFF Latch) and the ON latch unit (ON Latch) are respectively connected to the same group of corresponding input ports in the readout system (4).

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