Preparation method of flash memory device
By forming and etching the hard mask layer on the substrate surface during semiconductor manufacturing, a stable isolation trench depth difference is formed, the problem of isolation trench depth control of memory and peripheral logic regions is solved, reducing costs and improving flash memory The isolation effect and electrical parameters of the device.
Patent Information
- Application Number
- CN202411155594.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-21
- Publication Date
- 2024-12-13
AI Technical Summary
During semiconductor manufacturing, the difference in isolation trench depth between the memory area and the peripheral logic area is difficult to accurately control, resulting in the impact of the filling quality and isolation effect of the oxide layer material, and the existing process costs are relatively high.
By forming a first hard mask layer on the substrate surface and etching and removing it on the surface of the liner oxide layer, and then forming a second hard mask layer, the first and the first and the second hard mask layer are formed in the storage area and the peripheral logic area using a dry etching process. The second isolation trench ensures that the depth of the second isolation trench is greater than the first isolation trench, and a silicon nitride hard mask layer is formed through a high-temperature furnace tube process to reduce subsequent etching depth fluctuations.
The stable difference in the isolation trench depth between the memory area and the peripheral logic area is achieved, the process cost is reduced, the filling quality and isolation effect of the oxide layer material is improved, the precise control of the height of the floating gate layer is increased, and the electrical parameters of the flash memory device are improved. .
Smart Images
Figure CN119136552A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a flash memory device. Background Art
[0002] During the further miniaturization process of the storage area of the NORD non-volatile flash memory device, void defects are easily generated when the oxide layer material is filled in the isolation trenches (trench for preparing shallow trench isolation structure (STI)) of the storage area. It is necessary to reduce the depth of the isolation trench and at the same time maintain the depth of the STI in the peripheral logic area unchanged.
[0003] At present, the above problem (the depth of the shallow trench isolation structure in the storage area is inconsistent with the depth of the shallow trench isolation structure in the peripheral logic area) can be solved by Cell-AA & Peri-AA (active area of the storage area & active area of the storage area) separate plate preparation or Cell-AA & Peri-AA combined plate preparation, wherein,
[0004] 1. The isolation trench is prepared by Cell-AA & Peri-AA sub-plate. Although it can solve the problem of inconsistent depth between the shallow trench isolation structure in the storage area and the shallow trench isolation structure in the peripheral logic area, it needs to add at least one customized mask, which will increase the process cost.
[0005] 2. The process of preparing STI by Cell-AA&Peri-AA is as follows: first, a hard mask layer is deposited on the substrate surface of the storage area and the peripheral logic area, and then a special mask is used to etch a part of the hard mask layer of the peripheral logic area through a dry etching process, so that the remaining thickness of the hard mask layer of the peripheral logic area has a height difference with the hard mask layer of the storage area. When the AA etching isolation trench is subsequently performed, the etching opening time difference of the substrate is used to create the depth difference between the shallow trench isolation structure of the storage area and the shallow trench isolation structure of the peripheral logic area. However, the process fluctuation of the Cell-AA&Peri-AA STI process in the etching stage of the hard mask layer in the peripheral logic area is large, and the main problems are as follows:
[0006] 1) It is difficult to accurately control the remaining thickness of the hard mask layer through the dry etching process of the hard mask layer in the peripheral logic area controlled by the process time, which easily causes the etching depth difference of the subsequent isolation trench to produce process fluctuations, affecting the filling quality of the oxide layer material in the isolation trench and the isolation effect of the peripheral logic area device;
[0007] 2) The interface between the storage area and the peripheral logic area is prone to separation. After the CMP (chemical mechanical polishing) process of the STI (shallow trench isolation structure) filled with oxide layer material, the oxide layer material is prone to remain at the interface between the storage area and the peripheral logic area, which affects the subsequent removal of the hard mask layer and increases the risk of impurity contamination in the wet cleaning stage;
[0008] 3) The remaining thickness of the hard mask layer in the peripheral logic area serves as a grinding barrier for the floating gate layer. The process fluctuation of its etching thickness will affect the final height of the floating gate layer in the storage area, and there is a risk of increasing the electrical parameters (such as Sigma) of the flash memory device. Summary of the invention
[0009] The present application provides a method for preparing a flash memory device, which can solve at least one of the following problems: large fluctuations in the process of etching depth of the isolation trench in the peripheral logic area during the process of preparing the STI by CAA & PAA combined version, difficulty in accurately controlling the depth difference between the shallow trench isolation structure in the storage area and the shallow trench isolation structure in the peripheral logic area, and high manufacturing cost during the process of preparing the STI by CAA & PAA separate version.
[0010] The present invention provides a method for preparing a flash memory device, comprising:
[0011] Providing a substrate, the substrate comprising a storage area and a peripheral logic area, and a pad oxide layer and a first hard mask layer are formed on the surface of the substrate;
[0012] Etching and removing the first hard mask layer of the peripheral logic area, and stopping at the surface of the pad oxide layer;
[0013] forming a second hard mask layer, wherein the second hard mask layer covers the first hard mask layer of the storage area and the pad oxide layer of the peripheral logic area, wherein there is a certain height difference between the second hard mask layer of the storage area and the second hard mask layer of the peripheral logic area;
[0014] The second hard mask layer, the first hard mask layer, the pad oxide layer and a partial thickness of the substrate in the storage area are etched, and the second hard mask layer, the pad oxide layer and a partial thickness of the substrate in the peripheral logic area are etched to form a first isolation trench in the storage area and a second isolation trench in the peripheral logic area, wherein the depth of the second isolation trench in the substrate is greater than the depth of the first isolation trench in the substrate, and the depth difference between the first isolation trench and the second isolation trench in the substrate is greater than the height difference between the second hard mask layer in the storage area and the second hard mask layer in the peripheral logic area.
[0015] Optionally, in the method for preparing the flash memory device, a high-selectivity dry etching process is used to etch away the first hard mask layer of the peripheral logic area and stop at the surface of the pad oxide layer.
[0016] Optionally, in the method for preparing the flash memory device, in the process of etching and removing the first hard mask layer of the peripheral logic area using a high-selectivity dry etching process, the etching gases used are CF4, O2 and Ar, wherein the ratio of gas CF4 to gas O2 is 4:1 to 4.2:1.
[0017] Optionally, in the method for preparing the flash memory device, the second hard mask layer is formed by a high-temperature furnace tube process.
[0018] Optionally, in the preparation method of the flash memory device, in the process of forming the second hard mask layer by using a high-temperature furnace tube process, the process temperature is 750°C to 800°C, the nitrogen flow rate is 200sccm to 300sccm, and the process duration is 8h to 10h.
[0019] Optionally, in the method for preparing the flash memory device, the material of the second hard mask layer is silicon nitride.
[0020] Optionally, in the method for preparing the flash memory device, a height difference between the second hard mask layer of the storage area and the second hard mask layer of the peripheral logic area is equal to a thickness of the first hard mask layer of the storage area.
[0021] Optionally, in the method for preparing the flash memory device, the step of etching the second hard mask layer, the first hard mask layer, the liner oxide layer and a partial thickness of the substrate in the storage area and etching the second hard mask layer, the liner oxide layer and a partial thickness of the substrate in the peripheral logic area to form a first isolation trench in the storage area and a second isolation trench in the peripheral logic area includes:
[0022] The second hard mask layer of the storage area, the first hard mask layer and the second hard mask layer of the peripheral logic area are etched by a dry etching process, wherein the etching gases are CF4, O2 and Ar, the flow rate of the gas CF4 is 140sccm to 210sccm, and the flow rate of the gas O2 is 35sccm to 52sccm; the etching time is 2min to 3min;
[0023] The pad oxide layer of the storage area and the pad oxide layer of the peripheral logic area are etched by a dry etching process, wherein the etching gases are CHF3, O2 and Ar, the flow rate of the CHF3 gas is 120sccm to 180sccm, and the flow rate of the O2 gas is 20sccm to 30sccm; the etching time is 20s to 30s;
[0024] A dry etching process is used to etch a partial thickness of the substrate in the storage area and a partial thickness of the substrate in the peripheral logic area, wherein the etching gases are CF4, CHF3, SF6, O2 and Ar, the flow rate of gas CF4 is 50sccm~70sccm, the flow rate of gas CHF3 is 30sccm~40sccm, and the flow rate of SF6 is 70sccm~100sccm; the etching time is 20min~25min.
[0025] Optionally, in the method for preparing the flash memory device, the thickness of the first hard mask layer is
[0026]
[0027] Optionally, in the method for preparing the flash memory device, the material of the first hard mask layer is silicon nitride.
[0028] The technical solution of this application has at least the following advantages:
[0029] The present application prepares the second isolation trench and the first isolation trench through the CAA&PAA combined version. First, a first hard mask layer is formed on the substrate of the storage area and the peripheral logic area. Then, the pad oxide layer is used as an etch stop layer for etching the first hard mask layer in the peripheral logic area. The first hard mask layer in the peripheral logic area is completely removed, which can avoid the thickness fluctuation caused by the etching process of the first hard mask layer. Furthermore, a second hard mask layer with precisely controllable thickness is formed in the storage area and the peripheral logic area at the same time. In conjunction with the first hard mask layer, the fluctuation of the subsequent etching depth of the first / second isolation trench can be reduced, and a stable depth difference is formed between the second isolation trench and the first isolation trench. At the same time, the present application prepares the second isolation trench and the first isolation trench through the CAA&PAA combined version without the need for additional masks, thereby avoiding an increase in manufacturing costs.
[0030] In addition, the second hard mask layer of the peripheral logic area of the present application is subsequently used as a grinding barrier layer for the shallow trench isolation structure of the peripheral logic area and the floating gate layer of the storage area, thereby increasing the process windows of the subsequent CMP process of the shallow trench isolation structure of the peripheral logic area and the CMP process of the floating gate layer of the storage area. The thickness of the second hard mask layer of the peripheral logic area is precisely controllable, which is beneficial to stabilizing the height of the shallow trench isolation structure of the peripheral logic area and the process thickness of the floating gate layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0032] Figure 1 is a flow chart of a method for preparing a flash memory device according to an embodiment of the present invention;
[0033] Figure 2-Figure 5 is a schematic diagram of a semiconductor structure in each process step of preparing a flash memory device according to an embodiment of the present invention;
[0034] The reference numerals are described as follows:
[0035] 10 - substrate, 20 - pad oxide layer, 31 - first hard mask layer, 32 - second hard mask layer, 40 - photoresist layer, 51 - first isolation trench, 52 - second isolation trench. DETAILED DESCRIPTION
[0036] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0037] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0038] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0039] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0040] The present application provides a method for preparing a flash memory device, referring to Figure 1 , Figure 1 is a flowchart of a method for preparing a flash memory device according to an embodiment of the present invention, and Figure 2-Figure 5 , Figure 2-Figure 5 1 is a schematic diagram of a semiconductor structure in each process step of preparing a flash memory device according to an embodiment of the present invention. The method for preparing the flash memory device includes:
[0041] Step S1: Reference Figure 2 , Figure 2It is a schematic diagram of a semiconductor structure after a patterned photoresist layer is formed according to an embodiment of the present application. A substrate 10 is provided. The substrate 10 includes a storage area and a peripheral logic area. A pad oxide layer 20 and a first hard mask layer 31 are formed on the surface of the substrate 10.
[0042] Among them, the substrate 10 can be one of single crystal silicon, polycrystalline silicon, and amorphous silicon. The substrate 10 can also be gallium arsenide, gallium silicon compounds, etc. The substrate 10 can also have a silicon on insulating layer or an epitaxial layer on silicon structure; the substrate 10 can also be other semiconductor materials, which are not listed here one by one.
[0043] In this embodiment, the material of the first hard mask layer 31 is silicon nitride.
[0044] Preferably, the thickness of the first hard mask layer 31 is
[0045] Step S2: Continue to refer Figure 2 And reference Figure 3 , Figure 3 Schematic diagram of the semiconductor structure after etching away the first hard mask layer of the peripheral logic area and stopping at the surface of the pad oxide layer in the embodiment of the present application. First, a photoresist layer 40 is coated on the surface of the first hard mask layer 31, and then, Figure 2 , the photoresist layer of the peripheral logic area is opened by exposure and development processes to obtain a patterned photoresist layer 40, and then, with reference to Figure 3 , using the patterned photoresist layer 40 as a mask, the first hard mask layer 31 of the peripheral logic area is etched away, stopping at the surface of the pad oxide layer 20 , and finally, the patterned photoresist layer 40 is removed by ashing.
[0046] Preferably, a high-selectivity dry etching process is used to etch away the first hard mask layer 31 of the peripheral logic region and stop at the surface of the pad oxide layer 20 .
[0047] Preferably, in the process of etching and removing the first hard mask layer 31 of the peripheral logic area by a high-selectivity dry etching process, the etching gases used are CF4, O2 and Ar, wherein the ratio of gas CF4 to gas O2 is 4:1 to 4.2:1.
[0048] The present application can completely remove the first hard mask layer 31 of the peripheral logic area through a high-selectivity dry etching process, and planarize the surface of the pad oxide layer 20 of the peripheral logic area.
[0049] Step S3: Reference Figure 4 , Figure 4This is a schematic diagram of the semiconductor structure after the second hard mask layer is formed in an embodiment of the present application, wherein the second hard mask layer 32 is formed, and the second hard mask layer 32 covers the first hard mask layer 31 of the storage area and the pad oxide layer 20 of the peripheral logic area, wherein there is a certain height difference between the second hard mask layer 32 of the storage area and the second hard mask layer 32 of the peripheral logic area.
[0050] Preferably, the second hard mask layer 32 is formed by a high temperature furnace process.
[0051] In this embodiment, the second hard mask layer 32 is made of silicon nitride.
[0052] Furthermore, in the process of forming the second hard mask layer 32 by adopting the high temperature furnace tube process, the process temperature is 750° C. to 800° C., the nitrogen flow rate is 200 sccm to 300 sccm, and the process duration is 8 h to 10 h.
[0053] The height difference between the second hard mask layer 32 of the storage area and the second hard mask layer 32 of the peripheral logic area is equal to the thickness of the first hard mask layer 31 of the storage area.
[0054] Step S4: Reference Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after the first isolation trench and the second isolation trench are formed in an embodiment of the present application, and the second hard mask layer 32, the first hard mask layer 31, the liner oxide layer 20 and a partial thickness of the substrate 10 in the storage area are etched, and the second hard mask layer 32, the liner oxide layer 20 and a partial thickness of the substrate 10 in the peripheral logic area are etched to form a first isolation trench 51 in the storage area and a second isolation trench 52 in the peripheral logic area.
[0055] Among them, the depth of the second isolation trench 52 in the substrate 10 is greater than the depth of the first isolation trench 51 in the substrate 10, and the depth difference between the first isolation trench 51 and the second isolation trench 52 in the substrate 10 is greater than the height difference between the second hard mask layer 32 of the storage area and the second hard mask layer 32 of the peripheral logic area.
[0056] Preferably, the steps of etching the second hard mask layer 32, the first hard mask layer 31, the liner oxide layer 20 and a partial thickness of the substrate 10 in the storage area and etching the second hard mask layer 32, the liner oxide layer 20 and a partial thickness of the substrate 10 in the peripheral logic area to form the first isolation trench 51 in the storage area and the second isolation trench 52 in the peripheral logic area may specifically include:
[0057] Step S4.1: using a dry etching process to etch the second hard mask layer 32 of the storage area, the first hard mask layer 31 and the second hard mask layer 32 of the peripheral logic area, wherein the etching gases are CF4, O2 and Ar, the flow rate of the gas CF4 is 140 sccm to 210 sccm, and the flow rate of the gas O2 is 35 sccm to 52 sccm; the etching time is 2 min to 3 min;
[0058] Step S4.2: Etching the pad oxide layer 20 of the storage area and the pad oxide layer 20 of the peripheral logic area by dry etching process, wherein the etching gas is CHF3, O2 and Ar, the flow rate of CHF3 gas is 120sccm-180sccm, the flow rate of O2 gas is 20sccm-30sccm; the etching time is 20s-30s;
[0059] Step S4.3: Use a dry etching process to etch a portion of the thickness of the substrate 10 in the storage area and a portion of the thickness of the substrate 10 in the peripheral logic area, wherein the etching gases are CF4, CHF3, SF6, O2 and Ar, the flow rate of gas CF4 is 50sccm~70sccm, the flow rate of gas CHF3 is 30sccm~40sccm, and the flow rate of SF6 is 70sccm~100sccm; the etching time is 20min~25min.
[0060] Since the etching gas in the above step S4.3 has a greater selectivity to the substrate (silicon substrate) than to the first hard mask layer (silicon nitride), the second hard mask layer (silicon nitride) and the pad oxide layer, and since there is only the second hard mask layer on the surface of the peripheral logic area, and there are the second hard mask layer and the first hard mask layer on the surface of the storage area, the substrate has begun to be etched in the peripheral logic area before the first hard mask layer and the second hard mask layer in the storage area are fully opened. As time goes by, the peripheral logic area will etch the substrate with a step difference greater than the second hard mask layer between the storage area and the peripheral logic area. Therefore, the depth difference between the first isolation trench 51 and the second isolation trench 52 in the substrate 10 will be greater than the height difference between the second hard mask layer 32 in the storage area and the second hard mask layer 32 in the peripheral logic area.
[0061] Furthermore, after forming the first isolation trench 51 and the second isolation trench 52, the method for preparing the flash memory device may also include: filling the first isolation trench 51 and the second isolation trench 52 with an isolation material layer and depositing an isolation material layer on the surface of the second hard mask layer 32, grinding and removing excess isolation material layer through a CMP process to obtain a shallow trench isolation structure of the storage area and a shallow trench isolation structure of the peripheral logic area, respectively, and other conventional process steps for preparing a flash memory device.
[0062] In the present application, the first isolation trench of the storage area and the second isolation trench of the peripheral logic area are prepared based on the CAA&PAA combined plate preparation process. The present application first uses the liner oxide layer as the etching barrier layer (etching stop layer) of the first hard mask layer of the peripheral logic area, etches and removes the first hard mask layer of the peripheral logic area, and then deposits the second hard mask layer through a high-temperature furnace tube process, thereby improving the thickness uniformity of the second hard mask layer of the peripheral logic area, and forming a stable hard mask layer material step difference between the storage area and the peripheral logic area, which can stabilize the depth of the subsequent second isolation trench of the peripheral logic area. Therefore, a second isolation trench with a depth greater than the first isolation trench of the storage area can be etched in the peripheral logic area through a dry etching process, thereby avoiding the large process fluctuation of the depth of the isolation trench of the peripheral logic area in the traditional CAA&PAA combined plate preparation process and the difficulty in accurately controlling the depth difference between the first isolation trench of the storage area and the second isolation trench of the peripheral logic area. Furthermore, the second hard mask layer in the peripheral logic area of the present application is subsequently used as a grinding barrier layer for the shallow trench isolation structure in the peripheral logic area and the floating gate layer in the storage area, thereby increasing the process windows of the subsequent CMP process of the shallow trench isolation structure in the peripheral logic area and the CMP process of the floating gate layer in the storage area. The precise and controllable thickness of the second hard mask layer in the peripheral logic area is beneficial to stabilizing the height of the shallow trench isolation structure in the peripheral logic area and the process thickness of the floating gate layer, thereby improving the electrical performance of the device.
[0063] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for preparing a flash memory device, characterized in that: include: Providing a substrate, the substrate comprising a storage area and a peripheral logic area, and a pad oxide layer and a first hard mask layer are formed on the surface of the substrate; Etching and removing the first hard mask layer of the peripheral logic area, and stopping at the surface of the pad oxide layer; forming a second hard mask layer, wherein the second hard mask layer covers the first hard mask layer of the storage area and the pad oxide layer of the peripheral logic area, wherein there is a certain height difference between the second hard mask layer of the storage area and the second hard mask layer of the peripheral logic area; The second hard mask layer, the first hard mask layer, the pad oxide layer and a partial thickness of the substrate in the storage area are etched, and the second hard mask layer, the pad oxide layer and a partial thickness of the substrate in the peripheral logic area are etched to form a first isolation trench in the storage area and a second isolation trench in the peripheral logic area, wherein the depth of the second isolation trench in the substrate is greater than the depth of the first isolation trench in the substrate, and the depth difference between the first isolation trench and the second isolation trench in the substrate is greater than the height difference between the second hard mask layer in the storage area and the second hard mask layer in the peripheral logic area.
2. The method for preparing a flash memory device according to claim 1, wherein: A high-selectivity dry etching process is used to etch away the first hard mask layer of the peripheral logic area and stop at the surface of the pad oxide layer.
3. The method for preparing a flash memory device according to claim 1, wherein: In the process of etching and removing the first hard mask layer of the peripheral logic area by using a high-selectivity dry etching process, the etching gases used are CF4, O2 and Ar, wherein the ratio of gas CF4 to gas O2 is 4:1 to 4.2:
1.
4. The method for preparing a flash memory device according to claim 1, wherein: The second hard mask layer is formed by a high temperature furnace process.
5. The method for preparing a flash memory device according to claim 4, characterized in that: In the process of forming the second hard mask layer by adopting the high temperature furnace tube process, the process temperature is 750° C. to 800° C., the nitrogen flow rate is 200 sccm to 300 sccm, and the process duration is 8 h to 10 h.
6. The method for preparing a flash memory device according to claim 1, characterized in that: The material of the second hard mask layer is silicon nitride.
7. The method for preparing a flash memory device according to claim 1, characterized in that: A height difference between the second hard mask layer of the memory area and the second hard mask layer of the peripheral logic area is equal to a thickness of the first hard mask layer of the memory area.
8. The method for preparing a flash memory device according to claim 1, wherein: The steps of etching the second hard mask layer, the first hard mask layer, the liner oxide layer and a partial thickness of the substrate in the storage area and etching the second hard mask layer, the liner oxide layer and a partial thickness of the substrate in the peripheral logic area to form a first isolation trench in the storage area and a second isolation trench in the peripheral logic area include: The second hard mask layer of the storage area, the first hard mask layer and the second hard mask layer of the peripheral logic area are etched by a dry etching process, wherein the etching gases are CF4, O2 and Ar, the flow rate of the gas CF4 is 140sccm to 210sccm, and the flow rate of the gas O2 is 35sccm to 52sccm; the etching time is 2min to 3min; The pad oxide layer of the storage area and the pad oxide layer of the peripheral logic area are etched by a dry etching process, wherein the etching gases are CHF3, O2 and Ar, the flow rate of the CHF3 gas is 120sccm to 180sccm, and the flow rate of the O2 gas is 20sccm to 30sccm; the etching time is 20s to 30s; A dry etching process is used to etch a partial thickness of the substrate in the storage area and a partial thickness of the substrate in the peripheral logic area, wherein the etching gases are CF4, CHF3, SF6, O2 and Ar, the flow rate of gas CF4 is 50sccm~70sccm, the flow rate of gas CHF3 is 30sccm~40sccm, and the flow rate of SF6 is 70sccm~100sccm; the etching time is 20min~25min.
9. The method for preparing a flash memory device according to claim 1, characterized in that: The thickness of the first hard mask layer is 10. The method for preparing a flash memory device according to claim 1, characterized in that: The material of the first hard mask layer is silicon nitride.