A critical path optimization method, electronic device and storage medium

Abstract

The application relates to the field of EDA verification, in particular to a critical path optimization method, an electronic device and a storage medium, which obtains a timing dependency graph, and performs timing network and data flow localization on a critical path based on the timing dependency graph to obtain an optimization result. The timing dependency graph obtaining step comprises obtaining a detailed timing graph (DTG) and obtaining fixed units in data flow localization (DLOC); nodes in the DTG are traversed, when a node is a floating node, the floating node is combined with directly connected anchor points to generate a pin-based timing dependency graph (pin_TDG). The optimization of the critical path based on the timing dependency graph can associate the timing network and the data flow localization, and the two are no longer two completely independent processes, thereby solving the technical problem that the timing network and the data flow localization are independent and cannot be associated and optimized in the prior art.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of EDA verification, and in particular to a critical path optimization method, an electronic device and a storage medium. BACKGROUND

[0002] When a chip design is completed, the chip design needs to be simulated by a simulation processor. The chip design is designed for a physical processor, while the processor used for simulation generally uses a chip such as FPGA. Since the physical processor and the simulation processor are not the same type of processor, the standard cell libraries of the two are different. Therefore, in order to simulate the chip design using the simulation processor, the chip design needs to be adaptively modified before being divided into the corresponding simulation processor. For example, the timing logic cell in the original chip design needs to be replaced with a clock model. After the division step is completed, the chip design that has been divided into different simulation processors needs to be routed, and the process of routing involves optimization of the critical path, and the optimization means at least includes localization of the timing network and localization of the data flow, and the optimization purpose is to reduce the delay on the critical path and improve the performance of the chip.

[0003] Sequential localization (SLOC) generally focuses on reducing the number of clock path transitions by moving and / or duplicating circuit cells.

[0004] Unlike SLOC, data localization (DLOC) focuses on improving the slack of data paths by moving and / or duplicating cells. Since DLOC is a dynamic programming (DP) based method, moving and / or duplicating timing logic cells is not allowed in the heuristic algorithm, because moving timing logic cells will cause a dead cycle in the timing graph, which will violate the optimal condition of DP.

[0005] Since the methods adopted by SLOC and DLOC are essentially significantly different from each other, they are usually executed separately in the traditional localization framework. This framework has several shortcomings:

[0006] First, since LOC and DLOC are separate steps, their results will be submitted to the netlist immediately after completion. The timing structure between SLOC and LOC is completely different, and it is difficult to associate the optimization results and the optimization process of each other, resulting in redundant duplication.

[0007] Second, the traditional timing network localization SLOC is mainly based on netlist, which cannot accurately simulate timing criticality. Therefore, it is easy to have problems of area overflow and redundant replication. Compared with area overflow which leads to localization failure, the problem of redundant replication is more difficult, because redundant replication generates more endpoints that need to be optimized, which leads to more chip interconnections and worse quality of result (QoR). SUMMARY

[0008] For the first technical problem, the technical solution adopted by the present application is as follows: a critical path optimization method, the method comprising the following steps:

[0009] S100, acquiring a timing dependency graph, comprising:

[0010] S110, acquiring a detailed timing graph DTG, wherein the DTG includes a plurality of nodes and edges between the nodes, each node is a timing logic unit or a pin of a combinational logic unit, and each edge is a timing arc.

[0011] S120, acquiring a fixed unit in data flow localization DLOC.

[0012] S130, traversing the nodes in the DTG to generate a pin-based timing dependency graph pin_TDG; wherein when the ith node is traversed, the value of i ranges from 1 to N, N is the number of nodes in the DTG, and the following steps are included:

[0013] S131, when the ith node is an anchor point, directly traverse the i+1th node; wherein the conditions under which the ith node is an anchor point include that the ith node is a port, the ith node belongs to the pins of the fixed unit, and / or the ith node is a pin of the timing logic unit.

[0014] S132, otherwise, the ith node is a floating node, merge the ith node and its edges into the anchor point directly connected to the ith node, and after the merging is completed, traverse the i+1th node.

[0015] S200, localizing the timing logic on the critical path of the timing network and the data flow based on the timing dependency graph to obtain a localization result.

[0016] In addition, the present application also provides a non-transitory computer readable storage medium, the storage medium stores at least one instruction or at least one program, the at least one instruction or the at least one program is loaded and executed by the processor to realize the above method.

[0017] In addition, the present application also provides an electronic device, comprising a processor and the above non-transitory computer readable storage medium.

[0018] The present application has at least the following beneficial effects:

[0019] The application provides a critical path optimization method, an electronic device and a storage medium, which obtains a timing dependency graph, and localizes timing logic on a critical path of a timing network and a data flow based on the timing dependency graph to obtain a localization result. The timing dependency graph is obtained by traversing nodes in the DTG, and in the traversal process, it is determined whether the current node is an anchor point. When it is not an anchor point, the floating node is merged into the directly connected anchor point to obtain a timing dependency graph containing only anchor points. Optimizing the critical path based on the timing dependency graph can localize the timing network and the data flow and associate them. The two are no longer two completely independent processes, solving the technical problem that the localization of the timing network and the data flow in the prior art is independent and cannot be associated and optimized. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 A critical path optimization method flowchart is provided for the embodiments of the present application.

[0022] Figure 2 A timing dependency graph acquisition step flowchart is provided for the embodiments of the present application.

[0023] Figure 3 A partial node schematic diagram in a detailed timing diagram.

[0024] Figure 4 A schematic diagram of a first clock path in a timing dependency graph. Figure 3 A schematic diagram of a pin_TDG finally obtained.

[0025] Figure 5 A critical path optimization method flowchart based on a timing dependency graph is provided for the embodiments of the present application.

[0026] Figure 6 A schematic diagram of a first clock path in a timing dependency graph.

[0027] Figure 7 A schematic diagram of a connection structure in a detailed timing diagram. Figure 6 A schematic diagram of a connection structure in a detailed timing diagram.

[0028] Figure 8 A schematic diagram of a connection structure after data flow localization and instantiation. Figure 7

[0029] ​Figure 9 is a connection structure diagram in a detailed timing graph;

[0030] Figure 10 is a result diagram after timing network localization and instantiation;

[0031] Figure 11 is a result diagram after dynamic programming;

[0032] Figure 12 is a result diagram after relaxation;

[0033] Figure 13 is a result diagram after distillation. DETAILED DESCRIPTION

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0035] To solve the first technical problem, the present application provides embodiment one.

[0036] Embodiment one

[0037] Please refer to Figure 1 which shows a critical path optimization method flowchart, the method comprising the following steps:

[0038] S100, acquiring a timing dependency graph.

[0039] Further, please refer to Figure 2 S100 further comprises:

[0040] S110, acquiring a detailed timing graph DTG, wherein the DTG comprises a plurality of nodes and edges between the nodes, each node is a pin of a timing logic unit or a combinational logic unit, and each edge is a timing arc.

[0041] The detailed timing graph (DTG) describes the timing relationship and signal propagation delay between various components in a digital circuit design. The components are timing logic units or combinational logic units, for example, the timing logic unit is a register or a latch, and the combinational logic gate is a lookup table or a multiplexer.

[0042] In the DTG, the nodes represent pins in the circuit, and the pins can be pins of timing logic units or pins of combinational logic units.

[0043] Timing Arcs in the DTG, which are used to connect nodes, represent the path of signal propagation between two nodes. Timing Arc defines the causal relationship between two pins in terms of timing.

[0044] In the DTG, each edge or node is attached with detailed information about timing, such as delay, setup time, hold time, clock skew, etc. By traversing the Timing Graph, the STA tool can identify all possible clock paths and calculate the arrival time of each timing node.

[0045] S120, obtaining a fixed unit in data stream localization DLOC.

[0046] In the data stream localization (DLOC), the focus is on improving the relaxation of the path by moving and / or copying the combinational logic unit to achieve the purpose of critical path optimization.

[0047] In the DLOC, moving and / or copying includes moving, copying, moving and copying.

[0048] In the DLOC, the fixed units configured in the DLOC include timing logic units and endpoints, and the fixed units are not moved and / or copied during the DLOC process. Because in the process of DLOC, if the timing logic unit is also taken as the object of optimization, and the timing logic unit is moved and / or copied, due to the existence of ring timing dependency between the logic units in the timing graph, dynamic programming can always not reach the optimal, which will violate the best condition of dynamic programming.

[0049] S130, obtaining all anchor points in the DTG; wherein the ith node is an anchor point when the ith node meets the anchor point condition; otherwise, the ith node is a floating node; wherein the anchor point condition includes that the ith node is a port, the ith node belongs to the pins of the fixed unit, and / or the ith node is a pin of the timing logic unit; wherein the value range of i is 1 to N, and N is the number of nodes in the DTG.

[0050] In the chip design process, the port is a reserved external interface.

[0051] In the chip design process, the port is a reserved external interface.

[0052] S140, traversing the nodes in the DTG starting from each anchor point to generate a pin-based timing dependency graph pin_TDG; wherein when the rth anchor point is taken as the starting point to traverse to the ith node in the DTG, the value range of r is 1 to K, and K is the number of anchor points in the DTG.

[0053] S141, when the ith node is an anchor point, then end the traversal of the rth anchor point.

[0054] S142, when the ith node is a floating node, merge the ith node and its edges into the rth anchor point, after the merging, traverse the i+1th node.

[0055] It should be noted that the purpose of the traversal is to remove the nodes in the detailed timing graph (DTG) except the anchor points, and the most nodes among the nodes except the anchor points are the combinational logic units.

[0056] It should be noted that the pin_TDG is used for the timing network localization to move and / or copy the timing logic units to the target processor, and in the process, only the timing influence of the fan-out timing logic units when moving and / or copying a timing logic unit is concerned, that is, only the influence between the timing logic units is concerned, and the combinational logic units are not concerned.

[0057] In the pin_TDG obtained after the merging, only the anchor points are contained. And the condition that there is an edge between two nodes is that there is a DTG path which does not contain any other anchor points except the start and end nodes.

[0058] In the pin_TDG obtained after the merging of the floating nodes, the pin_TDG is still a directed graph. The pin_TDG reflects the mutual dependence relationship between the pins.

[0059] It should be noted that for each path between the nodes in the pin_TDG, the length of the path determines the lower bound of the optimal solution that can be achieved in the data flow localization, that is, the lower the lower bound is, the better the optimal timing that can be achieved is, and therefore the target of the timing circuit localization is to reduce the number of cross-chip connections of the paths between the timing logic units.

[0060] In the pin_TDG, for a specified pair of start and end points in the detailed timing graph (DTG), if the longest hop number of the path between the specified start and end points is N, then the path between the specified start and end points can always be optimized to the longest hop number N by moving and / or copying the nodes in the detailed timing graph to the target processor through DLOC.

[0061] Optionally, the search algorithm used in the traversal process is a depth-first search algorithm (DFS) or a breadth-first search algorithm (BFS). Other search algorithms also fall within the protection scope of the present application.

[0062] Preferably, the search algorithm is a depth-first search algorithm.

[0063] For the convenience of understanding, please refer toFigure 3 and Figure 4 In Figure 3 The figure is a schematic diagram of some nodes in the detailed timing graph, including the first node 10, the second node 20, the third node 30, the fourth node 40 and the fifth node 50. The first node 10, the fourth node 40 and the fifth node 50 are pins of the sequential logic, and the second node 20 and the third node 30 are pins of the combinational logic. Figure 4 The figure is a schematic diagram of some nodes in the detailed timing graph, including the first node 10, the second node 20, the third node 30, the fourth node 40 and the fifth node 50. The first node 10, the fourth node 40 and the fifth node 50 are pins of the sequential logic, and the second node 20 and the third node 30 are pins of the combinational logic. Figure 3 The figure is a schematic diagram of some nodes in the detailed timing graph, including the first node 10, the second node 20, the third node 30, the fourth node 40 and the fifth node 50. The first node 10, the fourth node 40 and the fifth node 50 are pins of the sequential logic, and the second node 20 and the third node 30 are pins of the combinational logic. Figure 3 The figure is a schematic diagram of some nodes in the detailed timing graph, including the first node 10, the second node 20, the third node 30, the fourth node 40 and the fifth node 50. The first node 10, the fourth node 40 and the fifth node 50 are pins of the sequential logic, and the second node 20 and the third node 30 are pins of the combinational logic.

[0064] As a preferred embodiment, in the process of critical path optimization, the target processor needs to be re-allocated to the cells on the critical path to reduce the path delay. When the target processor is re-allocated, the positions of the pins of the cells will also change with the change of the positions of the cells. The granularity of re-allocation in the timing network localization is a cell. Therefore, in order to obtain the timing dependency graph suitable for critical path optimization, S100 further includes:

[0065] S150, traversing all the anchors in the pin_TDG, merging the multiple anchors belonging to the same sequential logic or combinational logic into a cell node, and deleting the self-loop edges to obtain a timing dependency graph based on the cell node, cell_TDG.

[0066] It should be noted that the cell_TDG is a directed graph, which can directly reflect the dependency relationship between the cells.

[0067] The self-loop edge is an edge whose start point and end point are the same node.

[0068] The cell_TDG further includes clock paths and data paths. The clock paths are the paths that affect the clock in the chip design, and the data paths are the paths that affect the data in the chip design. The clock paths are mainly concentrated in the clock domain, and the data paths are mainly concentrated in the data domain. The number of data paths is much larger than the number of clock paths. The clock paths and the data paths are the basis for critical path optimization. The critical path optimization includes optimization through timing network localization and optimization through data flow localization. The objects optimized by the timing network localization are the clock paths, and the objects optimized by the data flow localization are the data paths. Therefore, before optimization, the two different paths need to be extracted from the cell_TDG.

[0069] S200, localizing the timing logic on the critical path of the timing network and the data flow based on the timing dependency graph, to obtain a localization result.

[0070] Further, S200 further comprises: S210, searching for a clock path for the timing network localization based on the timing dependency graph cell_TDG:

[0071] S211, dividing the cell nodes into two types of nodes according to whether each cell node in the cell_TDG belongs to a first clock model or a second clock model: a first type of cell node M1 belonging to the first clock model, and a second type of cell node M2 belonging to the second clock model.

[0072] Wherein, the structure of the first clock model or the second clock model is different. Since the timing logic cells in the original chip design have been replaced with clock models suitable for the processor when allocated to the processor, that is, the timing logic cells in the processor are clock models, and the clock model includes a first clock model and a second clock model, both of which are composed of timing logic cells and combinational logic cells, and the functions and internal structures of the two clock models are different.

[0073] As an example, taking a register as an example of a cell node in cell_TDG, both the first clock model and the second clock model include registers. In cell_TDG, if the register belongs to the first clock model, the cell node is M1; if it belongs to the second clock model, the cell node is M2. It should be noted that the cell node is not the clock model itself.

[0074] S212, obtaining different clock path types in cell_TDG according to the data flow direction between M1 and M2, the clock path types including: a first clock path in which data flows from M1 to M2, and a second clock path in which data flows from M2 to M1.

[0075] Wherein, the data flow direction is determined by the direction of the directed edge in cell_TDG, and the direction of the directed edge is the direction of data flow.

[0076] It should be noted that when optimizing the critical path, the critical path includes the first clock path and the second clock path, and the cell nodes in these paths need to be subjected to timing network localization, and through moving and / or copying to the target processor, zero-hop is achieved, and the time delay is reduced. In cell_TDG, the number of first paths is less than the number of second paths. In the process of timing network localization, the M1 to M1 path in cell_TDG is optimized.

[0077] Further, the obtaining step of the first clock path comprises:

[0078] S2121, performing a forward search algorithm starting from each M1 in the cell_TDG, and stopping when M2 is searched, to obtain a first clock path. Wherein, the processor to which M2 in the first clock path currently belongs is the target processor. In the process of localizing the timing network, all M1s in the first path are moved and / or copied to the target processor.

[0079] Preferably, the search algorithm is a depth-first search algorithm (DFS) or a breadth-first search algorithm (BFS). Other search algorithms for searching the first path are within the protection scope of the present application.

[0080] Preferably, the search algorithm is a depth-first search algorithm.

[0081] As a preferred embodiment, the S212 further comprises an obtaining step of a second clock path, which comprises:

[0082] S2122, performing a reverse search algorithm starting from each M1 in the cell_TDG, and stopping when M2 is searched, to obtain a second clock path composed of M2 and M1. Wherein, the processor to which M1 in the second clock path currently belongs is the target processor. In the process of localizing the timing network, all M2s in the second path are moved and / or copied to the target processor.

[0083] As a preferred embodiment, the lengths of the first clock path and the second clock path are optimized by the following steps, the optimization step comprising: first, starting from all M1 nodes, performing a reverse and forward search algorithm, and stopping when M2 nodes are encountered, and marking all traversed nodes as to-be-optimized nodes; starting from the M2 nodes in the to-be-optimized nodes, performing a reverse marking on all to-be-optimized nodes, and adding the processor where the starting node is located to the target processor set of the traversed nodes. Through this step, the lengths of all second clock paths (data flowing from M2 to M1), M1 to M1 paths, and first clock paths (data flowing from M1 to M2) will reach the minimum.

[0084] As a preferred embodiment, S200 further comprises: S220, performing timing network localization on each clock path to obtain a target processor; wherein, the target processor of M1 in the first clock path is the processor to which M2 belongs, and the target processor of M2 in the second clock path is the processor to which M1 belongs. By reconfiguring the target processor, the hop count between unit nodes can be reduced to zero hops.

[0085] In a preferred embodiment, S200 further includes:

[0086] S230, obtain the data path in cell_TDG, the data path being the path through which data flows from M2 into M2.

[0087] It's important to note that after clock paths are localized to zero-hop, data paths become timing-critical paths. The number of data paths is several orders of magnitude larger than that of clock paths. Localizing all of them to zero-hop paths is impractical due to the significant increase in partitioning and cell area.

[0088] Furthermore, to balance cell area and system performance, time-driven heuristic algorithms are typically used to optimize the data path. Therefore, S200 also includes: S240, performing data flow localization on the data path, wherein the i-th cell node M2 ​​is moved and / or copied on the data path. i The steps include:

[0089] S241, Obtain M2 i Fan-out nodes; when M2 i The fan-out node is the j-th element node M2. j At that time, obtain M2 j The processor it belongs to is G(M2) j ).

[0090] It should be noted that M2 i It must include at least one fan-out node. M2 i The movement and / or copying will directly affect M2. i Fan-in latency and M2 j Fan-in delay.

[0091] S242, comparing M2 i Move and / or copy to G(M2) j Before and after, M2 i The timing criticality of the input and fan-out pins, when timing benefits exist, will increase M2. i Move and / or copy to G(M2) j In this context, the temporal benefit is the reduction in latency on the critical path.

[0092] In a preferred embodiment, S242 further includes a step of obtaining time-series gains:

[0093] S2421, M2 i Move and / or copy M2 i To G(M2) j Before obtaining M2 i The worst relaxation min_slack among all inputsi and M2 j the worst slack in all fan-ins j .

[0094] It should be noted that when the processor to which a cell belongs is changed, the corresponding pin can be found by tracing back pin_TDG from cell_TDG, and then the corresponding timing can be found by tracing back DTG from pin_TDG.

[0095] S2422, if M2 i is configured into G(M2 j ), M2 i is acquired again. i the worst slack in all inputs j and M2 j .

[0096] S2423, if the minimum of min_slack i and min_slack j is smaller than the minimum of min_slack i and min_slack j , there is timing gain.

[0097] Other methods for acquiring timing gain before and after moving are within the protection scope of the present application.

[0098] As a preferred embodiment, the step of acquiring timing criticality comprises: finding the corresponding pin by tracing back pin_TDG from M2 i and M2 j in cell_TDG, and then finding the corresponding timing by tracing back DTG from pin_TDG. Other methods for finding timing in DTG according to M2 i and M2 j in cell_TDG are within the protection scope of the present application.

[0099] In summary, the application provides a critical path optimization method, which obtains a timing dependency graph, and obtains an optimization result by respectively localizing a timing network and a data flow based on the timing dependency graph. The timing dependency graph is obtained by traversing nodes in a DTG, and in the process of traversal, it is determined whether the current node is an anchor point. When it is not an anchor point, the floating node is merged into the directly connected anchor point to obtain a timing dependency graph containing only anchor points. Optimizing the critical path based on the timing dependency graph can localize the timing network and the data flow and associate them. The two are no longer two completely independent processes, solving the technical problem that the timing network and the data flow localization in the prior art are independent and cannot be associated and optimized, and providing a basis for solving redundant replication.

[0100] The embodiment of the application further provides a non-transitory computer-readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a method in the method embodiment, and the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided by the above-mentioned embodiment.

[0101] The embodiment of the application further provides an electronic device, comprising a processor and the aforementioned non-transitory computer-readable storage medium.

[0102] The embodiment of the application further provides a computer program product, which comprises program code, and when the program product is run on an electronic device, the program code is used to make the electronic device execute the steps in the method according to various exemplary embodiments of the application described in the specification.

[0103] To solve the second technical problem, the application provides embodiment two.

[0104] Embodiment two

[0105] Please refer to the accompanying drawings Figure 5 which shows a method flowchart for optimizing a critical path based on a timing dependency graph according to the embodiment two of the application, and the method comprises the following steps:

[0106] B100, a timing structure is established, and the timing structure comprises a cell_TDG based on a cell node.

[0107] It should be noted that the established timing structure further comprises a detailed timing graph DTG, a pin_TDG based on a pin, and a cell_TDG, and other timing structures established also fall within the protection scope of the application.

[0108] Among them, the timing dependency graph provided by the embodiment one of the application is applicable to the embodiment two of the application, and will not be repeated.

[0109] B300, obtaining the localization result of the timing logic on the critical path of the timing network according to the cell_TDG.

[0110] The timing network localization result comprises moving and / or copying the cell nodes in the clock path into the target processor and establishing the connection relationship between the moved and / or copied cell nodes and other nodes in the clock path. The step of establishing the connection relationship is referred to as an instantiation step, that is, the purpose of instantiation is to reestablish the connection relationship between the driving node and the fan-out node of the original node and the cell node after copying or moving, obtain the path after connection and ensure that the logical function is consistent with the original circuit. The original node is the cell node before moving and / or copying.

[0111] The target processor of the cell node moving and / or copying is obtained according to step S220 in embodiment one, and will not be described again. It should be noted that the target processor in the first clock path and the second clock path is the processor where the end point of the corresponding clock path is located.

[0112] As a preferred embodiment, B300 further comprises an instantiation step:

[0113] B310, obtaining the cell nodes in each clock path of the cell_TDG that are moved and / or copied to the respective target processor; each clock path comprises a start point and an end point.

[0114] The clock path comprises the first clock path and the second clock path. The clock path in embodiment one and the obtaining step thereof are also applicable to embodiment two of the present application, and will not be described again.

[0115] B330, the cell nodes moved and / or copied to the respective target processor are referred to as variable nodes, and the connection of each variable node is reestablished to obtain the timing network localization result.

[0116] It should be noted that the traditional timing network localization SLOC is mainly based on the netlist and cannot accurately simulate the timing criticality. Therefore, regional overflow and redundant copying will easily occur. Redundant copying is more troublesome than regional overflow because redundant copying will generate more nodes that need to be optimized, which leads to larger cuts and worse result quality (QoR). Regional overflow will lead to localization failure. The timing network localization provided by the present application depends on the cell_TDG, which can trace back to the detailed timing diagram, which can accurately simulate the timing criticality, and therefore can greatly reduce the problem of regional overflow and redundant copying.

[0117] Further, the step of reestablishing the connection comprises:

[0118] S331, the unit node before the moving and / or copying is referred to as an original node, and a detailed timing graph DTG is reversely searched according to a clock path where the original node is located, so as to obtain a target detailed path in the detailed timing graph; the target detailed path includes a driving node driving the original node and a driven node driven by the original node.

[0119] It should be noted that, according to the detailed timing graph in the embodiment one, the nodes in the detailed timing graph include not only the pins of the sequential logic units but also the pins of the combinational logic units. Therefore, the target detailed path reversely searched includes not only the pins of the sequential logic units but also the pins of the combinational logic units.

[0120] The driving node and the driven node can be pins of combinational logic units.

[0121] B333, according to a preset rule, the current variable node is connected with the driving node, and each driven node is connected with the current variable node or the original node with the shortest arrival time, so as to obtain an instantiation result of the current variable node. The logical connection relationship between the current variable node or the original node and other nodes is restored by the instantiation method. That is, if the arrival time of the current driven node and the current variable node is shorter than the arrival time of the driven node and the original node, the current driven node is connected with the current variable node; otherwise, the current driven node is connected with the original node.

[0122] As a preferred embodiment, B333 further includes the following steps of obtaining each driven node and the current variable node or the original node with the shortest arrival time: respectively estimating a first arrival time between the current driven node and the original node and a second arrival time between the current driven node and the variable node, when the first arrival time is shorter than the second arrival time, the current driven node is connected with the original node; otherwise, the current driven node is connected with the variable node. In this way, the time delay between the paths connected with each other can be the shortest. Other methods for connecting the driven node with the variable node or the original node with the shortest arrival time are also within the protection scope of the present application.

[0123] As a preferred embodiment, the preset rule in B333 comprises: obtaining a reference input pin of the original node driven by the driving node, connecting the reference input pin of the current variable node with the driving pin of the driving node; and obtaining a target input pin of the driven node, connecting the target input pin of the driven node with the driving pin of the current variable node or the original node. When the original node is variable, the original node is the variable node, and the logical connection relationship between the variable node and the driving node and the driven node is restored by the preset rule, so that the logical connection relationship is accurately restored. Other methods for establishing connection between the variable node, the original node, and the driving node and the driven node thereof also fall within the protection scope of the present application.

[0124] Other methods for moving and / or copying the corresponding unit node to the target processor and instantiating also fall within the protection scope of the present application.

[0125] For the convenience of understanding, taking two first clock paths as an example, please refer to Figure 6 、 Figure 7 and Figure 8 to understand the process of timing network localization.

[0126] Among them, please refer to Figure 6 , the figure shows two first clock paths in the timing dependency graph, which start from M1 and end at two M2, wherein the starting point M1 is the first register REG1, the first end point M21 is the second register REG2, and the second end point M22 is the third register REG3. At this time, REG1 is on the processor Fa, REG2 is on the processor Fb, and REG3 is on the processor Fc.

[0127] Among them, please refer to Figure 7 , Figure 7 for Figure 6 the connection structure in the detailed timing diagram, compared with the first clock path in the timing dependency graph, it restores the driving of the starting point REG1 in the chip design: the first combinational logic unit LUT1. The second combinational logic unit LUT2 on the sub-detailed path from REG1 to REG2, and the third combinational logic unit LUT3 on the sub-detailed path from REG1 to REG3. Among them, LUT2 and LUT3 are on the processor Fa. It should be noted that in the process of timing network localization, the processor where the driving node of the starting point is located does not need to be considered, so the processor where LUT1 is located is not considered.

[0128] Among them, please refer to Figure 8 , Figure 8 for the connection structure after data flow localization and instantiation based on the connection structure in Figure 7 , Figure 8REG1′ in the diagram is the modified node of REG1. When processing the path from M1 to M21, the target processor for REG1 is found to be processor Fb, where M21 is located. Therefore, REG1 is moved to the target processor Fb. When processing the path from M1 to M22, the target processor for REG1 is found to be processor Fc, where M22 is located. Therefore, the processor to which REG1′ is copied is configured as Fc. Figure 7 Obtaining the connection structure in Figure 8 The process includes: Based on B331 and B333, the driving node for REG1 is LUT1, and the fan-out nodes driven by REG1 are LUT2 and LUT3, respectively. LUT2 and LUT3 are also called driven nodes. REG1 and REG1' are connected to the driving node LUT1 respectively. If the arrival time from REG1 to LUT2 is less than the arrival time from REG1' to LUT2, then REG1 is connected to LUT2. If the arrival time from REG1 to LUT3 is greater than the arrival time from REG1' to LUT3, then REG1' is connected to LUT3. This yields... Figure 8 The connection structure after instantiation.

[0129] It should be noted that in B333, when establishing a connection between each driven node and the current replica node or the original node with the shortest arrival time, it is possible that the current replica node or the original node has no fan-out nodes. For example, for Figure 8 In this process, when the arrival time from REG1 to LUT2 is less than the arrival time from REG1' to LUT2, REG1 is connected to LUT2. When the arrival time from REG1 to LUT3 is also less than the arrival time from REG1' to LUT3, REG1 is connected to LUT3. At this time, the fanout of REG1' is not connected to any node, and its entire fanout is floating.

[0130] Based on the results of the previous iteration, B500 obtains the critical path with a specified optimization ratio in the chip design, uses the critical path as the object of the current iteration optimization, executes the next iteration optimization steps, and obtains the current iteration result.

[0131] In this process, after optimizing the cell nodes on the critical path of the clock path to zero hops, the data path becomes the critical path. The number of data paths is several orders of magnitude larger than that of clock paths. Localizing all data paths to zero hops is impractical, as this would significantly increase the partitioning and cell area. To balance cell area and system performance, dynamic programming (DP) is used to optimize the data paths and obtain the optimized results of data flow localization.

[0132] The data path in Embodiment 1 of the present invention is also applicable to Embodiment 2 of the present invention, which is a path from M2 to M2, and will not be described again.

[0133] It should be noted that after each iteration optimization step ends, the optimized critical path changes due to the time delay of the original critical path being optimized, and the system will select the worst critical path again for optimization based on the optimization that has been optimized, and optimize until the overall convergence. Each optimization of the iteration optimization step provided by the application is based on the results of the last optimization, and the timing structure is only constructed once. Subsequent iterations of the optimization do not need to construct the timing structure again, and the solution of the previous iteration does not need to be submitted to the netlist for further optimization. The iteration optimization step provided by the application reconstructs the label of each node according to the iteration result of the previous iteration, and performs delay evaluation and DP-based optimization according to the label. This is equivalent to starting timing evaluation and dynamic programming-based optimization again after applying the results of the last iteration to the netlist. For example, assuming that DLOC is performed three times, and the optimization ratio is 0.1 each time, the iteration optimization step provided by the application only needs to perform timing update and submit the netlist once, and perform dynamic programming three times. The traditional method needs to run this process three times, i.e., timing update, dynamic programming, and submitting the netlist. The method provided by the application only needs to run timing update and submit the netlist once compared to the traditional method, greatly reducing the optimization process and the amount of data to be processed, greatly saving the time to establish the timing structure, and greatly improving the Turn-Around-Time (TAT). With the increase of the number of iterations, the advantage of the iteration optimization step provided by the application is more significant.

[0134] In addition, in the optimization method provided by the embodiment of the application, the critical path of each optimization is based on the time of the last optimization iteration to determine the optimized data domain, and the traditional optimization method is based on the input time. Compared with the traditional optimization method, the iteration optimization step can change the target processor of a small part of the unit allocation and constantly reevaluate the timing. Using small changes in the netlist to update the timing can ensure that the timing estimates before and after optimization have high correlation.

[0135] Further, B500 further comprises the step of performing the next round of iteration optimization:

[0136] B510, performing initialization of dynamic programming (DP) on the unit nodes on the critical path according to the timing dependency graph, the timing network localization result and the data flow localization result, to obtain an initialization result.

[0137] Wherein, when performing the initialization of DP for the first time, the data flow localization result is initialized as empty. The data flow localization result is updated by the dynamic programming result obtained each time when performing DP, and then the initialization result is updated.

[0138] The time sequence dependency graph can trace the time sequence and its detailed connection structure in the detailed time sequence graph.

[0139] The time sequence network localization result is used as the basis for data flow localization. If the time sequence network localization result is changed and updated, the data flow localization needs to be re-executed. The data flow localization combined with the time sequence network localization result can avoid redundant copying.

[0140] The purpose of data flow localization is to improve the relaxation of the critical path by moving and / or copying the unit nodes, and the moved and / or copied unit nodes are combinational logic units.

[0141] In the iteration optimization step, if the time sequence network localization result is updated, it means that there is redundant copying and moving in the time sequence network localization result, and the result obtained by dynamic programming is not the optimal solution. When the time sequence network localization result or the data flow localization result is updated, the initialization result needs to be re-updated, and DP is executed again to obtain the optimal current iteration result. When the time sequence network localization result is no longer updated, it means that the optimal result is reached, and the current iteration is ended, and the final current iteration result is obtained.

[0142] B530, performing DP based on the initialization result to obtain a data flow localization result.

[0143] DP is an optimization of the data path. In the process of DP, only combinational logic units are allowed to be moved and / or copied, and timing logic units are not allowed to be moved and / or copied. DP calculates the delay on the critical path when each combinational logic unit is moved and / or copied to different processors, and the target processor of each combinational logic unit in the critical path with the shortest delay obtained by dynamic programming is used as the data flow localization result.

[0144] B550, distilling the data flow localization result to obtain an updated time sequence network localization result; if there is a timing logic unit deleted in the distillation process, returning to execute B500; otherwise, executing B570.

[0145] It should be noted that the distillation step will be called at the end of each DLOC iteration. If any timing logic unit is found to be deleted from the SLOC result, the current iteration step of DLOC will be redone using the distilled SLOC result until no further timing logic unit can be deleted. The distillation step further reduces the number of redundant copies caused by inaccurate timing during SLOC.

[0146] As a preferred embodiment, B550 further includes a distillation step:

[0147] B551, check the data stream localization result, when the current unit node without fan-out node is moved and / or copied when localized in the timing network, delete the current unit node.

[0148] For easy understanding, please refer to Figure 9 and Figure 10 , Figure 9 for the connection structure in the detailed timing diagram, Figure 9 the first node 1, the fourth node 4, the fifth node 5 and the sixth node 6 are all timing logic units, wherein the first node 1 is M1, and the fourth node 4, the fifth node 5 and the sixth node 6 are all M2. The second node 2 and the third node 3 are all combinational logic units, and the seventh node 7 and the eighth node 8 are all driver nodes, wherein the first node 1, the second node 2 and the sixth node 6 are all located in the processor F A , the fourth node 4 and the seventh node 7 are all located in the processor F B , and the fifth node 5 is located in the processor F C . Figure 10 is the result after timing network localization and instantiation, wherein the first node 1 is moved to the processor F B and at the same time is copied to the processor F C , wherein the node copied to the processor F C is marked as the copy node 1' of the first node 1. Figure 11 is the result diagram after dynamic programming, wherein the second node 2 is moved to the processor F B , the third node 3 is moved to the processor F C and at the same time is copied to the processor F A , wherein the node copied to the processor F A is marked as the copy node 3' of the third node 3. Figure 12 is the result diagram after relaxing the slack, since the slack of the fifth node 5 is large, the third node 3 is not moved to the processor F C and only the copy node 3' of the third node 3 copied to the processor F A in Figure 11 is retained, and the fifth node 5 is connected with the first node 1 through the copy node 3' to meet the requirements. Figure 13 is the result diagram after distillation, since the copy node 1' of the first node 1 is without fan-out and in a suspended state, the copy node 1' of the first node 1 is deleted to obtain the result after distillation.

[0149] As a preferred embodiment, B560 is further included to restore the connection relationship of the changed nodes to obtain the final data flow localization result. It should be noted that the unit nodes moved and / or copied to the target processor during the data flow localization process are the changed nodes. The connection relationship of the changed nodes is restored according to the step of B330, and thus is not described herein.

[0150] B570 is used to evaluate whether the delay between the processors is improved according to the data flow localization result. If the delay is improved, the data flow localization result is set as the current iteration result, and the process returns to B500. Otherwise, the iteration is stopped, and B700 is executed.

[0151] It should be noted that when the iteration result is not improved, it means that the iteration result has converged, and the optimal result is achieved.

[0152] B700 is used to update the netlist according to the current iteration result obtained after the iteration is completed.

[0153] It should be noted that the current iteration result includes the processor to which each unit node is moved and / or copied and the connection relationship thereof.

[0154] Compared with the prior art, the clock path and the data path are respectively optimized independently. After the optimization, the optimized result is directly used to update the netlist, and whether there is redundant copying between the clock path and the data path is not concerned. The present application can well fuse the results of the timing network localization and the data flow localization. For example, if the result of the timing network localization is changed during the data flow localization process, the iteration and update need to be performed again, and the technical problem of redundant copying is solved.

[0155] The embodiment of the present application further provides a non-transitory computer readable storage medium, which can be arranged in an electronic device to save at least one instruction or at least one program related to a method in the method embodiment, and the at least one instruction or the at least one program is loaded and executed by the processor to implement the method provided by the above-mentioned embodiment.

[0156] The embodiment of the present application further provides an electronic device, which comprises a processor and the aforementioned non-transitory computer readable storage medium.

[0157] The embodiment of the present application further provides a computer program product, which comprises a program code. When the program product is run on an electronic device, the program code is used to make the electronic device execute the steps in the method according to various exemplary embodiments of the present application described in the specification.

[0158] While certain specific embodiments of the application have been described in detail herein for the purposes of exemplification, numerous other variations and modifications will be apparent to persons skilled in the art. Alterations and modifications of detail can be made by those skilled in the art, having the benefit of the above description, without departing from the spirit and scope of the application. It is intended that all such alterations and modifications be included within the scope of the application whose limits are to be determined only by the appended claims.

Claims

1. A critical path optimization method, characterized in that, The method includes the following steps: S100, obtain the timing dependency graph, including: S110, obtain the detailed timing diagram DTG, which includes multiple nodes and edges between nodes. Each node is a pin of a sequential logic unit or a combinational logic unit, and each edge is a timing arc. S120, Obtain the fixed unit in the localized data stream DLOC; S130, Obtain all anchor points in the DTG; wherein, when the i-th node satisfies the anchor point condition, the i-th node is an anchor point; otherwise, the i-th node is a floating node; wherein, the anchor point condition includes the i-th node being a port, the i-th node being a pin of the fixed unit, and / or the i-th node being a pin of a sequential logic unit; wherein, the value of i ranges from 1 to N, and N is the number of nodes in the DTG; S140, starting from each anchor point, traverse the nodes in the DTG to generate a pin-based timing dependency graph pin_TDG; where, when traversing from the r-th anchor point to the i-th node of the DTG, the value of r ranges from 1 to K, where K is the number of anchor points in the DTG, including the following steps: S141, when the i-th node is an anchor point, the traversal of the r-th anchor point ends; S142, when the i-th node is a floating node, merge the i-th node and its edges into the r-th anchor point. After merging, traverse the (i+1)-th node. S200, based on the time dependency graph, the time logic on the critical path of the time network and data flow is localized to obtain the localization result; S100 also includes: S150, traverse all anchor points in pin_TDG, merge multiple anchor points belonging to the same sequential logic unit or combinational logic unit into one unit node, and delete self-loop edges to obtain the timing dependency graph cell_TDG based on unit nodes. The S200 also includes: S210, the step of searching for clock paths for localization of the timing network based on the timing dependency graph cell_TDG: S211, based on whether each cell node in cell_TDG belongs to the first clock model or the second clock model, the cell nodes are divided into two types of nodes: the first type of cell node M1 belonging to the first clock model and the second type of cell node M2 ​​belonging to the second clock model. S212, based on the data flow direction between M1 and M2, different clock path types in cell_TDG are obtained. The clock path types include: a first clock path where data flows from M1 to M2 and a second clock path where data flows from M2 to M1. S220, perform timing network localization on each clock path to obtain the target processor; wherein, in the first clock path, the target processor of M1 is the processor to which M2 belongs, and in the second clock path, the target processor of M2 is the processor mentioned in M1. S230, obtain the data path in cell_TDG, the data path being the path that includes data flowing from M2 into M2; S240, perform data stream localization on the data path, wherein the i-th node M2 ​​is moved and / or copied on the data path. i The steps include: S241, Obtain M2 i Fan-out nodes; when M2 i The fan-out node is the j-th node M2. j At that time, obtain M2 j The processor it belongs to is G(M2) j ); S242, according to M2 i and M2 j Find pin_TDG and DTG sequentially to obtain M2. i The worst relaxation min_slack among all fan-in inputs i and M2 j The worst relaxation min_slack among all fan-in inputs j ; S242, if M2 i Move and / or copy to G(M2) j In ), again based on M2 i and M2 j M2 is obtained by sequentially searching pin_TDG and DTG. i The worst relaxation min_slack among all fan-in inputs i ´ and M2 j The worst relaxation min_slack among all fan-in inputs j ´; S243, if min_slack i and min_slack j The minimum value in is less than min_slack i ´ and min_slack j When the minimum value of ´ is reached, M2 will be... i Move and / or copy to G(M2) j Otherwise, M2 will not be included. i Move and / or copy to G(M2) j )middle.

2. The method according to claim 1, characterized in that, In S212, the step of obtaining the first type of clock path includes: S2121: Starting with each M1 in cell_TDG, perform a forward search algorithm. Stop when M2 is found, and obtain the first clock path.

3. The method according to claim 1, characterized in that, S212 further includes a step for obtaining a second clock path, including: S2122, starting with each M1 in cell_TDG, executes a reverse search algorithm, stopping when M2 is found, thus obtaining a second clock path consisting of M2 to M1.

4. The method according to claim 1, characterized in that, The lengths of the first and second clock paths are optimized through the following steps: First, start with all M1 nodes and perform reverse and forward search algorithms. Stop when an M2 node is encountered and mark all traversed nodes as nodes to be optimized. Starting from the M2 node among the nodes to be optimized, reverse mark all nodes to be optimized and add the processor where the starting node is located to the target processor set of the traversed nodes.

5. The method according to claim 2, 3 or 4, characterized in that, The search algorithm is either a depth-first search algorithm or a breadth-first search algorithm.

6. A non-transitory computer-readable storage medium, wherein the storage medium stores at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by the processor to implement the method as described in any one of claims 1-5.

7. An electronic device, characterized in that, Includes a processor and the non-transitory computer-readable storage medium as described in claim 6.

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