Display back panel and display device

Abstract

The present application discloses a display backplane and a display device; the display backplane includes a sub-pixel unit and a mirror current source module, each sub-pixel unit includes a pixel driving circuit with an adjustment module and a light-emitting device, the mirror current source module is electrically connected to the adjustment modules in multiple pixel driving circuits, the mirror current source module is used to adjust the adjustment current input to the adjustment module, and the adjustment current input to sub-pixel units of different colors by the mirror current source module is different; the present application adjusts the adjustment current input to sub-pixel units of different colors by setting a mirror current source module connected to the adjustment module in the pixel driving circuit in the display backplane, so as to make the sub-pixel units of different colors drive the light-emitting devices to emit light with different driving currents, so that the light-emitting devices of different colors have preset luminous flux, and combines the digital sub-field scanning method to realize the regulation of different grayscales, so that the display backplane can achieve full-color display at the existing clock frequency.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display backplane and a display device. Background Art

[0002] Micro light-emitting diodes, such as Mini LED and Micro LED, have significant advantages such as higher brightness, better luminous efficiency and lower power consumption, and have become the focus of research in the display panel industry.

[0003] Currently, monochrome array display drivers for micro-LEDs typically utilize digital sub-field scanning for monochrome display. However, with increasing requirements for display panel resolution, refresh rate, and grayscale, and the need for 256 grayscales for each RGB sub-pixel in order to achieve full-color RGB display, existing clock frequencies are unable to meet the requirements for full-color display.

[0004] Therefore, a display backplane is urgently needed to solve the above technical problems. Summary of the Invention

[0005] The present application provides a display backplane and a display device to solve the technical problem that the existing display backplane cannot display full color due to the limitation of clock frequency.

[0006] To solve the above problem, the technical solution provided by this application is as follows:

[0007] The present application provides a display backplane, comprising:

[0008] a plurality of sub-pixel units, each of the sub-pixel units comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit comprising a signal receiving module, a signal storage module, a switch module, and a regulating module, the signal receiving module receiving a data signal from a data signal source and transmitting the data signal to the signal storage module and the switch module, the signal storage module being configured to store the data signal, and the switch module being configured to transmit a regulated current from the regulating module to the light-emitting device; and

[0009] a mirror current source module, electrically connected to the regulating modules in the plurality of pixel driving circuits, the mirror current source module being used to regulate a regulating current input to the regulating module;

[0010] Among them, the multiple sub-pixel units include multiple first sub-pixel units, multiple second sub-pixel units, and multiple third sub-pixel units. The luminous colors of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different, and the adjustment currents of the adjustment modules input by the mirror current source module to the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different.

[0011] In the display backplane of the present application, the mirror current source module includes a first mirror current unit, a second mirror current unit, and a third mirror current unit. The first mirror current unit is electrically connected to the adjustment module of at least one column of the first sub-pixel unit, the second mirror current unit is electrically connected to the adjustment module of at least one column of the second sub-pixel unit, and the third mirror current unit is electrically connected to the adjustment module of at least one column of the third sub-pixel unit.

[0012] In the display backplane of the present application, the mirror current source module includes a plurality of cascaded first mirror current units, a plurality of cascaded second mirror current units, and a plurality of cascaded third mirror current units;

[0013] Among them, a first mirror current unit is electrically connected to the adjustment module of a column of the first sub-pixel units, a second mirror current unit is electrically connected to the adjustment module of a column of the second sub-pixel units, and a second mirror current unit is electrically connected to the adjustment module of a column of the second sub-pixel units.

[0014] In the display backplane of the present application, the plurality of sub-pixel units include a first sub-pixel group and a second sub-pixel group arranged along a column direction;

[0015] In which, the display backplane includes a first mirror current source module and a second mirror current source module mirrored on both sides of the multiple sub-pixel units, the first mirror current source module is electrically connected to the adjustment module in the first sub-pixel group, and the second mirror current source module is electrically connected to the adjustment module in the second sub-pixel group.

[0016] In the display backplane of the present application, the display backplane further comprises a plurality of first transmission lines, a plurality of second transmission lines and a plurality of third transmission lines;

[0017] The first mirror current unit is electrically connected to the corresponding regulating module through a plurality of the first transmission lines, the second mirror current unit is electrically connected to the corresponding regulating module through a plurality of the second transmission lines, and the third mirror current unit is electrically connected to the corresponding regulating module through a plurality of the third transmission lines;

[0018] The first transmission line, the second transmission line and the third transmission line are arranged in different layers.

[0019] In the display backplane of the present application, the first end of the signal receiving module is connected to the scanning signal source, the second end of the signal receiving module is connected to the data signal source, the third end of the signal receiving module, the first end of the signal storage module, and the first end of the switch module are connected to the first node, the second end of the switch module is connected to the adjustment module, the third end of the switch module is connected to the light-emitting device, and the second end of the signal storage module and the adjustment module are connected to the constant voltage high level source.

[0020] In the display backplane of the present application, the switch module includes a first transistor, the signal receiving module includes a second transistor, the regulating module includes a third transistor, and the signal storage module includes a storage capacitor;

[0021] Among them, the gate of the second transistor is connected to the scan signal source, the source of the second transistor is connected to the first data signal source, the drain of the second transistor is connected to the first plate of the storage capacitor and the gate of the first transistor, the source of the first transistor is connected to the drain of the third transistor, the drain of the first transistor is connected to the anode of the light-emitting device, the source of the third transistor is connected to the constant voltage high-level source and the second plate of the storage capacitor, and the gate of the third transistor is connected to the mirror current source module.

[0022] In the display backplane of the present application, the first transistor, the second transistor, and the third transistor are P-type transistors.

[0023] In the display backplane of the present application, the signal receiving module includes a first receiving module and a second receiving module, the first ends of the first receiving module and the second receiving module are connected to a scanning signal source, the second end of the first receiving module is connected to a first data signal source, the second end of the second receiving module is connected to a second data signal source, the third end of the second receiving module, the first end of the signal storage module, and the first end of the switch module are connected to a second node, the third end of the first receiving module and the second end of the signal storage module are connected to a third node, the second end of the switch module is connected to the adjustment module, the third end of the switch module is connected to the light-emitting device, and the third end of the signal storage module and the adjustment module are connected to the constant voltage high level source.

[0024] In the display backplane of the present application, the switch module includes a first transistor, the first receiving module includes a first receiving transistor, the second receiving module includes a second receiving transistor, the adjustment module includes a third transistor, and the signal storage module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0025] The gate of the first receiving transistor is connected to a scan signal source, the source of the first receiving transistor is connected to a first data signal source, and the drain of the first receiving transistor is connected to the gates of the seventh and ninth transistors, the source of the eighth transistor, and the drain of the tenth transistor.

[0026] The gate of the second receiving transistor is connected to a scan signal source, the source of the second receiving transistor is connected to a second data signal source, and the drain of the second receiving transistor is connected to the gates of the eighth transistor and the tenth transistor, the source of the seventh transistor, the drain of the ninth transistor, and the gate of the first transistor;

[0027] The drains of the seventh transistor and the eighth transistor are connected to a constant voltage low-level source, the sources of the ninth transistor and the tenth transistor are connected to a constant voltage high-level source, the source of the first transistor is connected to the drain of the third transistor, the drain of the first transistor is connected to the anode of the light-emitting device, the source of the third transistor is connected to the constant voltage high-level source, and the gate of the third transistor is connected to the mirror current source module.

[0028] In the display backplane of the present application, the first receiving transistor, the second receiving transistor, the seventh transistor and the eighth transistor are N-type transistors, and the first transistor, the third transistor, the ninth transistor and the tenth transistor are P-type transistors.

[0029] In the display backplane of the present application, the mirror current unit in the mirror current source module includes a current source, a fourth transistor, a fifth transistor and a sixth transistor;

[0030] In which, the first end of the current source is connected to the digital-to-analog converter, the second end of the current source is connected to the gates of the fifth transistor and the sixth transistor, and the source of the sixth transistor, the drains of the fifth transistor and the sixth transistor are connected to a constant voltage low-level source, the source of the fifth transistor is connected to the gates of the third transistor and the fourth transistor, and the drain of the fourth transistor, and the source of the fourth transistor is connected to a constant voltage high-level source.

[0031] In the display backplane of the present application, the fourth transistor is a P-type transistor, and the fifth transistor and the sixth transistor are N-type transistors.

[0032] In the display backplane of the present application, the pixel driving circuit further includes a reference current line, and the reference current line is electrically connected to the gates of the third transistor and the fourth transistor.

[0033] In the display backplane of the present application, the display backplane further includes a timing controller, a data processor, a row scanning circuit, and a column scanning circuit, wherein the row scanning circuit is connected to the scanning lines in the display backplane, and the column scanning circuit is connected to the data lines in the display backplane;

[0034] The timing controller transmits a scan signal to the row scan circuit, and the timing controller controls the data processor to transmit a data signal to the column scan circuit.

[0035] In the display backplane of the present application, each sub-pixel unit includes multiple frames of display data, each frame of display data includes multiple sub-frames, each sub-frame includes a data writing phase and a light-emitting phase, and the light-emitting durations of the light-emitting phases in different sub-frames are different;

[0036] Wherein, when the data signal source received by the sub-pixel unit in the writing phase is a high level, the sub-pixel unit continues to emit light in the corresponding light-emitting phase; when the data signal source received by the sub-pixel unit in the writing phase is a low level, the sub-pixel unit does not emit light in the corresponding light-emitting phase; or,

[0037] When the data signal source received by the sub-pixel unit in the writing phase is at a low level, the sub-pixel unit continues to emit light in the corresponding light-emitting phase; when the data signal source received by the sub-pixel unit in the writing phase is at a high level, the sub-pixel unit does not emit light in the corresponding light-emitting phase.

[0038] The present application also proposes a display device, which includes the above-mentioned display backplane.

[0039] Beneficial effects: The present application sets a mirror current source module in the display backplane that is connected to the adjustment module in the pixel driving circuit to adjust the adjustment current input to the sub-pixel units of different colors, so that the sub-pixel units of different colors drive the light-emitting devices to emit light with different driving currents, so that the light-emitting devices of different colors have preset luminous fluxes, and combines the digital sub-field scanning method to achieve regulation of different gray levels, so that the display backplane can achieve full-color display at the existing clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0041] Figure 1 A simplified structural diagram of the back panel is shown for this application;

[0042] Figure 2 This is a sub-field segmentation diagram of a frame of display data in the display backplane of this application;

[0043] Figure 3 This is a schematic diagram of the first mirror current source module and circuit connection of the display backplane of this application;

[0044] Figure 4 This is a connection diagram of the first pixel driving circuit and mirror current unit of the display backplane of this application;

[0045] Figure 5 This is a connection diagram of the second pixel driving circuit and mirror current unit of the display backplane of this application;

[0046] Figure 6 This is a schematic diagram of the color RGB display of the display backplane in one frame of this application;

[0047] Figure 7 This is a schematic diagram of image data sub-field processing in the display backplane of this application;

[0048] Figure 8 A timing diagram showing the backplane neutron field scan for this application is shown;

[0049] Figure 9 This is a simplified structural diagram of the column scanning circuit in the display backplane of this application;

[0050] Figure 10 This is a schematic diagram of the second mirror current source module and circuit connection of the display backplane of this application;

[0051] Figure 11 This is a schematic diagram showing the third mirror current source module and circuit connection of the backplane of this application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0053] Currently, drivers for monochrome array displays of micro-LEDs typically utilize digital subfield scanning for monochrome display. However, with increasing demands for display panel resolution, refresh rate, and grayscale, and the need for 256 grayscale levels for each RGB subpixel to achieve full-color RGB display, existing clock frequencies are no longer sufficient. Therefore, a display backplane is urgently needed to address these technical issues.

[0054] See also Figures 1 to 11 The present application provides a display backplane 100 , which includes a plurality of sub-pixel units 10 and a mirror current source module 200 .

[0055] In this embodiment, each of the sub-pixel units 10 includes a pixel driving circuit 110 and a light-emitting device LED. The pixel driving circuit 110 includes a signal receiving module 111, a signal storage module 112, a switch module 113 and an adjustment module 114. The signal receiving module 111 receives a data signal from a data signal source Data and transmits the data signal to the signal storage module 112 and the switch module 113. The signal storage module 112 is used to store the data signal, and the switch module 113 is used to transmit the adjustment current from the adjustment module 114 to the light-emitting device LED.

[0056] In this embodiment, the mirror current source module 200 is electrically connected to the regulating modules 114 in the plurality of pixel driving circuits 110 . The mirror current source module 200 is used to regulate the regulating current input to the regulating module 114 .

[0057] In this embodiment, the multiple sub-pixel units 10 include multiple first sub-pixel units 101 that emit a first color, multiple second sub-pixel units 102 that emit a second color, and multiple third sub-pixel units 103 that emit a third color. The light-emitting colors of the first sub-pixel unit 101, the second sub-pixel unit 102, and the third sub-pixel unit 103 are different. For example, the first sub-pixel unit 101 is a red sub-pixel, the second sub-pixel unit 102 is a green sub-pixel, and the third sub-pixel unit 103 is a blue sub-pixel. The adjustment currents of the adjustment module 114 input by the mirror current source module 200 to the first sub-pixel unit 101, the second sub-pixel unit 102, and the third sub-pixel unit 103 are different.

[0058] It should be noted that the display backplane 100 may include a display area and a non-display area. The display area is provided with multiple scan lines and multiple data lines, which intersect to form multiple sub-pixel units 10. The pixel driving circuit 110 in each sub-pixel unit 10 is connected to the corresponding data line and scan line. The mirror current source module 200 is provided in the non-display area to adjust the operating current of the light-emitting device LED by adjusting the current input to the adjustment module 114, thereby adjusting the luminous flux of the light-emitting device LED of different colors.

[0059] It should be noted that the display backplane 100 can be used as a direct display device. For example, the light-emitting device LED of the display backplane 100 can be Mini LED or Micro LED, etc., or the display backplane 100 can also be used as a backlight source for a liquid crystal display panel. The following is an example of the display backplane 100 being a direct display device.

[0060] Please note that Figure 1 The display backplane 100 may further include a timing controller 300, a data processor 400, a row scanning circuit 500 and a column scanning circuit 600, wherein the row scanning circuit 500 is connected to the scanning line in the display backplane 100, and the column scanning circuit 600 is connected to the data line in the display backplane 100; the timing controller 300 transmits a scanning signal to the row scanning circuit 500, and the timing controller 300 controls the data processor 400 to transmit a data signal to the column scanning circuit 600.

[0061] It should be noted that the present application can realize grayscale display by using subfield scanning, that is, the scanning time of each frame of the display screen is divided into subfields of different sizes, and each subfield is controlled to emit light separately. The total light-emitting time of each subfield is combined to achieve the control of the total light-emitting time in this frame, thereby controlling the lighting time of each display unit in the display panel, so as to achieve the effect of each display unit having different grayscales.

[0062] It should be noted that each sub-pixel unit 10 includes multiple frames of display data, each frame of display data includes multiple sub-frames, each sub-frame includes a data writing phase t1 and a light-emitting phase t2, and the light-emitting phase t2 within different sub-frames has different light-emitting durations. The weighting value of each sub-frame is different, that is, the duration of the light-emitting phase t2 within each sub-frame is different, and the lighting duration of the light-emitting device LED is different. The weighting value can be set in a standard binary weighting value increment or a non-standard binary weighting value increment.

[0063] exist Figure 2 In the structure of , a frame of 1H display data includes 8 subframes, namely subframe F1, subframe F2, subframe F3, subframe F4, subframe F5, subframe F6, subframe F7 and subframe F8, using the standard binary weighted value increasing method, and the weighted value ratio of each subframe is 1(2 0 ):2(2 1 ):4(2 2 ):8(2 3 ):16(2 4 ):32(2 5 ):64(2 6 ):128(2 7 ), the display data of a frame of 1H is superimposed with the grayscale of each sub-frame, thereby realizing 255 grayscale display. In order to improve the luminance of the L255 grayscale of the sub-pixel unit 10, when the scanning signal scans each row of sub-pixel units 10, the sub-pixel units 10 in each row emit light after the addressing scanning time. Each sub-pixel unit 10 can continue to emit light during the driving time of the entire frame display image.

[0064] That is, when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a high level, the sub-pixel unit 10 continues to emit light in the corresponding light-emitting stage t2; when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a low level, the sub-pixel unit 10 does not emit light in the corresponding light-emitting stage t2; or, when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a low level, the sub-pixel unit 10 continues to emit light in the corresponding light-emitting stage t2; when the data signal source Data received by the sub-pixel unit 10 in the writing stage t1 is a high level, the sub-pixel unit 10 does not emit light in the corresponding light-emitting stage t2.

[0065] For example, to achieve 256-level grayscale adjustment for a single green Micro-LED array with a display frequency of 60Hz and a resolution of 1280x1024, 8 subfields (denoted as subfields 1 to 8) constitute a frame. The t2 ratio of the 8 subfields' light-emitting phases is set to 1:2:4:8:16:32:64:128, and the data input to the 8 subfields is denoted as d1 to d8. The grayscale calculation method can be:

[0066] Grayscale (Gray) = 1*d1+2*d2+4*d3+8*d4+16*d5+32*d6+64*d7+128*d8.

[0067] For example, when the Data input to the mth subfield is high, dm = 1; when the Data input to the mth subfield is low, dm = 0. When the Data input to all subfields is high, d1 to d8 are all 1, and Gray = 256; when the Data input to all subfields is low, d1 to d8 are all 0, and Gray = 0.

[0068] It's important to note that in a full-color display, white light (W) is the sum of the three primary colors: red (R), green (G), and blue (B). Under fixed color coordinates, the ratio of their luminous flux is also fixed. For example, under color coordinates of W (0.300, 0.315), R (0.682, 0.317), G (0.250, 0.710), and B (0.138, 0.051), the RGB luminous flux ratio (ΦR:ΦG:ΦB) is 3.18:9.27:1.

[0069] However, the present application separately regulates the luminous flux and grayscale of RGB. The grayscale is achieved by sub-field scanning, while the luminous flux is regulated by setting a mirror current source module 200 in the display backplane 100 and connected to the adjustment module 114 in the pixel driving circuit 110 to adjust the current input to the light-emitting device LED in the pixel driving circuit 110 in different sub-pixel units 10, so that the sub-pixel units 10 of different colors drive the light-emitting device LED to emit light with a preset proportion of driving current, so that the light-emitting device LED of different colors has a preset luminous flux, so that the display backplane 100 can achieve full-color display at the existing clock frequency.

[0070] It should be noted that the arrangement of the multiple sub-pixel units 10 in this application is not specifically limited, and the following description will be made using standard RGB as an example.

[0071] The technical solution of this application is now described in conjunction with specific embodiments.

[0072] See also Figure 3 The multiple sub-pixel units 10 include multiple first sub-pixel units 101 that emit a first color, multiple second sub-pixel units 102 that emit a second color, and multiple third sub-pixel units 103 that emit a third color. The first sub-pixel units 101, the second sub-pixel units 102, and the third sub-pixel units 103 emit different colors of light. For example, the first sub-pixel unit 101 is a red sub-pixel, the second sub-pixel unit 102 is a green sub-pixel, and the third sub-pixel unit 103 is a blue sub-pixel.

[0073] In this embodiment, the mirror current source module 200 may include a first mirror current unit 210, a second mirror current unit 220, and a third mirror current unit 230. The first mirror current unit 210 is electrically connected to the adjustment module 114 of at least one column of the first sub-pixel unit 101, the second mirror current unit 220 is electrically connected to the adjustment module 114 of at least one column of the second sub-pixel unit 102, and the third mirror current unit 230 is electrically connected to the adjustment module 114 of at least one column of the third sub-pixel unit 103.

[0074] In this embodiment, the display backplane 100 may further include a plurality of first transmission lines 241, a plurality of second transmission lines 242, and a plurality of third transmission lines 243, with one transmission line corresponding to one column of sub-pixel units 10. Figure 3In the structure, one of the first transmission lines 241 is connected to the adjustment module 114 in a column of red sub-pixels, one of the second transmission line 242 is connected to the adjustment module 114 in a column of green sub-pixels, and one of the third transmission line 243 is connected to the adjustment module 114 in a column of blue sub-pixels. The number of columns of red sub-pixels is the same as the number of first transmission lines 241, the number of columns of green sub-pixels is the same as the number of second transmission lines 242, and the number of columns of blue sub-pixels is the same as the number of third transmission lines 243.

[0075] In this embodiment, multiple first transmission lines 241 are connected in parallel, multiple second transmission lines 242 are connected in parallel, multiple third transmission lines 243 are connected in parallel, the first mirror current unit 210 is connected to the multiple first transmission lines 241, the second mirror current unit 220 is connected to the multiple second transmission lines 242, and the third mirror current unit 230 is connected to the multiple third transmission lines 243; that is, the current of the regulation module 114 in all red sub-pixels in the display backplane 100 is regulated by the first mirror current unit 210, the current of the regulation module 114 in all green sub-pixels is regulated by the second mirror current unit 220, and the current of the regulation module 114 in all blue sub-pixels is regulated by the second mirror current unit 220.

[0076] In this embodiment, the first transmission line 241, the second transmission line 242, and the third transmission line 243 may be arranged in different layers. For example, multiple source and drain layers may be provided, with multiple first transmission lines 241, multiple second transmission lines 242, and multiple third transmission lines 243 arranged in different source and drain layers, or arranged in the same source and drain layer, and connected by metal bridges at the locations where the transmission lines intersect.

[0077] In this embodiment, since the extension direction of the first transmission line 241, the second transmission line 242 and the third transmission line 243 can be the same as the extension direction of the data line and the constant voltage high level line, and the voltage transmitted in the transmission line and the constant voltage high level line is a constant voltage, the transmission line and the constant voltage high level line can be set on both sides of the data line, so that the coupling capacitance generated by the data line and the transmission line and constant voltage high level line on both sides is offset.

[0078] In the display backplane 100 of the present application, the first end of the signal receiving module 111 is connected to the scanning signal source Gate, the second end of the signal receiving module 111 is connected to the data signal source Data, the third end of the signal receiving module 111, the first end of the signal storage module 112, and the first end of the switch module 113 are connected to the first node Q, the second end of the switch module 113 is connected to the adjustment module 114, the third end of the switch module 113 is connected to the light-emitting device LED, and the second end of the signal storage module 112 and the adjustment module 114 are connected to the constant voltage high level source VDD.

[0079] See also Figure 4 The switch module 113 may include a first transistor T1, the signal receiving module 111 may include a second transistor T2, the regulating module 114 may include a third transistor T3, and the signal storage module 112 may include a storage capacitor Cst.

[0080] In this example, see Figure 4 The gate of the second transistor T2 is connected to the scan signal source, the source of the second transistor T2 is connected to the data signal source Data, the drain of the second transistor T2 is connected to the first plate of the storage capacitor Cst and the gate of the first transistor T1, the source of the first transistor T1 is connected to the drain of the third transistor T3, the drain of the first transistor T1 is connected to the anode of the light-emitting device LED, the source of the third transistor T3 is connected to the constant voltage high-level source VDD and the second plate of the storage capacitor Cst, and the gate of the third transistor T3 is connected to the mirror current source module 200.

[0081] In this example, see Figure 4 The mirror current unit in the mirror current source module 200 includes a current source 240, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; a first end of the current source 240 is connected to the digital-to-analog converter, a second end of the current source 240 is connected to the gates of the fifth transistor T5 and the sixth transistor T6, and the source of the sixth transistor T6, the drains of the fifth transistor T5 and the sixth transistor T6 are connected to a constant low-level voltage source VSS, the source of the fifth transistor T5 is connected to the gates of the third transistor T3 and the fourth transistor T4, and the drain of the fourth transistor T4, and the source of the fourth transistor T4 is connected to a constant high-level voltage source VDD.

[0082] In this embodiment, the analog-to-digital converter 700 is a current-mode DAC, and different current mirror units have different analog-to-digital converters 700. Different color sub-pixels are independently controlled by different current-mode DACs. For example, the first current mirror unit 210 is controlled by a current-mode DAC corresponding to the red sub-pixel, the second current mirror unit 220 is controlled by a current-mode DAC corresponding to the green sub-pixel, and the third current mirror unit 230 is controlled by a current-mode DAC corresponding to the blue sub-pixel.

[0083] In this embodiment, the pixel driving circuit 100 further includes a reference current line Iref, which is electrically connected to the gates of the third transistor T3 and the fourth transistor T4. At the same time, a reference current line Iref is provided in each column of sub-pixel units 10, and the reference current line Iref transmits the reference current output from the mirror current unit to the gate terminal of the third transistor T3 in the sub-pixel units 10 in the same column.

[0084] In this embodiment, the first transistor T1 , the second transistor T2 , and the third transistor T3 are P-type transistors, the fourth transistor T4 is a P-type transistor, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0085] Below Figure 4 The working principle of the circuit diagram is described in detail.

[0086] In the first phase, the low level transmitted by the data signal source Data turns on the second transistor T2. The data signal source transmits a low level to the first node Q through the source terminal of the second transistor T2, so that the first transistor T1 is turned on and the storage capacitor Cst begins to charge. At the same time, the analog-to-digital converter 700 receives data from the register and transmits a current signal to the current source 240, so that the current source 240 outputs the initial reference current Iref0.

[0087] The current mirror unit in this embodiment can accurately replicate the required current based on the W / L ratio of the corresponding transistor. For example, the fifth transistor T5 and the sixth transistor T6 form a first-stage current mirror circuit. Based on the characteristics of the current mirror circuit, the W / L parameters of the fifth transistor T5 and the sixth transistor T6 are adjusted. Then, the current flowing through the fifth transistor T5 can be k1*Iref0, where k1=(W5 / L5) / (W6 / L6).

[0088] At the same time, the third transistor T3 and the fourth transistor T4 form a second-stage mirror current circuit, and the W / L parameters of the third transistor T3 and the fourth transistor T4 are adjusted so that the current flowing through the third transistor T3 is k1*k2*Iref0, where k2=(W3 / L4) / (W4 / L4).

[0089] Therefore, since the first transistor T1 is turned on, the current flowing through the third transistor T3 is transferred to the light-emitting device LED through the source and drain of the first transistor T1, so that the light-emitting device LED emits light. The driving current of the light-emitting device LED is positively correlated with the initial reference current Iref0 output by the current source 240.

[0090] In the second stage, the storage capacitor Cst is discharged to maintain the potential of the first node Q, so that the first transistor T1 is turned on and the light emitting device LED continues to emit light.

[0091] In this embodiment, the present application can control the luminous brightness of the light-emitting device LED in the corresponding sub-pixel unit 10 by regulating the reference current output from the mirror current unit; and for sub-pixel units 10 of different colors, different reference currents can be set for sub-pixel units 10 of different colors. For example, under the color coordinate specifications of W (0.300, 0.315), R (0.682, 0.317), G (0.250, 0.710), and B (0.138, 0.051), the luminous flux ratio of RGB is ΦR:ΦG:ΦB=3.18:9.27:1. For details, please refer to the attached Figure 6 In the structure, the horizontal width is the luminous duration of the sub-pixel unit 10 of different colors, that is, the displayed grayscale, and the vertical height is the luminous brightness of the sub-pixels of different colors, that is, the luminous flux of the sub-pixels of different colors. Different luminous fluxes correspond to different driving currents of the light-emitting device LED. The present application can adjust the different reference currents output by the mirror current unit to make the light-emitting devices of different colors have different luminous fluxes, so that the luminous flux of the RGB sub-pixel unit meets the white light ratio in a preset ratio.

[0092] In the display backplane 100 of the present application, the signal receiving module 111 includes a first receiving module and a second receiving module, the first ends of the first receiving module and the second receiving module are connected to the scanning signal source Gate, the second end of the first receiving module is connected to the first data signal source Data1, the second end of the second receiving module is connected to the second data signal source Data2, the third end of the second receiving module, the first end of the signal storage module 112, and the first end of the switch module 113 are connected to the second node M, the third end of the first receiving module and the second end of the signal storage module 112 are connected to the third node N, the second end of the switch module 113 is connected to the adjustment module 114, the third end of the switch module 113 is connected to the light-emitting device LED, and the third end of the signal storage module 112 and the adjustment module 114 are connected to the constant voltage high level source VDD.

[0093] See also Figure 5The switch module 113 includes a first transistor T1, the first signal receiving module includes a first receiving transistor T21, the second signal receiving module includes a second receiving transistor T22, the adjustment module 114 includes a third transistor T3, and the signal storage module 112 includes a seventh transistor T7, an eighth transistor T8, a ninth transistor T9 and a tenth transistor T10.

[0094] See also Figure 5 The gate of the first receiving transistor T21 is connected to the scan signal source, the source of the first receiving transistor T21 is connected to the first data signal source Data1, and the drain of the first receiving transistor T21 is connected to the gates of the seventh transistor T7 and the ninth transistor T9, the source of the eighth transistor T8, and the drain of the tenth transistor T10; the gate of the second receiving transistor T22 is connected to the scan signal source, the source of the second receiving transistor T22 is connected to the second data signal source Data2, and the drain of the second receiving transistor T22 is connected to the eighth transistor T8 and the tenth transistor T10. The gate of the first transistor T1 is connected to the gate of the first transistor T10, the source of the seventh transistor T7, the drain of the ninth transistor T9, and the gate of the first transistor T1; the drains of the seventh transistor T7 and the eighth transistor T8 are connected to the constant voltage low level source VSS, the sources of the ninth transistor T9 and the tenth transistor T10 are connected to the constant voltage high level source VDD, the source of the first transistor T1 is connected to the drain of the third transistor T3, the drain of the first transistor T1 is connected to the anode of the light emitting device LED, the source of the third transistor T3 is connected to the constant voltage high level source VDD, and the gate of the third transistor T3 is connected to the mirror current source module 200.

[0095] In this embodiment, the pixel driving circuit 110 further includes a reference current line Iref, and the reference current line Iref is electrically connected to the gates of the third transistor T3 and the fourth transistor T4.

[0096] In this embodiment, the first receiving transistor T21, the second receiving transistor T22, the seventh transistor T7, and the eighth transistor T8 are N-type transistors, the first transistor T1, the third transistor T3, the ninth transistor T9, and the tenth transistor T10 are P-type transistors, the fourth transistor T4 is a P-type transistor, and the fifth transistor T5 and the sixth transistor T6 are N-type transistors.

[0097] Below Figure 5 The working principle of the circuit diagram is described in detail.

[0098] In the first stage, the signal storage module 112 is in the writing stage. The first data signal source Data1 is written at a low level, and the second data signal source Data2 is written at a high level. The high level output by the scanning signal source Scan turns on the second receiving transistor T22. The gate of the first transistor T1 is turned on by the low level output by the second data signal source Data2. The current output by the third transistor T3 is transmitted to the light-emitting device LED through the first transistor T1.

[0099] At the same time, the high level output by the scanning signal source Scan turns on the first receiving transistor T1, the gate of the seventh transistor T7 is turned on by the high level output by the first data signal source Data1, and the second node M between the seventh transistor T7 and the ninth transistor T9 is connected to the constant voltage low level source VSS, and the second node M maintains a low level; similarly, the gate of the tenth transistor T10 is turned on by the low level output by the second data signal source Data2, and the third node N between the eighth transistor T8 and the tenth transistor T10 is connected to the constant voltage high level source VDD, and the third node N maintains a high level.

[0100] In the second stage, the signal storage module 112 is in the reading stage, and the low level of the second node M maintains the first transistor T1 on, so that the light emitting device LED continues to emit light.

[0101] and Figure 4 Compared with the structure of FIG, this embodiment uses the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 to form two inverters, and the data signals transmitted by the first data signal source Data1 and the second data signal source Data2 are stored in the two inverters through the corresponding first receiving transistor T21 and the second receiving transistor T22 to replace the data signals transmitted by the first data signal source Data1 and the second data signal source Data2. Figure 4 The storage capacitor Cst in the storage capacitor Cst; since the capacitance in the storage capacitor Cst changes over time, the stored capacitance is unstable. In the second stage, the voltage data output by the storage capacitor Cst may be different from the voltage data input in the first stage. Figure 5 The inverter in the circuit outputs a digital signal that does not change over time and is more stable than a storage capacitor.

[0102] Secondly, Figure 5 The working principle of the mirror current unit in Figure 4 The mirror current source in is the same as that in the previous section. For the specific working principle, please refer to Figure 4 The recorded content.

[0103] It should be noted that Figure 4 and Figure 5 The pixel driving circuit 110 in the figure is only an example of the present application, and other pixel driving circuits 110 in the art are also applicable to the present application.

[0104] See also Figure 6 , Figure 6 This is a schematic diagram of the display backplane 100 of the present application displaying color RGB in one frame. The horizontal width is the luminous duration of the sub-pixel units 10 of different colors, that is, the displayed grayscale, and the vertical height is the luminous brightness of the sub-pixels of different colors, that is, the luminous flux.

[0105] In this embodiment, the light-emitting duration is achieved by sub-field scanning, for example Figure 7 In the structure, the binary value corresponding to the grayscale L200 is 00010011, the binary value corresponding to the grayscale L128 is 00000001, the binary value corresponding to the grayscale L64 is 00000010, and the binary value corresponding to the grayscale L0 is 00000000, and the binary value of each grayscale is parallel-to-serial converted. For example, the binary value of the first subframe SF is 0000, the binary value of the second subframe SF is 0000, the binary value of the third subframe SF is 0000, the binary value of the fourth subframe SF is 0001, the binary value of the fifth subframe SF is 0000, the binary value of the sixth subframe SF is 0000, the binary value of the seventh subframe SF is 0101, and the binary value of the eighth subframe SF is 1001; secondly, the data of the eight subfields in the above one frame are converted into serial values. Figure 8 The sub-field scanning timing in is written into the column scanning circuit 600.

[0106] See also Figure 9 , Figure 9 This is a structural diagram of the column scanning circuit 600 in the display backplane 100 of the present application. The column scanning circuit 600 may include modules such as a shift register, a latch, and a level shifter. The shift register and latch modules are activated by corresponding signal lines, and the shift register and latch modules perform serial-to-parallel conversion on the received binary data. The level shifter converts the potential corresponding to the "0" or "1" state into two potentials, one for turning off the pixel circuit driver tube and the other for turning on the pixel circuit driver tube, and outputs them from different output ports.

[0107] The present application separately regulates the luminous flux and grayscale of RGB. The grayscale is achieved by sub-field scanning, while the luminous flux is regulated by setting a mirror current source module 200 in the display backplane 100 and connected to the adjustment module 114 in the pixel driving circuit 110 to adjust the current input to the light-emitting device LED in the pixel driving circuit 110 in different sub-pixel units 10, so as to achieve different luminous fluxes of light-emitting devices LED of different colors, so that the display backplane 100 can achieve full-color display at the existing clock frequency.

[0108] As the resolution of the display device increases, the number of sub-pixel units 10 on the display backplane 100 increases, so that the potential received by the gate of the third transistor T3 of the sub-pixel unit 10 farther from the current source is different, for example Figure 3 In the structure, the reference currents transmitted from the mirror current source module 200 to the sub-pixel units 10 in different columns are different, thereby causing a display unevenness problem.

[0109] See also Figure 10 The mirror current source module 200 may include a plurality of cascaded first mirror current units 210, a plurality of cascaded second mirror current units 220, and a plurality of cascaded third mirror current units 230, wherein the plurality of cascaded first mirror current units 210 constitute a first mirror current group 211, the plurality of cascaded second mirror current units 220 constitute a second mirror current group 221, and the plurality of cascaded third mirror current units 230 constitute a third mirror current group 231; a first mirror current unit 210 is electrically connected to the adjustment module 114 of a column of the first sub-pixel units 101, a second mirror current unit 220 is electrically connected to the adjustment module 114 of a column of the second sub-pixel units 102, and a third mirror current unit 230 is electrically connected to the adjustment module 114 of a column of the third sub-pixel units 103.

[0110] and Figure 3 Compared with the structure of FIG, this embodiment provides the same number of mirror current units as the number of transmission lines, one transmission line is connected to one mirror current unit, and the number of first transmission lines 241 is the same as the number of first mirror current units 210, the number of second transmission lines 242 is the same as the number of second mirror current units 220, and the number of third transmission lines 243 is the same as the number of third mirror current units 230.

[0111] In this embodiment, any two first transmission lines 241 are separately provided, any two second transmission lines 242 are separately provided, and any two third transmission lines 243 are separately provided.

[0112] In this embodiment, due to the cascaded arrangement of multiple current mirror units, the current source 240 and the sixth transistor T6 in each current mirror unit are shared. The fourth transistor T4 and the fifth transistor T5 in each current mirror unit replicate the reference current output by the current source 240 and transmit it to the corresponding third transistor T3. The cascaded current mirror units provide each column of sub-pixel units 10 with an independent reference current, alleviating the technical issue of varying potentials received by the gate of the third transistor T3 due to transmission distance. Furthermore, each column of sub-pixel units 10 has an independent reference current, enhancing the stability of the pixel driver circuit 110.

[0113] In the display backplane 100 of this application, please refer to Figure 11 , the multiple sub-pixel units 10 include a first sub-pixel group 121 and a second sub-pixel group 122 arranged along the column direction; the display backplane 100 includes a first mirror current source module 131 and a second mirror current source module 132 mirrored on both sides of the multiple sub-pixel units 10, the first mirror current source module 131 is electrically connected to the adjustment module 114 in the first sub-pixel group 121, and the second mirror current source module 132 is electrically connected to the adjustment module 114 in the second sub-pixel group 122.

[0114] exist Figure 10 On the basis of FIG, since the number of sub-pixel units 10 in the column direction of the display backplane 100 is large, and due to the effect of the metal line impedance, the potential received by the gate of the third transistor T3 in the sub-pixel farther from the mirror current unit in the same column is different; and in this embodiment, the sub-pixels in the display backplane 100 are divided into upper and lower partitions, the first mirror current source module 131 is connected to the gate of the third transistor T3 in the first sub-pixel group 121, and the second mirror current source module 132 is connected to the gate of the third transistor T3 in the second sub-pixel group 122, so that the number of sub-pixel units 10 connected to each mirror current unit is reduced, Figure 10 compared to, Figure 11 The number of sub-pixel units 10 connected to a mirror current unit is reduced by one half, that is, the length of the corresponding transmission line is reduced by one half, thereby improving the technical problem that the potential received by the gate of the third transistor T3 has differences due to the transmission line impedance.

[0115] In this embodiment, Figure 10 and Figure 11 The pixel driving circuit 110 and the mirror current source module 200 can be connected to Figure 4 and Figure 5 The pixel driving circuit 110 and the mirror current source module 200 are the same.

[0116] This application also proposes a display device comprising a terminal body and the aforementioned display backplane, wherein the terminal body and the display panel are integrated into one body. For example, when the display backplane is a backlight source, the terminal body may be a liquid crystal display panel, and the display backplane and the liquid crystal display panel are combined to form the display device. When the display backplane is a direct display device, the terminal body may be a device such as a circuit board attached to the display panel, and a cover plate covering the display panel. The display device may include electronic devices such as mobile phones, televisions, and laptop computers.

[0117] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0118] The above is a detailed introduction to a display backplane and a display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display backplane, characterized in that: include: a plurality of sub-pixel units, each of the sub-pixel units comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit comprising a signal receiving module, a signal storage module, a switch module, and a regulating module, the signal receiving module receiving a data signal from a data signal source and transmitting the data signal to the signal storage module and the switch module, the signal storage module being configured to store the data signal, and the switch module being configured to transmit a regulated current from the regulating module to the light-emitting device; as well as a mirror current source module, electrically connected to the regulating modules in the plurality of pixel driving circuits, the mirror current source module being used to regulate a regulating current input to the regulating module; Among them, the multiple sub-pixel units include multiple first sub-pixel units, multiple second sub-pixel units, and multiple third sub-pixel units. The luminous colors of the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different, and the adjustment currents of the adjustment modules input by the mirror current source module to the first sub-pixel units, the second sub-pixel units, and the third sub-pixel units are different.

2. The display backplane according to claim 1, wherein: The mirror current source module includes a first mirror current unit, a second mirror current unit, and a third mirror current unit. The first mirror current unit is electrically connected to the adjustment module of at least one column of the first sub-pixel units, the second mirror current unit is electrically connected to the adjustment module of at least one column of the second sub-pixel units, and the third mirror current unit is electrically connected to the adjustment module of at least one column of the third sub-pixel units.

3. The display backplane according to claim 2, wherein: The mirror current source module includes a plurality of cascaded first mirror current units, a plurality of cascaded second mirror current units, and a plurality of cascaded third mirror current units; Among them, a first mirror current unit is electrically connected to the adjustment module of a column of the first sub-pixel units, a second mirror current unit is electrically connected to the adjustment module of a column of the second sub-pixel units, and a second mirror current unit is electrically connected to the adjustment module of a column of the second sub-pixel units.

4. The display backplane according to claim 2, wherein: The plurality of sub-pixel units include a first sub-pixel group and a second sub-pixel group arranged along a column direction; In which, the display backplane includes a first mirror current source module and a second mirror current source module mirrored on both sides of the multiple sub-pixel units, the first mirror current source module is electrically connected to the adjustment module in the first sub-pixel group, and the second mirror current source module is electrically connected to the adjustment module in the second sub-pixel group.

5. The display backplane according to any one of claims 2 to 4, characterized in that: The display backplane further includes a plurality of first transmission lines, a plurality of second transmission lines, and a plurality of third transmission lines; The first mirror current unit is electrically connected to the corresponding regulating module through a plurality of the first transmission lines, the second mirror current unit is electrically connected to the corresponding regulating module through a plurality of the second transmission lines, and the third mirror current unit is electrically connected to the corresponding regulating module through a plurality of the third transmission lines; The first transmission line, the second transmission line and the third transmission line are arranged in different layers.

6. The display backplane according to claim 5, wherein: The first end of the signal receiving module is connected to a scanning signal source, the second end of the signal receiving module is connected to a data signal source, the third end of the signal receiving module, the first end of the signal storage module, and the first end of the switch module are connected to a first node, the second end of the switch module is connected to the adjustment module, the third end of the switch module is connected to the light-emitting device, and the second end of the signal storage module and the adjustment module are connected to a constant voltage high-level source.

7. The display backplane according to claim 6, wherein: The switch module includes a first transistor, the signal receiving module includes a second transistor, the regulating module includes a third transistor, and the signal storage module includes a storage capacitor; Among them, the gate of the second transistor is connected to the scan signal source, the source of the second transistor is connected to the first data signal source, the drain of the second transistor is connected to the first plate of the storage capacitor and the gate of the first transistor, the source of the first transistor is connected to the drain of the third transistor, the drain of the first transistor is connected to the anode of the light-emitting device, the source of the third transistor is connected to the constant voltage high-level source and the second plate of the storage capacitor, and the gate of the third transistor is connected to the mirror current source module.

8. The display backplane according to claim 7, wherein: The first transistor, the second transistor, and the third transistor are P-type transistors.

9. The display backplane according to claim 5, wherein: The signal receiving module includes a first receiving module and a second receiving module, the first ends of the first receiving module and the second receiving module are connected to a scanning signal source, the second end of the first receiving module is connected to a first data signal source, the second end of the second receiving module is connected to a second data signal source, the third end of the second receiving module, the first end of the signal storage module, and the first end of the switch module are connected to a second node, the third end of the first receiving module and the second end of the signal storage module are connected to a third node, the second end of the switch module is connected to the adjustment module, the third end of the switch module is connected to the light-emitting device, and the third end of the signal storage module and the adjustment module are connected to a constant voltage high level source.

10. The display backplane according to claim 9, wherein: The switch module includes a first transistor, the first receiving module includes a first receiving transistor, the second receiving module includes a second receiving transistor, the regulating module includes a third transistor, and the signal storage module includes a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor; The gate of the first receiving transistor is connected to a scan signal source, the source of the first receiving transistor is connected to a first data signal source, and the drain of the first receiving transistor is connected to the gates of the seventh and ninth transistors, the source of the eighth transistor, and the drain of the tenth transistor. The gate of the second receiving transistor is connected to a scan signal source, the source of the second receiving transistor is connected to a second data signal source, and the drain of the second receiving transistor is connected to the gates of the eighth transistor and the tenth transistor, the source of the seventh transistor, the drain of the ninth transistor, and the gate of the first transistor; The drains of the seventh transistor and the eighth transistor are connected to a constant voltage low-level source, the sources of the ninth transistor and the tenth transistor are connected to a constant voltage high-level source, the source of the first transistor is connected to the drain of the third transistor, the drain of the first transistor is connected to the anode of the light-emitting device, the source of the third transistor is connected to the constant voltage high-level source, and the gate of the third transistor is connected to the mirror current source module.

11. The display backplane according to claim 10, wherein: The first receiving transistor, the second receiving transistor, the seventh transistor, and the eighth transistor are N-type transistors, and the first transistor, the third transistor, the ninth transistor, and the tenth transistor are P-type transistors.

12. The display backplane according to any one of claims 6 to 11, characterized in that: The mirror current unit in the mirror current source module includes a current source, a fourth transistor, a fifth transistor and a sixth transistor; In which, the first end of the current source is connected to the digital-to-analog converter, the second end of the current source is connected to the gates of the fifth transistor and the sixth transistor, and the source of the sixth transistor, the drains of the fifth transistor and the sixth transistor are connected to a constant voltage low-level source, the source of the fifth transistor is connected to the gates of the third transistor and the fourth transistor, and the drain of the fourth transistor, and the source of the fourth transistor is connected to a constant voltage high-level source.

13. The display backplane according to claim 12, wherein: The fourth transistor is a P-type transistor, and the fifth transistor and the sixth transistor are N-type transistors.

14. The display backplane according to claim 12, wherein: The pixel driving circuit further includes a reference current line electrically connected to the gates of the third transistor and the fourth transistor.

15. The display backplane according to claim 1, wherein: The display backplane further comprises a timing controller, a data processor, a row scanning circuit and a column scanning circuit, wherein the row scanning circuit is connected to the scanning lines in the display backplane, and the column scanning circuit is connected to the data lines in the display backplane; The timing controller transmits a scan signal to the row scan circuit, and the timing controller controls the data processor to transmit a data signal to the column scan circuit.

16. The display backplane according to claim 1, wherein: Each of the sub-pixel units includes multiple frames of display data, each frame of the display data includes multiple sub-frames, each sub-frame includes a data writing phase and a light-emitting phase, and the light-emitting durations of the light-emitting phases in different sub-frames are different; Wherein, when the data signal source received by the sub-pixel unit in the writing phase is a high level, the sub-pixel unit continues to emit light in the corresponding light-emitting phase; when the data signal source received by the sub-pixel unit in the writing phase is a low level, the sub-pixel unit does not emit light in the corresponding light-emitting phase; or, When the data signal source received by the sub-pixel unit in the writing phase is at a low level, the sub-pixel unit continues to emit light in the corresponding light-emitting phase. When the data signal source received by the sub-pixel unit in the writing phase is at a high level, the sub-pixel unit does not emit light in the corresponding light-emitting phase.

17. A display device, characterized in that: The display device comprises the display back panel according to any one of claims 1 to 16.

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