Memory system, memory device and method of forming same

Abstract

The semiconductor device includes a memory cell randomly presenting a first logic state or a second logic state and formed on a first side of a substrate; and a first bit line and a second bit line formed on a second side of the substrate opposite the first side. The memory cell includes: a program transistor having a first source / drain terminal and a second source / drain terminal; a first read transistor, a first source / drain terminal of the first read transistor being coupled to a first source / drain terminal of the program transistor; and a second read transistor having a first source / drain terminal coupled to a second source / drain terminal of the program transistor. A first bit line is operably coupled to a second source / drain terminal of the first read transistor, and a second bit line is operably coupled to a second source / drain terminal of the second read transistor. The embodiment of the invention also relates to a memory system and a method for forming the memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory system, a memory device, and a method for forming the same. Background Art

[0002] Integrated circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM), where data is not lost when the IC is powered off. One type of OTP device includes an anti-fuse memory. The anti-fuse memory includes a plurality of anti-fuse memory cells (or bit cells) whose terminals are disconnected before programming and short-circuited (e.g., connected) after programming. The anti-fuse memory can be based on metal oxide semiconductor (MOS) technology. For example, the anti-fuse memory cell can include a programming MOS transistor (or MOS capacitor) coupled in series and at least one reading MOS transistor. The gate dielectric of the programming MOS transistor can be broken down so that the gate and source or drain of the programming MOS transistor are interconnected. Depending on whether the gate dielectric of the programming MOS transistor is broken down, different data bits can be presented by the anti-fuse memory cell by reading the composite current flowing through the programming MOS transistor and the reading MOS transistor. The anti-fuse memory has the advantage of reverse engineering verification because the programming state of the anti-fuse cell is not determined by reverse engineering. Summary of the invention

[0003] Some embodiments of the present application provide a memory device, comprising: a memory cell, which randomly presents a first logic state or a second logic state, wherein the memory cell is formed on a first side of a substrate and comprises: a programming transistor, having a first source / drain terminal and a second source / drain terminal; a first read transistor, wherein the first source / drain terminal of the first read transistor is coupled to the first source / drain terminal of the programming transistor; and a second read transistor, wherein the first source / drain terminal of the second read transistor is coupled to the second source / drain terminal of the programming transistor; a first bit line formed on a second side of the substrate opposite to the first side; and a second bit line formed on the second side of the substrate; wherein the first bit line is operably coupled to the second source / drain terminal of the first read transistor, and the second bit line is operably coupled to the second source / drain terminal of the second read transistor.

[0004] Some other embodiments of the present application provide a memory system, comprising: a memory array, comprising a plurality of memory cells formed on a first side of a substrate, each of the plurality of memory cells presenting a logic state of any one of a first logic state or a second logic state, and comprising: a programming transistor, comprising a first source / drain terminal and a second source / drain terminal; a first reading transistor, comprising a first source / drain terminal operably coupled to the first source / drain terminal of the programming transistor, and a second source / drain terminal operably coupled to a first bit line formed on a second side of the substrate opposite to the first side; and a second reading transistor, comprising a first source / drain terminal coupled to the second source / drain terminal of the programming transistor, and a second source / drain terminal coupled to a second bit line formed on the second side of the substrate; and an authentication circuit, operably coupled to the memory array and configured to generate bits of a physically unclonable function (PUF) signature for each of the plurality of memory cells based on the logic state thereof.

[0005] Still other embodiments of the present application provide a method for forming a memory device, comprising: providing a substrate; forming a memory cell on a first side of the substrate, comprising: forming a programming transistor having a first source / drain terminal and a second source / drain terminal on the first side; forming a first read transistor on the first side, the first source / drain terminal of the first read transistor being coupled to the first source / drain terminal of the programming transistor; and forming a second read transistor on the first side, the first source / drain terminal of the second read transistor being coupled to the second source / drain terminal of the programming transistor; forming a first bit line formed on a second side of the substrate opposite to the first side; and forming a second bit line formed on the second side of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1A A block diagram of an exemplary memory system is shown in accordance with some embodiments.

[0008] Figure 1B According to some embodiments Figure 1A An exemplary circuit diagram of an anti-fuse memory cell of an anti-fuse memory array of a memory device in FIG.

[0009] Figure 1Cshows a circuit connected to a differential amplifier according to some embodiments Figure 1B An exemplary circuit diagram of an anti-fuse memory cell in FIG.

[0010] Figure 2A An exemplary circuit diagram of a portion of a memory device according to some embodiments is shown.

[0011] Figure 2B shows the formation according to some embodiments Figure 2A An exemplary layout of a portion of a memory device in FIG.

[0012] Figure 2C According to some embodiments Figure 2B An exemplary cross-sectional view of a portion of a memory device in FIG.

[0013] Figure 3 Exemplary circuit diagrams of portions of memory devices according to other embodiments are shown.

[0014] Figure 4 Exemplary circuit diagrams of portions of memory devices according to yet other embodiments are shown.

[0015] Figure 5 An exemplary circuit diagram of a portion of a memory device according to still other embodiments is shown.

[0016] Figure 6 is an exemplary flow chart of a method for operating a memory device according to some embodiments.

[0017] Figure 7 is an exemplary flow chart of a method for forming a memory device according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spatially relative terms such as "under," "beneath," "lower," "over," "upper," "top," "bottom," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0020] Physically Unclonable Functions (PUFs) are commonly used for authentication and key storage without the need for secure electrically erasable programmable read-only memory (EEPROM) and / or other expensive hardware (e.g., battery-backed static random access memory). Instead of storing secrets in digital memory, PUFs derive secrets from the physical properties of an integrated circuit (IC). PUFs are based on the idea that even if multiple ICs are manufactured using exactly the same manufacturing process, each IC may be slightly different from one another due to manufacturing variability. PUFs exploit this variability to obtain "secret" information unique to each IC (e.g., silicon biometrics). Typically, such secret information is referred to as the "PUF signature" of the IC. Furthermore, due to the manufacturing variability that defines the PUF signature, even if the design of the IC is fully understood, no two identical ICs can be manufactured. Various types of variability of the IC can be used to define such a signature, such as, for example, gate delays, the power-on state of the memory device, and / or any of the various physical properties of the IC.

[0021] Embodiments of the present disclosure provide various systems and methods for generating PUF signatures for / from a memory device including a plurality of memory cells. Each of the memory cells is implemented as an anti-fuse cell having a symmetrical configuration and includes at least: a first read transistor and a second read transistor; and a programming transistor, coupled in series between the first read transistor and the second read transistor and including a gate terminal having a gate metal and a gate dielectric layer. The gate dielectric layer includes a first dielectric portion coupled between the gate metal and the source / drain terminal of the programming transistor, and a second dielectric portion coupled between the gate metal and the other source / drain terminal of the programming transistor. Even if the first dielectric portion and the second dielectric portion of the gate dielectric layer of the programming transistor are formed of the same material and in the same size and are programmed simultaneously by the same programming voltage, one of the first dielectric portion and the second dielectric portion of the gate dielectric layer may be broken down before the other. When one of the first dielectric portion and the second dielectric portion is broken down, the programming process stops naturally. In other words, one of the two dielectric portions of the gate dielectric layer can be randomly programmed (or broken down) to equivalently form a resistor. Based on which of the first dielectric portion and the second dielectric portion has been broken down, the disclosed system can generate a PUF bit for / from a memory cell of a memory device. Applying the same principle to all memory cells, the disclosed system can generate a unique PUF signature for / from a memory device.

[0022] Because the read transistors are symmetrically arranged next to the programming transistors, the voltage level at the virtual node connecting the two read transistors to the virtual end of the programming transistor can be pulled closer to ground. Therefore, the programming voltage applied to the other virtual end of the programming transistor does not need to be so high to effectively program (or break down) the programming transistor. With such a symmetrical configuration, the memory cells of the memory device can be programmed at a relatively low programming voltage, thereby advantageously reducing power consumption and improving the life of the memory device.

[0023] In some embodiments, each of the anti-fuse cell memory cells includes a first read transistor and a second read transistor, a programming transistor coupled in series between the first read transistor and the second read transistor, one or more first-level (intermediate or complementary) transistors coupled in series between the programming transistor and the first read transistor, and one or more second-level (intermediate or complementary) transistors coupled in series between the programming transistor and the second read transistor. Each of the first-level transistors and the second-level transistors is formed to have the same structure and size. The number of first-level transistors (e.g., N=1, 2, 3, 4) and the number of second-level transistors are the same. Using additional level transistors, the IR drop in each of the memory cells can be reduced, thereby advantageously enhancing the programming and reading performance of the memory device.

[0024] In some embodiments, the memory device includes a programming transistor formed on the front side of the substrate and coupled in series between a first read transistor and a second read transistor, and a first bit line and a second bit line formed on the back side of the substrate and operably coupled to the first read transistor and the second read transistor. With such a configuration in which the bit lines are formed on the back side of the substrate, the PUF bit-cell size of the memory device is advantageously reduced.

[0025] Figure 1A 1 shows a memory system 100 according to various embodiments. Figure 1A As shown in FIG. 1 , memory system 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, authentication circuit 110, and control logic circuit 112. Although not shown in FIG. Figure 1A 1, all components of the memory system 100 may be coupled to each other and to the control logic circuit 112. Figure 1A In the illustrated embodiment of FIG. 1 , for the purpose of clarity of explanation, each component is shown as a separate box, but in some other embodiments, Figure 1A Some or all of the components shown in can be integrated together. For example, memory array 102 can include an embedded authentication circuit (eg, 110).

[0026] The memory array 102 is a hardware component that stores data. In one aspect, the memory array 102 is embodied as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other storage units) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R1 each extending in a first direction (e.g., X direction). M and a plurality of columns C1, C2, C3, ... C each extending in a second direction (eg, the Y direction). N Each of the rows / columns may include one or more conductive structures used as access lines. In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and may be operated based on a voltage or current through the corresponding conductive structures of the column and row.

[0027] Each memory cell 103 may be embodied as an anti-fuse memory cell. Figure 1B, the anti-fuse memory cell 103 includes a first read transistor 124 and a second read transistor 126, and a programming transistor 120 coupled in series therebetween. The programming transistor 120 includes a gate dielectric layer 123, which is disposed below the gate metal 121 and has a first dielectric portion 123A and a second dielectric portion 123B. The programming transistor 120 is programmed by applying a programming voltage, and randomly, one of the first dielectric portion 123A or the second dielectric portion 123B is broken down faster than the other. The programming then stops, and the other of the first dielectric portion 123A or the second dielectric portion 123B remains intact. Therefore, a logic state (e.g., 1 or 0) of the memory cell 103 can be generated based on which of the first dielectric portion 123A or the second dielectric portion 123B is broken down. Such randomly generated logic states for each of the memory cells 103 can form the basis of a PUF signature of the memory device 100.

[0028] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., a source line pair) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read, program) each of the memory cells 103 asserted by the row decoder 104 and the column decoder 106. The authentication circuit 110 is a hardware component that can generate a PUF signature based on the corresponding logic state of the memory cell read by the I / O circuit 108. The control logic circuit 112 is a hardware component that can control the coupled components (e.g., 102 to 110).

[0029] Figure 1B According to some embodiments Figure 1A 1 is an exemplary circuit diagram of a memory cell 103 of an array 102 of a memory device 100 in FIG. 1. In some embodiments, each memory cell 103 is embodied as an anti-fuse memory cell. It should be understood that the memory array 102 can have any number of anti-fuse memory cells 103 while remaining within the scope of the disclosed embodiments. Figure 1B The anti-fuse memory cell 103 in is explained in detail as a representative example in the following discussion.

[0030] In some embodiments, as mentioned above, Figure 1A Each of the memory cells 103 in the memory cell 104 may be operably coupled to the I / O circuit 108 for access (eg, programming or reading) via a corresponding program word line (WLP), read word line (WLR), and bit line (BL). Figure 1A and Figure 1B, the I / O circuit 108 may cause the row decoder 104 to assert WLP1, WLR1, and WLR2, and cause the column decoder 106 to assert BL1 and BL2, in order to select and thus enable programming or reading of a particular memory cell 103. Otherwise, the particular memory cell 103 is not selected and thus cannot be programmed or read. Thus, each of the memory cells 103 may be independently selected and thus may be programmed or read. Details regarding programming and reading memory cells will be discussed further below.

[0031] In some embodiments, each of the anti-fuse memory cells 103 includes one or more first read transistors and a second read transistor, and a programming transistor coupled in series between the one or more first read transistors and the second read transistor. In some embodiments, the number of the one or more first read transistors and the number of the one or more second read transistors are the same integer equal to or greater than 1 (such as 1, 2, 3 ... N).

[0032] like Figure 1B As shown in , in some embodiments, the memory cell 103 includes a programming transistor 120 gated by WLP1, a first read transistor 124 gated by WLR1, and a second read transistor 126 gated by WLR2, wherein the programming transistor 120 is coupled in series between the first read transistor 124 and the second read transistor 126. The source / drain (S / D) terminal of the first read transistor 124 is coupled to the first bit line BL1, and the source / drain (S / D) terminal of the second read transistor 126 is coupled to the second bit line BL2. More details on the configuration and connection of the memory cell 103 will be directed to Figure 2A , Figure 2B and Figure 2C To explain.

[0033] like Figure 1B As shown in , in some embodiments, the programming transistor 120 of the anti-fuse memory cell 103 includes a gate terminal 120G, the gate terminal 120G includes a gate metal 121 and a gate dielectric layer 123, the gate dielectric layer 123 is made of a dielectric material and is deposited below the gate metal 121. In some embodiments, the dielectric material of the gate dielectric layer 123 is selected from HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide and / or a combination thereof. The gate dielectric layer 123 includes a first dielectric portion 123A and a second dielectric portion 123B having the same size and can be turned on / off simultaneously or individually to enable / disable access to the programming transistor 120 (e.g., for programming or reading).

[0034] During the programming process, in some embodiments, to enable programming of the programming transistor 120 of the anti-fuse memory cell 103, a program enable voltage (e.g., 1.2V) may be applied simultaneously or separately to the gate 124G of the first read transistor 124 and the gate 126G of the second read transistor 126 of the memory cell 103. When enabled, the programming transistor 120 of the memory cell 103 may be programmed by applying a program voltage (e.g., 5V) to its gate 120G and applying a low bit line voltage (e.g., 0V) to the bit lines BL1 and BL2.

[0035] During the programming process, randomly, one of the first dielectric portion 123A and the second dielectric portion 123B of the gate dielectric layer 123 of the programming transistor 120 of the selected memory cell 103 may be broken down faster than the other, even if the probability or chance of either of them being broken down is 50%. After one of the first dielectric portion and the second dielectric portion (e.g., 123A) has been broken down first, the programming process stops, and thus the other (e.g., 123B) remains intact. Therefore, the logic state or a bit (e.g., 1) of the logic state (1 or 0) of the memory cell 103 can be randomly generated based on whether the first dielectric portion 123A or the second dielectric portion 123B of its gate dielectric layer 123 has been broken down, and thus a bit (or PUF signature bit) for the PUF signature of the anti-fuse memory cell 103 is generated. Such random generation is used Figure 1B The mechanism of applying the PUF signature bits in the anti-fuse memory cell 103 to Figure 1A In this way, it is possible to generate all memory cells 103. Figure 1A The PUF signature of the memory device 100 in FIG.

[0036] During a read process, in some embodiments, the anti-fuse memory cell 103 is selected and thus read by: applying a read select voltage (e.g., 1.5V) to the gate 120G of its programming transistor 120; applying a read select voltage (e.g., 0.75V Vdd) to the gate 124G of its first read transistor 124 and the gate 126G of its second read transistor 126; and applying a low BL voltage (e.g., 0V) to the corresponding source / drain terminals of its first read transistor 124 and the second read transistor 126 through the bit lines BL1 and BL2. During a read process, in other embodiments, the anti-fuse memory cell 103 is not selected and thus not read by: applying a non-select voltage (e.g., 0V) to the gate 120G of its programming transistor 120; applying a non-read voltage (e.g., Vss) to the gates of its first read transistor 124 and the second read transistor 126; and applying a high BL voltage (e.g., 0.75V) to its terminals coupled to BL1 and BL2, respectively.

[0037] Figure 1C shows a circuit connected to the differential amplifier 130 according to some embodiments. Figure 1B 1 is an exemplary circuit diagram of an anti-fuse memory cell 103 in FIG. In other embodiments, the anti-fuse memory cell includes a differential amplifier (not shown) therein while remaining within the scope of the disclosed embodiments. In some embodiments, the differential amplifier 130 has a first input terminal 131A and a second input terminal 131B coupled to the bit lines BL1 and BL2, respectively, and an output terminal 132 that outputs a state result (e.g., 1 or 0) of the memory cell 103. The result indicates whether the first dielectric portion 123A or the second dielectric portion 123B of the gate dielectric layer 123 of the memory cell 103 has been broken down based on the appreciable current detected in the first input terminal 131A or the second input terminal 131B, thereby determining the logic state of the memory cell 103.

[0038] For example, during a read process, when a significant current is detected in the first input terminal 131A, it is determined that the first dielectric portion 123A has been broken down, and thus the memory cell 103 is determined to be in the first logic state "1". Otherwise, when a significant current is detected in the second input terminal 131B, it is determined that the second dielectric portion 123B has been broken down, and thus the memory cell 103 is determined to be in the second logic state "0". Such a read Figure 1B The mechanism of the logical state of the memory cell 103 (PUF signature bit) is applied to Figure 1A In this way, all memory cells 103 are read and thus authenticated. Figure 1A The PUF signature of the memory device 100 in FIG.

[0039] Figure 2A 2 shows an exemplary circuit diagram of a memory device 200A according to some embodiments. Figure 2A The anti-fuse memory cell 103 of the memory device 200A shown in FIG. 1 is configured substantially similar to Figure 1B The anti-fuse memory cell 103 in FIG. Figure 2A As shown in , the anti-fuse memory cell 103 is implemented as a three-transistor (3T) symmetrical configuration and includes a programming transistor 120, a first read transistor 124, and a second read transistor 126, wherein the programming transistor 120 is electrically coupled in series between the first read transistor 124 and the second read transistor 126. In some embodiments, the memory device 200A also includes a first bit line BL1 and a second bit line BL2 coupled to the first read transistor 124 and the second read transistor 126 of the anti-fuse memory cell 103, respectively.

[0040] Also refer to Figure 2A, a source / drain terminal 120D of the programming transistor 120 is coupled to a source / drain terminal 124D of the first read transistor 124, and another source / drain terminal 120S of the programming transistor 120 is coupled to a source / drain terminal 126D of the second read transistor 126. The programming transistor 120 is gated by WLP1 via its gate terminal 120G, the first read transistor 124 is gated by WLR1 via its gate terminal 124G, and the second read transistor 126 is gated by WLR2 via its gate terminal 126G. In some embodiments, a source / drain terminal 124S of the first read transistor 124 is operably coupled to a first bit line BL1, and a source / drain terminal 126S of the second read transistor 126 is operably coupled to a second bit line BL2.

[0041] Further references Figure 2A , the gate terminal 120G of the anti-fuse memory cell 103 includes a gate metal 121 and a gate dielectric layer 123, and the gate dielectric layer 123 has a first dielectric portion 123A and a second dielectric portion 123B. The first dielectric portion 123A is coupled between the gate metal 121 and the source / drain terminal 120D of the programming transistor 120, and the second dielectric portion 123B is coupled between the gate metal 121 and the other source / drain terminal 120S of the programming transistor 120.

[0042] As mentioned above, based on which of the first dielectric portion 123A or the second dielectric portion 123B of the gate dielectric layer 123 of the memory cell 103 is determined to have been broken down, the memory cell 103 randomly assumes a logic state of either the first logic state (e.g., 1) or the second logic state (e.g., 0). Figure 1B The aforementioned method of the PUF signature bit (PUF signature bit) of the anti-fuse memory cell 103 is also applied to Figure 2A The anti-fuse memory cell 103 in FIG. Thus, a PUF signature for / from the memory device 200A may be generated and authenticated.

[0043] Figure 2B shows the formation according to some embodiments Figure 2A FIG. 2 is an exemplary layout 200B of the memory device 200A in FIG. Figure 2C According to some embodiments, Figure 2B200B is an exemplary cross-sectional view of a memory device 200C taken along line A1-A1 in FIG. Layout 200B includes a pattern 202 configured to form an active region (hereinafter referred to as “active region 202”), and a plurality of patterns 204, 206, and 208 configured to form gate structures (hereinafter referred to as “gate structure 204”, “gate structure 206”, and “gate structure 208”, respectively). It should be understood that for the purpose of illustration, the following is simplified. Figure 2B The layout 200B shown in FIG. 200B , and thus the layout 200B may include various other patterns while remaining within the scope of the embodiments of the present disclosure.

[0044] like Figure 2B As shown in FIG. 1 , the active region 202 may extend along a first lateral direction (eg, an X direction), while the gate structures 204, 206, and 208 may extend along a second lateral direction (eg, a Y direction) different from the first lateral direction. According to various embodiments, a layout for manufacturing an anti-fuse memory array may include a layout similar to that shown in FIG. Figure 2B The layout shown in FIG. 1 and multiple layouts are repeated along the X direction and the Y direction. However, it should be understood that such a layout may include any number of active regions and gate structures while remaining within the scope of the embodiments of the present disclosure.

[0045] According to an embodiment, the active region 202 is formed by a main surface (eg, Figure 2C The stack includes a plurality of semiconductor nanostructures (e.g., nanosheets) extending in the X direction and spaced apart vertically from each other. Portions of the semiconductor structures in the stack covered by gate structures 204, 206, and 208 are retained, while other portions are replaced with a plurality of epitaxial structures. In some embodiments, such active regions and gate structures are formed along the main front side surface of the substrate (sometimes referred to as part of the "front end of line (FEOL) process / network"). A plurality of front side metallization layers (e.g., Figure 2C M0 in (sometimes referred to as part of the "back-end of line (BEOL) processing / network") and on the backside surface of the substrate (e.g., Figure 2C A plurality of backside metallization layers (eg, Figure 2C BM0, BM1, BM2).

[0046] The remaining portion of the semiconductor structure can be configured as a channel of the corresponding transistor, the epitaxial structure coupled to both sides (or ends) of the remaining portion of the semiconductor structure can be configured as a source / drain structure (or terminal) of the transistor, and the portion of the gate structure covering (e.g., spanning) the remaining portion of the semiconductor structure can be configured as a gate structure (or terminal) of the transistor.

[0047] The portion of the active area portion 202 covered by the gate structure portion 206 may be formed and used as Figure 2A The channel of the programming transistor 120 in the active region portion 202 is replaced with an epitaxial structure. Such an epitaxial structure can be used as Figure 2A The gate structure portion 206 may be used as the source / drain terminals 120D and 120S of the programming transistor 120 in FIG. Figure 2A The gate terminal 120G of the programming transistor 120 in.

[0048] The portion of the active area portion 202 covered by the gate structure portion 204 may be formed and used as Figure 2A The channel of the first read transistor 124 in the active region portion 202 is replaced with an epitaxial structure. Such an epitaxial structure can be used as Figure 2A The gate structure portion 204 may be used as the source / drain terminals 124D and 124S of the first read transistor 124 in FIG. Figure 2A The gate terminal 124G of the first read transistor 124 in.

[0049] The portion of active area portion 202 covered by gate structure portion 208 may be formed and used as Figure 2A The channel of the second read transistor 126 in the active region portion 202 is replaced with an epitaxial structure. Such an epitaxial structure can be used as Figure 2A The gate structure portion 208 may be used as the source / drain terminals 126D and 126S of the second read transistor 126 in FIG. Figure 2A The gate terminal 126G of the second read transistor 126 in.

[0050] like Figure 2B As shown in , layout 200B also includes patterns for forming interconnect structures or via structures. For example, layout 200B includes patterns 211, 212, 213, and 214, each of which is configured to form a middle-end interconnect structure, sometimes referred to as an MD (hereinafter referred to as "MD 211", "MD 212", "MD 213", and "MD 214", respectively) that connects a corresponding source / drain terminal to an upper interconnect structure. Layout 200B also includes patterns 221, 222, 223, 224, and 225, each of which is configured to form a corresponding gate terminal (or gate structure) that connects to an upper interconnect structure (e.g., an M0 interconnect structure, such as MD211). Figure 2C) are sometimes referred to as VG (hereinafter referred to as “VG 221”, “VG 222”, “VG 223”, “VG 224” and “VG 225”, respectively).

[0051] Layout 200B also includes patterns 231 and 233, each of which is configured to form a backside via structure, sometimes referred to as a VB (hereinafter referred to as "VB 231" and "VB233", respectively), directly connected from its back side to the bottom of the corresponding MD (e.g., MD 211), and thereby connect the corresponding MD to the backside layer (e.g., BM0) on the back side of the substrate.

[0052] Over these mid-level structures on the front side of the substrate, metallization layers, such as M0, M1, M2, M3, etc., may be formed. Each of the metallization layers includes a plurality of metal tracks or lines (e.g., IMD / ILD) embedded in a corresponding dielectric material (e.g., IMD / ILD). Figure 2C 242, 243, 244 in the M0 layer). For example, the layout 200B may also include a pattern configured to form a metal track in the M0 layer (eg, Figure 2C “M0 track 242”, “M0 track 243” and “M0 track 244” in ).

[0053] The layout 200B may include other patterns to form corresponding interconnect structures or via structures to electrically couple a portion or component in one layer (e.g., M1) of the memory device to a corresponding portion or component in another layer (e.g., M2). For example, through via structures 222, 223, and 224 and other interconnect structures, the gate terminal 120G of the programming transistor 120 is coupled to WLP1, the gate terminal 124G of the first read transistor 124 is coupled to WLR1, and the gate terminal 126G of the second read transistor 126 is coupled to WLR2. For example, through VB 231 and VB 233 and other structures, the source / drain terminals 124S and 126S are respectively coupled to the bit lines BL1 and BL2 formed on the back side of the substrate ( Figure 2C middle).

[0054] like Figure 2B As shown in , in some embodiments, at least two VGs (such as 222 and 224) coupled to the gate terminals of the programming transistor and the reading transistor of the memory cell are formed along a virtual line (e.g., the X direction), and one of the VGs (such as 223) is offset relative to the virtual line. In other embodiments (not shown), all VGs (such as 222, 223, and 224) are aligned along the virtual line (e.g., the X direction).

[0055] refer to Figure 2CIn the active region 202, a plurality of channels (e.g., 251, 252, 253) and epitaxial structures (e.g., 261, 262, 263, 264) may be formed. Each of the channels may be covered or wrapped by a corresponding one of the gate structures (e.g., 124G, 120G, 126G), and each of the epitaxial structures may be covered by a corresponding one of the MDs (e.g., 211, 212, 213, 214). The programming transistor 120, the first read transistor 124, and the second read transistor 126 may be formed by the active region 202. VGs (e.g., 222, 223, and 224) are formed on the gate structures (e.g., 124G, 120G, 126G) to connect them to metal tracks (e.g., 242, 243, 244) formed in an upper layer (e.g., M0). VB (eg, 231 , 233 ) is formed to connect MD (eg, 211 , 214 ) of the second source / drain terminal 261 of the first read transistor 124 and the second source / drain terminal 264 of the second read transistor 126 to BL1 and BL2 disposed in the backside metallization layer (eg, BM0 ), respectively.

[0056] like Figure 2C As shown in , in some embodiments, a memory device 200C includes a substrate 201 having a first side (front side) 203 and a second side (back side) 205 opposite to the first side 203, and an anti-fuse memory cell 103 formed on the first side 203 of the substrate 201. The memory cell 103 randomly presents a first logic state (e.g., 1) or a second logic state (e.g., 0), and includes a programming transistor 120 having a first source / drain terminal 262 and a second source / drain terminal 263, a first read transistor 124, and a second read transistor 126, the first read transistor 124 having a first source / drain terminal 262 coupled to the first source / drain terminal of the programming transistor 120, and the second read transistor 126 having a first source / drain terminal 263 coupled to the second source / drain terminal of the programming transistor 120. The first read transistor 124 has a second source / drain terminal 261 operably coupled to a bit line BL1 disposed in a backside layer (e.g., BM0) via MD211 and VB 231, and the second read transistor 126 has a second source / drain terminal 264 operably coupled to a bit line BL2 disposed in a backside layer (e.g., BM0) via MD 214 and VB 233.

[0057] Figure 3 2 shows an exemplary circuit diagram of a memory device 300 according to other embodiments. In some embodiments, the memory device 300 includes an anti-fuse memory cell 103 and a first bit line BL1 and a second bit line BL2 coupled to the anti-fuse memory cell 103. Figure 3The anti-fuse memory cell 103 of the memory device 300 shown in FIG. 3 is configured substantially similar to the configuration shown in FIG. Figure 2A 1. The anti-fuse memory cell 103 of the memory device 200A shown in FIG. 1 is similar to the anti-fuse memory cell 103 of the memory device 200A shown in FIG. 1, but with some differences.

[0058] like Figure 3 As shown in the figure, the anti-fuse memory cell 103 of the memory device 300 is implemented as a five-transistor (5T) symmetrical configuration and includes a first read transistor 124, a second read transistor 126, a programming transistor 120 coupled in series between the first read transistor 124 and the second read transistor 126, a first-level transistor 302 coupled in series between the programming transistor 120 and the first read transistor 124, and a second-level transistor 304 coupled in series between the programming transistor 120 and the second read transistor 126.

[0059] Likewise Figure 3 As shown in , in some embodiments, programming transistor 120 is gated by WLP1, first read transistor 124 is gated by WLR1, second read transistor 126 is gated by WLR2, first stage transistor 302 is gated by WLB1, and second stage transistor 304 is gated by WLB2. In some embodiments, the source / drain terminal of first read transistor 124 is coupled to bit line BL1, and the source / drain terminal of second read transistor 126 is coupled to another bit line BL2. In some embodiments, reference Figure 2C , the anti-fuse memory cell 103 is formed over the front side 203 of the substrate 201 , and the bit lines BL1 and BL2 are formed in a metallization layer (eg, BM0 ) over the back side 205 of the substrate 201 .

[0060] Figure 4 2 shows an exemplary circuit diagram of a memory device 400 according to still other embodiments. Figure 4 The anti-fuse memory cell 103 of the memory device 400 shown in FIG. Figure 3 1. The anti-fuse memory cell 103 of the memory device 300 shown in FIG. 1 is similar to the anti-fuse memory cell 103 of the memory device 300 shown in FIG. 1, but with some differences.

[0061] like Figure 4 As shown in the figure, the anti-fuse memory cell 103 of the memory device 400 is implemented as a nine-transistor (9T) symmetrical configuration and includes a first read transistor 124 pair, a second read transistor 126 pair, a programming transistor 120 coupled in series between the first read transistor 124 pair and the second read transistor 126 pair, a first-level transistor 402 pair coupled in series between the programming transistor 120 and the first read transistor 124 pair, and a second-level transistor 404 pair coupled in series between the programming transistor 120 and the second read transistor 126 pair.

[0062] Likewise Figure 4 As shown in , in some embodiments, programming transistor 120 is gated by WLP, first read transistor pair 124 and second read transistor pair 126 are commonly gated by WLR, and first stage transistor pair 402 and second stage transistor pair 404 are commonly gated by WLB. In some embodiments, the source / drain terminal of one of the first read transistor pair 124 is coupled to bit line BL1, and the source / drain terminal of one of the second read transistor pair 126 is coupled to another bit line BL2. In some embodiments, reference is made to Figure 2C , the anti-fuse memory cell 103 is formed over the front side 203 of the substrate 201 , and the bit lines BL1 and BL2 are formed over the back side 205 of the substrate 201 .

[0063] Figure 5 2 shows an exemplary circuit diagram of a memory device 500 according to still other embodiments. Figure 5 The anti-fuse memory cell 103 of the memory device 500 shown in FIG. 5 is similar to that shown in FIG. Figure 4 4. The anti-fuse memory cell 103 of the memory device 400 shown in FIG. 4 is similar to that of FIG.

[0064] like Figure 5 As shown in, the anti-fuse memory cell 103 of the memory device 500 is implemented as a thirteen-transistor (13T) symmetrical configuration and includes a first read transistor 124 pair, a second read transistor 126 pair, a programming transistor 120 coupled in series between the first read transistor 124 pair and the second read transistor 126 pair, a first-level transistor 402 pair coupled in series between the programming transistor 120 and the first read transistor 124 pair, a second-level transistor 404 pair coupled in series between the programming transistor 120 and the second read transistor 126 pair, a third-level transistor 502 pair coupled in series between the programming transistor 120 and the first-level transistor 402 pair, and a fourth-level transistor 505 pair coupled in series between the programming transistor 120 and the second-level transistor 404 pair.

[0065] Likewise Figure 5 As shown in , in some embodiments, the programming transistor 120 is gated by WLP, the first read transistor pair 124 and the second read transistor pair 126 are commonly gated by WLR, the first stage transistor pair 402 and the second stage transistor pair 404 are commonly gated by WLB, and the third stage transistor pair 502 and the fourth stage transistor pair 505 are commonly gated by WLM. In some embodiments, the source / drain terminal of one first read transistor 124 is coupled to the bit line BL1, and the source / drain terminal of one second read transistor 126 is coupled to another bit line BL2.

[0066] In other embodiments, the anti-fuse memory cell 103 of the memory device 500 is implemented as an N-transistor (NT) symmetric configuration, where N can be an odd number, such as 3, 5, 7, 9, 11, 13, 15, while remaining within the scope of the disclosed embodiments. Utilizing the NT symmetric structure and the additional stage transistors inserted between the programming transistor and the first and second read transistors, the voltage difference between the transistors can be effectively reduced, thereby advantageously avoiding a large voltage difference.

[0067] Figure 6 is a method for operating a memory device (e.g., such as Figure 2A 200A) is an exemplary flow chart of method 600. It should be understood that in Figure 6 Additional operations are provided before, during, and after the processes discussed in the method, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes may be interchangeable, and at least some operations or processes may be implemented in a different order. In some embodiments, at least two or more operations or processes overlap in time or are implemented almost simultaneously.

[0068] In operation S610, FIG. 2A to FIG. 2C and Figure 6 As shown in , a memory cell 103 is provided over a front side 203 of a substrate 201. In some embodiments, the memory cell 103 includes a programming transistor 102, a first read transistor 124, and a second read transistor 126, wherein a programming transistor 120 is coupled in series between the first read transistor 124 and the second read transistor 126. The programming transistor 120 includes: a gate metal 121; and a gate dielectric layer 123, located below the gate metal 121 and including a first dielectric portion 123A and a second dielectric portion 123B.

[0069] In operation S620, FIG. 2A to FIG. 2C and Figure 6 As shown in , during the programming process, a programming voltage WLP1 is applied to the gate terminal 120G of the programming transistor 120 to randomly break down any one of the first dielectric portion 123A or the second dielectric portion 123B of the gate dielectric layer 123 of the programming transistor 120. As mentioned above, based on which of the first dielectric portion 123A or the second dielectric portion 123B has been broken down, the memory cell 103 randomly assumes a logic state of any one of a first logic state (e.g., 1) or a second logic state (e.g., 0). For example, the first logic state indicates that a first conductive path through the first dielectric portion 123A is established, while the second logic state indicates that a second conductive path through the second dielectric portion 123B is established.

[0070] In operation S630, FIG. 2A to FIG. 2C and Figure 6 As shown in FIG. 1 , during a read process, a read voltage is applied to the gate terminal 120G of the programming transistor 120 to identify whether a first conductive path through the dielectric portion 123A or a second conductive path through the second dielectric portion 123B is established. The first conductive path extends from the gate terminal 120G through the first dielectric portion 123A and the first read transistor 124 to the first bit line BL1, while the second conductive path extends from the gate terminal 120G through the second dielectric portion 123B and the second read transistor 126 to the second bit line BL2.

[0071] In some embodiments, Figure 2C As shown in FIG, a first bit line BL1 and a second bit line BL2 are formed in a metallization layer (e.g., M0) on a back side 205 of a substrate 201 opposite to a front side 203. In some embodiments, during a read process, a bit line voltage (e.g., a low BL voltage 0V or a high BL voltage 0.75V) is applied to corresponding source / drain terminals of a read transistor of a memory cell through the bit lines (e.g., BL1 and BL2) formed on the back side of the substrate.

[0072] In operation S640, if Figure 2A and Figure 6 As shown in , during or after the reading process, a bit of a physical unclonable function (PUF) signature for the memory cell 103 is detected based on whether the first conductive path or the second conductive path is established. In some embodiments, when it is determined that the first conductive path through the first dielectric portion 123A is established, a bit (e.g., 1) of the PUF signature for the memory cell 103 is detected. Otherwise, when it is determined that the second conductive path through the second dielectric portion 123B is established, another bit (e.g., 0) of the PUF signature for the memory cell 103 is detected.

[0073] In this way, it is possible to generate and detect Figure 1A All bits of the PUF signature of all anti-fuse memory cells 103 of the memory device 100 shown in , and thus the PUF signature of the memory device can be securely generated and detected.

[0074] Figure 7 is an exemplary flow chart of a method 700 for forming a memory device according to some embodiments. A memory device (eg, Figure 2A 200A, Figure 2C 200C) may include at least three transistors formed on the front side of the substrate and at least two bit lines formed on the back side of the substrate. In some embodiments, the method 700 may be implemented based on the following Figure 2BThe layout 200B shown in FIG. 2 forms a memory device, and therefore, some of the references used above may be reused in the following discussion of method 700. It should be noted that method 700 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the method 700 may be used in the following discussion of method 700. Figure 7 Additional operations are provided before, during, and after method 700, and some other operations may be only briefly described herein.

[0075] According to various embodiments, method 700 begins with operation 702, wherein a substrate is provided. The substrate comprises a semiconductor material substrate, for example, silicon. Alternatively, the substrate may comprise other elemental semiconductor materials, such as, for example, germanium. The substrate may also comprise a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and gallium indium phosphide. In one embodiment, the substrate comprises an epitaxial layer. For example, the substrate may have an epitaxial layer located above a bulk semiconductor. In addition, the substrate may comprise a semiconductor on insulator (SOI) structure. For example, the substrate may comprise a buried oxide (BOX) layer formed by a process such as isolation by implanted oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.

[0076] Method 700 continues to operation 704, where a stack comprising an alternating series of first and second nanostructures is formed according to various embodiments. Such a stack may be formed based on one of the (active area) patterns discussed above. The stack may be formed in the front side of the substrate. In some embodiments, the first nanostructure may include a SiGe sacrificial nanostructure, and the second nanostructure may include a Si channel nanostructure. Such a stack is sometimes referred to as a superlattice. In a non-limiting example, the SiGe sacrificial nanostructure may be SiGe 25%. The symbol "SiGe 25%" is used to indicate that 25% of the SiGe material is Ge. It should be understood that the percentage of Ge in each of the SiGe sacrificial nanostructures may be any value between 0 and 100 (excluding 0 and 100) while remaining within the scope of the disclosed embodiments. In some other embodiments, the second nanostructure may include a first semiconductor material other than Si, and the first nanostructure may include a second semiconductor material other than SiGe, as long as the first semiconductor material and the second semiconductor material have different etching characteristics (e.g., etching rates), respectively.

[0077] An alternating series of nanostructures can be formed by epitaxially growing one layer and then the next layer until a desired number and desired thickness of nanostructures are obtained. Epitaxial materials can be grown from gaseous or liquid precursors. Epitaxial materials can be grown using vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) or other suitable processes. Epitaxial silicon, silicon germanium and / or carbon-doped silicon (Si:C) can be doped (in-situ doping) by adding dopants, n-type dopants (e.g., phosphorus or arsenic) or p-type dopants (e.g., boron or gallium) during deposition, depending on the type of transistor.

[0078] The method 700 continues to operation 706, where a plurality of dummy gate structures are formed according to various embodiments. Such dummy gate structures may be formed based on one of the (gate structure) patterns discussed above. The dummy gate structures may extend in a direction perpendicular to the longitudinal direction of the dielectric fin structure (and the stack). Furthermore, in one of the various embodiments, the dummy gate structures may be formed to be shorter than the dielectric fin structures, and thus, the dummy gate structures as formed are cut (or otherwise separated) by the dielectric fin structures.

[0079] The pseudo gate structure can be formed by depositing amorphous silicon (a-Si) above the stack. Other materials suitable for forming a pseudo gate (e.g., polysilicon) can be used while remaining within the scope of the disclosed embodiment. The a-Si is then flattened to a desired level. A hard mask is deposited and patterned above the flattened a-Si. The hard mask can be formed by a nitride or oxide layer. An etching process (e.g., a reactive ion etching (RIE) process) is applied to the a-Si to form a pseudo gate structure. After the pseudo gate structure is formed, a gate spacer can be formed to extend along the sidewall of the pseudo gate structure. The gate spacer can be formed by conformal deposition of a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiBCN, SiOCN, SiOC, or any suitable combination of those materials) and subsequent directional etching (e.g., RIE).

[0080] Method 700 proceeds to operation 708, where, according to various embodiments, an internal spacer is formed by replacing the end portion of each of the SiGe sacrificial nanostructures with a dielectric material. When forming a pseudo gate structure covering certain portions of the stack (e.g., portions of the stack separated by a dielectric fin structure), the non-covered portion of the stack is removed. Next, the corresponding end portion of each SiGe sacrificial nanostructure of the covered stack is removed. The internal spacer is formed by: filling such a groove of each SiGe sacrificial nanostructure with a dielectric material by chemical vapor deposition (CVD) or by monomolecular layer doping (MLD) of a nitride and subsequent spacer RIE. The material of the internal spacer can be formed of the same or different material as the gate spacer described above. For example, the internal spacer can be formed of silicon nitride, silicon boron carbonitride, silicon carbonitride, silicon oxycarbonitride, or any other type of dielectric material (e.g., a dielectric material having a dielectric constant k of less than about 5).

[0081] Method 700 proceeds to operation 710, wherein a plurality of epitaxial structures are formed according to various embodiments. When forming the internal spacers, the epitaxial structures are formed on the exposed ends of the Si nanostructures using an epitaxial layer growth process. In-situ doping (ISD) can be applied to form doped epitaxial structures, thereby creating the necessary junctions for corresponding transistors (or sub-transistors). N-type and p-type FETs are formed by injecting different types of dopants into selected areas of the device to form the necessary junctions. N-type devices can be formed by injecting arsenic (As) or phosphorus (P), and p-type devices can be formed by injecting boron (B). After the epitaxial structure is formed, an interlayer dielectric (e.g., silicon dioxide) is deposited to cover the epitaxial structure.

[0082] Method 700 proceeds to operation 712, where, according to various embodiments, the dummy gate structure and the remaining SiGe sacrificial nanostructure are replaced with corresponding active gate structures. After forming the interlayer dielectric, the dummy gate structure is removed by an etching process, such as RIE or chemical oxide removal (COR). Next, the remaining SiGe sacrificial nanostructure is removed by applying a selective etch (e.g., hydrochloric acid (HCl)) while keeping the Si channel nanostructure substantially intact. After removing the SiGe sacrificial nanostructure, the top and bottom surfaces and sidewalls of each of the Si channel nanostructures can be exposed, except for the sidewalls that contact the dielectric fin structure. Next, a plurality of active gate structures can be formed to wrap each of the Si channel nanostructures, except for the sidewalls that contact the dielectric fin structure. Each of the active gate structures includes at least a gate dielectric layer (e.g., a high-k dielectric layer) and a gate metal layer (e.g., a work function metal layer). When the active gate structure is formed, a transistor of a memory device can be formed.

[0083] Method 700 proceeds to operation 714, wherein a plurality of front-side interconnect structures are formed according to various embodiments. When forming a transistor, a plurality of mid-stage process interconnect structures (e.g., VG, MD) are formed above the transistor. For example, a plurality of VGs (e.g., 222, 223, 224) may be formed to be connected to the gate terminals of the transistors, respectively, and a plurality of MDs (e.g., 211, 212, 213, 214) may be formed to be connected to the source / drain terminals of the transistors. In addition, a plurality of back-end process interconnect structures may be formed above the mid-stage process interconnect structure. Such a back-end process interconnect structure includes the M0 track (e.g., 242, 243, 244) described above and other metal tracks in the upper metallization layer (e.g., M1, M2, not shown). Each of the transistors may be gated by VG. For example, the programming transistor is gated to WLP, and the reading transistor is gated to WLR.

[0084] The front-side interconnect structure is formed of a metal material. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are also within the scope of the disclosed embodiments. The front-side interconnect structure can be formed by covering the front side of the substrate with the metal materials listed above, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating, or a combination thereof.

[0085] Method 700 proceeds to operation 716, where a plurality of backside interconnect structures are formed according to various embodiments. When forming the back-end process metal track, the substrate is flipped over, and a plurality of backside interconnect structures (e.g., BM0 track, BM1 track) are formed over the back side of the substrate. For example, after flipping the substrate, a polishing process can be performed on the back side of the substrate until the bottom surface of the epitaxial structure (e.g., the source / drain terminal formed in operation 710) is exposed. Next, one or more dielectric layers are formed over the polished backside surface, followed by the formation of backside via structures, which can each extend through one or more dielectric layers to reach the bottom surface of the corresponding epitaxial structure. Next, the backside interconnect structures can be formed in the corresponding backside metallization layer.

[0086] The backside interconnect structure is formed by a metal material. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chromium, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium and their combinations. Other metal materials are also within the scope of the disclosed embodiments. The backside interconnect structure can be formed by: covering the back side of the substrate with the metal material listed above by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), chemical plating, electroplating or their combination. For example, VB 231 and 233 are formed in the backside layer (e.g., BMO) on the back side of the substrate, and directly connect the bottoms of the corresponding MD 211 and 214 from their back sides.

[0087] In one aspect of an embodiment of the present disclosure, a memory device is disclosed. The memory device includes a memory cell that randomly presents any one of a first logic state or a second logic state, a first bit line, and a second bit line. The memory cell is formed on a first side of a substrate and includes: a programming transistor having a first source / drain terminal and a second source / drain terminal; a first read transistor, the first source / drain terminal of the first read transistor is coupled to the first source / drain terminal of the programming transistor; and a second read transistor, the first source / drain terminal of the second read transistor is coupled to the second source / drain terminal of the programming transistor. The first bit line is formed on a second side of the substrate opposite to the first side, and the second bit line is formed on the second side of the substrate. The first bit line is operably coupled to the second source / drain terminal of the first read transistor, and the second bit line is operably coupled to the second source / drain terminal of the second read transistor.

[0088] In another aspect of the disclosed embodiment, a memory system is disclosed. The memory system includes: a memory array including a plurality of memory cells formed on a first side of a substrate; and an authentication circuit operably coupled to the memory array and configured to generate bits of a physical unclonable function (PUF) signature for each of the plurality of memory cells based on their logic states. Each of the plurality of memory cells presents a logic state of any one of a first logic state or a second logic state, and includes: a programming transistor including a first source / drain terminal and a second source / drain terminal; a first reading transistor including a first source / drain terminal operably coupled to the first source / drain terminal of the programming transistor, and a second source / drain terminal operably coupled to a first bit line; and a second reading transistor including a first source / drain terminal coupled to the second source / drain terminal of the programming transistor, and a second source / drain terminal coupled to a second bit line.

[0089] In another aspect of the disclosed embodiment, a method for operating a memory device is disclosed. The method includes: providing a memory cell including at least a programming transistor, a first read transistor, and a second read transistor coupled in series, wherein the programming transistor is coupled between the first read transistor and the second read transistor; applying a programming voltage to the gate terminal of the programming transistor to randomly break down a first portion or a second portion of a gate dielectric layer of the programming transistor, wherein the first portion is coupled between the gate terminal of the first read transistor and the first source / drain terminal, and the second portion is coupled between the gate terminal of the second read transistor and the first source / drain terminal; applying a read voltage to the gate terminal of the programming transistor to identify whether a first conductive path through the first portion or a second conductive path through the second portion is established; and generating a bit of a physical unclonable function (PUF) signature for the memory cell based on whether the first conductive path or the second conductive path is established.

[0090] As used herein, the terms "about" and "approximately" generally represent a value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "about" can represent a value of a given quantity that varies within, for example, 10-30% of a value (e.g., +10%, 20%, or 30% of a value).

[0091] Some embodiments of the present application provide a memory device, comprising: a memory cell, which randomly presents a first logic state or a second logic state, wherein the memory cell is formed on a first side of a substrate and comprises: a programming transistor, having a first source / drain terminal and a second source / drain terminal; a first read transistor, wherein the first source / drain terminal of the first read transistor is coupled to the first source / drain terminal of the programming transistor; and a second read transistor, wherein the first source / drain terminal of the second read transistor is coupled to the second source / drain terminal of the programming transistor; a first bit line formed on a second side of the substrate opposite to the first side; and a second bit line formed on the second side of the substrate; wherein the first bit line is operably coupled to the second source / drain terminal of the first read transistor, and the second bit line is operably coupled to the second source / drain terminal of the second read transistor.

[0092] In some embodiments, the programming transistor has a gate terminal operably coupled to a programming word line, the first read transistor has a gate terminal operably coupled to a first read word line, and the second read transistor has a gate terminal operably coupled to a second read word line. In some embodiments, the gate terminal of the programming transistor has a gate metal and a gate dielectric layer, wherein the gate dielectric layer includes a first portion and a second portion, and wherein the first portion is coupled between the gate metal of the programming transistor and the first source / drain terminal, and the second portion is coupled between the gate metal of the programming transistor and the second source / drain terminal. In some embodiments, any one of the first portion or the second portion is configured to randomly break down. In some embodiments, the first portion is broken down to present the first logic state, and the second portion is broken down to present the second logic state. In some embodiments, the programming word line, the first read word line, and the second read word line are formed on the first side of the substrate. In some embodiments, any one of the first logic state or the second logic state is used as a bit of a physical unclonable function (PUF) signature. In some embodiments, the memory device further includes: a sense amplifier formed on the first side of the substrate and coupled to the first bit line and the second bit line. In some embodiments, the memory cell further comprises: one or more first-level transistors coupled in series between the programming transistor and the first read transistor; and one or more second-level transistors coupled in series between the programming transistor and the second read transistor. In some embodiments, the memory device further comprises: a first via structure connecting the second source / drain terminal of the first read transistor to the first bit line; and a second via structure connecting the second source / drain terminal of the second read transistor to the second bit line.

[0093] Some other embodiments of the present application provide a memory system, comprising: a memory array, comprising a plurality of memory cells formed on a first side of a substrate, each of the plurality of memory cells presenting a logic state of any one of a first logic state or a second logic state, and comprising: a programming transistor, comprising a first source / drain terminal and a second source / drain terminal; a first reading transistor, comprising a first source / drain terminal operably coupled to the first source / drain terminal of the programming transistor, and a second source / drain terminal operably coupled to a first bit line formed on a second side of the substrate opposite to the first side; and a second reading transistor, comprising a first source / drain terminal coupled to the second source / drain terminal of the programming transistor, and a second source / drain terminal coupled to a second bit line formed on the second side of the substrate; and an authentication circuit, operably coupled to the memory array and configured to generate bits of a physically unclonable function (PUF) signature for each of the plurality of memory cells based on the logic state thereof.

[0094] In some embodiments, the programming transistor includes a gate terminal operably coupled to a programming word line, the first read transistor includes a gate terminal operably coupled to a first read word line, and the second read transistor includes a gate terminal operably coupled to a second read word line. In some embodiments, the gate terminal of the programming transistor includes a gate metal and a gate dielectric layer, and wherein the gate dielectric layer includes a first portion coupled between the gate metal of the programming transistor and the first source / drain terminal, and a second portion coupled between the gate metal of the programming transistor and the second source / drain terminal. In some embodiments, the first portion or the second portion of the gate dielectric layer of the programming transistor is configured to randomly break down. In some embodiments, the logic state of each of the plurality of memory cells is determined based on a previous breakdown of the first portion or the second portion of the gate dielectric layer of the programming transistor. In some embodiments, upon identifying the previous breakdown of the first portion, the first logic state assumes the logic state, and wherein upon identifying the previous breakdown of the second portion, the second logic state assumes the logic state. In some embodiments, a first via structure connects the second source / drain terminal of the first read transistor to the first bit line, and wherein a second via structure connects the second source / drain terminal of the second read transistor to the second bit line. In some embodiments, each of the plurality of memory cells further comprises: one or more first-level transistors coupled in series between the programming transistor and the first read transistor; and one or more second-level transistors coupled in series between the programming transistor and the second read transistor.

[0095] Still other embodiments of the present application provide a method for forming a memory device, comprising: providing a substrate; forming a memory cell on a first side of the substrate, comprising: forming a programming transistor having a first source / drain terminal and a second source / drain terminal on the first side; forming a first read transistor on the first side, the first source / drain terminal of the first read transistor being coupled to the first source / drain terminal of the programming transistor; and forming a second read transistor on the first side, the first source / drain terminal of the second read transistor being coupled to the second source / drain terminal of the programming transistor; forming a first bit line formed on a second side of the substrate opposite to the first side; and forming a second bit line formed on the second side of the substrate.

[0096] In some embodiments, the method further comprises: forming a connection between the first bit line and a second source / drain terminal of the first read transistor. In some embodiments, the method further comprises: forming a connection between the second bit line and a second source / drain terminal of the second read transistor. In some embodiments, the memory cell is configured to randomly assume any one of the first logic state or the second logic state.

[0097] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A memory device, include: A memory cell, the memory cell randomly exhibiting a first logic state or a second logic state, wherein the memory cell is formed on a first side of a substrate and comprises: a programming transistor having a first source / drain terminal and a second source / drain terminal; a first read transistor having a first source / drain terminal coupled to the first source / drain terminal of the programming transistor; and a second read transistor having a first source / drain terminal coupled to the second source / drain terminal of the programming transistor; a first bit line formed on a second side of the substrate opposite the first side; and a second bit line formed on the second side of the substrate; Wherein, the first bit line is operably coupled to a second source / drain terminal of the first read transistor, and the second bit line is operably coupled to a second source / drain terminal of the second read transistor.

2. The memory device according to claim 1, in, The programming transistor has a gate terminal operably coupled to a programming word line, the first read transistor has a gate terminal operably coupled to a first read word line, and the second read transistor has a gate terminal operably coupled to a second read word line.

3. The memory device according to claim 2, in, The gate terminal of the programming transistor has a gate metal and a gate dielectric layer, wherein the gate dielectric layer includes a first portion and a second portion, and wherein the first portion is coupled between the gate metal of the programming transistor and the first source / drain terminals, and the second portion is coupled between the gate metal of the programming transistor and the second source / drain terminals.

4. The memory device according to claim 3, in, Either the first portion or the second portion is configured to randomly breakdown.

5. The memory device according to claim 4, in, The first portion is broken down to assume the first logic state, and the second portion is broken down to assume the second logic state.

6. The memory device according to claim 2, in, The programming word line, the first read word line, and the second read word line are formed on the first side of the substrate.

7. The memory device according to claim 1, in, Either the first logic state or the second logic state is used as a bit of a Physical Unclonable Function (PUF) signature.

8. The memory device according to claim 1, further comprising: include: A sense amplifier is formed on the first side of the substrate and coupled to the first bit line and the second bit line.

9. A memory system, include: A memory array comprising a plurality of memory cells formed on a first side of a substrate, each of the plurality of memory cells exhibiting a logic state of any one of a first logic state or a second logic state, and comprising: a programming transistor including a first source / drain terminal and a second source / drain terminal; a first read transistor including a first source / drain terminal operably coupled to the first source / drain terminal of the programming transistor and a second source / drain terminal operably coupled to a first bit line formed on a second side of the substrate opposite the first side; and a second read transistor including a first source / drain terminal coupled to the second source / drain terminal of the programming transistor and a second source / drain terminal coupled to a second bit line formed on the second side of the substrate; and An authentication circuit is operably coupled to the memory array and configured to generate bits of a physically unclonable function (PUF) signature for each of the plurality of memory cells based on the logic state thereof.

10. A method for forming a memory device, include: providing a substrate; forming a memory cell on a first side of the substrate, comprising: forming a programming transistor having a first source / drain terminal and a second source / drain terminal on the first side; forming a first read transistor on the first side, a first source / drain terminal of the first read transistor coupled to the first source / drain terminal of the programming transistor; and forming a second read transistor on the first side, a first source / drain terminal of the second read transistor coupled to the second source / drain terminal of the programming transistor; forming a first bit line formed on a second side of the substrate opposite the first side; and A second bit line is formed on the second side of the substrate.

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