Capacitor device and method of forming the same

Abstract

A capacitor device and a method for forming the same. The structure includes: a metal layer structure includes a plurality of first electrode layers arranged in a stack, a second electrode layer between any two adjacent first electrode layers, and a first dielectric layer between any adjacent first electrode layer and second electrode layer, each first electrode layer further extends to a first region, and each second electrode layer further extends to a third region; a first conductive plug on the first region, the first conductive plug penetrates each first electrode layer in a direction perpendicular to the substrate surface, and the first conductive plug connects each first electrode layer, the first conductive plug is also located on part of the top surface of each first electrode layer; a second conductive plug on the third region, the second conductive plug penetrates each second electrode layer in a direction perpendicular to the substrate surface, and the second conductive plug connects each second electrode layer, the second conductive plug is also located on part of the top surface of each second electrode layer, which is beneficial to reduce the contact resistance and improve the performance of the capacitor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a capacitor and a method for forming the same. Background Technology

[0002] In semiconductor integrated circuits, integrated capacitors, fabricated on the same chip as transistor circuits, are widely used. They mainly come in two forms: metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors.

[0003] MIM capacitors use upper and lower metal layers as capacitor plates. In traditional MIM capacitors, there is only a single dielectric layer between the capacitor plates, and its equivalent capacitance density is limited by the thickness and dielectric constant of the dielectric layer. Therefore, a multi-layer capacitor structure is introduced to achieve a higher equivalent capacitance density.

[0004] However, the performance of multilayer plate capacitor structures still needs further improvement. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a capacitor device and a method for forming the same, so as to improve the performance of semiconductor structures.

[0006] To solve the above-mentioned technical problems, the present invention provides a capacitor device, comprising: a substrate, the substrate including a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; a metal layer structure located on the second region, the metal layer structure including a plurality of first electrode layers stacked thereon, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer further extending to the first region, and each second electrode layer further extending to the third region; a first conductive plug located on the first region, the first conductive plug penetrating each first electrode layer along a direction perpendicular to the substrate surface, and the first conductive plug connecting each first electrode layer, the first conductive plug also being located on a portion of the top surface of each first electrode layer; and a second conductive plug located on the third region, the second conductive plug penetrating each second electrode layer along a direction perpendicular to the substrate surface, and the second conductive plug connecting each second electrode layer, the second conductive plug also being located on a portion of the top surface of each second electrode layer.

[0007] Optionally, the first electrode layer of each upper layer is located on the sidewall and part of the top surface of the second electrode layer of the lower layer; the second electrode layer of each upper layer is located on the sidewall and part of the top surface of the first electrode layer of the lower layer.

[0008] Optionally, it further includes: a first lower metal layer located in the first region; a second lower metal layer located in the third region; a second dielectric layer located on the surfaces of a plurality of first electrode layers and a plurality of second electrode layers; a first upper metal layer and a second upper metal layer located on the second dielectric layer and being separate from each other; a first conductive plug is also connected to the first lower metal layer and the first upper metal layer; and a second conductive plug is also connected to the second lower metal layer and the second upper metal layer.

[0009] Optionally, the material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0010] Optionally, the material of the first dielectric layer includes one or a combination of HfO, AlO, ZrO and LaO.

[0011] Optionally, the thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

[0012] Accordingly, the present invention also provides a method for forming a capacitor, comprising: providing a substrate, the substrate including a first region, a second region and a third region arranged along a first direction, the second region being located between the first region and the third region; forming a metal layer structure on the substrate, the metal layer structure including a plurality of first electrode layers stacked thereon, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers, each first electrode layer being located on the second region and extending to the first region, and each second electrode layer being located on the second region and extending to the third region; forming a first conductive plug on the first region, the first conductive plug penetrating each first electrode layer along a direction perpendicular to the substrate surface, and the first conductive plug connecting each first electrode layer, the first conductive plug also being located on a portion of the top surface of each first electrode layer; forming a second conductive plug on the third region, the second conductive plug penetrating each second electrode layer along a direction perpendicular to the substrate surface, and the second conductive plug connecting each second electrode layer, the second conductive plug also being located on a portion of the top surface of each second electrode layer.

[0013] Optionally, the method for forming the first conductive plug and the second conductive plug includes: forming a first contact hole in a first region, the first contact hole including a plurality of first openings arranged in a direction perpendicular to the substrate surface, each first opening penetrating a first electrode layer and exposing a portion of the top surface of the lower first electrode layer; forming a second contact hole in a third region, the second contact hole including a plurality of second openings arranged in a direction perpendicular to the substrate surface, each second opening penetrating a second electrode layer and exposing a portion of the top surface of the lower second electrode layer; forming a first conductive plug in the first contact hole; and forming a second conductive plug in the second contact hole.

[0014] Optionally, the method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on a substrate, or forming a lower first dielectric layer and a first electrode material layer on its surface within a second opening in a previously formed second electrode layer; patterning the first electrode material layer to form a lower first electrode layer and a first opening therein; forming an upper first dielectric layer and a second electrode material layer on its surface within a first opening on the surface of the lower first electrode layer; and patterning the second electrode material layer to form an upper second electrode layer and a second opening therein.

[0015] Optionally, after forming the metal layer structure and before forming the first conductive plug and the second conductive plug, a second dielectric layer is also formed on the substrate surface, the metal layer structure surface, within the plurality of first openings and the plurality of second openings; the first contact hole and the second contact hole are also located within the second dielectric layer; the method of forming the first contact hole and the second contact hole further includes: etching the second dielectric layer to expose the surfaces of the plurality of first opening sidewalls and the plurality of second opening sidewalls, and to expose a portion of the top surface of the first electrode layer adjacent to each first opening sidewall and a portion of the top surface of the second electrode layer adjacent to the bottom of each second opening, so as to form the first contact hole and the second contact hole.

[0016] Optionally, the substrate has a first lower metal layer located in a first region and a second lower metal layer located in a third region; the first conductive plug is also connected to the first lower metal layer; the second conductive plug is also connected to the second lower metal layer.

[0017] Optionally, the first contact hole is also located in the first region and exposes the first lower metal layer, and the second contact hole is also located in the third region and exposes the second lower metal layer; the method of forming the first contact hole and the second contact hole further includes: after etching the second dielectric layer, etching the exposed substrate until the top surface of the first lower metal layer and the top surface of the second lower metal layer are exposed.

[0018] Optionally, the method for forming the first conductive plug and the second conductive plug further includes: depositing a conductive material layer on the surface of the second dielectric layer, in the first contact hole and in the second contact hole; planarizing the conductive material layer to form the first conductive plug in the first contact hole and the second conductive plug in the second contact hole.

[0019] Optionally, a first upper metal layer and a second upper metal layer, which are mutually independent, are also formed on the surface of the second dielectric layer. The first upper metal layer is located on the surface of the first conductive plug, and the second upper metal layer is located on the surface of the second conductive plug.

[0020] Optionally, the process for patterning the first electrode material layer includes a dry etching process.

[0021] Optionally, the process for patterning the second electrode material layer includes a dry etching process.

[0022] Optionally, the formation process of the first electrode material layer includes physical vapor deposition; the formation process of the second electrode material layer includes physical vapor deposition.

[0023] Optionally, the material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0024] Optionally, the material of the first dielectric layer includes one or a combination of HfO, AlO, ZrO and LaO.

[0025] Optionally, the thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

[0026] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0027] In the capacitor device provided by the present invention, a first conductive plug located on a first region penetrates each first electrode layer along a direction perpendicular to the substrate surface and connects each first electrode layer. The first conductive plug is also located on a portion of the top surface of each first electrode layer, increasing the contact area between the first conductive plug and each first electrode layer, which helps to reduce the contact resistance between the first conductive plug and each first electrode layer and improve the performance of the capacitor device. Similarly, a second conductive plug penetrates each second electrode layer along a direction perpendicular to the substrate surface and is also located on a portion of the top surface of each second electrode layer, which helps to reduce the contact resistance between the second conductive plug and each second electrode layer and improve the performance of the capacitor device.

[0028] In the method for forming a capacitor provided by the present invention, a first conductive plug is formed on a first region. The first conductive plug penetrates each first electrode layer in a direction perpendicular to the substrate surface and connects each first electrode layer. The first conductive plug is also located on a portion of the top surface of each first electrode layer, which increases the contact area between the first conductive plug and each first electrode layer, thereby reducing the contact resistance between the first conductive plug and each first electrode layer and improving the performance of the capacitor. Similarly, a second conductive plug penetrates each second electrode layer in a direction perpendicular to the substrate surface and is also located on a portion of the top surface of each second electrode layer, thereby reducing the contact resistance between the second conductive plug and each second electrode layer and improving the performance of the capacitor.

[0029] Furthermore, the second dielectric layer is etched to expose several first opening sidewall surfaces and several second opening sidewalls, and to expose a portion of the top surface of the first electrode layer adjacent to each first opening sidewall and a portion of the top surface of the second electrode layer adjacent to each second opening sidewall, so as to form a first contact hole and a second contact hole. The etching process does not require etching the metal layer structure, which reduces the difficulty of forming the first contact hole and the second contact hole and improves the etching process window. Attached Figure Description

[0030] Figure 1 This is a structural schematic diagram of a capacitor device;

[0031] Figures 2 to 8 This is a schematic diagram of the structure corresponding to each step in the capacitor device forming method of the present invention. Detailed Implementation

[0032] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.

[0033] As mentioned in the background section, the performance of capacitors in the prior art needs improvement. A capacitor will now be described and analyzed in conjunction with this example.

[0034] Figure 1 This is a schematic diagram of the structure of a capacitor.

[0035] Please refer to Figure 1The capacitor device includes: a substrate 100, which includes a first region I, a second region II, and a third region III arranged along a first direction X, wherein the second region II is located between the first region I and the third region II; the first region I has a first lower metal layer 101, and the third region III has a second lower metal layer 102; and a plurality of first electrode structures and a plurality of second electrode structures stacked on the substrate 100. The first electrode structures include a first lead-out terminal 103 located on the first region I and a first electrode layer 104 located on the second region II; the second electrode structures include a second lead-out terminal 105 located on the third region III and a second electrode layer 106 located on the second region II; and each first electrode layer 104 on the second region II is located between adjacent second electrode layers 106. The following are components: a first dielectric layer 107 located between adjacent first electrode layers 104 and second electrode layers 106; a dummy electrode layer 108 located on several first electrode structures in the first region I; a second dielectric layer 109 located on the surfaces of several first electrode structures and several second electrode structures; a first upper metal layer 110 and a second upper metal layer 111 located on the second dielectric layer 109 and separated from each other; a first conductive plug 112 located within the second dielectric layer 109, the first conductive plug 112 connecting the first lower metal layer 101, the first upper metal layer 110 and each first lead-out terminal 103; and a second conductive plug 113 located within the second dielectric layer 109, the second conductive plug 113 connecting the second lower metal layer 102, the second upper metal layer 111 and each second lead-out terminal 105.

[0036] In the above-mentioned MIM capacitor, each adjacent first electrode layer 104, second electrode layer 106 and the first dielectric layer 107 between them form a single capacitor. The first conductive plug 112 is connected to each first lead-out terminal 103 for electrically leading out each first electrode layer 104, and the second conductive plug 113 is connected to each second lead-out terminal 105 for electrically leading out each second electrode layer 106, thereby forming multiple parallel capacitors to obtain a larger equivalent capacitance density. However, the first conductive plug 112 is connected to each first lead 103 by passing through each first lead 103 vertically. The side wall of the first conductive plug 112 located inside the first lead 103 is approximately perpendicular to the bottom surface of the first lead 103. The contact surface A between each first lead 103 and the first conductive plug 112 is small, resulting in a large contact resistance between the first conductive plug 112 and each first lead 103. Similarly, the contact resistance between the second conductive plug 113 and each second lead 105 is also large, thus affecting the performance of the capacitor.

[0037] To address the aforementioned problems, the present invention provides a capacitor and a method for forming the same. A first conductive plug is formed on a first region. The first conductive plug penetrates each first electrode layer along a direction perpendicular to the substrate surface and connects to each first electrode layer. The first conductive plug is also located on a portion of the top surface of each first electrode layer, increasing the contact area between the first conductive plug and each first electrode layer, which helps to reduce the contact resistance between the first conductive plug and each first electrode layer and improve the performance of the capacitor. Similarly, a second conductive plug penetrates each second electrode layer along a direction perpendicular to the substrate surface and is also located on a portion of the top surface of each second electrode layer, which helps to reduce the contact resistance between the second conductive plug and each second electrode layer and improve the performance of the capacitor.

[0038] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0039] Figures 2 to 8 This is a schematic diagram of the structure corresponding to each step in the capacitor device forming method of the present invention.

[0040] Please refer to Figure 2 A substrate 200 is provided, the substrate 200 includes a first region I, a second region II and a third region III arranged along a first direction Y, the second region II being located between the first region I and the third region III.

[0041] In this embodiment, the substrate 200 has a first lower metal layer 201 located in the first region I and a second lower metal layer 202 located in the third region III.

[0042] In this embodiment, the substrate 200 further includes a substrate (not shown in the figure), a device layer (not shown in the figure) located on the substrate, and a metal interconnect layer located on the device layer. The metal interconnect layer includes a third dielectric layer (not shown in the figure), a first lower metal layer 201 and a second lower metal layer 202 located within the third dielectric layer, and the metal interconnect layer and the device layer are electrically connected.

[0043] Subsequently, a metal layer structure is formed on the substrate 200. The metal layer structure includes a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers. Each first electrode layer is located on a second region II and extends to a first region I, and each second electrode layer is located on a second region II and extends to a third region III. A first conductive plug is formed on the first region I. The first conductive plug penetrates each first electrode layer in a direction perpendicular to the surface of the substrate 200 and is connected to each first electrode layer. The first conductive plug is also located on a portion of the top surface of each first electrode layer. A second conductive plug is formed on the third region III. The second conductive plug penetrates each second electrode layer in a direction perpendicular to the surface of the substrate 200 and is connected to each second electrode layer. The second conductive plug is also located on a portion of the top surface of each second electrode layer.

[0044] In this embodiment, the method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on a substrate 200, or forming a lower first dielectric layer and a first electrode material layer on its surface within a second opening in a formed second electrode layer; patterning the first electrode material layer to form a lower first electrode layer and a first opening therein; forming an upper first dielectric layer and a second electrode material layer on its surface within the first opening on the surface of the lower first electrode layer; and patterning the second electrode material layer to form an upper second electrode layer and a second opening therein.

[0045] For specific methods on the formation of metal layer structures, please refer to [link / reference]. Figures 3 to 5 .

[0046] Please refer to Figure 3 A first electrode material layer (not shown in the figure) is formed on the substrate 200; the first electrode material layer is patterned to form a first electrode layer 203 and a first opening 204 therein.

[0047] In this embodiment, the formation process of the first electrode material layer includes physical vapor deposition.

[0048] In this embodiment, the process for patterning the first electrode material layer includes a dry etching process.

[0049] In this embodiment, the material of the first electrode layer 203 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0050] In this embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms.

[0051] Please refer to Figure 4A first dielectric layer 205 and a second electrode material layer (not shown in the figure) are formed on the surface of the first electrode layer 203 and within the first opening 204 therein; the second electrode material layer is patterned to form a first second electrode layer 206 and a second opening 207 therein.

[0052] In this embodiment, the formation process of the second electrode material layer includes physical vapor deposition.

[0053] In this embodiment, the process for patterning the second electrode material layer includes a dry etching process.

[0054] In this embodiment, the material of the second electrode layer 206 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0055] In this embodiment, the material of the first dielectric layer 205 includes one or more of HfO, AlO, ZrO and LaO.

[0056] It should be noted that each first electrode layer 203, the adjacent second electrode layer 206, and the first dielectric layer 205 between them form a single capacitor. The metal layer structure includes multiple capacitors connected in parallel. The material of the first dielectric layer 205 in each capacitor can be the same or different.

[0057] In this embodiment, the thickness of the second electrode layer 206 ranges from 300 angstroms to 800 angstroms.

[0058] Please refer to Figure 5 A second first dielectric layer 205 and a first electrode material layer on its surface (not shown in the figure) are formed within the first second electrode layer 206 and the second opening 207 therein; the first electrode material layer is patterned to form a second first electrode layer 203 and a first opening 204 therein.

[0059] It should be noted that the lower first opening 204 has a first projection on the surface of the substrate 200, and the upper first opening 204 has a second projection on the surface of the substrate 200. The first projection is located within the range of the second projection, so that when the first contact hole is subsequently formed, after opening the first opening 204, a portion of the top surface of the lower first electrode layer 203 is exposed. Similarly, in embodiments where multiple layers of second electrode layers 206 need to be formed, the lower second opening 207 has a third projection on the substrate surface, and the upper first opening 204 has a fourth projection on the substrate surface, with the third projection located within the range of the fourth projection.

[0060] In this embodiment, the first electrode layer 203 has two layers, and the second electrode layer 206 has one layer. In other embodiments, the number of the first electrode layer and the second electrode layer can be set according to actual needs.

[0061] Subsequently, a first conductive plug is formed on the first region I, and a second conductive plug is formed on the third region III.

[0062] In this embodiment, after the metal layer structure is formed and before the first conductive plug and the second conductive plug are formed, please refer to... Figure 6 .

[0063] Please refer to Figure 6 A second dielectric layer 210 is formed on the surface of the substrate 200, the surface of the metal layer structure, within a plurality of first openings 204 and a plurality of second openings 207.

[0064] In this embodiment, the method for forming the first conductive plug and the second conductive plug is described in [reference needed]. Figures 7 to 8 .

[0065] Please refer to Figure 7 A first contact hole 208 is formed in the first region I. The first contact hole 208 includes a plurality of first openings 204 arranged in a direction perpendicular to the surface of the substrate 200 (e.g., ...). Figure 5 As shown), each first opening 204 penetrates a first electrode layer 203 and exposes a portion of the top surface of the lower first electrode layer 203; a second contact hole 209 is formed in the third region III, the second contact hole 209 including a plurality of second openings 207 arranged in a direction perpendicular to the surface of the substrate 200 (e.g., ...). Figure 4 As shown, each second opening 207 penetrates a second electrode layer 206 and exposes part of the top surface of the lower second electrode layer 206.

[0066] In this embodiment, the first contact hole 208 and the second contact hole 209 are also located within the second dielectric layer 210.

[0067] In this embodiment, the method for forming the first contact hole 208 and the second contact hole 209 further includes: etching the second dielectric layer 210 to create a plurality of first openings 204 (such as...). Figure 3 (As shown) sidewall surface and several second openings 207 (as shown) Figure 4 As shown, the sidewalls are exposed, and a portion of the top surface of the first electrode layer 203 adjacent to the sidewall of each first opening 204 and a portion of the top surface of the second electrode layer 206 adjacent to the sidewall of each second opening 207 are exposed to form a first contact hole 208 and a second contact hole 209. The etching process does not require etching the metal layer structure, reducing the difficulty of forming the first contact hole 208 and the second contact hole 209 and increasing the etching process window.

[0068] Specifically, during the etching process to form the first contact hole 208 and the second contact hole 209, it is also necessary to etch and remove several layers of first dielectric layer 205 within the first opening 204 and the second opening 207. The several layers of first dielectric layer 205 are easier to etch than the metal layer structure.

[0069] In this embodiment, the first contact hole 208 is also located in the first region I and exposes the first lower metal layer 201, and the second contact hole 209 is also located in the third region III and exposes the second lower metal layer 202.

[0070] In this embodiment, the method for forming the first contact hole 208 and the second contact hole 209 further includes: after etching the second dielectric layer 210, etching the exposed substrate 200 until the top surface of the first lower metal layer 201 and the top surface of the second lower metal layer 202 are exposed.

[0071] Please refer to Figure 7 A first conductive plug 211 is formed in the first contact hole 208; a second conductive plug 212 is formed in the second contact hole 209.

[0072] Thus, a first conductive plug 211 is formed on the first region I. The first conductive plug 211 penetrates each of the first electrode layers 203 along a direction perpendicular to the surface of the substrate 200 and is also located on a portion of the top surface of each of the first electrode layers 203. This increases the contact area between the first conductive plug 211 and each of the first electrode layers 203, which helps to reduce the contact resistance between the first conductive plug 211 and each of the first electrode layers 203 and improve the performance of the capacitor. Similarly, a second conductive plug 212 penetrates each of the second electrode layers 206 along a direction perpendicular to the surface of the substrate 200 and is also located on a portion of the top surface of each of the second electrode layers 206. This helps to reduce the contact resistance between the second conductive plug 212 and each of the second electrode layers 206 and improve the performance of the capacitor.

[0073] In this embodiment, the method for forming the first conductive plug 211 and the second conductive plug 212 further includes: depositing a conductive material layer (not shown in the figure) on the surface of the second dielectric layer 210, in the first contact hole 208, and in the second contact hole 209; planarizing the conductive material layer to make the first contact hole 208 (e.g., in the first contact hole 208) Figure 7 A first conductive plug 211 is formed within the second contact hole 209 (as shown). Figure 7 A second conductive plug 212 is formed inside (as shown).

[0074] In this embodiment, the first conductive plug 211 is also connected to the first lower metal layer 201; the second conductive plug 212 is also connected to the second lower metal layer 202.

[0075] In this embodiment, a first upper metal layer 213 and a second upper metal layer 214, which are mutually independent, are also formed on the surface of the second dielectric layer 210. The first upper metal layer 213 is located on the surface of the first conductive plug 211, and the second upper metal layer 214 is located on the surface of the second conductive plug 212.

[0076] In this embodiment, during the formation of the first conductive plug 211 and the second conductive plug 212, the conductive material layer is planarized until the surface of the second dielectric layer 210 is exposed; after the formation of the first conductive plug 211 and the second conductive plug 212, a metal material layer is formed on the surface of the second dielectric layer 210, and the metal material layer is etched until the surface of the second dielectric layer 210 is exposed to form the first upper metal layer 213 and the second upper metal layer 214.

[0077] In another embodiment, the method for forming a first conductive plug, a second conductive plug, a first upper metal layer, and a second upper metal layer includes: depositing a conductive material layer on the surface of a second dielectric layer, in a first contact hole, and in a second contact hole; planarizing the conductive material layer; and after the planarization process, etching the conductive material layer until the surface of the second dielectric layer is exposed to form a first conductive plug and a first upper metal layer on the first conductive plug, and forming a second conductive plug and a second upper metal layer on the second conductive plug.

[0078] Accordingly, embodiments of the present invention also provide a capacitor device formed by the above method; please refer to further details. Figure 8 The substrate 200 includes a first region I, a second region II, and a third region III arranged along a first direction Y, wherein the second region II is located between the first region I and the third region III; a metal layer structure located on the second region II, the metal layer structure including a plurality of first electrode layers 203 stacked together, a second electrode layer 206 located between two adjacent first electrode layers 203, and a first dielectric layer 205 located between adjacent first electrode layers 203 and second electrode layers 206, wherein each first electrode layer 203 extends to the first region I, and each second electrode layer 206 extends to the third region III; the first region II is located on the second region II. A first conductive plug 211 on region I penetrates each first electrode layer 203 in a direction perpendicular to the surface of substrate 200, and the first conductive plug 211 is connected to each first electrode layer 203. The first conductive plug 211 is also located on a portion of the top surface of each first electrode layer 203. A second conductive plug 212 on region III penetrates each second electrode layer 206 in a direction perpendicular to the surface of substrate 200, and the second conductive plug 212 is connected to each second electrode layer 206. The second conductive plug 212 is also located on a portion of the top surface of each second electrode layer 206.

[0079] Thus, the first conductive plug 211 penetrates each of the first electrode layers 203 along a direction perpendicular to the surface of the substrate 200, and is also located on a portion of the top surface of each of the first electrode layers 203, increasing the contact area between the first conductive plug 211 and each of the first electrode layers 203, which helps to reduce the contact resistance between the first conductive plug 211 and each of the first electrode layers 203 and improve the performance of the capacitor. Similarly, the second conductive plug 212 penetrates each of the second electrode layers 206 along a direction perpendicular to the surface of the substrate 200, and is also located on a portion of the top surface of each of the second electrode layers 206, which helps to reduce the contact resistance between the second conductive plug 212 and each of the second electrode layers 206 and improve the performance of the capacitor.

[0080] In this embodiment, the first electrode layer 203 of each upper layer is located on the sidewall and part of the top surface of the second electrode layer 206 below it; the second electrode layer 206 of each upper layer is located on the sidewall and part of the top surface of the first electrode layer 203 below it.

[0081] In this embodiment, the capacitor further includes: a first lower metal layer 201 located in the first region I; a second lower metal layer 202 located in the third region III; a second dielectric layer 210 located on the surfaces of a plurality of first electrode layers 203 and a plurality of second electrode layers 206; a first upper metal layer 213 and a second upper metal layer 214 located on the second dielectric layer 210 and separated from each other; a first conductive plug 211 is also connected to the first lower metal layer 201 and the first upper metal layer 213; and a second conductive plug 212 is also connected to the second lower metal layer 202 and the second upper metal layer 214.

[0082] In this embodiment, the material of the first electrode layer 203 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer 206 includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

[0083] In this embodiment, the material of the first dielectric layer 205 includes one or more of HfO, AlO, ZrO and LaO.

[0084] In this embodiment, the thickness of the first electrode layer 203 ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer 206 ranges from 300 angstroms to 800 angstroms.

[0085] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A capacitor component, characterized in that, include: A substrate, the substrate comprising a first region, a second region, and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A metal layer structure located on the second region includes a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers. Each first electrode layer extends into the first region, and each second electrode layer extends into the third region. Each first electrode layer has a first opening that exposes a portion of the top surface of the lower first electrode layer. The first opening penetrates the first electrode layer. The first opening in the lower layer has a first projection on the substrate surface, and the first opening in the upper layer has a second projection on the substrate surface. The first projection is located within the range of the second projection. A first contact hole located on the first region, the first contact hole comprising a plurality of first openings arranged in a direction perpendicular to the surface of the substrate; A first conductive plug is located in the first contact hole, the first conductive plug penetrates each of the first electrode layers in a direction perpendicular to the surface of the substrate, and the first conductive plug is connected to each of the first electrode layers. The first conductive plug is also located on a portion of the top surface of each of the first electrode layers. A second conductive plug is located on the third region, the second conductive plug penetrates each of the second electrode layers in a direction perpendicular to the surface of the substrate, and the second conductive plug is connected to each of the second electrode layers, the second conductive plug is also located on a portion of the top surface of each of the second electrode layers.

2. The capacitor as described in claim 1, characterized in that, The first electrode layer of each upper layer is located on the sidewall and part of the top surface of the second electrode layer below it; the second electrode layer of each upper layer is located on the sidewall and part of the top surface of the first electrode layer below it.

3. The capacitor as described in claim 1, characterized in that, Also includes: A first lower metal layer located within the first region; a second lower metal layer located within the third region; a second dielectric layer located on the surfaces of the plurality of first electrode layers and the plurality of second electrode layers; A first upper metal layer and a second upper metal layer are located on the second dielectric layer and are separate from each other; the first conductive plug is also connected to the first lower metal layer and the first upper metal layer; the second conductive plug is also connected to the second lower metal layer and the second upper metal layer.

4. The capacitor as claimed in claim 1, characterized in that, The material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

5. The capacitor as claimed in claim 1, characterized in that, The material of the first dielectric layer includes one or more of HfO, AlO, ZrO and LaO.

6. The capacitor as claimed in claim 1, characterized in that, The thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

7. A method for forming a capacitor element, characterized in that, include: A substrate is provided, the substrate including a first region, a second region and a third region arranged along a first direction, wherein the second region is located between the first region and the third region; A metal layer structure is formed on the substrate. The metal layer structure includes a plurality of first electrode layers stacked together, a second electrode layer located between two adjacent first electrode layers, and a first dielectric layer located between adjacent first electrode layers and second electrode layers. Each first electrode layer is located on a second region and extends to the first region. Each second electrode layer is located on the second region and extends to the third region. Each first electrode layer has a first opening and exposes a portion of the top surface of the lower first electrode layer. The first opening penetrates the first electrode layer. The first opening located on the lower layer has a first projection on the substrate surface, and the first opening located on the upper layer has a second projection on the substrate surface. The first projection is located within the range of the second projection. A first conductive plug is formed on the first region, the first conductive plug penetrating each of the first electrode layers in a direction perpendicular to the substrate surface, and the first conductive plug connecting each of the first electrode layers, the first conductive plug also being located on a portion of the top surface of each of the first electrode layers, the method of forming the first conductive plug comprising: forming a first contact hole on the first region, the first contact hole including a plurality of first openings arranged in a direction perpendicular to the substrate surface; and forming the first conductive plug within the first contact hole; A second conductive plug is formed on the third region, the second conductive plug penetrating each of the second electrode layers in a direction perpendicular to the surface of the substrate, and the second conductive plug is connected to each of the second electrode layers, and the second conductive plug is also located on a portion of the top surface of each of the second electrode layers.

8. The method for forming a capacitor element as described in claim 7, characterized in that, The method of forming the second conductive plug includes: forming a second contact hole on the third region, the second contact hole including a plurality of second openings arranged in a direction perpendicular to the surface of the substrate, each of the second openings penetrating a second electrode layer and exposing a portion of the top surface of the lower second electrode layer; forming the first conductive plug in the first contact hole; and forming the second conductive plug in the second contact hole.

9. The method for forming a capacitor element as described in claim 8, characterized in that, The method for forming adjacent first electrode layers and second electrode layers includes: forming a first electrode material layer on the substrate, or forming a lower first dielectric layer and a first electrode material layer on its surface within a second opening in a previously formed second electrode layer; patterning the first electrode material layer to form a lower first electrode layer and the first opening therein; forming an upper first dielectric layer and a second electrode material layer on its surface within the first opening on the surface of the lower first electrode layer; and patterning the second electrode material layer to form an upper second electrode layer and the second opening therein.

10. The method for forming a capacitor element as described in claim 9, characterized in that, After the metal layer structure is formed, and before the first conductive plug and the second conductive plug are formed, a second dielectric layer is also formed on the substrate surface, the surface of the metal layer structure, in the plurality of first openings and in the plurality of second openings. The first contact hole and the second contact hole are also located within the second dielectric layer; The method for forming the first contact hole and the second contact hole further includes: etching the second dielectric layer to expose a plurality of first opening sidewall surfaces and a plurality of second opening sidewalls, and exposing a portion of the top surface of the first electrode layer adjacent to each first opening sidewall and a portion of the top surface of the second electrode layer adjacent to the bottom of each second opening, so as to form the first contact hole and the second contact hole.

11. The method for forming a capacitor element as claimed in claim 10, characterized in that, The substrate has a first lower metal layer located in the first region and a second lower metal layer located in the third region; the first conductive plug is also connected to the first lower metal layer; the second conductive plug is also connected to the second lower metal layer.

12. The method for forming a capacitor element as claimed in claim 11, characterized in that, The first contact hole is also located in the first region and exposes the first lower metal layer, and the second contact hole is also located in the third region and exposes the second lower metal layer; the method of forming the first contact hole and the second contact hole further includes: after etching the second dielectric layer, etching the exposed substrate until the top surface of the first lower metal layer and the top surface of the second lower metal layer are exposed.

13. The method for forming a capacitor element as claimed in claim 10, characterized in that, The method for forming the first conductive plug and the second conductive plug further includes: depositing a conductive material layer on the surface of the second dielectric layer, the first contact hole, and the second contact hole; planarizing the conductive material layer to form the first conductive plug in the first contact hole and the second conductive plug in the second contact hole.

14. The method for forming a capacitor element as described in claim 13, characterized in that, A first upper metal layer and a second upper metal layer, which are mutually independent, are also formed on the surface of the second dielectric layer. The first upper metal layer is located on the surface of the first conductive plug, and the second upper metal layer is located on the surface of the second conductive plug.

15. The method for forming a capacitor element as described in claim 9, characterized in that, The process of patterning the first electrode material layer includes a dry etching process.

16. The method for forming a capacitor element as described in claim 9, characterized in that, The process for patterning the second electrode material layer includes a dry etching process.

17. The method for forming a capacitor element as claimed in claim 9, characterized in that, The formation process of the first electrode material layer includes physical vapor deposition; the formation process of the second electrode material layer includes physical vapor deposition.

18. The method for forming a capacitor element as described in claim 7, characterized in that, The material of the first electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni; the material of the second electrode layer includes one or more of TiN, TaN, Ta, W, TiO, Ti, Pt and Ni.

19. The method for forming a capacitor element as claimed in claim 7, characterized in that, The material of the first dielectric layer includes one or more of HfO, AlO, ZrO and LaO.

20. The method for forming a capacitor element as described in claim 7, characterized in that, The thickness of the first electrode layer ranges from 300 angstroms to 800 angstroms; the thickness of the second electrode layer ranges from 300 angstroms to 800 angstroms.

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