Memory device and forming method thereof

Abstract

The embodiment of the invention provides a memory device and a forming method thereof. The memory device includes a plurality of peripheral transistors formed along a first surface of a substrate; a plurality of memory cells formed in one or more of a plurality of first metallization layers disposed over the first surface, each of the plurality of memory cells operably coupled to a subset of the peripheral transistors and including a program transistor and at least a first read transistor; and a plurality of second metallization layers disposed over a second surface of the substrate opposite the first surface; wherein a first source / drain terminal of the program transistor is electrically connected with a first source / drain terminal of the first read transistor, and a second source / drain terminal of the first read transistor is electrically connected with a bit line formed in a corresponding one of the second metallization layers.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming the same. Background Art

[0002] The development of electronic devices (such as computers, portable devices, smartphones, IoT devices, etc.) has led to an increase in demand for memory devices. Generally, memory devices can be volatile memory devices and non-volatile memory devices. Volatile memory devices can store data when power is supplied, but once the power is turned off, the stored data may be lost. Unlike volatile memory devices, non-volatile memory devices can retain data even after the power is turned off, but may be slower than volatile memory devices. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a memory device is provided, comprising: a plurality of peripheral transistors formed along a first surface of a substrate; a plurality of memory cells formed in one or more first metallization layers of a plurality of first metallization layers disposed above the first surface, each of the plurality of memory cells being operably coupled to a subset of the peripheral transistors and comprising a programming transistor and at least a first read transistor; and a plurality of second metallization layers disposed above a second surface of the substrate opposite to the first surface; wherein a first source / drain terminal of the programming transistor is electrically connected to a first source / drain terminal of the first read transistor, and a second source / drain terminal of the first read transistor is electrically connected to a bit line formed in a corresponding one of the second metallization layers.

[0004] According to another aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell. The memory cell comprises: a programming transistor; and a first reading transistor electrically connected in series with the programming transistor and electrically connected to a bit line. The memory cell is formed in one of a plurality of first metallization layers formed above a first surface of a substrate; and the bit line is formed in one of a plurality of second metallization layers formed above a second surface of the substrate opposite to the first surface.

[0005] According to another aspect of an embodiment of the present application, a method for forming a memory device is provided, comprising: forming a plurality of peripheral transistors along a first surface of a substrate; forming a plurality of first metallization layers disposed above the first surface; forming a plurality of memory cells in one or more of the plurality of first metallization layers, wherein each of the plurality of memory cells is operably coupled to a subset of the peripheral transistors and includes a programming transistor and at least a read transistor; forming a plurality of second metallization layers disposed above a second surface of the substrate opposite to the first surface; and coupling the source / drain terminal of the read transistor of each memory cell to a bit line formed in a corresponding one of the second metallization layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A An example block diagram of a memory device according to some embodiments is shown.

[0008] Figure 1B According to some embodiments Figure 1A An example circuit diagram of a portion of a memory device.

[0009] Figure 2A According to some embodiments Figure 1A and Figure 1B An example circuit diagram of an anti-fuse memory cell of a memory device of FIG.

[0010] Figure 2B According to other embodiments Figure 1A and Figure 1B An example circuit diagram of an anti-fuse memory cell of a memory device of FIG.

[0011] Figure 2C According to other embodiments Figure 1A and Figure 1B An example circuit diagram of an anti-fuse memory cell of a memory device of FIG.

[0012] Figure 3A According to some embodiments Figure 2A-2C An example diagram of an access transistor of a memory cell.

[0013] Figure 3B According to other embodiments Figure 2A-2C An example diagram of an access transistor of a memory cell.

[0014] Figure 4 , Figure 5 and Figure 6 Various cross-sectional views of a memory device according to some embodiments are shown.

[0015] Figure 7 , Figure 8 and Fig. 9 Various cross-sectional views of memory devices according to other embodiments are shown.

[0016] Fig.10 A block diagram of a memory device according to some embodiments is shown.

[0017] Fig.11 The manufacturing method according to some embodiments is shown Fig.10 A flowchart of a method for a memory device. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0020] Integrated circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM) in which data is not lost when the IC is powered off. One type of OTP device includes an anti-fuse memory. The anti-fuse memory includes a plurality of anti-fuse memory cells (or bit cells) whose terminals are disconnected before programming and short-circuited (e.g., connected) after programming. The anti-fuse memory can be based on metal oxide semiconductor (MOS) technology. For example, an anti-fuse memory cell can include a programming MOS transistor (or MOS capacitor) and at least one reading MOS transistor coupled in series. The gate dielectric of the programming MOS transistor can be broken down so that the gate and source or drain of the programming MOS transistor are interconnected. Depending on whether the gate dielectric of the programming MOS transistor is broken down, the anti-fuse memory cell can present different data bits by reading the composite current flowing through the programming MOS transistor and the reading MOS transistor. Since the programming state of the anti-fuse cell cannot be determined by reverse engineering, the anti-fuse memory has the advantageous feature of reverse engineering proof.

[0021] Embodiments of the present disclosure provide various embodiments of a memory device, which includes a plurality of peripheral transistors formed along a first surface of a substrate, a plurality of memory cells formed in one or more of a plurality of first metallization layers disposed above the first surface, and a plurality of second metallization layers disposed on a second surface of the substrate opposite to the first surface. Each of the plurality of memory cells includes a programming transistor and at least one reading transistor, operably coupled to a subset of the peripheral transistors, and serves as an anti-fuse memory cell, wherein the gate dielectric of the programming transistor is configured to be permanently broken down after being programmed. The source / drain terminal of the reading transistor is electrically connected to the source / drain terminal of the programming transistor, and the other source / drain terminal of the reading transistor is electrically connected to a bit line formed in one of the second metallization layers. Utilizing various combinations of different types of transistors in each memory cell, and a stacked arrangement of the memory cells relative to the peripheral transistors and the bit lines, the memory device can advantageously have a reduced area and an improved reading speed, thereby advantageously leading to a more compact chip design and more robust chip performance.

[0022] Figure 1A 1 shows an example block diagram of a memory device 100 according to some embodiments. Figure 1A In the illustrated embodiment, memory system 100 includes memory array 102, row decoder 104, column decoder 106, input / output (I / O) circuit 108, and control logic circuit 112. Although not shown in FIG. Figure 1A 1, all components of memory system 100 may be coupled to each other and to control logic circuit 112. Figure 1AIn the illustrated embodiment, for the purpose of clarity, each component is shown as a separate block, but in some other embodiments, Figure 1A Some or all of the components shown in are integrated together.

[0023] The memory array 102 is a hardware component that stores data. In one aspect, the memory array 102 is embodied as a semiconductor memory device. The memory array 102 includes a plurality of memory cells (or other memory cells) 103. The memory array 102 includes a plurality of rows R1, R2, R3, ... R M , each row extends in a first direction (eg, X direction), and a plurality of columns C1, C2, C3 . . . C N , each column extends in a second direction (eg, the Y direction). Each of the rows / columns may include one or more conductive structures that function as access lines.

[0024] In some embodiments, each memory cell 103 is arranged at the intersection of a corresponding row and a corresponding column, and can be operated according to a voltage or current through a corresponding conductive structure of the row and column. In some embodiments, each memory cell 103 is implemented as an anti-fuse memory cell including a programming transistor and one or more read transistors. Details about the anti-fuse memory cell 103 (e.g., 103A) will be described below with respect to Figure 2A , Figure 2B and Figure 2C Have a discussion.

[0025] The row decoder 104 is a hardware component that can receive a row address of the memory array 102 and assert a conductive structure (e.g., a word line) at the row address. The column decoder 106 is a hardware component that can receive a column address of the memory array 102 and assert one or more conductive structures (e.g., a pair of source lines) at the column address. The I / O circuit 108 is a hardware component that can access (e.g., read or program) each of the memory cells 103 asserted by the row decoder 104 and the column decoder 106. The control logic circuit 112 is a hardware component that can control the coupled components (e.g., the memory array 102 to the I / O circuit 108).

[0026] Figure 1B 1 shows an example circuit diagram of a portion of a memory device 100 (eg, some memory cells 103) according to some embodiments. Figure 1B In the Figure 1A 1. The memory array 102 of FIG. 1 includes anti-fuse memory cells 103A, 103B, 103C, and 103D, however it should be understood that the memory array 102 may have any number of anti-fuse memory cells 103 while remaining within the scope of the present disclosure.

[0027] As described above, the memory cells 103 may be arranged in an array. Figure 1B In the embodiment, memory cells 103A and 103B may be arranged in the same row but in different columns; and memory cells 103C and 103D may be arranged in the same row but in different columns. For example, memory cells 103A and 103B are arranged in row R1, but in different columns C1 and C2; and memory cells 103C and 103D are arranged in row R2, but in different columns C1 and C2. With such a configuration, each memory cell may be operably coupled to an access line in a corresponding row and column, respectively.

[0028] In some embodiments, each of the memory cells 103A to 103D can be operably coupled to the I / O circuit 108 through the corresponding WLR, WLP, and BL to be accessed (e.g., programmed, read). For example, the I / O circuit 108 can cause the row decoder 104 to assert WLP1 and WLR1, and cause the column decoder 106 to assert BL1, in order to access the memory cell 103A. Thus, each of the memory cells 103A to 103D can be individually selected for programming or reading. The details of programming and reading the memory cells will be discussed in further detail below.

[0029] Each of the memory cells 103A to 103D includes a programming transistor and at least one reading transistor coupled in series. According to various embodiments, in each memory cell, the programming transistor is gated by WLP and at least one reading transistor is gated by WLR. Figure 1B As shown, for example, memory cell 103A includes a programming transistor 120 gated by WLP1 and a reading transistor 124 gated by WLR1. In the following discussion, memory cell 103A is selected as a representative example.

[0030] Figure 2A According to some embodiments Figure 1A and Figure 1B 1. Each of the other memory cells (e.g., Figure 1B 103B, 103C, 103D) in the memory cell 103A can be configured substantially similar to the memory cell 103A. In some embodiments, the anti-fuse memory cell 103A is implemented as a three-transistor (3T) symmetrical configuration and includes a programming transistor 120, a first read transistor 124, and a second read transistor 126, wherein the programming transistor 120 is electrically coupled in series between the first read transistor 124 and the second read transistor 126.

[0031] like Figure 2AAs shown, in some embodiments, a source / drain terminal 120D of the programming transistor 120 is coupled to a source / drain terminal 124D of the first read transistor 124, and another source / drain terminal 120S of the programming transistor 120 is coupled to a source / drain 126D of the second read transistor 126. In some embodiments, the source / drain terminal 124S of the first read transistor 124 and the source / drain terminal 126S of the second read transistor 126 are commonly coupled to the bit line BL1.

[0032] Likewise Figure 2A As shown, in some embodiments, the programming transistor 120 is gated by WLP1. The first read transistor 124 and the second read transistor 126 are commonly gated by WLR1 via the gate terminal 124G of the read transistor 124 and the gate terminal 126G of the read transistor 126, respectively. However, it should be understood that the gate terminals of the read transistors can be coupled to different WLRs.

[0033] Figure 2B According to other embodiments Figure 1A and Figure 1B An example circuit diagram of an anti-fuse memory cell 103A of a memory device of FIG. Figure 2B The anti-fuse memory cell 103A shown is also implemented as a 3T configuration, but unlike Figure 2A The anti-fuse memory cell 205A is shown with some differences.

[0034] like Figure 2B As shown, in some embodiments, the anti-fuse memory cell 103A includes a programming transistor 120, a first read transistor 124, and a second read transistor 126, wherein the second read transistor 126 is electrically coupled in series between the first read transistor 124 and the programming transistor 120. The programming transistor 120 is gated by WLP1, and the first read transistor 124 and the second read transistor 126 are commonly gated by WLR1.

[0035] like Figure 2B As shown, in some embodiments, a source / drain terminal 126S of the second read transistor 126 is coupled to a source / drain terminal 124D of the first read transistor 124, and another source / drain terminal 126D of the second read transistor 126 is coupled to a source / drain 120D of the programming transistor 120. In some embodiments, another source / drain terminal 124S of the first read transistor 124 is coupled to the bit line BL1, and another source / drain terminal 120S of the programming transistor 120 is floating.

[0036] Figure 2C According to other embodiments Figure 1A and Figure 1BAn example circuit diagram of an anti-fuse memory cell 103A of a memory device of FIG. Figure 2A and Figure 2B The anti-fuse memory cell 103A shown is different, as Figure 2C The anti-fuse memory cell 205A is shown implemented as a two-transistor (2T) configuration.

[0037] like Figure 2C As shown, in some embodiments, the anti-fuse memory cell 103A includes a programming transistor 120 and a first reading transistor 124 coupled in series, wherein the programming transistor 120 is gated by WLP1 and the first reading transistor 124 is gated by WLR1. In some embodiments, a source / drain terminal 120S of the programming transistor 120 is coupled to a source / drain terminal 124D of the first reading transistor 124, another source / drain terminal 124S of the first reading transistor 124 is coupled to the bit line BL1, and another source / drain terminal 120D of the programming transistor 120 is floating.

[0038] Figure 3A According to some embodiments Figure 2A-2C 1. An example diagram of an access transistor 300A of a memory cell 103A. Figure 3A The access transistor 300A shown may be implemented as Figure 2A-2C Any one of the programming transistor 120, the first read transistor 124 and the second read transistor 126 shown.

[0039] like Figure 3A As shown, in some embodiments, the access transistor 300A includes a bottom gate 316, a gate dielectric 318 disposed above the bottom gate 316, a channel structure 320 disposed above the gate dielectric 318, and a pair of source / drain structures 322 and 324 disposed above the channel structure 320. The access transistor 300A may be referred to as a "two-dimensional back-gate transistor" or "2D transistor". The term "two-dimensional back-gate transistor" may refer to a transistor whose gate is formed as a relatively planar or thin structure and whose channel structure contacts the top surface of its gate. In some embodiments, the bottom gate 316 includes TiN, the gate dielectric 318 includes a high-K dielectric material (e.g., HfO2), the channel structure 320 includes InGaZnO (IGZO), and the source / drain structures 322 and 324 include TiN.

[0040] Figure 3B According to other embodiments Figure 2A-2C 103A of the memory cell 103A. Figure 3B The access transistor 300B shown may be implemented as Figure 2A-2CAny one of the programming transistor 120, the first read transistor 124 and the second read transistor 126 shown.

[0041] like Figure 3B As shown, in some embodiments, the access transistor 300B includes a bottom gate 326, a gate dielectric 328 disposed above the bottom gate 326, a channel structure 330 disposed above the gate dielectric 328, and a pair of source / drain structures 332 and 334 disposed above the channel structure 330. The access transistor 300B may be referred to as a "three-dimensional back-gate transistor" or "3D transistor". The term "three-dimensional back-gate transistor" may refer to a transistor whose gate is formed as a relatively protruding structure and whose channel structure contacts multiple surfaces of its gate. In some embodiments, the bottom gate 326 includes TiN, the gate dielectric 328 includes a high-K dielectric material (e.g., HfO2), the channel structure 330 includes InGaZnO (IGZO), and the source / drain structures 332 and 334 include TiN.

[0042] In some embodiments, the programming transistor and one or more read transistors in the memory cell are implemented as a single type of transistor (eg, 2D transistor 300A) (eg, Figure 4 , Figure 5 and Figure 6 In other embodiments, the programming transistor and one or more read transistors in the memory cell are implemented as a combination of different types of transistors (e.g., 2D transistors and 3D transistors) (e.g., Figure 7 , Figure 8 and Fig. 9 ). Figure 4-Figure 9 Details regarding the arrangement and configuration of a programming transistor and one or more read transistors in a memory cell of a memory device are explained.

[0043] Figure 4 , Figure 5 and Figure 6 4 and 5. The memory devices 400, 500 and 600 according to some embodiments of the present disclosure are shown in respective cross-sectional views, each memory device including an anti-fuse memory cell (corresponding to Figure 2A-2C 103A), which includes a programming transistor and one or more reading transistors (corresponding to Figure 2A-2C 120 and 124 / 126), are implemented as a single type (e.g., Figure 3A 2D transistor shown). Figure 4 , Figure 5 and Figure 6Simplified to illustrate the configuration and relative spatial arrangement of relevant features and structures. Therefore, it should be understood that each of the memory devices 400, 500 and 600 can include one or more other features and structures while remaining within the scope of the present disclosure. With such configuration and arrangement, the memory devices 400, 500 and 600 can advantageously obtain an increased read window.

[0044] refer to Figure 4 In some embodiments, the memory device 400 includes a substrate 401 having a first surface (or front side) 402 and a second surface (or back side) 403 opposite to the first surface 402, a plurality of peripheral transistors (e.g., peripheral transistors 410) formed along the first surface 402 of the substrate 401, a plurality of first metallization layers 430 (e.g., M0, M1, M2, M3, ...) disposed above the first surface 402, a plurality of anti-fuse memory cells (e.g., anti-fuse memory cells 420) formed in one or more of the plurality of first metallization layers 430, and a plurality of second metallization layers 440 (e.g., BM0) disposed above the second surface 403 of the substrate 401. In some embodiments, the anti-fuse memory cells 420 are operably coupled to the one or more peripheral transistors (e.g., 410) and are operably coupled to a bit line (BL) 482 formed in a corresponding one (e.g., BM0) of the second metallization layers 440 formed above the second surface 403 of the substrate 401.

[0045] In some embodiments, the peripheral transistor 410 is implemented as a full-all-around FET (GAA FET). However, it should be understood that the peripheral transistor 410 can be implemented as any of a variety of other types of transistor structures while remaining within the scope of the present disclosure. In some embodiments, the peripheral transistor 410 includes a channel structure 408, a source / drain structure 412, and an active (e.g., metal) gate structure 414. The channel structure 408 includes one or more nanostructures (e.g., nanosheets, nanowires) vertically spaced apart from each other along the Z direction. The metal gate structure 414 surrounds each nanostructure of the channel structure 408, wherein the source / drain structure 412 is coupled to the end of the channel structure 408 along the X direction.

[0046] The peripheral transistor 410 may also include a plurality of intermediate conductor (e.g., metal) structures, and each intermediate conductor structure may provide an electrical connection path for a corresponding gate structure 414 or source / drain structure 412. For example, the peripheral device 410 includes intermediate conductor structures 432 and 434. The intermediate conductor structure 434 is formed as a via structure and is in electrical contact with the gate structure 414 (sometimes referred to as "VG"), and the intermediate conductor structure 432 is formed as a via structure and is electrically connected to the source / drain structure 412 (sometimes referred to as "MD"). Hereinafter, the peripheral transistor 410 is referred to as being formed in a front-end process (FEOL) network.

[0047] Above the middle-end interconnect structures (e.g., VG and MD), the memory device 400 may further include a plurality of front-side metallization layers, such as M0, M1, M2, etc. Each metallization layer includes a plurality of back-end conductor structures, such as metal lines and via structures, embedded in a corresponding dielectric material (e.g., IMD or ILD). The IMD / ILD may include one or more of a low-k dielectric layer (i.e., a dielectric having a dielectric constant less than about 3.9), an ultra-low-k dielectric layer, or an oxide (e.g., silicon oxide).

[0048] like Figure 4 As shown, the memory device 400 includes multiple front-side metallization layers, such as M0, M1, M2, and M3. Although four front-side metallization layers are shown, it should be understood that the memory device 400 may include any number of front-side metallization layers while remaining within the scope of the present disclosure. For example, metallization layer M0 includes metal lines, such as 442, 443, and 444 (sometimes referred to as "M0 tracks"), and via structures, such as 452, 453, and 454 (sometimes also referred to as "V0"); metallization layer M1 includes metal lines, such as 462, 463, and 464 (sometimes referred to as "M1 tracks"), and via structures, such as 472 and 473 (sometimes also referred to as "V1"); metallization layer M2 includes metal lines such as 483 (sometimes referred to as "M2 tracks") and via structures such as 493 (sometimes also referred to as "V2"). In Figure 4 In the example shown, an anti-fuse memory cell 420 including three anti-fuse transistors 422, 424, and 426 is formed in the M2 layer. Hereinafter, the anti-fuse memory cell 420 is referred to as being formed in a back-end-of-line (BEOL) network.

[0049] like Figure 4 and Figure 2A As shown, in some embodiments, the anti-fuse memory cell 420 in the BEOL network is implemented as a 3T configuration and includes a first read transistor 424, a second read transistor 426, and a programming transistor 422 coupled in series between the first read transistor 424 and the second read transistor 426 (corresponding to Figure 2A In some embodiments, all programming transistors 422 and first read transistor 424 and second read transistor 426 are of the same type (e.g., Figure 3A 2D transistor shown).

[0050] like Figure 4 and Figure 2A As shown, the programming transistor 422 is electrically connected in series between the first read transistor 424 and the second read transistor 426, and the first read transistor 422 and the second read transistor 426 are commonly electrically connected to a bit line 482 formed in one of the second metallization layers 440 on the back side of the substrate.

[0051] Next reference Figure 5 , the memory device 500 is similar to Figure 4 A memory device 400 is shown. Figure 5 The relative spatial arrangement of the components described above is simplified to illustrate the structure and some structures and components are omitted. All programming transistors and first and second reading transistors are of the same type (e.g., Figure 3A 2D type shown). The memory device 500 includes a plurality of peripheral transistors 510 formed on a first (front side) surface of a substrate in a FEOL network, a plurality of first metallization layers 530 disposed above the first surface, a plurality of anti-fuse memory cells 520 formed in one or more of the plurality of first metallization layers in a BEOL network, and a plurality of second metallization layers 540 disposed on a second surface (back side) of the substrate opposite to the first surface. In some embodiments, the anti-fuse memory cells 520 are operably coupled to the one or more peripheral transistors 510 and are operably coupled to a bit line (BL) 582 formed in one of the second metallization layers.

[0052] However, if Figure 5 The memory cell 520 (corresponding to Figure 2B The configuration of the memory cell 103A) shown is different from that shown in FIG. Figure 4 The memory cell 420 (corresponding to Figure 2A In some embodiments, the anti-fuse memory cell 520 includes a first read transistor 524, a programming transistor 522, and a second read transistor 526 coupled in series between the first read transistor 524 and the programming transistor 522. In some embodiments, the first read transistor 524 is electrically connected to a bit line 582 formed in one of the second metallization layers over the back side of the substrate 501. In some embodiments, one of the source / drain terminals of the programming transistor 522 is floating.

[0053] Next, further reference Figure 6 , the memory device 600 is similar to Figure 4 A memory device 400 is shown. Figure 6 The memory device 600 includes a plurality of peripheral transistors 610 formed along a first surface of a substrate 601, a plurality of first metallization layers 630 disposed above the first (front) surface, a plurality of anti-fuse memory cells 620 formed in one or more of the plurality of first metallization layers, and a plurality of second metallization layers 640 disposed above a second (back) surface of the substrate opposite to the first surface. In some embodiments, the anti-fuse memory cells 620 are operably coupled to one or more peripheral transistors 610 and are operably coupled to a bit line (BL) 682 formed in one of the second metallization layers.

[0054] However, if Figure 6 The memory cell 620 (corresponding to Figure 2C The configuration of the memory cell 103A) shown is different from that shown in FIG. Figure 4 The memory cell 420 (corresponding to Figure 2A 103A). In some embodiments, the anti-fuse memory cell 620 includes a first read transistor 624 and a programming transistor 622 connected in series. In some embodiments, the first read transistor 624 is electrically connected to a bit line 682 formed in one of the second metallization layers. In some embodiments, one of the source / drain terminals of the programming transistor 622 is floating. The programming transistor and the first read transistor are both implemented as the same type of transistor (e.g., Figure 3A 2D transistor shown).

[0055] Figure 7 , Figure 8 and Fig. 9 700, 800, and 900 are cross-sectional views of memory devices according to other embodiments of the present disclosure, each memory device including an anti-fuse memory cell (eg, corresponding to Figure 2A-2C 103A), the anti-fuse memory cell includes a programming transistor and one or more read transistors of different types (eg, 2D and 3D transistors) (eg, Figure 2A-2C 120 and 124 / 126 shown correspond). Figure 7 , Figure 8 and Fig. 9 It is simplified to illustrate the relative spatial arrangement of the above-mentioned components, and some structures and components are omitted.

[0056] Figure 7 , Figure 8 and Fig. 9 The embodiment shown is Figure 4 , Figure 5 and Figure 6 The embodiments shown are similar, except that the programming transistor and one or more read transistors are implemented as transistors of different types (e.g., 2D and 3D) in combination. In some embodiments, the programming transistor is formed as a 2D transistor, and one or more read transistors are formed as a 3D transistor in combination. Therefore, the read transistor of the memory device can advantageously obtain a faster read speed.

[0057] refer to Figure 7 , except that the configuration of the three-transistor (3T) memory cell 720 of the memory device 700 is different from Figure 4 In addition to the configuration of the 3T memory cell 420 shown, the memory device 700 is similar to Figure 4 4. In some embodiments, the 3T memory cell 720 includes a first read transistor 724 and a second read transistor 726 configured as 3D-type transistors (eg, Figure 3B ), and a programming transistor 722 configured as a 2D transistor (as in Figure 3A As shown in FIG. 7 , the programming transistor 722 is coupled in series between the first reading transistor 724 and the second reading transistor 726 .

[0058] Next reference Figure 8 , the memory device 800 is similar to Figure 7 The memory device 700 shown in FIG. 1 is different in that, in the 3T memory cell 820 , the 3D second read transistor 826 is coupled in series between the 3D first read transistor 824 and the 2D programming transistor 822 . Fig. 9 , the memory device 900 is similar to Figure 6 The memory device 600 shown in FIG. 1 is different in that the configuration of the 2T memory cell 920 of the memory device 900 is the same as that of the memory device 600 shown in FIG. Figure 6 The configuration of the 2T memory cell 620 shown in FIG. 6 is different. In some embodiments, the 2T anti-fuse memory cell 920 includes a 3D first read transistor 924 and a 2D programming transistor 922 .

[0059] Fig.10 1 shows a block diagram of a memory device 1000 including anti-fuse memory cells (eg, 1020) according to some embodiments, each of which includes a programming transistor and one or more read transistors (eg, Figure 5-Figure 9 shown). Fig.10It is simplified to illustrate the relative spatial configuration of the above-mentioned components. Therefore, it should be understood that the memory device 1000 can include one or more other features and structures while remaining within the scope of the present disclosure.

[0060] like Fig.10 As shown, the memory device 1000 includes at least one peripheral transistor (such as GAA FET 1010) formed along the main front surface 1002 of the substrate 1001 in the FEOL network, and at least one anti-fuse memory cell 1020 each including a programming transistor and at least one reading transistor (such as 1022 and 1024) formed in the BEOL network on the FEOL network. The peripheral transistor 1010 is operable to serve as a function or control circuit of the anti-fuse memory cell 1020 (e.g., corresponding to Figure 1A The row decoder 104, column decoder 106, I / O circuit 108, and control logic circuit 112 are shown. The programming transistor 1022 and at least one read transistor 1024 of the anti-fuse memory cell 1020 are both formed in one of a plurality of front-side metallization layers formed in the BEOL network. For example, the programming transistor 1021 and the read transistor 1024 are both formed in the front-side metallization layer M2 (e.g., Figure 4 In some embodiments, the anti-fuse memory cell 1020 is operably coupled to a bit line (BL) 1082 formed on a plurality of backside metallization layers (e.g., as shown) disposed above the backside surface 1003 of the substrate 1001. Figure 4 One or more of BM0, BM1, MB2, etc. Fig.10 As shown, the bit line 1082 is formed in the backside metallization layer BM0. In this way, in particular, the area of ​​the memory device 1000 can be advantageously reduced.

[0061] In some embodiments, all programming transistors 1402 and at least one reading transistor 1404 may be configured as 2D back-gate transistors (eg, Figure 4-Figure 6 In other embodiments, the programming transistor 1402 may be configured as a combination of 2D and 3D back-gate transistors (eg, Figure 7-Figure 9 shown).

[0062] Fig.11 The manufacturing method according to some embodiments is shown as follows Fig.10 1100 of the memory device shown in FIG. 1101 . It should be understood that additional embodiments of the method may be Fig.11Additional operations may be provided before, during, and after the processes discussed in the foregoing, and some operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable, and at least some operations or processes may be performed in different orders. In some embodiments, at least two or more operations or processes overlap in time or are performed almost simultaneously.

[0063] In operation S1110, Fig.10 and Fig.11 As shown, a plurality of peripheral transistors (eg, 1010) are formed along a first surface (front side) 1002 of a substrate 1001 in a FEOL network. For example, various oxidation, photolithography, deposition, and etching methods may be used to form the plurality of peripheral transistors 1010.

[0064] In some embodiments, the substrate includes a single crystal semiconductor layer at least on a surface portion thereof. The substrate may include a single crystal semiconductor material, such as but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 1001 is a silicon wafer. The substrate may include one or more buffer layers (not shown) in its surface region. The buffer layer may be used to gradually change the lattice constant from the lattice constant of the substrate to the lattice constant of the source / drain region.

[0065] In operation S1120, Fig.10 and Fig.11 As shown, a plurality of first metallization layers 1030 (such as Figure 4 The metallization layers 103 are stacked above the first surface 1002 of the substrate 1001 in the BEOL network. As part of the BEOL network, these metallization layers 103 are generally disposed on the main surface 1002 of the front side of the substrate 1001, and each metallization layer includes a plurality of metal structures (such as metal lines or vias) embedded in an interlayer dielectric (ILD) or an intermetallic dielectric (IMD).

[0066] In operation S1130, Fig.10 and Fig.11 As shown, a plurality of memory cells 1020 are formed in one of a plurality of first metallization layers 1030 in a BEOL network. Fig.10 As shown, a memory cell 1020 including a programming transistor 1022 and a reading transistor 1024 is formed in a metallization layer M2 of the plurality of first metallization layers 103. As part of a BEOL network, each memory cell 1020 is operably coupled to a subset of peripheral transistors (such as peripheral transistor 1010), which are part of a FEOL network. For example, referring to Figure 4-Figure 9There are various configurations of memory cells based on combinations of transistor types (e.g., 2D and 3D transistors), and there are multiple arrangements of memory cells based on the spatial relationship of the programming transistor and one or more read transistors in each memory cell.

[0067] In operation S1140, Fig.10 and Fig.11 As shown, the substrate 1001 is flipped over so that various operations such as oxidation, photolithography, deposition, CMP, and etching (wet etching or dry etching) can be performed from the back side 1003 of the substrate 1001.

[0068] In operation S1150, if Fig.10 and Fig.11 As shown, a plurality of second metallization layers 1040 (eg, BM0, BM1, BM2, ...) may be formed over a second surface (back side) 1003 of the substrate 1001 opposite to the first surface 1002. For example, as Fig.10 As shown, the bit line BL 1082 is formed in layer BM0 of the plurality of second metallization layers 1040 on the back side of the substrate 1001. The plurality of second metallization layers 1040 may be formed on the back side of the substrate 1001 using various methods such as oxidation, photolithography, deposition, and etching (wet or dry etching).

[0069] In operation S1160, if Figure 4 As shown, the source / drain terminals of the read transistor of each memory cell formed on the front side of the substrate are coupled to a bit line formed in a corresponding one of the second metallization layers (e.g., BM0) formed on the back side of the substrate. In other embodiments, for example, Figure 2A As shown, the source / drain terminals of the first read transistor and the drain / source terminals of the second read transistor of each memory cell are commonly coupled to a bit line formed in a corresponding one of the second metallization layers on the back side of the substrate.

[0070] In some embodiments, Figure 4 As shown, the source / drain terminals of the read transistor (eg, 424) of each memory cell 400 are coupled to the bit line 482 through a first via structure (eg, 493), the first via extending in a vertical direction and having a first width. Figure 4As shown, the source / drain terminal of the read transistor 424 of each memory cell 400 is coupled to the bit line 482 through a second via structure (e.g., 473), which extends in a vertical direction and has a second width greater than the first width of the first via structure 493. The first via structure can save space in the memory device, while the second via structure can result in a reduced resistance in the programming path. Various combinations and configurations of via structures can be adjusted to reduce resistance in the programming path while saving space in the memory device.

[0071] In the present disclosure, in some embodiments, a memory device includes a plurality of peripheral transistors formed along the front side of a substrate in a FEOL network, a plurality of anti-fuse memory cells formed in one of a plurality of first metallization layers, the plurality of first metallization layers being formed in a BEOL network on the FEOL network, and a plurality of bit lines formed in one of a plurality of second metallization layers, the second metallization layer being formed on the back side of the substrate opposite to the front side. Each of the plurality of anti-fuse memory cells is operably coupled to a subset of the plurality of peripheral transistors and is operably coupled to a bit line in the plurality of bit lines. Each of the plurality of anti-fuse memory cells includes a programming transistor and one or more read transistors. Based on, for example, the type of transistor (2D and 3D) and the number of transistors (e.g., 2T, 3T, or more T), there are various connections, combinations, and configurations for the programming transistor and the one or more read transistors in each of the plurality of anti-fuse memory cells. Therefore, the space of the memory device can be advantageously reduced, and the read speed of the memory can be advantageously increased, resulting in a more compact chip design and more robust chip performance.

[0072] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes: a plurality of peripheral transistors formed along a first surface of a substrate; a plurality of memory cells formed in one or more first metallization layers of a plurality of first metallization layers disposed above the first surface, each of the plurality of memory cells being operably coupled to a subset of the peripheral transistors and including a programming transistor and at least a first reading transistor; and a plurality of second metallization layers disposed above a second surface of the substrate opposite to the first surface; wherein a first source / drain terminal of the programming transistor is electrically connected to a first source / drain terminal of the first reading transistor, and a second source / drain terminal of the first reading transistor is electrically connected to a bit line formed in a corresponding one of the second metallization layers.

[0073] In some embodiments, each of the memory cells is operable to function as an anti-fuse memory cell, wherein the gate dielectric of the programming transistor is configured to permanently break down.

[0074] In some embodiments, the second source / drain terminal of the programming transistor is floating.

[0075] In some embodiments, each of the programming transistor and the first reading transistor has a semiconducting behavior material as its channel.

[0076] In some embodiments, the semiconductive behavior material is formed in a corresponding one of the first metallization layers and is formed as a two-dimensional film.

[0077] In some embodiments, the semiconductive behavior material is formed in a corresponding one of the first metallization layers and is formed into a three-dimensional structure.

[0078] In some embodiments, the subset of peripheral transistors includes a first peripheral transistor and a second peripheral transistor, the first peripheral transistor and the second peripheral transistor being operably coupled to a gate terminal of the programming transistor and a gate terminal of the first read transistor, respectively.

[0079] In some embodiments, each of the memory cells further includes a second read transistor electrically connected in series to the programming transistor and the first read transistor.

[0080] In some embodiments, the programming transistor is laterally interposed between the first read transistor and the second read transistor.

[0081] In some embodiments, the second read transistor is laterally interposed between the first read transistor and the programming transistor.

[0082] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory cell, the memory cell including a programming transistor and a first read transistor electrically connected in series with the programming transistor and electrically connected to a bit line. The memory cell is formed in one of a plurality of first metallization layers formed above a first surface of a substrate. The bit line is formed in one of a plurality of second metallization layers formed above a second surface of the substrate opposite to the first surface.

[0083] In some embodiments, the memory cell is operably coupled to a subset of a plurality of peripheral transistors formed along the first surface of the substrate.

[0084] In some embodiments, each of the programming transistor and the first reading transistor has a semiconducting behavior material as its channel.

[0085] In some embodiments, the memory cell further includes a second read transistor electrically connected in series with the programming transistor and the first read transistor.

[0086] In some embodiments, the programming transistor is electrically connected between the first read transistor and the second read transistor.

[0087] In some embodiments, the second read transistor is electrically connected between the first read transistor and the programming transistor.

[0088] In another aspect of the present disclosure, a method for manufacturing a memory device is disclosed. The method includes: forming a plurality of peripheral transistors along a first surface of a substrate; forming a plurality of first metallization layers disposed above the first surface; forming a plurality of memory cells in one or more of the plurality of first metallization layers, wherein each of the plurality of memory cells is operably coupled to a subset of the peripheral transistors and includes a programming transistor and at least a read transistor; forming a plurality of second metallization layers disposed above a second surface of the substrate opposite to the first surface; and coupling a source / drain terminal of the read transistor of each memory cell to a bit line formed in a corresponding one of the second metallization layers.

[0089] In some embodiments, source / drain terminals of the read transistor of each of the memory cells are coupled to the bit line through a first via structure, the first via structure extending in a lateral direction and having a first width.

[0090] In some embodiments, the source / drain terminals of the read transistor of each of the memory cells are further coupled to the bit line through a second via structure extending in the lateral direction and having a second width greater than the first width.

[0091] In some embodiments, each of the memory cells includes a plurality of transistors connected in series, and wherein each of the plurality of transistors has a semiconducting behavior material as its channel.

[0092] As used herein, the terms "about" and "approximately" generally refer to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may refer to a value of a given quantity that varies, for example, within a range of 10-30% of that value (e.g., +10%, ±20%, or ±30% of that value).

[0093] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, include: a plurality of peripheral transistors formed along a first surface of the substrate; a plurality of memory cells formed in one or more of a plurality of first metallization layers disposed over the first surface, each of the plurality of memory cells operably coupled to a subset of the peripheral transistors and including a programming transistor and at least a first read transistor; as well as a plurality of second metallization layers disposed over a second surface of the substrate opposite the first surface; The first source / drain terminal of the programming transistor is electrically connected to the first source / drain terminal of the first read transistor, and the second source / drain terminal of the first read transistor is electrically connected to a bit line formed in a corresponding one of the second metallization layers.

2. The memory device according to claim 1, in, Each of the memory cells is operable to function as an anti-fuse memory cell, wherein the gate dielectric of the programming transistor is configured to permanently break down.

3. The memory device according to claim 1, in, The second source / drain terminal of the programming transistor is floating.

4. The memory device according to claim 1, in, The subset of the peripheral transistors includes a first peripheral transistor and a second peripheral transistor, the first peripheral transistor and the second peripheral transistor being operably coupled to a gate terminal of the programming transistor and a gate terminal of the first reading transistor, respectively.

5. A memory device, include: A memory unit, the memory unit comprising: programming transistors; and a first read transistor electrically connected in series with the programming transistor and electrically connected to a bit line; wherein the memory cell is formed in one of a plurality of first metallization layers formed above a first surface of the substrate; and The bit line is formed in one of a plurality of second metallization layers formed on a second surface of the substrate opposite to the first surface.

6. The memory device according to claim 5, in, Each of the programming transistor and the first reading transistor has a semiconducting behavior material as a channel thereof.

7. The memory device according to claim 5, in, The memory cell also includes a second read transistor electrically connected in series with the programming transistor and the first read transistor.

8. A method for forming a memory device, include: forming a plurality of peripheral transistors along a first surface of the substrate; forming a plurality of first metallization layers disposed over the first surface; forming a plurality of memory cells in one or more of the plurality of first metallization layers, wherein each of the plurality of memory cells is operably coupled to a subset of the peripheral transistors and includes a programming transistor and at least a read transistor; forming a plurality of second metallization layers disposed over a second surface of the substrate opposite the first surface; and A source / drain terminal of the read transistor of each of the memory cells is coupled to a bit line formed in a corresponding one of the second metallization layers.

9. The method according to claim 8, in, The source / drain terminals of the read transistor of each of the memory cells are coupled to the bit line through a first via structure extending in a lateral direction and having a first width.

10. The method according to claim 9, in, The source / drain terminals of the read transistor of each of the memory cells are further coupled to the bit line through a second via structure extending in the lateral direction and having a second width greater than the first width.

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