Universal method for testing single event effect of SiP device

Abstract

The invention discloses a general method for testing the single event effect of a SiP device, and the method comprises the steps: carrying out the uncapping or thinning of the SiP device according to the depth information of a sensitive region of the SiP device; the method comprises the following steps: determining sensitive modules of embedded chips according to structures and models of the embedded chips of the SiP device, and carrying out irradiation test analysis on the sensitive modules to obtain single event effect test items of the SiP device; determining a test scheme, and performing targeted design on test software and hardware; carrying out simulation verification on the designed software and hardware injection error mode, if the simulation verification is not passed, modifying the test program, and carrying out simulation verification again; performing a single particle test on each embedded chip; carrying out an irradiation test on the SiP device; and after the test is completed, uploading, storing and analyzing test data, and ending the test. The problems that the SiP single event effect ground test is inaccurate, and the test method and the test device are limited by specific models are solved.

Description

Technical Field

[0001] The invention relates to a general method for testing single particle effects of a SiP device, belonging to the technical field of single particle experiments. Background Art

[0002] Since the 21st century, with the rapid development of aerospace technology, higher requirements have been placed on the integration and miniaturization of onboard computer electronic systems. From the perspective of system integration, system-level packaging (SiP) is an effective way to promote the miniaturization, high performance, low power consumption, and high reliability of electronic systems. It uses three-dimensional stacking packaging technology to package multiple bare chips of electronic components with different functions into a microsystem, mainly including field programmable gate arrays (FPGAs), memories, analog-to-digital converters (ADCs), digital signal processors (DSPs), etc. It has become the first choice for onboard computers because of its miniaturization, high performance, low power consumption, low cost, short R&D cycle, and rapid iteration.

[0003] In space, affected by space radiation, when a single high-energy particle hits a SiP device, a large number of electron-hole pairs will be generated near the particle track. These electron-hole pairs are collected by sensitive modules in the SiP, causing device malfunction or failure, which is called single event effect (SEE). Therefore, aerospace-grade SiP needs to undergo ground-based radiation hardening testing and evaluation.

[0004] Currently in the field of single particle effect testing of SiP devices, there is no universal method for single particle effect testing of SiP devices due to the differences in the chips packaged in different types of SiP devices. Summary of the invention

[0005] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a general method for testing single particle effects of SiP devices, and to solve the problems of inaccurate ground testing of SiP single particle effects and the limitation of testing methods and testing devices to specific models.

[0006] The technical solution of the present invention is: a general method for testing single-particle effects of SiP devices, comprising:

[0007] According to the depth information of the sensitive area of ​​the SiP device, the SiP device is opened or thinned;

[0008] According to the structure and model of the embedded chip of the SiP device, the sensitive modules of each embedded chip are determined, and each sensitive module is subjected to irradiation test and analysis to obtain the single event effect test items of the SiP device;

[0009] Determine the test plan and design the test equipment accordingly;

[0010] Perform simulation verification on the designed test device by injecting errors. If the simulation verification fails, modify the test program and perform simulation verification again.

[0011] Conduct single-particle tests on each embedded chip;

[0012] Conduct irradiation tests on SiP devices;

[0013] After the test is completed, upload, save, and analyze the test data to end the test.

[0014] Preferably, the embedded chips of the SiP device include: a field programmable gate array FPGA chip, a memory PROM chip, a digital signal processor DSP chip and an analog-to-digital converter ADC chip;

[0015] The test device includes a hardware part and a software part. The hardware part includes a DUT test board and a control board, and the software part includes an upper computer software unit and a lower computer software unit.

[0016] Preferably, the DUT test board should be designed to meet the self-startup power-on operation of the SiP device during single-chip testing, BPI and JTAG program configuration functions, and the design of the communication between the SiP device and the control board SelectMAP interface during dual-chip testing, specifically:

[0017] When designing the power-on circuit, two LTM4644s are selected as DCDC power chips to lead out 8 voltages and currents;

[0018] The JTAG interface and BPI interface are introduced to realize the configuration program loading of the SiP device, and the RS485 interface circuit is introduced to complete the data transmission between the DUT test board and the host computer, thereby meeting the requirements of self-starting test during single chip testing;

[0019] The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board are introduced, and the SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time to meet the needs of dual-chip testing.

[0020] Preferably, the control board uses an FPGA chip to achieve remote control of the DUT test board and data communication with the host computer. During the design:

[0021] The control board leads out at least two general BANKs of the FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board;

[0022] The FPGA chip of the control board needs to be equipped with an external storage chip to store the power-on configuration program and test data of the DUT test board;

[0023] When the control board exchanges data with the host computer, a serial port channel needs to be reserved.

[0024] Preferably, the host computer software unit is a remote control terminal developed based on LabVIEW, and its design needs to meet the following conditions:

[0025] Real-time display of single event upset and single event functional interrupt information of sensitive modules of the device under test;

[0026] Real-time monitoring of the time-varying curves of each SiP working current in the irradiation environment is performed to determine whether single-particle locking occurs, and then all test results are saved in txt format.

[0027] Preferably, the lower computer software unit includes single particle test programs of the FPGA module, the PROM module and the ADC module.

[0028] Preferably, the design method of the FPGA module in the lower computer software unit is:

[0029] Power on the FPGA chip and monitor the working current of the FPGA chip in real time. When the working current exceeds 1.5 times of its working current during irradiation, it is determined that a single-particle lock occurs. At this time, the FPGA chip is powered off and restarted, and the error information is recorded.

[0030] Send control instructions to the FPGA chip through the control board, load the configuration code stream to the FPGA chip, turn on the beam after completion, and conduct irradiation test;

[0031] By real-time monitoring of the level of the corresponding signal of the FPGA chip, it is determined whether a single-particle functional interruption occurs. If the level changes from 0 to 1, a single-particle functional interruption is recorded and the configuration code stream of the FPGA is reloaded. If no single-particle functional interruption occurs, a single-particle upset test is performed;

[0032] The control board reads the program configuration code stream of the FPGA chip in real time through the SelectMAP interface of the FPGA chip, and compares it with the configuration code stream initially written. If they are inconsistent, it is determined that a single particle upset has occurred, and the number of single particle upsets and frame addresses are recorded; finally, all test results are uploaded to the host computer.

[0033] Preferably, the design process of the ADC module and the PROM module in the lower computer software unit is:

[0034] First, the PROM chip and the ADC chip are powered on by a digital power supply, and the operating current of the PROM chip and the ADC chip is monitored in real time during the irradiation process to determine whether single-event locking occurs.

[0035] Then, the configuration code stream is written into the ADC chip and the PROM chip through the FPGA chip to put them in normal working state, and the irradiation test is started;

[0036] Secondly, the configuration code stream written into the ADC chip and the PROM chip is read during the irradiation process and compared with the initial configuration code stream to obtain the single-particle upset results of the PROM chip and the ADC chip, as well as the single-particle transient test data of the ADC chip;

[0037] Finally, all the test data are uploaded to the host computer for storage and display.

[0038] Preferably, when the SiP device is subjected to the irradiation test, if the beam spot cannot completely cover the SiP device, the embedded chips are subjected to the irradiation test one by one.

[0039] Compared with the prior art, the present invention has the following advantages:

[0040] (1) The present invention proposes a general method for single particle effect testing based on SiP devices, and provides a set of single particle effect detection devices for typical microsystem devices, which can simply and effectively implement single particle effect testing of SiP devices, instead of only being able to perform targeted testing on SiP devices of fixed models as in the prior art. The present invention provides technical support for overall single particle testing of other models of SiP devices and independent single particle testing of each built-in chip;

[0041] (2) When developing the DUT test board, the present invention designs two schemes to realize the test code stream loading of the SiP chip, namely, single-chip self-start and dual-chip external control startup. Among them, the single-chip self-start method uses the JTAG interface to directly configure the test code stream, shortening the development cycle of the lower computer test program; the dual-chip control startup uses commercial development as the control board to realize the code stream loading of the SiP to be tested, that is, there is no need to develop a control board, shortening the hardware development time in the dual-chip startup mode and saving costs;

[0042] (3) The present invention uses a remote-controlled digital power supply to measure the multi-channel working current of the SiP chip in real time to prevent the chip from burning out due to SEL. Finally, the current data over time is saved in a txt format to provide assistance for the subsequent analysis of the current change characteristics during SEU and SEFI, thereby improving the test analysis efficiency and having good economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is the overall flow chart of the present invention;

[0044] Figure 2 It is a DUT test board framework diagram of the present invention;

[0045] Figure 3 This is a diagram of the host computer interface of the FPGA chip of the present invention;

[0046] Figure 4 The FPGA chip lower computer program design idea of ​​the present invention;

[0047] Figure 5 It is a schematic diagram of the ADC and PROM chip programming ideas of the present invention;

[0048] Figure 6 It is a schematic diagram of FPGA module simulation injection of the present invention. DETAILED DESCRIPTION

[0049] The present invention realizes the testing of single event lock (SEL), single event functional interrupt (SEFI) and single event upset (SEU) of different chips inside the SiP device, and can provide technical support for the single event effect testing of most models of SiP devices on the market.

[0050] A general method for single event effect testing of SiP devices comprises the following steps:

[0051] (1) Opening or thinning the SiP device;

[0052] (2) Based on the information of the chip packaged inside the SiP device, the single-particle effect sensitive module of the embedded chip to be tested is obtained; usually it mainly includes the built-in FPGA chip of the SiP device (including configuration memory (CRAM), configurable logic block (CLB), block memory (BRAM) and interface circuit module), storage chip (PROM), ADC chip, DSP chip (including operation processing module and interface circuit module).

[0053] (3) Determine the test plan and design the hardware and software; Design the hardware and software according to the single particle effect of the sensitive module to be tested in step (2). The hardware design includes the design of the test device (DUT) test board and the control board, and the software includes the host computer software and the slave computer software. The host computer software is the test monitoring and control software developed based on LabVIEW, and the slave computer software is a single particle test program written in Verilog language for the SiP sensitive module.

[0054] (4) Verify the feasibility of the test system by injecting errors into the DUT through simulation. Before conducting a single-particle test, it is necessary to verify whether the designed test system can meet the test requirements. Therefore, the method of simulated error injection is used for board-level debugging verification.

[0055] (5) Conduct irradiation tests on the entire SiP device and individual chips inside it one by one to verify the feasibility of the test method and evaluate whether the SiP device meets the radiation resistance indicators.

[0056] The specific steps of the present invention are described in detail below with reference to the accompanying drawings.

[0057] like Figure 1 As shown, the present invention provides a general method for testing single-particle effects based on SiP devices, and its main steps are as follows:

[0058] (1) According to the depth information of the SiP sensitive area, the SiP is uncapped or thinned; most SiP devices for aerospace are flip-chip devices, and the sensitive area is about several hundred μm, while the range of domestic heavy ion accelerators in Si is generally less than 100 μm, so the SiP needs to be uncapped and thinned. However, when doing proton and electron experiments, since both have strong penetrating power and the range in Si is generally greater than several hundred μm, it only needs to be uncapped.

[0059] (2) According to the structure and model of the embedded chip of the SiP device, the sensitive modules of each chip are determined, and each module is subjected to radiation test analysis to obtain the single particle effect test items of the SiP device; the embedded chip is usually a combination package of four chips: FPGA, DSP, ADC and PROM. Taking the FPGA chip as an example, its single particle test is mainly for the SEU test of CRAM, BRAM and CLB modules; SEFI test of the power-on startup circuit (POR circuit), communication interface circuit (SelectMAP or JTAG circuit), global control signal (GS signal) and frame address register (FAR); and SEL test of the normal working current of the entire chip in the radiation environment.

[0060] (3) After determining the test items, it is necessary to determine the test plan and design the test software and hardware in a targeted manner. The present invention designs a general software and hardware design method to meet the single particle test requirements of most sensitive modules of SiP devices, and selects a typical SiP device for design verification. The idea is as follows:

[0061] (a) When designing the hardware, select the dual-chip and single-chip power-on startup modes. The hardware design includes the design of the DUT test board and the control board; Figure 2The figure shows the design framework of the DUT test board. The DUT test board serves as a self-starting test board during single-chip testing and as a passively started sub-board during dual-chip testing. Therefore, the test board must meet the self-starting power-on operation of the SiP device during single-chip testing, the BPI and JTAG program configuration functions, and the design of the SelectMAP communication interface between the SiP device and the control board during dual-chip testing. The first is the design of the power-on circuit. The SiP device requires multiple working voltages and currents when working, so two LTM4644s are selected as DCDC power chips to lead out 8 voltages and currents to meet the power-on requirements of most SiP devices; secondly, in order to meet the needs of self-starting test during single-chip testing, the JTAG interface, BPI interface and RS485 interface circuits are introduced. The configuration program of the SiP device can be loaded through the JTAG interface and BPI interface, and the data transmission between the DUT test board and the host computer can be realized with the help of the RS485 interface; finally, in order to meet the dual-chip test, the SiP device and SelectMAP interface circuit are introduced, and the interface is designed as a universal FMC interface. The control board can realize remote control and real-time monitoring of the DUT test board through this interface.

[0062] The SiP device single particle effect test control board needs to use the FPGA chip to realize the remote control of the DUT test board and the data communication with the host computer software. First, since the DUT test board has reserved two BANK FMC data channels, the control board must at least lead out two general BANKs of the FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board; secondly, the FPGA chip of the control board needs to be equipped with an external storage chip to store the power-on configuration program and test data of the DUT test board. Finally, when the control board interacts with the host computer, a serial port channel needs to be reserved. Through the analysis of the control board requirements, the commercial development board Venusstar V2.0 can be selected as the control board to realize dual-chip control, which greatly saves development time.

[0063] (b) The software design is divided into host software and slave software; the host software is a remote control terminal developed based on LabVIEW, which can display the single-particle upset and single-particle functional interruption information of the sensitive module of the device under test in real time, and monitor the time-varying curve of the working current of each channel of SiP in the irradiation environment in real time to determine whether SEL is generated, and then save all test results in txt format. Taking FPGA chip as an example, its host computer interface is as follows Figure 3 shown.

[0064] The lower computer software is a test program developed based on ISE14.7, which includes the design of single-particle test programs for each sensitive module of FPGA, PROM and ADC chip. Specifically:

[0065] Figure 4Design a flow chart for the FPGA chip lower computer program. First, the FPGA chip is powered on through the digital power supply, and the working current of the FPGA chip is monitored in real time. When the working current surges during the irradiation process (exceeding 1.5 times its working current), it is determined that SEL is generated. At this time, the FPGA chip is powered off and restarted, and the error information is recorded; then, the control board sends control instructions to the FPGA chip to load the configuration code stream of the CRAM, BRAM and CLB test program of the FPGA chip. After the program code stream of the FPGA chip is configured, the beam is turned on and the irradiation test is performed; secondly, by real-time monitoring of the GS of the FPGA chip The control board checks the level of the signal, communication interface, and POR signal to determine whether SEFI is generated. If the level changes from 0 to 1, SEFI is recorded once and the FPGA configuration code stream is reloaded. If SEFI is not generated, SEU test is performed. Thirdly, the control board reads the CRAM, BRAM, and CLB program configuration code streams of the FPGA chip in real time through the SelectMAP interface of the FPGA chip, and compares them with the initially written configuration code stream. If they are inconsistent, it is determined that SEU is generated, and the number of SEUs and frame addresses are recorded. Finally, all test results are uploaded to the host computer.

[0066] Figure 5 The program design ideas for ADC chip and PROM chip are as follows. First, the PROM chip and ADC chip are powered on by digital power supply, and the working current of PROM chip and ADC chip is monitored in real time during irradiation to determine whether SEL is generated; then, the configuration code stream is written to ADC and PROM through FPGA chip to make them in normal working state, and start irradiation test; secondly, the configuration code stream written to ADC and PROM is read during irradiation, and compared with the initial code stream, the single particle flip results of PROM and ADC, as well as the single particle transient test data of ADC are obtained; finally, all the test data are uploaded to the host computer for storage and display.

[0067] (4) Before each embedded chip performs a single-particle test, the feasibility of the entire software and hardware is verified by injecting errors into the designed software and hardware. If the simulation test passes, a single-particle test is performed on it. Otherwise, return to step (3) to modify the test program. Taking the FPGA chip as an example, in the FPGA single-particle test, the host computer needs to display the number of single-particle flips, single-particle function interruptions, and real-time changes in the working current of the FPGA chip's sensitive module in real time. Figure 6 It can be seen that the module captures the error information, error address and current changes injected by the BRAM module and DRAM (CLB) module, meeting the design requirements.

[0068] (5) Perform irradiation test on the entire SiP device. Since the SiP device is made up of multiple bare cores and has a certain size, if the beam spot cannot completely cover the SiP device during the irradiation test, the embedded chips are irradiated one by one.

[0069] (6) After the SiP device is irradiated as a whole and tested or the embedded chips are tested individually, upload, save and analyze the test data, and then turn off the beam to end the test.

[0070] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. A general method for single event effect testing of SiP devices. Features include: According to the depth information of the sensitive area of ​​the SiP device, the SiP device is opened or thinned; According to the structure and model of the embedded chip of the SiP device, the sensitive modules of each embedded chip are determined, and each sensitive module is subjected to irradiation test and analysis to obtain the single event effect test items of the SiP device; Determine the test plan and design the test equipment accordingly; Perform simulation verification on the designed test device by injecting errors. If the simulation verification fails, modify the test program and perform simulation verification again. Conduct single-particle tests on each embedded chip; Conduct irradiation tests on SiP devices; After the test is completed, upload, save, and analyze the test data to end the test.

2. A general method for single event effect testing of SiP devices according to claim 1, Features: The embedded chips of SiP devices include: field programmable gate array FPGA chip, memory PROM chip, digital signal processor DSP chip and analog-to-digital converter ADC chip; The test device includes a hardware part and a software part. The hardware part includes a DUT test board and a control board, and the software part includes an upper computer software unit and a lower computer software unit.

3. A general method for single event effect testing of SiP devices according to claim 2, Features: The DUT test board must be designed to meet the self-startup power-on operation of the SiP device during single-chip testing, BPI and JTAG program configuration functions, and the design of the communication between the SiP device and the control board SelectMAP interface during dual-chip testing. Specifically: When designing the power-on circuit, two LTM4644s are selected as DCDC power chips to lead out 8 voltages and currents; The JTAG interface and BPI interface are introduced to realize the configuration program loading of the SiP device, and the RS485 interface circuit is introduced to complete the data transmission between the DUT test board and the host computer, thereby meeting the requirements of self-starting test during single chip testing; The interface between the DUT test board and the SiP device, as well as the SelectMAP interface with the control board are introduced, and the SelectMAP interface with the control board is designed as a universal FMC interface. The control board uses this interface to remotely control and monitor the DUT test board in real time to meet the needs of dual-chip testing.

4. The general method for single event effect testing of SiP devices according to claim 2, Features: The control board uses the FPGA chip to achieve remote control of the DUT test board and data communication with the host computer. During the design: The control board leads out at least two general BANKs of the FPGA chip to establish a data transmission channel with the FMC interface of the DUT test board; The FPGA chip of the control board needs to be equipped with an external storage chip to store the power-on configuration program and test data of the DUT test board; When the control board exchanges data with the host computer, a serial port channel needs to be reserved.

5. The general method for single event effect testing of SiP devices according to claim 2, Features: The host computer software unit is a remote control terminal developed based on LabVIEW, and its design needs to meet the following conditions: Real-time display of single event upset and single event functional interrupt information of sensitive modules of the device under test; Real-time monitoring of the time-varying curves of each SiP working current in the irradiation environment is performed to determine whether single-particle locking occurs, and then all test results are saved in txt format.

6. A general method for single event effect testing of SiP devices according to claim 2, Features: The lower computer software unit includes the single particle test programs of the FPGA module, PROM module and ADC module.

7. A general method for single event effect testing of SiP devices according to claim 6, Features: The design method of the FPGA module in the lower computer software unit is: Power on the FPGA chip and monitor the working current of the FPGA chip in real time. When the working current exceeds 1.5 times of its working current during irradiation, it is determined that a single-particle lock occurs. At this time, the FPGA chip is powered off and restarted, and the error information is recorded. Send control instructions to the FPGA chip through the control board, load the configuration code stream to the FPGA chip, turn on the beam after completion, and conduct irradiation test; By real-time monitoring of the level of the corresponding signal of the FPGA chip, it is determined whether a single-particle functional interruption occurs. If the level changes from 0 to 1, a single-particle functional interruption is recorded and the configuration code stream of the FPGA is reloaded. If no single-particle functional interruption occurs, a single-particle upset test is performed; The control board reads the program configuration code stream of the FPGA chip in real time through the SelectMAP interface of the FPGA chip, and compares it with the configuration code stream initially written. If they are inconsistent, it is determined that a single particle upset has occurred, and the number of single particle upsets and frame addresses are recorded; finally, all test results are uploaded to the host computer.

8. The general method for single event effect testing of SiP devices according to claim 6, Features: The design process of the ADC module and PROM module in the lower computer software unit is as follows: First, the PROM chip and the ADC chip are powered on by a digital power supply, and the operating current of the PROM chip and the ADC chip is monitored in real time during the irradiation process to determine whether single-event locking occurs. Then, the configuration code stream is written into the ADC chip and the PROM chip through the FPGA chip to put them in normal working state, and the irradiation test is started; Secondly, the configuration code stream written into the ADC chip and the PROM chip is read during the irradiation process and compared with the initial configuration code stream to obtain the single-particle upset results of the PROM chip and the ADC chip, as well as the single-particle transient test data of the ADC chip; Finally, all the test data are uploaded to the host computer for storage and display.

9. The general method for single event effect testing of SiP devices according to claim 1, Features: When performing irradiation test on SiP device, if the beam spot cannot completely cover the SiP device, the embedded chips are irradiated one by one.

Images