Display panel, display device and manufacturing method of display panel

Abstract

The invention discloses a display panel, a display device and a manufacturing method of the display panel. The problem that in the prior art, a display panel has scratches and moire patterns is solved. The display panel comprises an array substrate and an opposite substrate which are oppositely arranged, the array substrate comprises a grid line, a data line, a plurality of pixel electrodes, a plurality of transistors and a plurality of first via holes, the display panel comprises a first dark fringe, a second dark fringe which is connected to one end of the first dark fringe and extends along the first direction, and a third dark fringe which is connected to the other end of the first dark fringe and extends along the first direction when being powered up; wherein in the area where the same pixel electrode is located, the second dark fringes are located on the sides, close to the first via holes, of the third dark fringes; at least part of the orthographic projection of the first via hole on the substrate and the orthographic projection of the second dark fringe on the substrate are respectively located on different sides of the orthographic projection of the first dark fringe extension line on the substrate.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel, a display device and a method for manufacturing a display panel. Background Art

[0002] With the development of display technology, flat display devices such as liquid crystal displays (LCD) have been widely used in various consumer electronic products such as mobile phones, televisions, personal digital assistants, digital cameras, laptops, desktop computers, etc. due to their advantages of high image quality, power saving, thin body and wide application range, becoming the mainstream of display devices.

[0003] However, the LCD display of the prior art has a common problem of trace mura, that is, when a customer slides a LCD panel with a finger on a white screen, dark stripes are likely to appear in the swiped area, affecting the customer's user experience. Summary of the invention

[0004] The present invention provides a display panel, a display device and a method for manufacturing the display panel, so as to solve the problem of scratch moiré existing in the display panel of the prior art.

[0005] An embodiment of the present invention provides a display panel, comprising: an array substrate and a counter substrate arranged opposite to each other; the array substrate comprises: a substrate, and a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, a plurality of pixel electrodes, a plurality of transistors, and a plurality of first via holes located on one side of the substrate; the transistor comprises: a first electrode and a second electrode; wherein the first electrode is electrically connected to the data line; and the second electrode is electrically connected to the pixel electrode through the first via hole;

[0006] Wherein, when the display panel is powered on, it includes: a first dark line extending along the second direction and passing through the central area of ​​the pixel electrode, a second dark line connected to one end of the first dark line and extending along the first direction, and a third dark line connected to the other end of the first dark line and extending along the first direction; wherein, in the same area where the pixel electrode is located, the second dark line is located on a side of the third dark line close to the first via hole;

[0007] At least a portion of the orthographic projection of the first via hole on the substrate and the orthographic projection of the second dark pattern on the substrate are located on different sides of the orthographic projection of the first dark pattern extension line on the substrate.

[0008] In a possible implementation, when the display panel is powered on, the display panel further includes: a fourth dark line extending along the first direction and passing through the central area of ​​the pixel electrode, and a fifth dark line connected to one end of the fourth dark line and extending along the second direction; the fifth dark line and the second dark line are located on the same side of the fourth dark line;

[0009] The first via hole is located in at least a portion of the orthographic projection of the substrate, in a region between the first dark line extension line and the fifth dark line extension line on the orthographic projection of the substrate.

[0010] In a possible implementation manner, the data line includes: a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode;

[0011] The pixel electrode, and the first data line and the second data line adjacent to the pixel electrode satisfy: the fifth dark line is located on a side of the first dark line close to the first data line, the pixel electrode is electrically connected to the second data line, and the second dark line is located in a region between the first dark line and the second data line.

[0012] In a possible implementation manner, the data line includes: a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode;

[0013] The pixel electrode, and the first data line and the second data line adjacent to the pixel electrode satisfy: the pixel electrode is electrically connected to the first data line, the fifth dark line is located on a side of the first dark line close to the second data line, and the second dark line is located in an area between the first dark line and the first data line.

[0014] In a possible implementation, the array substrate comprises a first insulating layer between the pixel electrode and the layer where the second electrode is located, and a second insulating layer located on a side of the layer where the second electrode is located facing the substrate; the first via hole is located in the first insulating layer;

[0015] The first via hole partially exposes a portion of the surface of the second electrode facing away from the substrate, and partially exposes a portion of the surface of the second insulating layer facing away from the substrate.

[0016] In a possible implementation manner, in the same region where the pixel electrode is located, the second electrode has a first outer edge away from a side of the fourth dark pattern;

[0017] The orthographic projection of the first via hole on the substrate covers a portion of the orthographic projection of the first outer edge on the substrate.

[0018] In a possible implementation, the pixel electrode includes: a pixel electrode body and a pixel electrode extension portion; wherein the pixel electrode extension portion is located on a side of the pixel electrode body facing the gate line electrically connected through the transistor;

[0019] The pixel electrode extension portion includes: a first extension portion extending along the first direction, and a second extension portion connected to one end of the first extension portion and extending away from the pixel electrode body; the pixel electrode is electrically connected to the second electrode through the second extension portion via the first via hole.

[0020] In a possible implementation manner, a first gap extending along the first direction is provided between the pixel electrode extension portion and the pixel electrode body.

[0021] In a possible implementation manner, the display panel further includes: a first spacer located at a side of the layer where the pixel electrode is located away from the substrate;

[0022] The pixel electrode has a first recessed portion in the area where the first via hole is located; the first spacer is filled in the first recessed portion.

[0023] In a possible implementation manner, in a direction perpendicular to the substrate, a height of the first spacer is equal to a depth of the first recessed portion.

[0024] In a possible implementation manner, the array substrate further includes: a first alignment film layer located on a side of the pixel electrode facing the counter substrate;

[0025] The opposite substrate further includes: a common electrode layer, and a second alignment film layer located on a side of the common electrode layer facing the array substrate.

[0026] An embodiment of the present invention further provides a display device, comprising the display panel provided by the embodiment of the present invention.

[0027] The embodiment of the present invention further provides a method for manufacturing the display panel provided in the embodiment of the present invention, the manufacturing method comprising:

[0028] Forming an array substrate having a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes, a plurality of transistors, and a first alignment film layer, and aligning the array substrate using ultraviolet light;

[0029] Forming an opposite substrate having a common electrode and a second alignment film layer, and aligning the opposite substrate using ultraviolet light;

[0030] The array substrate and the counter substrate are assembled into a box.

[0031] In a possible implementation, the first alignment film layer includes: a plurality of first alignment units corresponding to the pixel electrodes; and the use of ultraviolet light to align the array substrate includes:

[0032] A first mask plate is used to align the first area of ​​the first alignment unit in a first light alignment direction, and a second mask plate is used to align the second area of ​​the first alignment unit in a second light alignment direction, wherein the first area and the second area extend along the second direction and are arranged along the first direction, and in the area where the same pixel electrode is located, the first area is located between the first dark line and the data line, the first light alignment direction is a direction from the third dark line to the second dark line, and the second light alignment direction is a direction from the second dark line to the third dark line.

[0033] In a possible implementation manner, the first alignment film layer includes: a plurality of second alignment units corresponding to the pixel electrodes; and the use of ultraviolet light to align the opposite substrate includes:

[0034] A third mask plate is used to align the third area of ​​the second alignment unit in a third optical alignment direction, and a fourth mask plate is used to align the fourth area of ​​the second alignment unit in a fourth optical alignment direction, wherein the third area and the fourth area extend along the first direction and are arranged along the second direction, and in the area where the same pixel electrode is located, the third area is located on the side of the fourth dark line away from the gate line electrically connected to the pixel electrode, the third optical alignment direction is the direction from the first dark line to the side of the data line electrically connected to the pixel electrode, and the fourth optical alignment direction is opposite to the third optical alignment direction.

[0035] The beneficial effects of the embodiments of the present invention are as follows: In the embodiments of the present invention, at least a portion of the orthographic projection of the first via hole on the substrate and the orthographic projection of the second dark line on the substrate are located on different sides of the orthographic projection of the first dark line on the substrate, that is, at the peripheral position of the first via hole, the second lateral dark line is staggered with the first via hole, so that the second dark line is farther away from the first via hole. On the one hand, the liquid crystal at the position of the first via hole and the liquid crystal in the pixel area can be smoothly transitioned, the difference in the azimuth angle of the liquid crystal in the two areas can be reduced, the orientation stability of the liquid crystal is improved, and thus the disorder of the liquid crystal is reduced; on the other hand, the second dark line is farther away from the first via hole, so that when the liquid crystal at the first via hole is disordered after being pressed, the distance from the first via hole to the pixel area is farther, the morphology of the dark line in the pixel area is less affected, and it is not easy to be disordered, thereby improving Trace Mura. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1Schematic diagram of dark lines affected by liquid crystal at the via hole and dark lines not affected by liquid crystal at the via hole;

[0037] Figure 2 One of the schematic diagrams of the display panel structure provided by an embodiment of the present invention;

[0038] Figure 3 for Figure 2 Schematic diagram of the cross section along the dotted line e1;

[0039] Figure 4 A second schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0040] Figure 5 The third schematic diagram of the structure of the display panel provided by the embodiment of the present invention;

[0041] Figure 6 A fourth schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0042] Figure 7 One of the schematic diagrams of a first via hole provided by an embodiment of the present invention;

[0043] Fig. 8A This is one of the schematic diagrams of UV2A light alignment in the related art;

[0044] Figure 8B This is the second schematic diagram of UV2A light alignment in the related art;

[0045] Fig. 9A It is a corresponding diagram of the UV2A mask plate and the display substrate in the related art;

[0046] Fig. 9B Design of splicing of UV2A mask plates for mass production in related technologies;

[0047] Fig.10 It is a schematic diagram of the mass production UV2A alignment direction and dark patterns in the related technology;

[0048] Fig.11 A schematic diagram of the UV2A alignment direction and dark patterns provided by an embodiment of the present invention;

[0049] Fig.12 A schematic diagram of a display panel manufacturing process provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] As used herein, "approximately" or "substantially the same" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "substantially the same" may mean that the difference relative to the stated value is within one or more standard deviations, or within ±30%, 20%, 10%, 5%.

[0053] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. In this way, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Thus, the embodiments described herein should not be interpreted as being limited to the specific shapes of the regions as shown herein, but include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0054] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of well-known functions and well-known components.

[0055] Most of the liquid crystal display devices on the current market are backlight type liquid crystal displays, which include a liquid crystal display panel and a backlight module. Usually, the liquid crystal display panel is composed of a color filter (CF) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame. However, the liquid crystal display panel of this structure often has the problem of poor alignment between the color filter substrate and the thin film transistor substrate, which in turn causes problems such as pixel light leakage or low aperture ratio. In order to solve this problem, a technology of preparing a color filter layer on an array substrate (Color Filter on Array, COA) has been developed. Because the liquid crystal display panel with a COA structure does not have the problem of alignment between the color filter substrate and the array substrate, it can reduce the difficulty of the box alignment process during the preparation of the display panel and avoid errors during box alignment. Therefore, the black matrix can be designed with a narrow line width, which improves the aperture ratio and is widely used in high-end monitor (MNT) products.

[0056] In the related art, the liquid crystal at the pixel via position is distorted due to the direction of the electric field, which is different from the azimuth angle of the liquid crystal in the pixel area. When the azimuth angle of the liquid crystal at the pixel via is opposite to the azimuth angle of the pixel area, it is easy to affect the normal orientation of the liquid crystal in the pixel area; when pressed, the electric field in the disordered area of ​​the liquid crystal becomes stronger, and the range of the disordered area increases, affecting the normal orientation of the liquid crystal in the pixel area, and dark lines appear disordered, such as Figure 1 As shown on the left side, Figure 1 The figure on the right is a schematic diagram when it is not affected by the liquid crystal at the via hole.

[0057] See also Figure 2 and Figure 3 As shown, Figure 3 Can be Figure 2 A cross-sectional schematic diagram along the dotted line e, an embodiment of the present invention provides a display panel, comprising: an array substrate and a counter substrate arranged opposite to each other; the array substrate comprises: a substrate 1, and a plurality of gate lines 2 extending along a first direction X and a plurality of data lines 3 extending along a second direction Y, a plurality of pixel electrodes 4, a plurality of transistors T, and a plurality of first via holes K1 located on one side of the substrate 1; the transistor T comprises: a first electrode TA and a second electrode TB; wherein the first electrode TA is electrically connected to the data line 3; the second electrode TB is electrically connected to the pixel electrode 4 through the first via hole K1;

[0058] When the display panel is powered on, it includes: a first dark line 51 extending along the second direction Y and passing through the central area of ​​the pixel electrode 4, a second dark line 52 connected to one end of the first dark line 51 and extending along the first direction X, and a third dark line 53 connected to the other end of the first dark line 51 and extending along the first direction X; wherein, in the area where the same pixel electrode 4 is located, the second dark line 52 is located on the side of the third dark line 53 close to the first via hole K1;

[0059] At least a portion of the orthographic projection of the first via K1 on the substrate 1 and the orthographic projection of the second dark line 52 on the substrate 1 are located on different sides of the orthographic projection of the extended line e2 of the first dark line 51 on the substrate 1 .

[0060] In the embodiment of the present invention, at least a portion of the orthographic projection of the first via K1 on the substrate 1 and the orthographic projection of the second dark line 52 on the substrate 1 are located on different sides of the orthographic projection of the extension line of the first dark line 51 on the substrate 1, that is, at the peripheral position of the first via K1, the transverse second dark line 52 is staggered with the first via K1, so that the second dark line 52 is farther from the first via K1. On the one hand, the liquid crystal at the position of the first via K1 and the liquid crystal in the pixel area can be smoothly transitioned, the difference in the azimuth angle of the liquid crystal in the two areas can be reduced, the orientation stability of the liquid crystal is improved, and thus the disorder of the liquid crystal is reduced; on the other hand, the second dark line 52 is farther from the first via K1, so that when the liquid crystal at the first via K1 is disordered after being pressed, the distance from the first via K1 to the pixel area is farther, the morphology of the dark line in the pixel area is less affected, and it is not easy to be disordered, thereby improving Trace Mura.

[0061] In one possible implementation, see Figure 2 As shown, when the display panel is powered on, it also includes: a fourth dark line 54 extending along the first direction X and passing through the central area of ​​the pixel electrode, and a fifth dark line 55 connected to one end of the fourth dark line 54 and extending along the second direction Y; the fifth dark line 55 and the second dark line 52 are located on the same side of the fourth dark line 54; at least part of the positive projection of the first via K1 on the substrate 1 is located in the area between the extension line e2 of the first dark line 51 and the extension line e3 of the fifth dark line 55 on the substrate 1.

[0062] In one possible implementation, see Figure 2As shown, the data line 3 includes: a first data line 31 and a second data line 32 that are adjacent to the pixel electrode 4 and are located on different sides of the pixel electrode 4; the pixel electrode 4, and the first data line 31 and the second data line 32 adjacent to the pixel electrode 4 satisfy that the fifth dark stripe 55 is located on the side of the first dark stripe 51 close to the first data line 31, the pixel electrode 4 is electrically connected to the second data line 32, and the second dark stripe 52 is located in the area between the first dark stripe 51 and the second data line 32. That is, in the embodiment of the present invention, the second dark stripe 52 is located at a position close to the data line 3 (i.e., the second data line 32) electrically connected to the pixel electrode 4 where the second dark stripe 52 is located (electrically connected through the transistor T), so that the horizontal second dark stripe 52 and the first via hole K1 are staggered, the positions of the second dark stripe 52 and the first via hole K1 are far apart, the liquid crystal at the position of the first via hole K1 and the liquid crystal in the pixel area are smoothly transitioned, the liquid crystal disorder is reduced, and the shape of the dark stripe in the pixel area is less affected and not easily disordered, thereby improving Trace Mura.

[0063] It should be noted that for a pixel electrode 4, among the first data line 31 and the second data line 32 adjacent to it, the second data line 32 is electrically connected to the pixel electrode 4; but for another pixel electrode 4 adjacent to the pixel electrode 4, the second data line 32 can also be used as the first data line 31 of another pixel electrode 4. That is, for any data line 3, it is both the first data line 31 and the second data line 32, but for a certain pixel electrode 4, the data line 3 electrically connected to the pixel electrode 4 is fixed. That is, for the pixel electrode 4, the second data line 32 is fixed.

[0064] In a possible implementation manner, refer to Figure 4 As shown, the data line 3 includes: a first data line 31 and a second data line 32 that are adjacent to the pixel electrode 4 and are located on different sides of the pixel electrode 4; the pixel electrode 4, and the first data line 31 and the second data line 32 adjacent to the pixel electrode 4 satisfy that the pixel electrode 4 is electrically connected to the first data line 31, the fifth dark stripe 55 is located on the side of the first dark stripe 51 close to the second data line 32, and the second dark stripe 52 is located in the area between the first dark stripe 51 and the first data line 31. In the embodiment of the present disclosure, by adjusting the mask plate during the optical alignment process of the display panel, the "卐" - shaped dark stripe can be rotated to become a "卍" - shaped dark stripe, or the second dark stripe 52 can be located at a position close to the data line 3 (i.e., the first data line 31) electrically connected to the pixel electrode 4 where the second dark stripe 52 is located (electrically connected through the transistor T), so that the horizontal second dark stripe 52 and the first via hole K1 are staggered, the positions of the second dark stripe 52 and the first via hole K1 are far apart, the liquid crystal at the position of the first via hole K1 and the liquid crystal in the pixel area are smoothly transitioned, the liquid crystal disorder is reduced, and the shape of the dark stripe in the pixel area is less affected and not easily disordered, thereby improving Trace Mura.

[0065] The UV2A photo-alignment technology is a pixel-level scanning exposure technology. Through the light-shielding areas and light-transmitting areas configured on the mask plate, the photo-alignment of the alignment films of the array substrate and the color filter substrate is carried out in the polarization-opposite directions in the corresponding pixel areas respectively. After pairing, a four-domain or multi-domain display effect is achieved. Specifically, as shown in Figure 8A-8B shown, the mask plate is mounted on two stages. One sub-pixel unit corresponds to the light-shielding areas and light-transmitting areas on different stages. The sizes of the light-shielding area 101 and the light-transmitting area 102 configured on the mask plate are both nearly half the size of a sub-pixel. An adjacent light-shielding area + light-transmitting area corresponds to one sub-pixel unit; the photo-alignment polarization direction is horizontal to the pixel scanning direction, and the photo-alignment polarization directions of the two stages are opposite; the photo-alignment methods of the array substrate TFF and the color filter substrate CF are the same, but the photo-alignment directions of the sub-pixels are different. After pairing and bonding, the liquid crystal orientations on the array substrate TFF and the color filter substrate CF sides are different between different domains. The liquid crystal rotates orderly in the cell to form a unique UV2A display mode; the theoretical integrated light amounts of the array substrate TFF and the color filter substrate CF are the same, and the azimuth angles of the liquid crystal in different domains are both 45° with respect to the polarizing axes of the TFT / CF. At this time, the transmittance of the product is the highest.

[0066] Specifically, in the related art of the UV2A photo-alignment technology, due to the limited size of the mask plate, multiple mask plates are required to expose the display substrate in a splicing manner. The mask plate splicing method and the corresponding method of the display substrate are as shown in Fig. 9A and Fig. 9B shown. Among them, the mask plates of the first stage Stage1 and the second stage Stage2 are arranged in an interleaved splicing manner; in the first stage Stage1 and the second stage Stage2, the photo-alignment directions of column A are the same, the photo-alignment directions of column B are the same, and the photo-alignment direction of column B is horizontally opposite to that of column A. The four-domain exposure of the pixels is completed through the Scan method. The mass-production UV2A alignment method in the related art is as shown in Fig.10 shown. The array substrate TFT is left A / right B, and the color filter substrate CF is upper B / lower A. After bonding, the alignment dark line is in the shape of a swastika. At the pixel via, it interferes with the horizontal dark line in the lower right corner. At the pixel via part, due to the existence of complex electric fields such as the hole taper and the metal cushion layer, the alignment dark line is distorted under the action of the electric field; when swiping forcefully, the liquid crystal in the display area is affected by the complex electric field around the pixel via and cannot be restored to the original regular arrangement state in time, resulting in a decrease in the light flux through the pixel and thus showing TraceMura.

[0067] In the embodiments of the present invention, the A / B column exposure positions of the array substrate TFT and the color filter substrate CF can be exchanged, as shown in Fig.11As shown, for the array substrate TFT, it is left B / right A, and for the color filter substrate CF, it is upper A / lower B. After lamination, the dark line is in the shape of "卐". There is no horizontal alignment dark line between the pixel via hole (i.e., the first via hole K1) and the display area. The disordered electric field around the pixel via hole (i.e., the first via hole K1) has no effect on the longitudinal edge dark line and will not affect the liquid crystal arrangement in the display area during sliding, thus improving Trace Mura.

[0068] In a possible implementation manner, referring to Figure 3 As shown, between the pixel electrode 4 and the layer where the second pole TB is located on the array substrate, there is a first insulating layer 91, and a second insulating layer 92 located on the side of the layer where the second pole TB is located facing the substrate 1; the first via hole K1 is located in the first insulating layer 91; a part of the first via hole K1 exposes a part of the surface of the second pole TB facing away from the substrate 1, and a part of the first via hole K1 exposes a part of the surface of the second insulating layer 92 facing away from the substrate 1. In the embodiment of the present invention, a part of the first via hole K1 exposes a part of the surface of the second pole TB facing away from the substrate 1, and a part of the first via hole K1 exposes a part of the surface of the second insulating layer 92 facing away from the substrate 1, that is, the first via hole K1 is set as a semi-lap hole structure, which can also increase the distance between the second dark stripe 52 and the first via hole K1, make the liquid crystal at the position of the first via hole K1 transition smoothly with the liquid crystal in the pixel area, reduce liquid crystal disorder, and make the shape of the dark stripe in the pixel area less affected and not easily disordered, thus improving Trace Mura.

[0069] In a possible implementation manner, in combination with Figure 2 As shown, in the area where the same pixel electrode 4 is located, the second pole TB has a first outer edge w1 far from the fourth dark stripe 54; the orthographic projection of the first via hole K1 on the substrate 1 covers a part of the orthographic projection of the first outer edge w1 on 1. That is, the first via hole K1 is moved upward, and can be partially moved to the area above the second pole TB to make the distance between the first via hole K1 and the second dark stripe 52 larger.

[0070] In a possible implementation manner, referring to Figure 5As shown, the pixel electrode 4 includes: a pixel electrode body 41, and a pixel electrode extension portion 42; wherein the pixel electrode extension portion 42 is located on the side of the pixel electrode body 41 facing the gate line 2 electrically connected through the transistor T; the pixel electrode extension portion 42 includes: a first extension portion 421 extending along the first direction X, and a second extension portion 422 connected to one end of the first extension portion 421 and extending away from the pixel electrode body 41; the pixel electrode 4 is electrically connected to the second electrode TB through the second extension portion 422 via the first via hole K1. In the embodiment of the present invention, the pixel electrode 4 further includes: a first extension portion 421, and a second extension portion 422. The pixel electrode 4 is electrically connected to the second electrode TB via the first via hole K1 through the second extension portion 422, that is, the pixel electrode 4 overlaps with the first via hole K1 by finger connection, thereby isolating the influence of the first via hole K1 on the alignment dark line (dark pattern), thereby achieving a smooth transition between the liquid crystal at the position of the first via hole K1 and the liquid crystal in the pixel area, reducing liquid crystal disorder, and reducing the influence on the morphology of the dark pattern in the pixel area, making it less likely to be disordered, thereby improving Trace Mura.

[0071] In one possible implementation, see Figure 5 As shown, there is a first gap F extending along the first direction X between the pixel electrode extension portion 42 and the pixel electrode body 41. In this way, the influence of the first via hole K1 on the alignment dark line (dark pattern) is isolated, so that the liquid crystal at the position of the first via hole K1 and the liquid crystal in the pixel area are smoothly transitioned, the liquid crystal disorder is reduced, and the morphology of the dark pattern in the pixel area is less affected and less prone to disorder, thereby improving Trace Mura.

[0072] In one possible implementation, see Figure 6 and Figure 7 As shown, the display panel further includes: a first spacer PS1 located on the side of the layer where the pixel electrode 4 is located away from the substrate 1; the pixel electrode 4 has a first recessed portion Q in the area where the first via K1 is located; and the first spacer PS1 is filled in the first recessed portion Q. In the embodiment of the present invention, the display panel further includes: a first spacer PS1 located in the first recessed portion Q in the pixel electrode 4, that is, the first spacer PS1 is used to fill the recess at the position of the first via K1, and after filling, the influence of the first via K1 on the arrangement of liquid crystal molecules can be effectively controlled, the interference of the first via K1 on the arrangement of liquid crystal in the display area can be weakened, and Trace Mura can be improved.

[0073] In a possible implementation manner, the material of the first spacer PS1 may be the same as the material of the main spacer or the sub-spacer in the display panel, and the first spacer PS1 may be formed at the same time as the main spacer or the sub-spacer is formed.

[0074] In one possible implementation, see Figure 6 and Figure 7As shown, in the direction perpendicular to the substrate 1 , the height h1 of the first spacer PS1 is equal to the depth h2 of the first recess Q.

[0075] In one possible implementation, combining Figure 2 or Figure 3 As shown, the transistor T also includes an active pattern 6; the first insulating layer 91 may include a first sub-insulating layer 911, and a second sub-insulating layer 912 located between the first sub-insulating layer 911 and the layer where the second electrode TB is located; wherein the first sub-insulating layer 911 may be an organic insulating layer; the second sub-insulating layer 912 may be a passivation layer; a color resist layer 7 may also be provided between the first sub-insulating layer 911 and the second sub-insulating layer 912; the second insulating layer 92 may specifically be a gate insulating layer; optionally, the layer where the gate line 2 is located may also include a plurality of first wirings 20, the first wiring 20 may be a common wiring, and a storage capacitor may be formed with the second electrode (such as a drain) of the transistor in the layer where the data line is located, and each first wiring 20 may be connected to the gate line 20. They are independent of each other or connected to each other; the layer where the pixel electrode 4 is located may also include multiple second routings 40, and the second routing 40 may include a first sub-routing 401 extending along the first direction X, and a second sub-routing 402 extending along the second direction Y; wherein, the orthographic projection of the second sub-routing 402 on the substrate may overlap with the orthographic projection of the data line 3 on the substrate, and may be used to shield the coupling capacitance between the data line 3 and the pixel electrode 4; the first sub-routing 401 may be used to electrically connect the second sub-routing 402 to each other to form an interconnected structure; the first sub-routing 401 and the second sub-routing 402 may be loaded with a common voltage, and the materials of the two may be the same as the material of the pixel electrode 4, for example, both are indium tin oxide.

[0076] In a possible implementation, the array substrate further includes: a first alignment film layer located on the side of the pixel electrode 4 facing the opposite substrate; the opposite substrate further includes: a common electrode layer, and a second alignment film layer located on the side of the common electrode layer facing the array substrate.

[0077] Based on the same inventive concept, an embodiment of the present invention further provides a display device, including a display panel provided by an embodiment of the present invention. The implementation of the display device can refer to the embodiment of the display panel above, and the repeated parts will not be repeated.

[0078] In specific implementation, in the embodiments of the present disclosure, the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device are well understood by those skilled in the art, and are not described in detail here, nor should they be used as limitations to the present disclosure.

[0079] Based on the same inventive concept, the embodiment of the present invention further provides a method for manufacturing a display panel as provided in the embodiment of the present invention, see Fig.12 As shown, the production method includes:

[0080] Step S100, forming an array substrate having a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes, a plurality of transistors, and a first alignment film layer, and aligning the array substrate using ultraviolet light;

[0081] Step S200, forming an opposite substrate having a common electrode and a second alignment film layer, and aligning the opposite substrate using ultraviolet light;

[0082] Step S300: assembling the array substrate and the counter substrate.

[0083] In a possible implementation, the first alignment film layer includes: a plurality of first alignment units corresponding to the pixel electrodes; Fig.11 As shown, in step S100, the array substrate is aligned using ultraviolet light, including:

[0084] The first mask Mask1 is used to align the first area S1 of the first alignment unit PP1 in the first light alignment direction V1, and the second mask Mask2 is used to align the second area S2 of the first alignment unit PP1 in the second light alignment direction V2, wherein the first area S1 and the second area S2 extend along the second direction Y and are arranged along the first direction X, and in the area where the same pixel electrode is located, the first area S1 is located on the side of the first dark line 51 facing the data line 3 electrically connected to the pixel electrode, the first light alignment direction V1 is the direction from the third dark line 53 to the second dark line 52, and the second light alignment direction V2 is the direction from the second dark line 52 to the third dark line 53. The light-transmitting area of ​​the first mask Mask1 corresponds to the first area S1, and the light-transmitting area of ​​the second mask Mask2 corresponds to the second area S2, that is, the first mask Mask1 transmits light in the first area S1 and shields light in the second area S2; the second mask Mask2 transmits light in the second area S2 and shields light in the first area S1.

[0085] In a possible implementation manner, the second alignment film layer includes: a plurality of first alignment units PP2 corresponding to the pixel electrodes, Fig.11 As shown, in step S200, using ultraviolet light to align the opposite substrate includes:

[0086] The third mask plate Mask3 is used to align the third area S3 of the second alignment unit PP2 in a third light alignment direction V3, and the fourth mask plate Mask4 is used to align the fourth area S4 of the second alignment unit PP2 in a fourth light alignment direction V4, wherein the third area S3 and the fourth area S4 extend along the first direction X and are arranged along the second direction Y, and in the area where the same pixel electrode is located, the third area S3 is located on the side of the fourth dark line 54 away from the gate line 2 electrically connected to the pixel electrode, the third light alignment direction V3 is the direction from the first dark line 51 to the side of the data line 3 electrically connected to the pixel electrode, and the fourth light alignment direction V4 is opposite to the third light alignment direction V3. Among them, the light-transmitting area of ​​the third mask plate Mask3 corresponds to the third area S3, and the light-transmitting area of ​​the fourth mask plate Mask4 corresponds to the fourth area S4, that is, the third mask plate Mask3 transmits light in the third area S3 and blocks light in the fourth area S4; the fourth mask plate Mask4 transmits light in the fourth area S4 and blocks light in the third area S3.

[0087] In a possible implementation, the first mask plate, the second mask plate, the third mask plate and the fourth mask plate may be independent mask plates. In another possible implementation, the first mask plate, the second mask plate, the third mask plate and the fourth mask plate may also be the same mask plate, and only the area not requiring alignment is shielded, so the shielding of the area not requiring alignment is adjusted to achieve alignment in different positions or areas of the array substrate and the color filter substrate.

[0088] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

[0089] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A display panel, characterized in that: include: An array substrate and a counter substrate arranged opposite to each other; The array substrate comprises: a substrate, and a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, a plurality of pixel electrodes, a plurality of transistors, and a plurality of first via holes located on one side of the substrate; the transistor comprises: a first electrode and a second electrode; wherein the first electrode is electrically connected to the data line; and the second electrode is electrically connected to the pixel electrode through the first via hole; Wherein, when the display panel is powered on, it includes: a first dark line extending along the second direction and passing through the central area of ​​the pixel electrode, a second dark line connected to one end of the first dark line and extending along the first direction, and a third dark line connected to the other end of the first dark line and extending along the first direction; wherein, in the same area where the pixel electrode is located, the second dark line is located on a side of the third dark line close to the first via hole; At least a portion of the orthographic projection of the first via hole on the substrate and the orthographic projection of the second dark pattern on the substrate are located on different sides of the orthographic projection of the first dark pattern extension line on the substrate.

2. The display panel according to claim 1, wherein: When the display panel is powered on, the display panel further includes: a fourth dark line extending along the first direction and passing through the central area of ​​the pixel electrode, and a fifth dark line connected to one end of the fourth dark line and extending along the second direction; the fifth dark line and the second dark line are located on the same side of the fourth dark line; The first via hole is located in at least a portion of the orthographic projection of the substrate, in a region between the first dark line extension line and the fifth dark line extension line on the orthographic projection of the substrate.

3. The display panel according to claim 2, wherein: The data line comprises: a first data line and a second data line adjacent to the pixel electrode and located at different sides of the pixel electrode; The pixel electrode, and the first data line and the second data line adjacent to the pixel electrode satisfy: the fifth dark line is located on a side of the first dark line close to the first data line, the pixel electrode is electrically connected to the second data line, and the second dark line is located in a region between the first dark line and the second data line.

4. The display panel according to claim 2, wherein: The data line comprises: a first data line and a second data line adjacent to the pixel electrode and located on different sides of the pixel electrode; The pixel electrode, and the first data line and the second data line adjacent to the pixel electrode satisfy: the pixel electrode is electrically connected to the first data line, the fifth dark line is located on a side of the first dark line close to the second data line, and the second dark line is located in an area between the first dark line and the first data line.

5. The display panel according to claim 2 or 3, characterized in that: The array substrate comprises a first insulating layer between the pixel electrode and the layer where the second electrode is located, and a second insulating layer located on a side of the layer where the second electrode is located facing the substrate; The first via hole is located in the first insulating layer; The first via hole partially exposes a portion of the surface of the second electrode facing away from the substrate, and partially exposes a portion of the surface of the second insulating layer facing away from the substrate.

6. The display panel according to claim 5, wherein: In the region where the same pixel electrode is located, the second electrode has a first outer edge away from a side of the fourth dark pattern; The orthographic projection of the first via hole on the substrate covers a portion of the orthographic projection of the first outer edge on the substrate.

7. The display panel according to claim 1, wherein: The pixel electrode comprises: a pixel electrode body and a pixel electrode extension portion; wherein the pixel electrode extension portion is located on a side of the pixel electrode body facing the gate line electrically connected through the transistor; The pixel electrode extension portion includes: a first extension portion extending along the first direction, and a second extension portion connected to one end of the first extension portion and extending away from the pixel electrode body; the pixel electrode is electrically connected to the second electrode through the second extension portion via the first via hole.

8. The display panel according to claim 7, wherein: A first gap extending along the first direction is defined between the pixel electrode extension portion and the pixel electrode body.

9. The display panel according to claim 1, wherein: The display panel further comprises: a first spacer located at a side of the layer where the pixel electrode is located away from the substrate; The pixel electrode has a first recessed portion in the area where the first via hole is located; the first spacer is filled in the first recessed portion.

10. The display panel according to claim 9, wherein: In a direction perpendicular to the substrate, a height of the first spacer is equal to a depth of the first recessed portion.

11. The display panel according to claim 1, wherein: The array substrate further comprises: a first alignment film layer located on a side of the pixel electrode facing the opposite substrate; The opposite substrate further includes: a common electrode layer, and a second alignment film layer located on a side of the common electrode layer facing the array substrate.

12. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-11.

13. A method for manufacturing a display panel according to any one of claims 1 to 11, characterized in that: The production method comprises: Forming an array substrate having a plurality of gate lines, a plurality of data lines, a plurality of pixel electrodes, a plurality of transistors, and a first alignment film layer, and aligning the array substrate using ultraviolet light; Forming an opposite substrate having a common electrode and a second alignment film layer, and aligning the opposite substrate using ultraviolet light; The array substrate and the counter substrate are assembled into a box.

14. The method according to claim 13, characterized in that: The first alignment film layer includes: a plurality of first alignment units corresponding to the pixel electrodes; the use of ultraviolet light to align the array substrate includes: A first mask plate is used to align the first area of ​​the first alignment unit in a first light alignment direction, and a second mask plate is used to align the second area of ​​the first alignment unit in a second light alignment direction, wherein the first area and the second area extend along the second direction and are arranged along the first direction, and in the area where the same pixel electrode is located, the first area is located between the first dark line and the data line, the first light alignment direction is a direction from the third dark line to the second dark line, and the second light alignment direction is a direction from the second dark line to the third dark line.

15. The manufacturing method according to claim 14, characterized in that: The first alignment film layer includes: a plurality of second alignment units corresponding to the pixel electrodes; the use of ultraviolet light to align the opposite substrate includes: A third mask plate is used to align the third area of ​​the second alignment unit in a third optical alignment direction, and a fourth mask plate is used to align the fourth area of ​​the second alignment unit in a fourth optical alignment direction, wherein the third area and the fourth area extend along the first direction and are arranged along the second direction, and in the area where the same pixel electrode is located, the third area is located on the side of the fourth dark line away from the gate line electrically connected to the pixel electrode, the third optical alignment direction is the direction from the first dark line to the side of the data line electrically connected to the pixel electrode, and the fourth optical alignment direction is opposite to the third optical alignment direction.

Images