B code time synchronization precision compensation method and device for nuclear power station

Abstract

The embodiment of the invention discloses a B code time synchronization precision compensation method, device and equipment for a nuclear power station, a product and a storage medium. The method, device and equipment are applied to time synchronization equipment comprising a time synchronization device, a B code time synchronization module, a display screen and a single-board digital signal processor (DSP). The single-board DSP is provided with an external interrupt IO port. The B code time synchronization module is respectively connected with the time synchronization device and the display screen; the display screen is connected with the single-board DSP; the single-board DSP is connected with the time synchronization device through the external interruption IO port; comprising the following steps: determining a first time error from synchronization time sent by the time synchronization device to the display screen; determining a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP; determining a third time error of the time synchronization device based on the first time error and the second time error; and compensating the time set in the time synchronization equipment by using the third time error.

Description

Technical Field

[0001] The present application relates to the field of signal transmission technology, and in particular to a B-code timing accuracy compensation method, device, equipment, product and storage medium for a nuclear power plant. Background Art

[0002] For nuclear power plant projects, the equipment is equipped with B-code timing modules, which can be used to set the time of the single board. However, due to the increase in transmission media, the time setting has a large delay in the data transmission process, resulting in a large time error in the single board setting. Summary of the invention

[0003] In view of this, the embodiments of the present application hope to provide a B-code timing accuracy compensation method, device, equipment, product and storage medium for a nuclear power plant.

[0004] The technical embodiment of the embodiment of the present application is implemented as follows:

[0005] The embodiment of the present application provides a B-code timing accuracy compensation method for a nuclear power plant, which is applied to a time synchronization device including a time synchronization device, a B-code timing module, a display screen, and a single-board digital signal processor (DSP); the single-board DSP is provided with an external interrupt IO port; the B-code timing module is connected to the time synchronization device and the display screen respectively; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt IO port; the method comprises:

[0006] Determine a first time error between the synchronization time sent by the time synchronization device and the display screen;

[0007] Determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP;

[0008] determining a third time error of the time synchronization device based on the first time error and the second time error;

[0009] The third time error is used to compensate the time set in the time synchronization device.

[0010] In the above solution, the step of determining a first time error between the synchronization time sent by the time synchronization device and the display screen includes:

[0011] Obtain the first time when the single-board DSP records the synchronization time sent by the time synchronization device to cause the external interrupt IO port to act, and the second time when the display screen receives the synchronization time;

[0012] The first time error is determined based on the first time and the second time.

[0013] In the above solution, determining the first time error based on the first time and the second time includes:

[0014] determining a first difference between the second time and the first time;

[0015] The first difference is used as the first time error.

[0016] In the above scheme, the determining of the second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP includes:

[0017] Recording a third time when the display screen sends the time setting information;

[0018] Recording a fourth time when the single-board DSP receives the time setting information;

[0019] Recording a fifth time when the single-board DSP completes time setting based on the time setting information;

[0020] Recording the sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting;

[0021] The second time error is determined based on the third time, the fourth time, the fifth time, and the sixth time.

[0022] In the above solution, the determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time includes:

[0023] determining a second difference between the sixth time and the third time;

[0024] determining a third difference between the fifth time and the fourth time;

[0025] The second time error is determined based on the second difference and the third difference.

[0026] In the above solution, determining the second time error based on the second difference and the third difference includes:

[0027] Subtract the second difference from the third difference to obtain a fourth difference;

[0028] The fourth difference is used as the second time error.

[0029] In the above solution, when the transmission route between the display screen and the single-board DSP is symmetrical, the method further includes:

[0030] Determine the delay time between the display screen and the single-board DSP based on the second time error;

[0031] The delay time is used to compensate for the setup time of the single-board DSP.

[0032] In the above solution, when the transmission route between the display screen and the single-board DSP is asymmetric, the method further includes:

[0033] Re-determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP;

[0034] calculating an average value of the second time error and the re-determined second time error;

[0035] The average value is used to compensate for the setup time of the single-board DSP.

[0036] In the above solution, determining the third time error of the time synchronization device based on the first time error and the second time error includes:

[0037] The first time error and the second time error are summed to obtain the third time error.

[0038] The embodiment of the present application provides a B-code timing accuracy compensation device for a nuclear power plant, which is arranged in a time synchronization device including a time synchronization device, a B-code timing module, a display screen, and a single-board digital signal processor DSP; the single-board DSP is provided with an external interrupt IO port; the B-code timing module is connected to the time synchronization device and the display screen respectively; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt IO port; the device comprises:

[0039] A first determining unit, configured to determine a first time error between the synchronization time sent by the time synchronization device and the display screen;

[0040] A second determining unit, used to determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP;

[0041] a third determining unit, configured to determine a third time error of the time synchronization device based on the first time error and the second time error;

[0042] A compensation unit is used to compensate the time set in the time synchronization device by using the third time error.

[0043] The embodiment of the present application provides a B code timing accuracy compensation device for a nuclear power plant, comprising:

[0044] A memory for storing executable instructions;

[0045] The processor is used to implement any step of the above-mentioned method when executing the executable instructions stored in the memory.

[0046] An embodiment of the present application provides a computer program product, including a computer program, which implements any step of the above-mentioned method when executed by a processor.

[0047] An embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, any step of the method described above is implemented.

[0048] The embodiment of the present application provides a B-code timing accuracy compensation method, device, equipment, product and storage medium for a nuclear power plant, which is applied to a time synchronization device including a time synchronization device, a B-code timing module, a display screen, and a single-board digital signal processor DSP; the single-board DSP is provided with an external interrupt IO port; the B-code timing module is connected to the time synchronization device and the display screen respectively; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt IO port; the method includes: determining a first time error from the synchronization time sent by the time synchronization device to the display screen; determining a second time error from the time setting information sent by the display screen to the single-board DSP to complete the time setting; determining a third time error of the time synchronization device based on the first time error and the second time error; and using the third time error to compensate for the time set in the time synchronization device. The technical solution of the embodiment of the present application is adopted, by determining the time error from the synchronization time sent by the time synchronization device to the display screen and the time error from the time setting information sent by the display screen to the single-board DSP to complete the time setting, and then adding them to obtain a total time error, and then using the total time error to compensate for the set time, eliminating the time error caused by communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a schematic diagram of a flow chart of a method for implementing B-code timing accuracy compensation for a nuclear power plant according to an embodiment of the present application;

[0050] Figure 2 This is a schematic diagram of a time synchronization device in an embodiment of the present application;

[0051] Figure 3 A schematic diagram of information transmission in the time synchronization device of the present application;

[0052] Figure 4 A schematic diagram of calculating the transmission error of time information between the display screen and the DSP in an embodiment of the present application;

[0053] Figure 5 A schematic diagram of an application scenario of the error in the transmission of time information from a time synchronization device to a display screen in an embodiment of the present application;

[0054] Figure 6 A schematic diagram of a flow chart for calculating the error in the transmission of time information from a time synchronization device to a display screen in an embodiment of the present application;

[0055] Figure 7 A schematic diagram of delay error elimination of a time synchronization device in an embodiment of the present application;

[0056] Figure 8 This is a structural schematic diagram of a B-code timing accuracy compensation device for a nuclear power plant according to an embodiment of the present application;

[0057] Fig. 9 This is a schematic diagram of the structure of a B-code timing accuracy compensation device for a nuclear power plant according to an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the specific technical solution of the invention will be further described in detail below in conjunction with the drawings in the embodiments of the present application. The following embodiments are used to illustrate the present application, but are not used to limit the scope of the present application.

[0059] For nuclear power plant projects, the equipment is equipped with B-code timing modules, which can be used to set the time of the single board. However, due to the increase in transmission media, the time setting has a large delay in the data transmission process, resulting in a large time error in the single board setting.

[0060] Based on this, this embodiment proposes a B-code timing accuracy compensation method for nuclear power plants. The method can be applied to B-code timing accuracy compensation equipment for nuclear power plants. The functions implemented by the method can be implemented by calling program codes by the processor in the B-code timing accuracy compensation equipment for nuclear power plants. Of course, the program codes can be stored in the memory of the processing device. It can be seen that the processing device at least includes a processor and a memory.

[0061] Figure 1The present invention is a flowchart of a method for compensating the B-code timing accuracy for a nuclear power plant according to an embodiment of the present invention. The present invention provides a method for compensating the B-code timing accuracy for a nuclear power plant, which is applied to a time synchronization device including a time synchronization device, a B-code timing module, a display screen, and a single-board digital signal processor DSP; the single-board DSP is provided with an external interrupt IO port; the B-code timing module is respectively connected to the time synchronization device and the display screen; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt IO port; Figure 1 As shown, the method includes:

[0062] Step S101: determining a first time error between the synchronization time sent by the time synchronization device and the display screen.

[0063] Step S102: Determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP.

[0064] Step S103: Determine a third time error of the time synchronization device based on the first time error and the second time error.

[0065] Step S104: using the third time error to compensate for the time set in the time synchronization device.

[0066] It should be noted that the compensation for the delay error based on the B-code timing signal used in the nuclear power plant can be understood as compensating for the delay error caused by the transmission of the B-code timing signal.

[0067] The time synchronization device can be determined according to actual conditions and is not limited here. As an example, the time synchronization device can include a time synchronization instrument.

[0068] The B code timing module may be determined according to actual conditions and is not limited here. As an example, the B code timing module may include a B code decoding module and the like.

[0069] The time synchronization device can be determined according to the actual situation, and is not limited here. For the sake of convenience, it can be combined with Figure 2 To understand, Figure 2 Schematic diagram of a time synchronization device in an embodiment of the present application.

[0070] The display screen is connected to the single-board DSP, and the connection can be determined according to actual conditions and is not limited here. As an example, the connection can be a wired connection or a wireless connection; wherein the wired connection can be a wire connection capable of transmitting data; the wireless connection can be a short-range communication technology, such as Bluetooth, Zigbee, etc.; or a long-range communication technology, such as (WiFi, Wireless Fidelity) connection.

[0071] The single-board DSP is connected to the time synchronization device via the external interrupt IO port, which can be understood as an IO port being provided on the single-board DSP, and the time synchronization device being connected to the IO port.

[0072] In step S101, the specific determination process of determining the first time error from the synchronization time sent by the time synchronization device to the display screen can be determined according to actual conditions and is not limited here. As an example, determining the first time error from the synchronization time sent by the time synchronization device to the display screen may include obtaining the first time when the single-board DSP records the synchronization time sent by the time synchronization device to cause the external interrupt IO port to act and recording the second time when the display screen receives the synchronization time; determining the first time error based on the first time and the second time. Among them, the first time error can be determined according to actual conditions and is not limited here. As an example, the first time error can be recorded as Tdly1.

[0073] In step S102, the specific determination process of determining the second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP can be determined according to actual conditions, and is not limited here. As an example, the determination of the second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP can include recording the third time when the display screen sends the time setting information; recording the fourth time when the single-board DSP receives the time setting information; recording the fifth time when the single-board DSP completes the time setting based on the time setting information; recording the sixth time when the display screen receives the flag information sent by the single-board DSP to complete the time setting; and determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time. Among them, the second time error can be determined according to actual conditions, and is not limited here. As an example, the second time error can be recorded as Tdly2.

[0074] In step S103, the specific determination process of determining the third time error of the time synchronization device based on the first time error and the second time error can be determined according to actual conditions, and is not limited here. As an example, determining the third time error of the time synchronization device based on the first time error and the second time error can include summing the first time error and the second time error to obtain the third time error. The third time error can be determined according to actual conditions, and is not limited here. As an example, the third time error can be recorded as Tdly.

[0075] In step S104, the specific process of using the third time error to compensate for the time set in the time synchronization device can be determined according to actual conditions and is not limited here. As an example, using the third time error to compensate for the time set in the time synchronization device can be understood as calibrating the time set in the time synchronization device using the third time error and the set time. Among them, the set time can be determined according to actual conditions and is not limited here. As an example, the set time can be recorded as Tset.

[0076] In this embodiment, the time error from the synchronization time sent by the time synchronization device to the display screen and the time error from the time setting information sent by the display screen to the single-board DSP to complete the time setting are determined, and then the total time error is added to obtain the total time error, and the set time is compensated using the total time error to eliminate the time error caused by communication.

[0077] In an optional embodiment of the present application, determining a first time error between the synchronization time sent by the time synchronization device and the display screen includes:

[0078] Obtain the first time when the single-board DSP records the synchronization time sent by the time synchronization device to cause the external interrupt IO port to act, and the second time when the display screen receives the synchronization time;

[0079] The first time error is determined based on the first time and the second time.

[0080] In this embodiment, both the first time and the second time can be determined according to actual conditions and are not limited here. As an example, the first time can be recorded as T1'; the second time can be recorded as T2'.

[0081] The specific determination process of determining the first time error based on the first time and the second time can be determined according to actual conditions and is not limited here. As an example, determining the first time error based on the first time and the second time may include determining a first difference between the second time and the first time; and using the first difference as the first time error.

[0082] In an optional embodiment of the present application, determining the first time error based on the first time and the second time includes:

[0083] determining a first difference between the second time and the first time;

[0084] The first difference is used as the first time error.

[0085] In this embodiment, as an example, the first time may be recorded as T1'; the first time may be recorded as T2'. Determining the first difference between the second time and the first time may be understood as determining T2'-T1' as the first difference.

[0086] As an example, the first time error may be recorded as Tdly1. Taking the first difference as the first time error may be understood as Tdly1=T2'-T1'.

[0087] In practical applications, the information transmission from the time synchronization device to the display screen is one-way transmission, and the transmission error cannot be corrected by the two-way timestamp method, but the one-way timestamp recording method can be used to calculate the delay time. The external interrupt function is used to sample the time sent by the synchronization device. The display screen records the time when the time information is received, and the delay time of the data transmission in the process can be calculated through this time difference. Specifically, it includes: the time synchronization device sends the synchronization time, the display screen receives the synchronization time and records T2', and at the same time the external interrupt IO port is activated, the DSP records the interrupt departure time T1' and the time T2' sent by the display screen is received, and the delay time Tdly1=T2'-T1' is calculated.

[0088] In an optional embodiment of the present application, determining a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP includes:

[0089] Recording a third time when the display screen sends the time setting information;

[0090] Recording a fourth time when the single-board DSP receives the time setting information;

[0091] Recording a fifth time when the single-board DSP completes time setting based on the time setting information;

[0092] Recording the sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting;

[0093] The second time error is determined based on the third time, the fourth time, the fifth time, and the sixth time.

[0094] In this embodiment, the third time, the fourth time, the fifth time, and the sixth time can be determined according to actual conditions and are not limited here. As an example, the third time can be recorded as T1; the fourth time can be recorded as T2; the fifth time can be recorded as T3; and the sixth time can be recorded as T4.

[0095] The specific determination process of determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time can be determined according to actual conditions and is not limited here. As an example, determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time may include determining the second difference between the sixth time and the third time; determining the third difference between the fifth time and the fourth time; and determining the second time error based on the second difference and the third difference.

[0096] In an optional embodiment of the present application, determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time includes:

[0097] determining a second difference between the sixth time and the third time;

[0098] determining a third difference between the fifth time and the fourth time;

[0099] The second time error is determined based on the second difference and the third difference.

[0100] In this embodiment, as an example, the third time can be recorded as T1; the sixth time can be recorded as T4; and the determination of the second difference between the sixth time and the third time can be understood as determining T4-T1 as the second difference.

[0101] As an example, the fourth time may be recorded as T2; the fifth time may be recorded as T3; and determining the third difference between the fifth time and the fourth time may be understood as determining T3-T2 as the third difference.

[0102] The specific determination process of determining the second time error based on the second difference and the third difference can be determined according to actual conditions and is not limited here. As an example, determining the second time error based on the second difference and the third difference may include subtracting the second difference from the third difference to obtain a fourth difference; and using the fourth difference as the second time error.

[0103] In an optional embodiment of the present application, determining the second time error based on the second difference and the third difference includes:

[0104] Subtract the second difference from the third difference to obtain a fourth difference;

[0105] The fourth difference is used as the second time error.

[0106] In this embodiment, the fourth difference obtained by subtracting the second difference from the third difference can be understood as the fourth difference being equal to (T4-T1)-(T3-T2).

[0107] As an example, the second time error is recorded as Tdly2, and the fourth difference is taken as the second time error, which can be understood as Tdly2=(T4-T1)-(T3-T2).

[0108] In actual applications, for data transmission between the display screen and the single board, this section is bidirectional. Due to the time delay in data transmission and data processing, there is an error between the set time and the actual time. In order to minimize or compensate for this error, the time points generated in each step of the setting process can be recorded and the delay time can be calculated for compensation. Specifically, it can include: the display screen records the current timestamp T1 while sending the time setting instruction; after the single board receives the instruction, it records the current timestamp T2; after the single board sets the time, it records the current timestamp T3; after the display screen receives the single board time setting completion mark, it records the current timestamp T4; the delay time can be calculated: Tdly2 = (T4-T1)-(T3-T2); for ease of understanding, here is an example, assuming that T1 can be 2 o'clock; T2 can be one second after 2 o'clock; T3 can be two seconds after 2 o'clock; T4 can be three seconds after 2 o'clock; send once every 1s, and set once every minute.

[0109] In an optional embodiment of the present application, when the transmission route between the display screen and the single-board DSP is symmetrical, the method further includes:

[0110] Determine the delay time between the display screen and the single-board DSP based on the second time error;

[0111] The delay time is used to compensate for the setup time of the single-board DSP.

[0112] In this embodiment, when the transmission route between the display screen and the single-board DSP is symmetrical, it can be understood that since the transmission lines are the same, the delay times are also symmetrical and substantially the same.

[0113] The specific determination process of determining the delay time between the display screen and the single-board DSP based on the second time error can be determined according to the actual situation and is not limited here. As an example, the second time error is recorded as Tdly2, and the delay time can be recorded as Td; the delay time between the display screen and the single-board DSP determined based on the second time error can be understood as Tb = Tdly2 / 2. If Tdly2 = (T4-T1)-(T3-T2), then Tb = [(T4-T1)-(T3-T2)] / 2.

[0114] Using the delay time and the setup time to compensate for the setup time of the single-board DSP can be understood as using the delay time and the setup time to calibrate the setup time of the single-board DSP; wherein the setup time can be determined according to actual conditions and is not limited here. As an example, the setup time can be recorded as Tset. Using the delay time and the setup time to calibrate the setup time of the single-board DSP can be understood as the time after calibration is T=Tb+Tset.

[0115] In practical applications, since the transmission lines are the same, the delay time symmetry is also basically the same, so the required compensation delay time Tb=Tdly / 2; the time after calibration is T=Tb+Tset.

[0116] In an optional embodiment of the present application, when the transmission route between the display screen and the single-board DSP is asymmetric, the method further includes:

[0117] Re-determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP;

[0118] calculating an average value of the second time error and the re-determined second time error;

[0119] The average value is used to compensate for the setup time of the single-board DSP.

[0120] In this embodiment, the asymmetry of the transmission route between the display screen and the single-board DSP is mainly considered. When the asymmetry of the transmission route needs to be considered, that is, the delays of sending and receiving are different, the error can be reduced by multiple measurements and averaging.

[0121] The re-determination of the second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP can be understood as measuring the second time error multiple times.

[0122] The specific compensation process of compensating the setup time of the single-board DSP using the average value can be determined according to actual conditions and is not limited here. As an example, compensating the setup time of the single-board DSP using the average value may include compensating the setup time of the single-board DSP after weighted processing using the average value.

[0123] In practice, when it is necessary to consider asymmetric transmission paths, i.e. different delays in sending and receiving, the error can be reduced by taking multiple measurements and averaging them. Compensation can include multiple measurements: taking multiple measurements and calculating the average to reduce the error. And adjusting the model: if it is known that the delay in one direction is longer, the delay in that direction can be weighted in the calculation.

[0124] In an optional embodiment of the present application, determining a third time error of the time synchronization device based on the first time error and the second time error includes:

[0125] The first time error and the second time error are summed to obtain the third time error.

[0126] In this embodiment, as an example, the first time error can be recorded as Tdly1; the second time error can be recorded as Tdly2; the third time error can be recorded as Tdly, and the first time error and the second time error are summed to obtain the third time error, which can be understood as Tdly=Tdly1+Tdly2.

[0127] In practical applications, the delay error elimination of the entire system is mainly divided into the error elimination from the synchronization device to the display screen and the error elimination from the display screen to the DSP. The sorting method is to use the scheme of recording timestamps, but due to transmission differences, it is necessary to sample the one-way timestamp separately to calculate the error Tdly1, and the two-way timestamp to calculate Tdly2. The calculated time difference is used to compensate the set time to eliminate the time error caused by communication. Specifically, it includes calculating the time error Tdly1 from the synchronization device to the display screen; calculating the time error Tdly2 from the display screen to the DSP; calculating the total time error Tdly = Tdly1 + Tdly2; and setting the time compensation T = Tdly + Tset.

[0128] In order to facilitate the understanding of the present application, the B-code timing accuracy compensation method used in nuclear power plants is exemplified here as a method for compensating for the delay error caused by the transmission of the B-code timing signal, and is applied to a time synchronization device including a time synchronization device, a B-code timing module, a display screen, and a single-board digital signal processor DSP. Assume that the time synchronization device is specifically a time synchronization instrument, and the B-code timing module is specifically a B-code decoding module. The time synchronization instrument sends the synchronization time to the B-code decoding module; the B-code decoding module decodes the time and sends it to the display screen; the display screen sends a time setting frame to the single-board DSP; the single-board DSP feeds back to the display screen whether the time setting is completed. This content can be combined with Figure 3 To understand, Figure 3 This is a schematic diagram of information transmission in the time synchronization device of this application.

[0129] The specific implementation steps are as follows:

[0130] First, calculate the transmission error of time information between the display screen and DSP.

[0131] The data transmission between the display screen and the single board is bidirectional. Due to the time delay in data transmission and data processing, there is an error between the set time and the actual time. In order to minimize or compensate for this error, the time points of each step in the setting process can be recorded and the delay time can be calculated for compensation.

[0132] step:

[0133] 1. When the display screen sends the time setting instruction, it records the current timestamp T1;

[0134] 2. After receiving the command, the board records the current timestamp T2;

[0135] 3. After the board sets the time, it records the current timestamp T3;

[0136] 4. After receiving the board time setting completion mark, the display screen records the current timestamp T4;

[0137] 5. The delay time can be calculated: Tdly = (T4-T1)-(T3-T2);

[0138] 6. Since the transmission lines are the same, the delay time symmetry is also basically the same, so the required compensation delay time Tb = Tdly / 2;

[0139] 7. The time after calibration is T=Tb+Tset.

[0140] For ease of understanding, here you can combine Figure 4 To understand, Figure 4 Schematic diagram of calculating the transmission error of time information between the display screen and the DSP in an embodiment of the present application.

[0141] When it is necessary to consider the asymmetry of the transmission path, that is, the delays of sending and receiving are different, the error can be reduced by multiple measurements and averaging.

[0142] Compensation methods may include:

[0143] 1. Multiple measurements: Take multiple measurements and calculate the average to reduce errors. Adjust the model;

[0144] 2. If it is known that the delay in a certain direction is longer, the delay in that direction can be weighted in the calculation.

[0145] Second, calculate the error in the transmission of time information from the time synchronization device to the display screen.

[0146] The information transmission from the time synchronization device to the display screen is one-way transmission, so the transmission error cannot be calculated using the two-way timestamp method. However, the one-way timestamp recording method can be used to calculate the delay time. The external interrupt function is used to sample the time sent by the synchronization device. The display screen records the time when the time information is received, and the delay time of the data transmission in the process can be calculated through this time difference.

[0147] For ease of understanding, here you can combine Figure 5 , Figure 6 To understand, Figure 5 A schematic diagram of an application scenario of the error in the transmission of time information from a time synchronization device to a display screen in an embodiment of the present application; Figure 6 It is a schematic diagram of a flow chart for calculating the error of time information transmission from a time synchronization device to a display screen in an embodiment of the present application.

[0148] Third, the delay error elimination of the entire system is mainly divided into the error elimination from the synchronization device to the display screen and the error elimination from the display screen to the DSP. The sorting method is to use the solution of recording timestamps, but due to transmission differences, it is necessary to sample the one-way timestamp separately to calculate the error Tdly1, and the two-way timestamp to calculate Tdly2. The calculated time difference is used to compensate the set time to eliminate the time error caused by communication.

[0149] For ease of understanding, here you can combine Figure 7 To understand, Figure 7 A schematic diagram of delay error elimination of a time synchronization device in an embodiment of the present application.

[0150] In this embodiment, the visual early warning system based on fault recording can detect potential faults in advance and present them visually, allowing operation and maintenance personnel to intuitively understand the health status and potential risks of the system and quickly take corresponding measures, which can effectively reduce the time and economic losses caused by faults. In addition, when a certain fault occurs multiple times, this system will actively allocate resources for uninterrupted query. When the conditions in the fault early warning model are triggered, a corresponding alarm will be generated for the entire system, so that the staff can perceive the arrival of the alarm in advance and make corresponding prevention strategies.

[0151] The embodiment of the present application also provides a B-code timing accuracy compensation device for a nuclear power plant, which is arranged in a time synchronization device including a time synchronization device, a B-code timing module, a display screen, and a single-board digital signal processor DSP; the single-board DSP is provided with an external interrupt IO port; the B-code timing module is respectively connected to the time synchronization device and the display screen; the display screen is connected to the single-board DSP; the single-board DSP is connected to the time synchronization device through the external interrupt IO port; Figure 8 As shown, Figure 8 This is a schematic diagram of the structure of a B-code timing accuracy compensation device for a nuclear power plant according to an embodiment of the present application. The device 800 includes:

[0152] A first determining unit 801 is used to determine a first time error between the synchronization time sent by the time synchronization device and the display screen;

[0153] The second determining unit 802 is used to determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP;

[0154] A third determining unit 803 is configured to determine a third time error of the time synchronization device based on the first time error and the second time error;

[0155] The compensation unit 804 is configured to compensate the time set in the time synchronization device by using the third time error.

[0156] In one embodiment, the first determination unit 801 is further used to obtain the first time when the single-board DSP records the synchronization time sent by the time synchronization device to cause the external interrupt IO port to act and to record the second time when the display screen receives the synchronization time; and determine the first time error based on the first time and the second time.

[0157] In one embodiment, the first determining unit 801 is further configured to determine a first difference between the second time and the first time; and use the first difference as the first time error.

[0158] In one embodiment, the second determination unit 802 is further used to record a third time when the display screen sends the time setting information; record a fourth time when the single-board DSP receives the time setting information; record a fifth time when the single-board DSP completes the time setting based on the time setting information; record a sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting; and determine the second time error based on the third time, the fourth time, the fifth time, and the sixth time.

[0159] In one embodiment, the second determination unit 802 is further used to determine a second difference between the sixth time and the third time; determine a third difference between the fifth time and the fourth time; and determine the second time error based on the second difference and the third difference.

[0160] In one embodiment, the second determining unit 802 is further configured to subtract the second difference from the third difference to obtain a fourth difference; and use the fourth difference as the second time error.

[0161] In one embodiment, when the transmission route between the display screen and the single-board DSP is symmetrical, the third determining unit 803 is further used to determine the delay time between the display screen and the single-board DSP based on the second time error;

[0162] The compensation unit 804 is further configured to use the delay time to compensate for the setup time of the single-board DSP.

[0163] In one embodiment, when the transmission route between the display screen and the single-board DSP is asymmetric, the second determining unit 802 is further used to re-determine a second time error from the time setting information sent by the display screen to the single-board DSP completing the time setting;

[0164] The compensation unit 804 is further configured to use the average value to compensate for the setup time of the single-board DSP.

[0165] In one embodiment, the third determining unit 803 is further configured to sum the first time error and the second time error to obtain the third time error.

[0166] It should be noted that in the embodiment of the present application, if the B-code timing accuracy compensation method for a nuclear power plant is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical embodiment of the embodiment of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a B-code timing accuracy compensation system for a nuclear power plant (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a disk or an optical disk. In this way, the embodiment of the present application is not limited to any specific combination of hardware and software.

[0167] Based on the hardware implementation of the above-mentioned program module, an embodiment of the present application also provides a B-code timing accuracy compensation device for a nuclear power plant, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and when the processor executes the program, the steps in the B-code timing accuracy compensation method for a nuclear power plant provided in the above-mentioned embodiment are implemented.

[0168] Correspondingly, an embodiment of the present application provides a computer program product, which, when executed by a processor, implements the steps in the B-code timing accuracy compensation method for a nuclear power plant provided in the above embodiment.

[0169] Correspondingly, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the B-code timing accuracy compensation method for a nuclear power plant provided in the above embodiment are implemented.

[0170] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0171] Based on the hardware implementation of the above-mentioned program module, an embodiment of the present application also provides a B-code timing accuracy compensation device for a nuclear power plant, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned method when executing the program;

[0172] Correspondingly, an embodiment of the present application provides a computer program product, including a computer program, on which a computer program is stored, and the computer program implements the steps of the above-mentioned method when being executed by a processor.

[0173] Correspondingly, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned method are implemented.

[0174] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0175] It should be noted that Fig. 9 This is a schematic diagram of the structure of the B-code timing accuracy compensation device for a nuclear power plant according to an embodiment of the present application. Fig. 9 As shown, the device 900 includes: a processor 901 and a memory 903 . Optionally, the device 900 may also include a communication interface 902 .

[0176] It can be understood that the memory 903 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disk, or a compact disk read-only memory (CD-ROM); the magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM, SyncLink Dynamic Random Access Memory), and direct RAMbus random access memory (DRRAM, Direct Rambus Random Access Memory).The memory 903 described in the embodiments of the present application is intended to include but is not limited to these and any other suitable types of memories.

[0177] The method disclosed in the above embodiment of the present application can be applied to the processor 901, or implemented by the processor 901. The processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 901 or an instruction in the form of software. The above processor 901 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 901 can implement or execute the methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor or any conventional processor, etc. In combination with the steps of the method disclosed in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in the memory 903, and the processor 901 reads the information in the memory 903 and completes the steps of the above method in combination with its hardware.

[0178] In an exemplary embodiment, the device may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD), field programmable gate array (FPGA), general processor, controller, microcontroller (MCU), microprocessor, or other electronic components to execute the aforementioned method.

[0179] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0180] It should be noted that, in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0181] The methods disclosed in several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0182] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0183] The features disclosed in several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0184] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A B-code timing accuracy compensation method for a nuclear power plant, characterized in that: The invention is applied to a time synchronization device including a time synchronization device, a B code time synchronization module, a display screen, and a single-board digital signal processor DSP; the single-board DSP is provided with an external interrupt IO port; the B code time synchronization module is connected to the time synchronization device and the display screen respectively; The display screen is connected to the single-board DSP; The single-board DSP is connected to the time synchronization device through the external interrupt IO port; the method includes: Determine a first time error between the synchronization time sent by the time synchronization device and the display screen; Determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP; determining a third time error of the time synchronization device based on the first time error and the second time error; The third time error is used to compensate the time set in the time synchronization device.

2. The method according to claim 1, characterized in that: The determining of a first time error from the synchronization time sent by the time synchronization device to the display screen comprises: Obtain the first time when the single-board DSP records the synchronization time sent by the time synchronization device to cause the external interrupt IO port to act, and the second time when the display screen receives the synchronization time; The first time error is determined based on the first time and the second time.

3. The method according to claim 2, characterized in that The determining the first time error based on the first time and the second time includes: determining a first difference between the second time and the first time; The first difference is used as the first time error.

4. The method according to claim 1, characterized in that The determining of a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP includes: Recording a third time when the display screen sends the time setting information; Recording a fourth time when the single-board DSP receives the time setting information; Recording a fifth time when the single-board DSP completes time setting based on the time setting information; Recording the sixth time when the display screen receives the flag information sent by the single-board DSP after completing the time setting; The second time error is determined based on the third time, the fourth time, the fifth time, and the sixth time.

5. The method according to claim 4, characterized in that The determining the second time error based on the third time, the fourth time, the fifth time, and the sixth time includes: determining a second difference between the sixth time and the third time; determining a third difference between the fifth time and the fourth time; The second time error is determined based on the second difference and the third difference.

6. The method according to claim 5, characterized in that The determining the second time error based on the second difference and the third difference comprises: Subtract the second difference from the third difference to obtain a fourth difference; The fourth difference is used as the second time error.

7. The method according to claim 6, characterized in that When the transmission route between the display screen and the single-board DSP is symmetrical, the method further includes: Determine the delay time between the display screen and the single-board DSP based on the second time error; The delay time is used to compensate for the setup time of the single-board DSP.

8. The method according to claim 6, characterized in that When the transmission route between the display screen and the single-board DSP is asymmetric, the method further includes: Re-determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP; calculating an average value of the second time error and the re-determined second time error; The average value is used to compensate for the setup time of the single-board DSP.

9. The method according to any one of claims 1 to 6, characterized in that: The determining a third time error of the time synchronization device based on the first time error and the second time error comprises: The first time error and the second time error are summed to obtain the third time error.

10. A B-code timing accuracy compensation device for a nuclear power plant, characterized in that: A time synchronization device is provided which includes a time synchronization device, a B code time synchronization module, a display screen, and a single-board digital signal processor DSP; the single-board DSP is provided with an external interrupt IO port; the B code time synchronization module is connected to the time synchronization device and the display screen respectively; The display screen is connected to the single-board DSP; The single-board DSP is connected to the time synchronization device through the external interrupt IO port; the device includes: A first determining unit, configured to determine a first time error between the synchronization time sent by the time synchronization device and the display screen; A second determining unit, used to determine a second time error from the time setting information sent by the display screen to the time setting completed by the single-board DSP; a third determining unit, configured to determine a third time error of the time synchronization device based on the first time error and the second time error; A compensation unit is used to compensate the time set in the time synchronization device by using the third time error.

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