Method for improving storage performance

Abstract

The invention relates to a method for improving storage performance. Belongs to the field of data storage. It is identified whether an access request to access the memory falls within a single logical cluster, and an operation is performed on the memory in accordance with the original access request if the access request does not span a different logical cluster. Otherwise, if the access request crosses different logic clusters, the different logic clusters related to the access request are combined into an elastic logic cluster with a variable logic position, and repeated contents, aiming at the different logic clusters, in the access request are reformed into similar requests with single contents; thereby performing an operation on the memory in accordance with the reformed access request. The typical advantage is that the data stream generated by the storage operation action can be compressed, and the bandwidth is saved and the data storage operation performance of the memory is remarkably improved during the period of constructing, transmitting and parsing the storage operation request.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a method for improving storage performance in a storage system such as a mechanical hard disk or a solid state disk that supports data storage. Background Art

[0002] The development of storage systems is accompanied by updates to hardware interface technology and communication protocols. Early mechanical hard disks and solid-state drives were limited by the inherent characteristics of the internal physical storage media, such as small capacity and small data width used for single read and write, so low-level bandwidth interfaces did not show problems. Currently, with the update and iteration of storage media, for example, the bandwidth of hard disk input and output IO has increased by several times or even hundreds of times. The currently used low-level bandwidth storage operations (such as fragmentation of instructions, repetition of some abstract content, etc.) will seriously restrict the improvement of storage performance in the face of high-level bandwidth scenarios.

[0003] In layman's terms, even if the storage operation is optimized, traditional optimizations such as priority cannot highlight the superiority of such optimization or provide a matching adaptive solution channel. Typically, limited bandwidth will still put the reading and writing of data and the corresponding optimization operations and other channel information in a state of resource grabbing, and performance improvement is out of the question. For example, the host and the mechanical hard disk or solid-state drive exchange data through a single queue mode, and although high concurrency allows data to be read from multiple different locations of the storage medium at the same time, the single queue becomes a bottleneck for concurrency.

[0004] In the storage system, during the communication process between the host and the hard disk, based on the premise of accurately writing the data to be stored to the memory and accurately reading the data from the memory, how to compress unnecessary communication data and streamline various types of interactive data to reduce the pressure on the interface, reduce communication delays, and ensure the smoothness of software execution are concerns that need to be improved in the storage system. Solving these problems will bring great performance improvements to the storage system. The development of communication protocols has brought room for improvement in storage operation optimization. For example, the speed improvement of communication protocols such as PCIe / NVMe in IO bandwidth is unprecedented, and there is great room for improvement in storage operations between the host and the hard disk. Summary of the invention

[0005] The present application relates to a method for improving storage performance, which is characterized in that it mainly includes: identifying whether an access request to access a memory falls within the scope of a single logical cluster, and if the access request does not cross different logical clusters, performing operations on the memory according to the original access request; otherwise, if the access request crosses different logical clusters, combining the different logical clusters involved in the access request into a flexible logical cluster with variable logical positions, and reorganizing the repeated contents within the access request for different logical clusters into a similar request with a single content, so as to perform operations on the memory according to the reorganized access request.

[0006] In the above method, the operation category of the access request on the memory at least includes a data read operation, a data write operation or a data erase operation.

[0007] The above method: the type of the memory includes a solid-state hard disk based on flash memory, and the memory maps the logical address (address information) carried by the original access request or the reorganized access request to the physical address inside itself.

[0008] In the above method, the total number of logical clusters included in the elastic logical cluster is a positive integer multiple of a single logical cluster, and the change of its logical position is implemented in a manner of covering one or more complete logical clusters at a time.

[0009] The above method: for the logical cluster covered by the elastic logical cluster but not involved in the current access request, the information corresponding to its logical address performs the same operation as the current access request, and the execution time of the same operation is synchronized with the execution time of the current access request.

[0010] The above method: if the access request spans across different logical clusters, the same type of requests for different logical clusters at least include a read request or a write request or an erase request (for example, the same type of requests are embodied in the reorganization step).

[0011] The above method: in the elastic logical cluster, the addresses of different logical clusters involved in the access request are continuous or the addresses of different logical clusters involved in the access request are separated by logical clusters not involved in the access request.

[0012] The above method: when the memory receives a plurality of consecutive access requests, firstly determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests;

[0013] A series of access requests with the same minimum command execution unit and the same operation category are synchronously executed once according to the physical addresses mapped to their respective logical addresses and according to their operation categories, thereby replacing the memory's sequential execution of several access requests.

[0014] The above method: when the memory receives a plurality of consecutive access requests, firstly determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests;

[0015] Execute a series of access requests with the same minimum command execution unit but different operation categories in sequence according to the physical addresses mapped to their respective logical addresses and according to their operation categories; or

[0016] A series of access requests with different minimum command execution units and the same or different operation categories are synchronously executed according to the physical addresses mapped to the respective logical addresses and according to their operation categories.

[0017] The present application relates to a method for improving storage performance, which is characterized by comprising:

[0018] Identify whether the access request falls within the scope of a single logical cluster of the memory. If the access request spans across different logical clusters, combine the different logical clusters involved in the access request into a flexible logical cluster with variable logical positions, and reorganize the repeated contents within the access request for different logical clusters into a single content request of the same type, so as to perform operations on the memory according to the reorganized access request;

[0019] When the memory receives several consecutive access requests, it will synchronously execute a corresponding operation on a series of the access requests with the same minimum command execution unit and the same operation category according to the physical addresses mapped to their respective logical addresses and according to their operation categories, thereby replacing the memory's sequential execution of the several access requests.

[0020] The present application relates to a method for improving storage performance, which is characterized by comprising:

[0021] Identify whether the access request falls within the scope of a single logical cluster of the memory. If the access request spans across different logical clusters, combine the different logical clusters involved in the access request into a flexible logical cluster with variable logical positions, and reorganize the repeated contents within the access request for different logical clusters into a single content request of the same type, so as to perform operations on the memory according to the reorganized access request;

[0022] When the memory receives a plurality of consecutive access requests, it first determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests;

[0023] Execute a series of access requests with the same minimum command execution unit but different operation categories in sequence according to the physical addresses mapped to their respective logical addresses and according to their operation categories; or

[0024] A series of access requests with different minimum command execution units and the same or different operation categories are synchronously executed according to the physical addresses mapped to the respective logical addresses and according to their operation categories.

[0025] The present application relates to a method for improving storage performance, which is characterized by comprising:

[0026] Identify whether an access request to access the memory falls within the scope of a single logical cluster, wherein if the access request does not cross different logical clusters, perform an operation on the memory according to the original access request;

[0027] When the memory receives a plurality of consecutive access requests, it first determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests;

[0028] A series of access requests with the same minimum command execution unit and the same operation category are synchronously executed once according to the physical addresses mapped to their respective logical addresses and according to their operation categories, thereby replacing the memory's sequential execution of several access requests.

[0029] The present application relates to a method for improving storage performance, which is characterized by comprising:

[0030] Identify whether an access request to access the memory falls within the scope of a single logical cluster, wherein if the access request does not cross different logical clusters, perform an operation on the memory according to the original access request;

[0031] When the memory receives a plurality of consecutive access requests, it first determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests;

[0032] Execute a series of access requests with the same minimum command execution unit but different operation categories in sequence according to the physical addresses mapped to their respective logical addresses and according to their operation categories; or

[0033] A series of access requests with different minimum command execution units and the same or different operation categories are synchronously executed according to the physical addresses mapped to the respective logical addresses and according to their operation categories.

[0034] Traditional mechanical hard disks (HDDs) in electronic products contain mechanical parts, and the magnetic head needs to move to the target position on the fast-rotating disk to write and read, and a large number of tasks are consumed by inefficient mechanical movements. Solid-state drives (SSDs), which have much faster reading speeds than mechanical hard disks, no longer focus on mechanical movements. Moreover, solid-state drives are more shock-resistant and drop-resistant than mechanical hard disks in terms of physical structure. The reason is that solid-state drives are made of solid-state electronic storage chip arrays and use integrated circuits instead of traditional rotating disks.

[0035] Although there are many storage advantages of solid-state hard disks, such as extremely high storage density, it also means that storage particles or storage chips need to use more word lines and bit lines to manipulate transistors that store bit data. Moreover, high-density transistor arrays also bring about the complexity of various aspects of storage management. Typically, there will inevitably be a large amount of repeated content in the communication instructions between the host and the hard disk, but how to deal with repeated content is one of the thorny problems. If it is possible to compress unnecessary operating data and streamline storage interaction data to reduce the pressure on the interface and reduce communication delays, the data access of the storage system will be much smoother and faster, and this is one of the goals that the context scheme of this application can achieve. In conjunction with the current mainstream high-speed communication protocol, memory performance (such as storage operation performance) is greatly improved and improved. Therefore, the method for improving storage performance can be referred to as a method for improving the data storage operation performance of the memory in this article.

[0036] The advantage of the example introduced in the context of this application is that during information storage operations, even if some requests are repeated and even if the storage operation requests overlap in construction, transmission and parsing, it is still possible to minimize unnecessary information of storage operations and save bandwidth to the maximum extent while ensuring data security and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0038] Figure 1 Data interaction occurs between the host and the solid-state drive with physical blocks, pages, and sectors.

[0039] Figure 2 It is to identify whether the access request to access the memory falls into the scope of a single logical cluster.

[0040] Figure 3 There are a lot of duplicate data segments in the interaction between the host and the hard disk, which causes blocking.

[0041] Figure 4 The storage operation needs to process data construction, transmission, and parsing, and generates redundant data.

[0042] Figure 5 It is the access request across different logical clusters and combines them into a resilient logical cluster.

[0043] Figure 6 The access request may or may not span different logical clusters.

[0044] Figure 7 The storage operation generates no or very little redundant data and hardly consumes bandwidth. DETAILED DESCRIPTION

[0045] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0046] See also Figure 1 One parameter of SSD is the reading speed. Traditional SSDs are usually designed to communicate with the host device through a serial advanced attachment technology (such as SATA) interface. As the access speed of flash memory chips in SSDs is increasing, such as improvements in chips and hardware, the accompanying interface technology has gradually become an advantage in further improving the data transmission speed between SSDs and hosts or similar devices. This advantage is extremely beneficial and crucial to the improvement of data storage performance and storage involved in this article.

[0047] See also Figure 1 , the relevant SATA interface is developed by the "Serial ATA Working Group". The main function is to transfer data between the motherboard and data storage devices (such as hard disks and optical drives). It is named because it uses serial data transmission. It has the advantages of simple structure and hot plug support. It belongs to the computer bus. The SATA bus uses an embedded clock frequency signal and has a stronger error correction capability than traditional interfaces. It can check the transmission instructions and data and automatically correct them when errors are found. The main purpose is to improve the reliability of data transmission.

[0048] See also Figure 1The related PCIe interface is a high-speed serial computer expansion bus standard interface. PCIe is mainly based on replacing the traditional PCI bus. PCI-Express (Peripheral Component Interconnect express) is designed based on a point-to-point topology and a separate serial link connects each device to the root system / host. Based on a shared bus topology, the PCI bus in a single direction can be arbitrated in the case of multiple hosts, and is limited to one host at a time. In terms of clock schemes, the traditional PCI bus limits the bus clock to the slowest peripheral on the bus. In contrast, the PCIe bus link supports full-duplex communication between any two endpoints, concurrent access across multiple endpoints, and no inherent limitations.

[0049] See also Figure 1 , the relevant NVMe interface specifications are as the name suggests. VM Express (NVMe) is called the Non-Volatile Memory Host Control Interface Specification (Non Volatile Memory). It is a bus transmission protocol specification based on the device logical interface, which is equivalent to the application layer in the communication protocol. It is used to access non-volatile memory media such as flash memory attached through the PCI-Express (PCIe) bus. In theory, it does not necessarily require the use of the PCIe bus protocol. The NVMe specification mainly provides a low-latency, internally concurrent native interface specification for flash-based storage devices, and also provides native storage concurrency support for current mainstream processors and computer platforms and related applications, so that host hardware and software can fully utilize the parallel storage capabilities of solid-state storage devices. Relying on the PCIe bus, NVMe devices can be mounted on various physical slots that support the PCIe bus or on related hardware.

[0050] See also Figure 1 , data is stored in the memory in the form of files on computers or electronic devices, and the target data is generally in the form of ASCII code or binary. For storage media such as Flash memory chips, designing a driver function that matches it can easily read and write data on the memory. The target content can be converted into ASCII code, stored in an array, and the array content is written to the specified address of the Flash memory chip. Then, when needed, the data can be read from the address and the read data can be interpreted in ASCII code format.

[0051] See also Figure 1 ,With the development of interface technology from SATA to PCIe and NVMe, data access has been improved by several times, dozens of times or even higher.

[0052] See also Figure 1 A typical SATA interface has a theoretical transmission speed of hundreds of megabytes per second.

[0053] See also Figure 1 In comparison, the theoretical transmission speed of PCIe / NVMe interface is several gigabits per second.

[0054] See also Figure 1 In an optional embodiment, unnecessary communication data should be compressed and various interactive data should be streamlined to reduce the pressure on the interface, reduce the intermediate communication delay, ensure the smoothness of software execution, etc. Preferably, the implementation of this improvement plan should take into account both high and low energy level bandwidths.

[0055] See also Figure 1 A solid-state drive (SSD) usually contains one or more storage particles or storage chips (LUN), which is basically the smallest unit for executing commands. Different LUNs can execute different command sequences.

[0056] See also Figure 1 A single storage particle or storage chip of a solid-state drive (SSD) has multiple planes. In order to optimize the flash memory access speed, each plane has independent data registers and cache registers.

[0057] See also Figure 1 A single plane of a solid-state drive (SSD) contains one or more blocks. A block usually contains many pages. For example, some manufacturers stipulate that the number of blocks should be a multiple of 32.

[0058] See also Figure 1 , using one block (Block_0) and another block (Block_63) as examples, in actual applications, the number of blocks in a single plane is far more than the number shown in the figure.

[0059] See also Figure 1 , a page of a solid-state drive (SSD) contains many bytes. The size of a page is usually a power of 2 but does not include the capacity of the spare area. A single page includes several sectors.

[0060] See also Figure 1 , spare area (spare) and data area (user data) are common concepts in memory.

[0061] See also Figure 1, a detailed explanation of the internal structure of the solid-state drive SSD can be described as follows. The space occupied by a single storage block usually includes a data area (user data) and a spare area (spare). Taking a single storage block containing 64 pages as an example, the data area of ​​a single storage block can be divided into 64 parts, each used to store the write data or information of each page. The spare area or redundant space of the storage block can also be divided into 64 parts, each used to store the redundant data or spare data of each page. Therefore, the space occupied by a single page includes a data area and a spare area. For example, block Block_0 includes pages P0-P63, etc.

[0062] See also Figure 1 , taking a single page containing 8 sectors as an example, the data area of ​​the page can also be divided into 8 parts, each used to store the data of each sector. The spare area of ​​the page can also be divided into 8 parts, and each used to store the redundant data or spare data of each sector. In addition, the information storage method of the page can also be adaptively modified. For example, a single page opens up a spare space or redundant space to uniformly store the redundant data or spare data of all sectors in the page. The figure shows that some single pages P3 or P4 are divided into 8 sectors Sec1, Sec2, Sec3,...Sec8, etc. The solid-state drive can maintain the mapping relationship between the logical block address and the physical storage block address through a mapping table.

[0063] See also Figure 1 In an optional embodiment, the SSD substantially integrates the main control chip and the storage particles, and the main control chip can also be called an SSD controller or a logic control unit (commond & control logic). The naming of different storage manufacturers may be slightly different. Regarding the logic control unit contained in the memory, it contains a mode register and a command decoder. The external host HOST inputs commands to the logic control unit through the command bus and the address bus. After the command is decoded by the command decoder, the control parameters are saved to the mode register and the logic control unit to control the logic operation. The external host HOST inputs address information through the address bus. The address information plays an auxiliary role when the logic control unit performs logic control. In addition, the multiplexed address bus works together with the control logic and the internal devices such as the row address multiplexer, the column address count latch, and the column address decoder to accurately select the storage unit corresponding to the row and column addresses in the storage array, and then perform data access operations. The functions of the logic control unit may also be different in different storage manufacturers. The above is only an example and does not constitute any limitation.

[0064] See also Figure 1, direct storage on the storage medium will bring great inconvenience, such as difficulty in recording the location of valid data and difficulty in determining the remaining space of the storage medium, and in what format the data should be interpreted. It is like a huge storage space that is left unattended, storing various contents in a disorderly manner, and it is difficult to find the required documents. Imagine that when you operate a computer and use the storage space, you just write the content into the storage space without managing it. When you operate the computer again and try to read a document, you have to search one by one from various mounted spaces.

[0065] See also Figure 1 Through analysis, it can be seen that the aforementioned direct data storage method is acceptable for small-capacity storage media such as EEPROM, but for large-capacity devices such as Flash storage chips or SD cards and SSD solid-state hard drives, an efficient way to manage its storage content is required. Otherwise, a large amount of complex address information that is easy to change with the amount of written data must be memorized to match the written data. If the storage system is considered from an enterprise-level commercial scenario, large-capacity SSD solid-state hard drives designed as unified storage or distributed storage are supported as the main research object and storage medium, so that massive storage requirements, data credibility and security are prerequisites that must be considered.

[0066] See also Figure 1 The conventional way to manage the storage content of storage media is the file system, which is an organizational structure established on the storage medium for the purpose of storing and managing data. For example, these organizational structures include necessary modules such as the operating system boot area, directories, and files.

[0067] See also Figure 1 For example, file system formats include FAT32, NTFS, exFAT, etc. These formats are common file systems under Windows operating systems. Before using the file system, you can format the storage medium. Formatting first erases the original content, for example, you can create a new file allocation table and directory on the storage medium. In this way, the file system can record information such as the physical address where the data is stored and the remaining space.

[0068] See also Figure 1 ,When using a file system, data is basically stored in the form of files.

[0069] See also Figure 1 When writing a new file, you need to first create a file index in the directory, which indicates the physical address where the file is stored, and then store the data at that address.

[0070] See also Figure 1When you need to read data, you can find the index of the file from the directory, and then read the data at the corresponding address based on the index. In addition, it also involves a series of auxiliary structures or processing processes such as logical address, cluster size, and discontinuous storage.

[0071] See also Figure 1 Through the process of the file system participating in the management of the storage content of the storage medium, it can be seen that the existence of the file system makes it no longer a simple matter of directly reading and writing data to the physical address of the storage medium when accessing data, but should follow the reading and writing format of the file system. For example, after logical conversion, a complete holistic file may be divided into multiple segments and stored in discontinuous physical addresses, and the location of the next segment is known by means of a directory or a linked list. If the volume of the holistic file is large and requires a large storage space, the participation of the file system is undoubtedly necessary.

[0072] See also Figure 2 In an optional embodiment, the capacity of the hard disk is constantly expanding, and the early definition of 512 bytes per sector is no longer so reasonable. Some manufacturers set the sector of 512 bytes to 4096 bytes. As NTFS and other file systems become standard hard disk file systems, the default allocation unit size (cluster) of their file systems can be selected as 4096 bytes. Considering that clusters and sectors correspond to each other, even if the physical hard disk partitions are aligned with the logical partitions used by the computer, and based on ensuring the hard disk read and write efficiency and read and write speed, it is necessary to design interactive optimization measures for cluster and hard disk interaction.

[0073] See also Figure 2 In an optional embodiment, if the access request spans across different logical clusters, the hard disk may need to write two physical storage space units when the file system operates a certain cluster. But in fact, at this time, a single physical storage space unit is sufficient to meet the data operation and storage requirements of the file system. If the logical clusters match the physical storage space, such as sectors, not only will the write speed of the hard disk be increased, but the service life of the hard disk can also be extended. On the contrary, if the logical clusters operated by the computer and the physical storage space, such as sectors, are mismatched, not only will the operating speed of the hard disk be reduced, but the service life of the hard disk will also be prematurely ended due to the imbalance of the read and write areas of the hard disk, and some spaces are prone to become bad areas.

[0074] See also Figure 2 In a specific embodiment, the data of a logical cluster corresponds to 8 logical blocks, the data size of each logical block is defined as 512B bytes, and the 8 logical blocks are Log1, Log2, ... Log 8, etc. Note that the listed data size and number of logical blocks are examples given only for the convenience of explanation, and real computers are not limited to this.

[0075] See also Figure 2In a specific embodiment, an access request such as a read request Real_D spans across different logical clusters, such as across logical cluster CLU_1 and logical cluster CLU_2. In this embodiment, the starting position of the partition of logical cluster CLU_1 is cluster logical block C0 and the ending position is cluster logical block C7, totaling 8 blocks. The starting position of the partition of logical cluster CLU_2 is cluster logical block C8 and the ending position is cluster logical block C15, totaling 8 blocks. Then the access request spans two physical storage space units, and the hard disk may write two physical storage space units when the file system writes a certain cluster, or the hard disk may read two physical storage space units when the file system reads a certain cluster.

[0076] See also Figure 2 In a specific embodiment, an access request such as a read request Real_D is not prohibited from crossing different logical clusters, but the problem arises in that during the interaction of the access request, a control node needs to be allocated to each physical storage space unit, and in the control nodes belonging to the same instruction, most of the information or number segments are highly repeated. For example, the information usually carried by the access request: access request operation type, logical address information and physical address information, etc., thus causing a large waste of computer resources.

[0077] See also Figure 2 In a specific embodiment, the first type of request content of the read request Real_D for the logical cluster CLU_1 and the second type of request content of the read request Real_D for the logical cluster CLU_2 have the same part, and of course there will be different contents. The two types or two access requests of the read request Real_D will have the same part, and the information carried by each of the two access requests has repeated content, which belongs to the redundant amount. Generally speaking, the object of operation, that is, the data itself and the access ancillary information coexist within the access request information. The operation object is, for example, the data to be read, the data to be stored, the data to be erased, or any related data.

[0078] See also Figure 2In a specific embodiment, an example is given to illustrate: if a read request Real_D accesses different logical clusters, such as the logical clusters CLU_1 and CLU_2, there is duplication between the amount of information of the read request Real_D accessing the logical cluster CLU_1 and the amount of information of the same read request accessing the logical cluster CLU_1. As mentioned above, the amount of information usually includes various operation types such as read operation or write operation or erase operation type, instruction information included in the amount of information such as interactive master-slave mode or interactive one-way and two-way communication mode or based on hardware control or software control, address information included in the amount of information such as storage particle LUN address or other logical address or physical address and other types of addresses, data validity record and other identifiers included in the amount of information, clock information included in the amount of information such as clock polarity or phase or frequency division factor, of course, all the amount of information included in the amount of information will not be repeated here. It can be seen that in addition to the object of operation, that is, the data itself, there is also a large amount of access-related information accompanying the data. The duplicated part of the information of the read request Real_D accessing the logical clusters CLU_1 and CLU_2 includes, for example, the operation type, instruction information, address information, identification information, clock information, and some other necessary information such as MSB / LSB first agreement, CRC check expression, data frame length, etc. In addition to the operation object, i.e., the data itself, access to the auxiliary information is also an indispensable and important part of the access request.

[0079] See also Figure 2 In a specific embodiment, if analyzed from the perspective of the host HOST, its processor will need to process repeated access data and various access information because the read request Real_D spans different logical clusters CLU_1 and CLU_2. However, in essence, the processor's processing process for logical cluster CLU_1 and the processor's processing process for logical cluster CLU_2 are filled with many of the same contents. In other words, the computer's memory part, such as SRAM or DRAM, will have the same content throughput inside, which will greatly affect the computing performance and memory performance of the computer system and seriously occupy the interface bandwidth of both. Under the low bandwidth limitation of the SATA interface, it is easy to detect that the repeated throughput content greatly occupies the interface bandwidth. Under the high bandwidth of the PCIe / NVMe interface, it is often difficult to intuitively find the relationship between the repeated throughput content and the interface bandwidth, but a large part of the bandwidth of PCIe / NVMe is used to carry the ancillary information of these access information volumes.

[0080] See also Figure 2In a specific embodiment, if analyzed from the perspective of the memory MMRY, the controller or logic control unit (commond & control logic) involved also needs to handle repeated various storage operations and various access information. The memory MMRY and the host HOST have both differences and similarities.

[0081] See also Figure 2 , the logic control unit of the memory MMRY typically needs to decode the first type of request content for the logical cluster CLU_1 and the second type of request content for the logical cluster CLU_2 in the read request Real_D. The same parts of the two types of read requests or two access requests will be repeatedly decoded and translated on the memory MMRY side. Therefore, the processing process on the memory side is also full of the same content, which restricts the performance of the memory. The memory side also needs to spend a lot of hardware and software resources to process the redundancy implicit in the access request. It is worth noting that the redundancy mentioned here is based on consideration and cognition from a human perspective. In fact, from the perspective of the host HOST and the memory MMRY, whether it is a duplicate content or not, it must be executed in sequence according to the pre-specified instructions.

[0082] See also Figure 3 Ideally, the read request Real_D should have a reasonable time Real_T during the operation of a computer or storage device. In the figure, the time axis TIME represents the time taken to execute an event (such as a data read operation, a data write operation, or a data erase operation, etc.). The logical cluster CLU_1 starts at cluster logical block C0 and ends at cluster logical block C7, which belongs to a partition block. The logical cluster CLU_2 partition starts at cluster logical block C8 and ends at cluster logical block C15, which belongs to a partition block. Due to the partition characteristics of the logical clusters CLU_1 and CLU_2, the first request content of the read request Real_D in the first physical storage space unit consumes some time, which is represented by WAIT_T1 in the figure; the second request content of the read request Real_D in the second physical storage space unit consumes some time, which is represented by WAIT_T2 in the figure. If an access request such as a read request Real_D spans more physical storage space units, it will consume more time.

[0083] See also Figure 3, the ideal time Real_T of the host HOST to execute the read request Real_D and the total time of the time execution event will be seriously delayed, because the main content of the information volume usually needs to complete the data construction and transmission and analysis processes in sequence when executing the event. The processor and memory will be equivalent to a blocking situation due to repeated processing of repeated content, although the computer or memory executes tasks according to its own program. Therefore, from the task side, there will be no blocking. From the perspective of the computer or memory executing tasks, there is no blocking. There is no resistance or hardware factors that prevent the program from executing normally during the execution phase, and it will not be terminated. Therefore, the tricky problem is that the blocking is hidden.

[0084] See also Figure 4 , the same content will be throughputed inside the memory SRAM or DRAM, which can be represented as: there is a data stream STREAM1 representing the throughput when executing the first event (assuming that the data stream STREAM1 is the information of a request that needs to be set when the first independent logic cluster is executed with data operation); similarly, there is also a data stream STREAM2 representing the throughput when executing the second event (assuming that STREAM2 is the information of a request that needs to be set when the second independent logic cluster is executed with data operation); similarly, there is also a data stream STREAM3 representing the throughput when executing the third event (assuming that STREAM3 is the information of a request that needs to be set when the third independent logic cluster is executed with data operation). More data streams are not shown in the figure.

[0085] See also Figure 4 The first independent logical cluster, the second independent logical cluster, the third independent logical cluster or more independent logical clusters belong to different physical storage space units. Therefore, when the file system reads and writes a cluster, the hard disk may read and write three or more physical storage space units.

[0086] See also Figure 4 , the data streams STREAM1-STREAM3 contain normal data such as the object of operation, that is, the data itself that is read or stored, and generate normal caches Buff0-Buff2. STREAM1-STREAM3 contains a large amount of duplicate content and generates redundant caches OV1 / OV2, etc. Assume that OV1 is a large amount of duplicate content between STREAM1 / STREAM2, such as the same read operation or write operation type, and OV2 is a large amount of duplicate content between STREAM2 / STREAM3, such as the same storage particle LUN address or the same instruction information. It will be found that even simple operations will generate huge memory overhead, which is unbearable in many storage occasions. Typically, fields such as artificial neural networks involve a large number of matrix operations, and memory overhead directly drags down the computing speed of the entire system.

[0087] See also Figure 5 In the illustrated example, the partition of logical cluster CLU_1 starts at cluster logical block C0 and ends at cluster logical block C7, totaling 8 blocks. The partition of logical cluster CLU_2 starts at cluster logical block C8 and ends at cluster logical block C15, totaling 8 blocks.

[0088] See also Figure 5 In the illustrated example, it is identified whether the access request Real_D0 for accessing the memory falls into the scope of a single logical cluster. The access request Real_D0 falls into the cluster logical blocks C4-C7 of the logical cluster CLU_1. At the same time, it is also found that the access request Real_D0 falls into the cluster logical blocks C8-C11 of the logical cluster CLU_2. Obviously, the access request spans different logical clusters CLU_1 and CLU_2 at the same time.

[0089] See also Figure 5 In an optional embodiment, if the access request spans across different logical clusters, the different logical clusters involved in the access request are combined into a flexible logical cluster with a variable logical position. If the request of Real_D0 spans across different logical clusters CLU_1 and CLU_2, it is necessary to combine the different logical clusters involved in the access request, such as Real_D0, into a flexible logical cluster CLU_PR0 with a variable logical position. It includes the logical cluster CLU_1 located at C4-C7 and the logical cluster CLU_2 located at C8-C15. Note that cluster logic blocks C4-C7 and cluster logic blocks C8-C11 cannot be combined into the flexible logical cluster CLU_PR0 separately. Only the logical clusters represented by cluster logic blocks C4-C7 and cluster logic blocks C8-C11 (such as CLU_1 and CLU_2) can be integrated into the flexible logical cluster CLU_PR0 as a whole.

[0090] See also Figure 5 In an optional embodiment, the access request Real_D0 internally targets different logical clusters (eg, different logical clusters CLU_1 and CLU_2) but duplicate contents are reorganized into similar requests with single contents, so that the memory is operated according to the reorganized access requests.

[0091] See also Figure 5In an optional embodiment, if the access request Real_D0 contains repeated contents for different logical clusters (e.g., different logical clusters CLU_1 and CLU_2), such as a read operation, and the read operation originally records the first read operation information based on CLU_1 in the data structure of the access request, and the read operation originally records the second read operation information based on CLU_2 in the data structure of the access request, then the first and second read operation information are merged and reorganized into a single read operation request. If the access request Real_D0 contains repeated contents for different logical clusters (e.g., different logical clusters CLU_1 and CLU_2), such as a write operation, and the write operation originally records the first write operation information based on CLU_1 in the data structure of the access request, and the read operation originally records the second write operation information based on CLU_2 in the data structure of the access request, then the first and second write operation information are merged and reorganized into a single write operation request. If the access request Real_D0 contains repeated content for different logical clusters (for example, different logical clusters CLU_1 and CLU_2), and the LUN originally records a first LUN information based on CLU_1 in the data structure of the access request, and at the same time, the LUN originally records a second LUN information based on CLU_2 in the data structure of the access request, then the first and second address operation information are merged and reorganized into the same LUN address operation request with a single content.

[0092] See also Figure 5 Regarding the elastic logical cluster CLU_PR0 with variable logical position: if the request of Real_D0 spans different logical clusters CLU_1 and CLU_2, for example, it is known that the access request Real_D0 falls into the cluster logical blocks C0-C3 and C4-C7 of the logical cluster CLU_1, and at the same time the access request Real_D0 falls into the cluster logical blocks C8-C11 of the logical cluster CLU_2, then it is necessary to combine the different logical clusters involved in the access request, such as Real_D0, into an elastic logical cluster CLU_PR0 with variable logical position, which includes the logical cluster CLU_1 whose position is adjusted to C0-C7 and the logical cluster CLU_2 whose previous position was C8-C15. Note that cluster logic blocks C0-C7 and cluster logic blocks C8-C11 cannot be combined into the flexible logic cluster CLU_PR0 individually. Only the logical clusters represented by cluster logic blocks C0-C7 and cluster logic blocks C8-C11 (such as CLU_1 and CLU_2) can be integrated into the flexible logic cluster CLU_PR0 as a whole.

[0093] See also Figure 6In the illustrated example, it is identified whether an access request such as Real_D1 for accessing the memory falls within the scope of a single logical cluster. The access request Real_D1 falls within the cluster logical block C0-C7 of the logical cluster CLU_1. At the same time, it is also found that the access request Real_D1 does not fall into any cluster logical block of other logical clusters. Obviously, the access request does not span different logical clusters at the same time. If the access request such as Real_D1 does not span different logical clusters, the operation on the memory is performed according to the original access request such as Real_D1. The operation category of the original access request on the memory at least includes data read operation, data write operation or data erase operation. In other words, if the access request Real_D1 does not span different logical clusters, the logical cluster involved in the access request is regarded as a fixed logical cluster CLU_PR1, or the current so-called fixed logical cluster CLU_PR1 is the logical cluster itself or itself involved in the access request Real_D1.

[0094] See also Figure 6 In the illustrated example, access request Real_D1 and access request Real_D2 coexist, which means that there are multiple accesses between the computer or the memory. Of course, the request contents of Real_D1 and Real_D2 can be the same or different, for example, the former is a read operation and the latter is a write operation, or vice versa.

[0095] See also Figure 6 In the illustrated example, the partition of logical cluster CLU_2 starts at cluster logical block C8 and ends at cluster logical block C15, totaling 8 blocks. The partition of logical cluster CLU_3 starts at cluster logical block C16 and ends at cluster logical block C23, totaling 8 blocks.

[0096] See also Figure 6 In the illustrated example, it is identified whether the access request Real_D2 for accessing the memory falls into the scope of a single logical cluster. The access request Real_D2 falls into the cluster logical blocks C8-C11 of the logical cluster CLU_2. At the same time, it is also found that the access request Real_D2 falls into the cluster logical blocks C16-C23 of the logical cluster CLU_3. Obviously, the access request spans different logical clusters CLU_2 and CLU3 at the same time, but does not involve CLU_1.

[0097] See also Figure 6In an optional embodiment, if the access request spans across different logical clusters, the different logical clusters involved in the access request are combined into a flexible logical cluster with a variable logical position. If the request of Real_D2 spans across different logical clusters CLU_2 and CLU_3, it is necessary to combine the different logical clusters involved in the access request, such as Real_D2, into a flexible logical cluster CLU_PR2 with a variable logical position. It includes the logical cluster CLU_2 located at C8-C11 and the logical cluster CLU_3 located at C16-C23. Cluster logic blocks C8-C11 and cluster logic blocks C16-C23 cannot be combined into the flexible logical cluster CLU_PR2 alone, and the logical clusters (such as CLU_2 and CLU_3) represented by cluster logic blocks C8-C11 and cluster logic blocks C16-C23 respectively need to be integrated into the flexible logical cluster CLU_PR2 as a whole.

[0098] See also Figure 6 Regarding the elastic logical cluster CLU_PR2 with variable logical position: If the request of Real_D2 spans different logical clusters CLU_2 and CLU_3, for example, it is known that the access request Real_D2 falls into the cluster logical blocks C8-C11 and C12-C15 of the logical cluster CLU_2, and at the same time the access request Real_D2 falls into the cluster logical blocks C16-C23 of the logical cluster CLU_3, then it is necessary to combine the different logical clusters involved in the access request, such as Real_D2, into an elastic logical cluster CLU_PR2 with variable logical position, which includes the logical cluster CLU_2 adjusted to C8-C15 and the logical cluster CLU_3 whose previous position was C16-C23.

[0099] See also Figure 6 In an optional embodiment, the access request Real_D2 internally targets different logical clusters (eg, different logical clusters CLU_2 and CLU_3) but duplicate contents are reorganized into similar requests with single contents, so that the memory is operated according to the reorganized access request.

[0100] See also Figure 6In an optional embodiment, the access request Real_D2 contains repeated contents such as a mode instruction for different logical clusters (e.g., different logical clusters CLU_2 and CLU_3), and the instruction originally recorded a first master-slave mode based on CLU_2 in the data structure of the access request, and the instruction originally recorded a second master-slave mode based on CLU_3 in the data structure of the access request, then the first and second master-slave information are merged and reorganized into a master-slave request with a single content. The access request Real_D2 contains repeated contents such as a data frame length for different logical clusters (e.g., different logical clusters CLU_2 and CLU_3), and the data format originally recorded a first data frame length based on CLU_2 in the data structure of the access request, and the data format originally recorded a second data frame length based on CLU_3 in the data structure of the access request, then the first and second data format operation information are merged and reorganized into a data frame length request with a single content.

[0101] See also Figure 7 , the same content will be throughputd inside the memory SRAM or DRAM which can be represented as: it contains data stream STREAM1 representing the throughput when executing the first event (assuming that data stream STREAM1 is the information of a request that needs to be set when the first independent logical cluster is to be operated on); similarly, it also contains data stream STREAM2 representing the throughput when executing the second event (assuming that STREAM2 is the information of a request that needs to be set when the second independent logical cluster is to be operated on).

[0102] See also Figure 4 , the data streams STREAM1-STREAM3 contain normal data such as the object of operation, i.e., the data read or stored, and generate normal caches Buff0-Buff2. STREAM1-STREAM3 contain a large amount of duplicate content and generate redundant caches OV1 / OV2, etc. Assume that OV1 is a large amount of duplicate content between STREAM1 / STREAM2, such as the same read operation or write operation type, and OV2 is a large amount of duplicate content between STREAM2 / STREAM3, such as the same storage particle LUN address or the same instruction information, etc. Figure 7 In the data flow, redundant caches are merged and reorganized into similar requests with single content. OV1 / OV2 appears almost once.

[0103] See also Figure 7, you will find that any storage operation will no longer generate a huge additional memory overhead. This is highly recommended regardless of the storage occasion. The saved memory is suitable for the high-speed operation of the entire computer storage. The various hardware parts of the computer include interface modules and memory modules, etc. The same or repeated content that was originally throughput according to the traditional solution is compressed and greatly reduced in this article. This will greatly improve the computing performance and memory performance of the computer system and release the interface bandwidth occupied by the redundant information of both. The interface SATA or PCIe / NVMe no longer needs to consume a lot of resources to carry the redundant information attached to the information volume of these access requests. The controller or logic control unit (commond & control logic) involved in the memory MMRY also does not need to handle various repeated storage operations and various repeated access information volumes. This significantly improves the storage performance. The relevant data operations of the computer and memory involved in this article can be considered as a feasible way of in-memory computing.

[0104] See also Figure 6 In an optional embodiment, the operation category of the access request such as Real_D1 and Real_D2 on the memory includes at least a data read operation, a data write operation, or a data erase operation. Figure 1 Solid-state drives, especially solid-state drives based on flash memory. The memory MMRY maps the logical address carried by the original access request or the reorganized access request to its own internal physical address. Case of the original access request: Under this condition, if the access request does not cross different logical clusters, the memory is operated according to the original access request. Case of the reorganized access request: Under this condition, if the access request crosses different logical clusters, the different logical clusters involved in the access request are combined into a flexible logical cluster with variable logical positions, and the repeated content within the access request for different logical clusters can be reorganized into a single content of the same type of request (that is, the reorganized access request), so that the memory is operated according to the reorganized access request.

[0105] See also Figure 6 In an optional embodiment, for a logical cluster covered by the elastic logical cluster but not involved in the current access request, the information corresponding to its logical address performs the same operation as the current access request, and the execution time of the same operation is synchronized with the execution time of the current access request.

[0106] See also Figure 5In a specific embodiment, for a logical cluster such as CLU_1 (specifically, a cluster logical block of the logical cluster CLU_1, such as cluster logical blocks C0-C3) covered by an elastic logical cluster such as CLU_PR0 but not involved in a current access request such as Real_D0, the information corresponding to the logical address of the logical cluster such as CLU_1 is used to perform the same operation (such as read / write, etc.) as the current access request such as Real_D0, and the execution time of the same operation (such as read / write, etc.) is synchronized with the execution time of the current access request such as Real_D0.

[0107] See also Figure 5 In a more detailed embodiment, for cluster logic blocks such as cluster logic blocks C0-C3 of CLU_1 that are covered by an elastic logical cluster such as CLU_PR0 but are not involved in a current access request such as Real_D0 (specifically, cluster logic blocks of the logical cluster CLU_1 that are covered by an elastic logical cluster but are not involved in a current access request), in this embodiment, the information corresponding to the logical addresses of cluster logic blocks C0-C3 of a logical cluster such as CLU_1 can be used to perform the same operation (such as read / write, etc.) as the current access request such as Real_D0, and the execution time of the same operation (such as read / write, etc.) is synchronized with the execution time of the current access request such as Real_D0. For example, the information corresponding to cluster logic blocks C0-C3 and the information corresponding to cluster logic blocks such as cluster logic blocks C4-C7 and C8-C11 covered by elastic logic clusters such as CLU_PR0 and involved in the current access request such as Real_D0 perform the same operation, and the execution time of the same operation is synchronized with the execution time of the current access request such as Real_D0 (for example, for C4-C7 and C8-C11). The advantage is that the adaptation relationship that makes clusters and sectors correspond can be followed, and the physical space partitions are aligned with the logical partitions of the computer, without wasting storage space and ensuring the high speed of data read and write operations. And keep a balance with the interface speed of mainstream PICe / NVMe. Let data operations be evenly implemented on all cluster logic blocks of the logical cluster, rather than tending to always continuously perform data operations on a few cluster logic blocks and prematurely end the life of the entire logical cluster where these few cluster logic blocks are located.

[0108] See also Figure 5 In an optional embodiment, the total number of logical clusters included in the elastic logical cluster CLU_PR0 is a positive integer multiple of a single logical cluster (for example Figure 5 2 times or Figure 6The change of the logical position of the elastic logical cluster is implemented in a way of covering one or more complete logical clusters at a time. The change of the logical position of the elastic logical cluster is not allowed to cover only half of the logical cluster, nor is the change of the logical position of the elastic logical cluster allowed to cover only other number of cluster logical blocks (such as 1-7) in a single logical cluster that is less than the total number of cluster logical blocks (such as 8).

[0109] See also Figure 5 In an optional embodiment, the logical position of the elastic logical cluster CLU_PR0 is implemented in a manner of covering two complete logical clusters, for example, covering logical clusters CLU_1 and CLU_2. The change of the logical position of the elastic logical cluster is not allowed to cover only the other number of cluster logical blocks in the single logical cluster CLU_1 that is less than the total number of its cluster logical blocks (such as 8) (such as 4 cluster logical blocks C4-C7 in the logical cluster CLU_1). The change of the logical position of the elastic logical cluster is not allowed to cover only the other number of cluster logical blocks in the single logical cluster CLU_2 that is less than the total number of its cluster logical blocks (such as 8) (such as 4 cluster logical blocks C8-C11 in the logical cluster CLU_2).

[0110] See also Figure 5 In an optional example, if an access request spans across different logical clusters, the different logical clusters involved in the access request are combined into a flexible logical cluster with a variable logical position, and the repeated contents within the access request for different logical clusters are reorganized into similar requests with a single content (the similar requests for different logical clusters include at least a read request or a write request or an erase request), and operations are performed on the memory according to the reorganized access request.

[0111] See also Figure 5 In an optional embodiment, in the elastic logical cluster, addresses of different logical clusters involved in the access request are continuous, or their addresses are separated by logical clusters not involved in the access request.

[0112] See also Figure 5 In an optional example, the addresses of different logical clusters (such as CLU_1 and CLU_2) involved in the access request such as Real_D0 in the flexible logical cluster CLU_PR0 are continuous. Figure 6 Assume that the request of Real_D2 does not include logical cluster CLU_2 but only includes logical cluster CLU_3. Figure 6It is assumed that the requests of Real_D1 and D2 belong to the same operation, and the addresses of CLU_1 of the request of Real_D1 and CLU_3 of the request of Real_D2 are separated by the logical cluster CLU_2 that is not involved in the access requests of Real_D1 and D2. Regarding the assumption that the requests of Real_D1 and D2 belong to the same operation: if Real_D1 and Real_D2 belong to the same read operation or write operation, merging them into a single operation is an optional solution (the access request can be recorded as Real_D1 / D2), and they belong to two different operations, which is also an optional solution (the access request can be recorded as Real_D1 and Real_D2).

[0113] See also Figure 5 In an optional embodiment, in the elastic logical cluster, the addresses of the cluster logical blocks of different logical clusters involved in the access request are continuous, or the addresses of the cluster logical blocks of different logical clusters involved in the access request are separated by logical cluster blocks not involved in the access request. From this embodiment, it can be seen that the method for improving storage performance mentioned in this article has excellent adaptability, and its solution for improving storage performance is applicable to the case where the address of the access logical cluster is continuous (or the address of the cluster logical blocks of the logical cluster is continuous) and the case where the address of the access logical cluster is discontinuous (or the address of the cluster logical blocks of the logical cluster is discontinuous). This consideration is mainly based on the fact that the data in the actual storage environment may be randomly in a continuous distribution state or a discontinuous distribution state in the storage space.

[0114] See also Figure 6 In the alternative example, assuming that the request of Real_D2 already includes logical cluster CLU_2 and includes logical cluster CLU_3, Figure 6 It is assumed that the requests of Real_D1 and D2 belong to the same operation, and the addresses of the cluster logic blocks C0-C7, C8-C15, C16-C23 of different logical clusters involved in the access request, such as CLU_1 to CLU_3, are continuous rather than discontinuous. This is an optional example. At this time, the access request belongs to Real_D1 / D2.

[0115] See also Figure 6 In an alternative example, assume that the request of Real_D2 does not include logical cluster CLU_2 but only includes logical cluster CLU_3. Figure 6 It is assumed that the requests of Real_D1 and D2 belong to the same operation, and the addresses of cluster logical blocks C0-C7, C16-C23 of different logical clusters involved in the access request, such as CLU_1 and CLU_3, are discontinuous and separated by logical clusters or logical cluster blocks such as C8-C15 that are not involved in the access request. This is also an optional example and the access request at this time belongs to Real_D1 / D2.

[0116] See also Figure 6 In an optional embodiment, when the memory MMRY receives several consecutive access requests, it can first determine whether the minimum command execution units of the several access requests (such as Real_D1 and Real_D2), such as LUN, are consistent and determine the respective operation categories of the several access requests (such as Real_D1 and Real_D2). A series of access requests (such as Real_D1 and Real_D2) with the same minimum command execution unit and the same operation category are synchronously executed once according to the physical addresses mapped by their respective logical addresses and according to their operation categories, replacing the memory's sequential execution of the several access requests (such as no longer executing Real_D1 first and then Real_D2). In this example, Real_D1 and D2 are assumed to be access requests that access the same LUN and are of the same category, for example, they are all read operations or they are all write operations. Real_D1 and D2 perform an operation (read operation) synchronously according to the physical addresses mapped by their respective logical addresses and their operation categories (such as read operation). The requests of Real_D1 and D2 are executed synchronously in this example, not sequentially as in the traditional solution. The main advantages are to enhance the robustness of data operations, reduce the latency of data operations, and improve the balance of the overall storage space of the memory.

[0117] See also Figure 6 In an optional embodiment, when the memory MMRY receives several consecutive access requests, it can first determine whether the minimum command execution units of the several access requests (such as Real_D1 and Real_D2) are consistent, such as LUN, and determine the respective operation categories of the several access requests (such as Real_D1 and Real_D2). A series of access requests (such as Real_D1 and Real_D2) with the same minimum command execution unit and different operation categories are executed in sequence according to the physical addresses mapped to their respective logical addresses and their operation categories. In this example, Real_D1 and D2 are assumed to be access requests that access the same LUN and belong to different categories, such as one of them is a read operation and the other of them is a write operation. Real_D1 and D2 are executed in sequence according to the physical addresses mapped to their respective logical addresses and their operation categories (such as read operation and write operation, respectively). The requests of Real_D1 and D2 are executed in sequence in this example, for example, Real_D1 is executed first and Real_D2 is executed later. The main advantages are enhancing the robustness of data operations, reducing the latency of data operations, and improving the balance of the overall storage space of the memory.

[0118] See also Figure 6In an optional embodiment, when the memory MMRY receives several consecutive access requests, it can first determine whether the minimum command execution units of the several access requests (such as Real_D1 and Real_D2) are consistent, such as LUN, and determine the respective operation categories of the several access requests (such as Real_D1 and Real_D2). A series of access requests (such as Real_D1 and Real_D2) with different minimum command execution units and the same or different operation categories are synchronously executed according to the physical addresses mapped to their respective logical addresses and according to their operation categories. In a certain example, Real_D1 and D2 are assumed to be access requests that access different LUN1 and LUN2, and they belong to the same category, for example, they are all read operations or they are all write operations. Real_D1 and D2 synchronously execute an operation (such as read) according to the physical addresses mapped to their respective logical addresses and their operation categories (such as read). The requests of Real_D1 and D2 are synchronously executed in this example but not sequentially as in the traditional solution. In contrast, in a certain example, Real_D1 and D2 are assumed to access different LUN1 and LUN2, and they belong to different categories of access requests, such as one of them is a write operation and the other is a read operation. Real_D1 and D2 perform an operation synchronously according to the physical addresses mapped by their respective logical addresses and according to their operation categories (such as write operation and read operation respectively). The requests of Real_D1 and D2 are executed synchronously in this example but not sequentially as in the traditional solution. The main advantages are to enhance the robustness of data operations, reduce the latency of data operations, and improve the balance of the overall storage space of the memory.

[0119] See also Figure 6 , about the method of improving storage performance, combined with Figure 5 , mainly including: for example, identifying whether the access request falls into the scope of a single logical cluster of the memory at the computer end or the memory end, and if the access request spans different logical clusters, combining the different logical clusters involved in the access request into a flexible logical cluster with variable logical positions, and reorganizing the repeated contents within the access request for different logical clusters into the same type of requests with a single content, so as to perform operations on the memory according to the reorganized access request. As mentioned above, once the memory receives several consecutive access requests mentioned above, a series of access requests with the same minimum command execution unit and the same operation category will be synchronously executed once according to the physical addresses mapped to their respective logical addresses and according to their operation categories, thereby replacing the memory's sequential execution of several access requests.

[0120] See also Figure 5In an optional embodiment, if an access request spans across different logical clusters, the different logical clusters involved in the access request are combined into an elastic logical cluster with a variable logical position, and the repeated contents within the access request for different logical clusters are reorganized into similar requests with a single content, so as to perform operations on the memory according to the reorganized access request. In the elastic logical cluster, the address order of the cluster logical blocks of different logical clusters is disrupted, and the cluster logical blocks that need to perform the operation (i.e., perform the operation on the memory according to the reorganized access request) are based on the condition of disrupted address order and perform the operation in sequence according to the random addresses (random addresses are addresses with disrupted order). During the implementation of the operation, if the data information of any cluster logical block does not match the preset verification between the operation, the operation is immediately canceled in the elastic logical cluster until all cluster logical blocks that need to perform the operation return to their original state. Canceling the operation midway here is essentially equivalent to operation failure. The file system needs to automatically cancel the operation and restore the data to its original state. Combined with Figure 6 .

[0121] See also Figure 5For example, if the access request Real_D0 spans the logical clusters CLU_1 and CLU_2, the logical clusters CLU_1 and CLU_2 involved in the access request are combined into a flexible logical cluster CLU_PR0 with a variable logical position, and the repeated contents in the access request for different logical clusters are reorganized into a request of the same type with a single content, so as to perform operations on the memory according to the reorganized access request. In an optional embodiment, for the flexible logical cluster CLU_PR0, the original address order of the cluster logic blocks of different logical clusters such as CLU_1 and CLU_2 is first shuffled, and a small number of cluster logic blocks such as cluster logic blocks C0-C9 are taken as examples, but the actual cluster logic blocks are not limited thereto. The cluster logic blocks that need to perform the operation are, for example, C0-C9 as an example, and the operation is performed in sequence according to the shuffled addresses based on the shuffled address order. The shuffled addresses with shuffled address order are, for example, C0, C3, C6, C9, C1, C4, C7, C2, C5, and C8. For comparison, the original addresses whose address order is not disrupted are, for example, C0, C1, C2, C3, C4, C5, C6, C7, C8, and C9. It should be noted that the address ordering rules are not limited here, but it should be avoided that the same logical cluster, such as CLU_1 or CLU_2, directly executes the operation without data recovery. During the implementation of the operation (such as a write operation or an erase operation or data overwriting, etc.), if the data information of any cluster logic block, such as any cluster logic block in C9, does not match the preset verification between the operations, the operation is canceled in the elastic logical cluster until all cluster logic blocks that need to execute the operation, such as C0, C3, C6, and C9, return to the original state, that is, those cluster logic blocks that have executed the operation still need to return to the original state, and the cluster logic blocks that have not executed the operation will no longer continue to execute the operation. The provisions of address ordering disruption can effectively prevent the cluster logic blocks arranged in sequence within the same logical cluster from executing the operation and losing all original information. In terms of preset verification, for example, a given operation (taking digital quantity A as an example) and the data information as the operation object (taking digital quantity B as an example) implement a preset verification operation (for example, requiring digital quantities A and B to implement XOR or other verifications), if the preset verification between the data information of any cluster logic block and the operation does not match, the operation of all cluster logic blocks C0-C9 is canceled. Here, the verification operation using XOR verification as an example is only an optional solution and not a restrictive solution.

[0122] See also Figure 5, according to the foregoing, if the verification between the data of any cluster logic block and the operation instruction does not match during the execution of the operation, the operation will be canceled immediately. Canceling the operation midway is equivalent to the failure of the operation, so the file system is set to automatically cancel the operation and restore the data to its original state. Similar to data overwrite, if the data overwrite is exited midway, it is allowed to actively cancel the data overwrite and actively guide the automatic cancellation of this data overwrite operation. The reason is: the current technical conditions cannot ensure that the storage operation between the computer and the memory is always 100% accurate. Many scenarios such as the operation instruction itself or the combination of the operation instruction loaded on the data or the intermediate process of construction, transmission, and parsing of any information (such as the operation instruction and the operation object) between different devices will cause them to make mistakes in storage operations. In this application, the different logical clusters involved in the access request are combined into a flexible logical cluster with variable logical positions, in which the data error of any cluster logic block of any logical cluster will cause all the data of the entire flexible logical cluster to be wrong, such as Figure 5 If a single access request operation error (such as erasing or writing, etc.) occurs in the sub-cluster logic block Log1 of the cluster logic block C7, it will cause all data in the entire elastic logic cluster CLU_PR0 to be erroneous rather than just limited to the logic cluster C7 itself. This situation usually results in irreversible data error operation consequences for all the data in the memory MMRY. The different logic clusters involved in the access request are combined into a flexible logic cluster with variable logical positions, and the repeated contents within the access request for different logic clusters are reorganized into similar requests with a single content, so as to perform operations on the memory according to the reorganized access request: Obviously, this solution can bring advantages but also disadvantages. Regarding the main cause of the disadvantage, you can compare Figure 2 , if the access request is not a reorganized access request, such disadvantages can be avoided, for example, the first access request operates CLU_1 first and after the operation is completed, the second access request operates CLU_2. If CLU_1 and CLU_2 are not combined into a flexible logical cluster with variable logical positions, there will be no consequences of data errors in the memory. If CLU_1 fails, it is only an error of itself and will not affect CLU_2, and CLU_2 errors will not affect CLU_1. On the contrary, if the memory is operated according to the reorganized access request, CLU_1 errors may affect more space from CLU_1 to CLU_4096 or even more space from the flexible logical cluster CLU_PR0; CLU_2 errors may affect more space from CLU_1 to CLU_4096 or even more space from the flexible logical cluster CLU_PR0. Avoiding these disadvantages may lose the aforementioned advantages. Obviously, there is a difficult problem here and how to eliminate the disadvantages is a question that needs to be solved urgently. The aforementioned solution involving random addressing is a feasible solution.

[0123] See also Figure 5According to the above, if the access request spans across different logical clusters and the different logical clusters involved in the access request are combined into a flexible logical cluster with variable logical positions, some disadvantages will be brought about. In this case, the repeated contents within the access request for different logical clusters are reorganized into similar requests with a single content, so as to perform operations on the memory according to the reorganized access request, which will also bring about related disadvantages. The disadvantage event is: when any logical cluster within the elastic logical cluster has an error when executing the operation, it will induce all logical clusters within the elastic logical cluster to have an error at the same time and cause irreversible data loss or error. Note that the fundamental reason for the occurrence of disadvantage events is that different single logical clusters are combined together as a whole and different single logical clusters synchronously execute the reorganized access request as a whole. The main purpose of the scheme described above in this article is to avoid the occurrence of the above disadvantage events.

[0124] See also Figure 5 According to the above, the measures are equivalent to: performing the operation once every several cluster logic blocks and leaving a series of reserved cluster logic blocks without performing the operation, until the operation flows to the last cluster logic block and then performing the same operation on the reserved cluster logic block again. This is also a data operation verification method that disrupts the cluster logic block sorting rules, that is, the correctness of the data operation is not verified according to the original logical cluster sorting, but the address sorting of the cluster logic blocks of different logical clusters in the elastic logical cluster is disrupted, and the cluster logic blocks that need to perform the operation are verified according to the disordered address under the condition of the disrupted address sorting. The advantage is that there is still an opportunity to cancel the erroneous operation during the discovery of the erroneous operation, and the scheme of this paper provides multiple verifications for the operation, thereby ensuring the complete correctness of the operation. This is an advantage that traditional storage operation schemes do not have and are difficult to achieve. Here, multiple verifications are embodied in, for example, providing each cluster logic block with a verification opportunity and providing each logical cluster with at least one data recovery and regression opportunity. This is determined based on the specific scheme for performing the operation on the memory.

[0125] See also Figure 7 Regarding the method for improving storage performance, a person of ordinary skill in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the above program can be stored in a computer-readable storage medium, which executes the steps of the above method embodiment when executed. The above storage medium includes various media that can store program codes, such as ROM, RAM, magnetic disk or optical drive disk.

[0126] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above invention provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention.

Claims

1. A method for improving storage performance, characterized in that: include: Identify whether an access request to access the memory falls within the scope of a single logical cluster. If the access request does not span across different logical clusters, perform operations on the memory in accordance with the original access request. Otherwise, if the access request spans across different logical clusters, combine the different logical clusters involved in the access request into a flexible logical cluster with variable logical positions, and reorganize the repeated contents within the access request for different logical clusters into a similar request with a single content, so as to perform operations on the memory in accordance with the reorganized access request.

2. The method according to claim 1, characterized in that: The operation category of the access request on the memory at least includes a data read operation, a data write operation, or a data erase operation.

3. The method according to claim 1, characterized in that: The type of the memory includes a solid-state hard disk based on flash memory, and the memory maps a logical address carried by an original access request or a reorganized access request to a physical address inside the memory.

4. The method according to claim 1, characterized in that: The total number of logical clusters included in the flexible logical cluster is a positive integer multiple of a single logical cluster, and the change of its logical position is implemented in a manner of covering one or more complete logical clusters at a time.

5. The method according to claim 1, characterized in that: For the logical cluster covered by the elastic logical cluster but not involved in the current access request, the information corresponding to the logical address thereof executes the same operation as the current access request, and the execution time of the same operation is synchronized with the execution time of the current access request.

6. The method according to claim 1, characterized in that: The same type of requests for different logical clusters at least include a read request, a write request, or an erase request.

7. The method according to claim 1, characterized in that: In the elastic logical cluster, addresses of different logical clusters involved in the access request are continuous, or their addresses are separated by logical clusters not involved in the access request.

8. The method according to claim 1, characterized in that: When the memory receives a plurality of consecutive access requests, it first determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests; A series of access requests with the same minimum command execution unit and the same operation category are synchronously executed once according to the physical addresses mapped to their respective logical addresses and according to their operation categories, thereby replacing the memory's sequential execution of several access requests.

9. The method according to claim 1, characterized in that: When the memory receives a plurality of consecutive access requests, it first determines whether the target minimum command execution units of the plurality of access requests are consistent, and determines the operation categories of the plurality of access requests; Execute a series of access requests with the same minimum command execution unit but different operation categories in sequence according to the physical addresses mapped to their respective logical addresses and according to their operation categories; or A series of access requests with different minimum command execution units and the same or different operation categories are synchronously executed according to the physical addresses mapped to the respective logical addresses and according to their operation categories.

10. A method for improving storage performance, characterized in that: include: Identify whether the access request falls within the scope of a single logical cluster of the memory. If the access request spans across different logical clusters, combine the different logical clusters involved in the access request into a flexible logical cluster with variable logical positions, and reorganize the repeated contents within the access request for different logical clusters into a single content request of the same type, so as to perform operations on the memory according to the reorganized access request; When the memory receives several consecutive access requests, it will synchronously execute a corresponding operation on a series of the access requests with the same minimum command execution unit and the same operation category according to the physical addresses mapped to their respective logical addresses and according to their operation categories, thereby replacing the memory's sequential execution of the several access requests.

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