Read optimization method under read-write mixed scene and storage device

Abstract

The invention relates to the technical field of storage, in particular to a read optimization method under a read-write mixed scene, which comprises the following steps: judging whether a received I < O > command is a write command or not; if the I < O > command is a write command, checking whether an idle write on-chip cache is enough to be used for processing the write command; in response to an idle write on-chip cache which is not enough to be used for processing the write command, storing the write command into a write waiting processing resource pool, and continuing to receive a new IO command; the write command is processed in response to there being an idle write on-chip cache sufficient to be used to process the write command. According to the method, the influence of the write operation on the read operation can be reduced, so that the waiting time of the read operation is shortened, and the read operation delay is optimized.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a method and storage device for read optimization in a mixed read-write scenario. Background Art

[0002] Storage device QoS (Quality-of Service) aims to ensure consistent response time and IOPS (Input / Output Operations Per Second) performance for both read and write requests in a dynamic environment where mixed read and write operations are frequently exchanged. However, when the storage device is tested for mixed read and write operations, the read and write operations are mixed together. Among them, the write operation has more steps and takes a long time to process in the storage device firmware, while the read operation is relatively simple and takes a short time to process in the storage device firmware. At the same time, since the write resources in the storage device firmware are limited, when the mixed read and write pressure is large, the write operation takes a long time, which will cause the write resources to be easily completely occupied by the write operation, and then cause the storage device firmware to stop receiving new read and write commands from the host. Until a write operation is completed and part of the occupied write resources are released, the storage device firmware can receive new read and write commands from the host. Therefore, the delay of the read operation is limited by the delay of the write operation, thereby increasing the waiting time of the read operation on the host side, resulting in a delay "long tail effect".

[0003] Therefore, how to reduce the impact of write operations on read operations in a mixed read-write IO scenario, thereby reducing the waiting time of read operations and optimizing read operation delays, is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] The present application provides a method and storage device for read optimization in a mixed read-write scenario to reduce the impact of the processing time of the write operation on the read operation, thereby reducing the waiting time of the read operation and optimizing the read operation delay.

[0005] In order to solve the above technical problems, this application provides the following technical solutions:

[0006] In a first aspect, the present application provides a method for processing IO commands in a mixed read-write scenario, comprising the following steps: step S210, determining whether the received IO command is a write command; step S220, if the IO command is a write command, checking whether there is sufficient idle write-chip cache to be used to process the write command; step S230, in response to the absence of sufficient idle write-chip cache to be used to process the write command, storing the write command in a write waiting processing resource pool, and continuing to receive new IO commands; step S240, in response to the presence of sufficient idle write-chip cache to be used to process the write command, processing the write command.

[0007] The method for processing IO commands in the read-write hybrid scenario as described above, wherein preferably, step S240 also includes: in response to there being sufficient idle write-chip cache to be used to process the write command, obtaining the write command from the host, and allocating a corresponding size of write-chip cache to the write command to process the write command; or, in response to the write-chip cache being released, if the idle write-chip cache is sufficient to process the write command, obtaining the write command from a write waiting-to-process resource pool, and allocating a corresponding size of write-chip cache to the write command to process the write command.

[0008] The method for processing IO commands in the mixed read-write scenario as described above, wherein, preferably, further includes the following steps: step S250, if the IO command is a read command, checking whether there is idle read-chip cache sufficient to be used to process the read command; step S260, in response to there being no idle read-chip cache sufficient to be used to process the read command, stopping receiving IO commands; step S270, in response to there being idle read-chip cache sufficient to be used to process the read command, processing the read command.

[0009] As described above, the method for processing IO commands in a mixed read-write scenario, wherein preferably, step S270 also includes: in response to there being enough free read-chip cache to be used to process the write command, allocating a corresponding read-chip cache to the read command obtained from the host to process the read command; or, in response to the read-chip cache being released, if the free read-chip cache is sufficient to process the read command, obtaining the read command from the host and allocating a corresponding read-chip cache to the read command to process the read command.

[0010] On the second aspect, the present application also provides a method for processing IO commands in a mixed read-write scenario, including the following steps: step S302, determining whether the received IO command is a write command; step S304, if the IO command is a write command, checking whether the write waiting processing resource pool is empty; step S306, in response to the write waiting processing resource pool being not empty, storing the write command in the write waiting processing resource pool, and continuing to receive new IO commands; step S308, in response to the write waiting processing resource pool being empty, checking whether there is enough idle write-chip cache to be used to process the write command; step S310, in response to the lack of enough idle write-chip cache to be used to process the write command, storing the write command in the write waiting processing resource pool, and continuing to receive new IO commands; step S312, in response to the presence of enough idle write-chip cache to be used to process the write command, applying for a corresponding idle write-chip cache for the write command to process the write command.

[0011] As described above, the method for processing IO commands in a mixed read-write scenario, wherein preferably, step S312 also includes: in response to there being sufficient idle write-chip cache to be used to process the write command, obtaining the write command from the host, and allocating a corresponding size of write-chip cache to the write command to process the write command; or, in response to the write-chip cache being released, if the idle write-chip cache is sufficient to process the write command, obtaining the write command from a write waiting processing resource pool, and allocating a corresponding size of write-chip cache to the write command to process the write command.

[0012] The method for processing IO commands in the read-write mixed scenario as described above, wherein, preferably, further includes the following steps: step S322, checking whether the write waiting processing resource pool is empty; step S324, in response to the write waiting processing resource pool being not empty, checking whether there is idle write-chip cache sufficient to be used to process the write command in the write waiting processing resource pool; step S326, in response to there being idle write-chip cache sufficient to be used to process the write command, obtaining the write command from the write waiting processing resource pool, and allocating a write-chip cache of corresponding size to the write command to process the write command.

[0013] The method for processing IO commands in the mixed read-write scenario as described above, wherein, preferably, further includes the following steps: step S328, if the IO command is a read command, checking whether there is idle read-chip cache sufficient to be used to process the read command; step S330, in response to there being no idle read-chip cache sufficient to be used to process the read command, stopping receiving the IO command; step S332, in response to there being idle read-chip cache sufficient to be used to process the read command, applying for a corresponding idle read-chip cache for the read command to process the read command.

[0014] In a third aspect, the present application also provides a storage device, including: a DRAM, an NVM chip and a control component; the control component executes the processing method of IO commands in the read-write hybrid scenario described in any of the above items.

[0015] The storage device as described above, wherein preferably, the control component includes: a front-end module and a back-end module; wherein the front-end module includes: a data management module; the back-end module includes: a scheduling management module and a flash memory channel controller module; wherein the data management module provides a read / write on-chip cache, and is responsible for decoding and processing host read / write commands to obtain flash memory read / write commands, and sends the flash memory read / write commands to the scheduling management module, the scheduling management module receives the flash memory read / write commands, and sends the flash memory read / write commands to the flash memory channel controller module, and the flash memory channel controller module performs priority scheduling on the flash memory read / write commands and processes them according to the priority. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic diagram of the processing process of the internal IO command of the storage device in the read-write hybrid scenario provided in the first embodiment of the present application;

[0018] Figure 2 It is a flowchart of a method for processing IO commands in a read-write hybrid scenario provided in Embodiment 2 of the present application;

[0019] Figure 3 It is a schematic diagram of the processing process of the internal IO command of the storage device in the read-write hybrid scenario provided in the third embodiment of the present application;

[0020] Figure 4 It is a flowchart of the background processing of write commands in the write waiting processing buffer pool in the read-write hybrid scenario provided by the third embodiment of the present application;

[0021] Figure 5 This is a schematic diagram of the internal logic module of the storage device provided in Example 4 of the present application. DETAILED DESCRIPTION

[0022] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be interpreted as limiting the present invention.

[0023] In view of the fact that the delay of the read command in the above-mentioned read-write hybrid scenario is limited by the delay caused by the write command, the waiting time of the read operation on the host side is reduced. The present application provides a method for processing IO commands in a read-write hybrid scenario. For the IO read-write hybrid command on the host side, the storage device can make a judgment based on the IO command obtained from the host side. If it is a write command, the write command obtained from the host is first stored in the write waiting processing resource pool of the storage device, but it is not in a hurry to process the write command. Instead, it waits until there are enough resources to process the write command, and then processes the write operation on the write command in the write waiting processing resource pool. In this way, the read command after the write command can be received and processed by the storage device in time, thereby reducing the waiting time of the read command on the host side.

[0024] Embodiment 1

[0025] See also Figure 1 , Figure 1It is a schematic diagram of the processing process of the internal IO command of the storage device in the read-write hybrid scenario provided in the first embodiment of the present application;

[0026] The present application provides a method for processing IO commands in a mixed read-write scenario, comprising the following steps:

[0027] Step S102: Determine whether the received IO command is a write command.

[0028] In a mixed read-write scenario, the read commands and write commands sent by the host to the storage device are cross-mixed, so the IO command obtained from the host interface of the storage device (that is, the interface located in the storage device and used to transmit commands between the storage device and the host) may be a read command or a write command. Therefore, it is necessary to determine whether the IO command at the host interface of the storage device is a read command or a write command, so that the read command and the write command are processed differently in subsequent processing.

[0029] Step S104: If the IO command is a write command, check whether there is enough free on-chip write buffer to process the write command.

[0030] When processing a write command, it is not certain whether the idle on-chip write buffer of the current storage device is sufficient for processing the write command. Therefore, it is necessary to check whether the remaining idle on-chip write buffer of the storage device is sufficient for processing the write command.

[0031] Among them, the write-on-chip cache can be DTCM or other cache devices with higher access rates. DTCM (Data TCM) is a type of TCM (Tightly Coupled Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can be placed in DTCM to save access time.

[0032] In this step, it is checked whether there is enough free write-chip cache to be used to process the write command, including the following three situations. In the first situation, there are enough free write-chip caches, and these free write-chip caches are enough to process the write command, that is, these free write-chip caches are larger than the write-chip caches required to process the write command; in the second situation, there are some free write-chip caches, but these free write-chip caches are not enough to process the write command, that is, these free write-chip caches are smaller than the write-chip caches required to process the write command; in the third situation, there is no free write-chip cache.

[0033] Step S106: In response to the fact that there is not enough idle on-chip write buffer to process the write command, stop receiving the IO command.

[0034] If the storage device does not have enough free on-chip write cache to process the write command, the second and third situations mentioned above will occur, so the write command cannot be processed temporarily. Therefore, the write command is still stored at the host interface, waiting for processing until there is enough free on-chip write cache in the storage device to be used to process the write command.

[0035] Step S108: In response to there being enough idle on-chip write cache to be used for processing the write command, applying for a corresponding idle on-chip write cache for the write command to process the write command.

[0036] In this step, if the free on-chip write cache of the storage device is sufficient to process the write command, and the free on-chip write cache is larger than the on-chip write cache required to process the write command, that is, the first situation mentioned above occurs, the write command is obtained from the host interface of the storage device, and a corresponding size of on-chip write cache is allocated to the write command to process the write command.

[0037] Alternatively, as the on-chip write cache is released, the free on-chip write cache of the storage device increases, so that the free on-chip write cache of the storage device is sufficient to process the write command. These free on-chip write caches are larger than the on-chip write cache required to process the write command. This is the first case mentioned above. In this case, the write command is obtained from the host interface, and a corresponding size of on-chip write cache is allocated to the write command to process the write command.

[0038] Step S110: Apply for a corresponding off-chip flash memory for the write command, so as to write the data indicated by the write command into the applied off-chip flash memory during the process of processing the write command.

[0039] In addition, an off-chip flash memory (DRAM, dynamic random access memory) of a corresponding size is applied for the write command, and the data indicated by the write command is written to the applied off-chip flash memory during the process of processing the write command by the write-chip cache of the storage device. Optionally, the data indicated by the write command is written to the off-chip flash memory applied for the write command through DMA (Direct Memory Access).

[0040] Step S112: Allocate an NVM chip address to the data indicated by the write command, and write the data indicated by the write command from the off-chip flash memory to the NVM chip according to the NVM chip address.

[0041] A corresponding NVM (non-volatile memory) chip address is also assigned to the data indicated by the write command, and then the data indicated by the write command is obtained from the off-chip flash memory, and the data indicated by the write command is moved from the off-chip flash memory to the location indicated by the NVM chip address in the NVM chip.

[0042] Step S114: Record the allocated NVM chip address into the FTL table to update the FTL table.

[0043] After the data indicated by the write command is completely moved to the NVM chip, the NVM chip address assigned to the data indicated by the write command is recorded in the FTL table, and the logical address of the write command is also recorded in the FTL table, so that the NVM chip address and the logical address of the data indicated by the write command form a mapping relationship in the FTL table, thereby updating the FTL table.

[0044] Step S116: Send a write completion message to the host and release the write on-chip buffer occupied by the write command.

[0045] After the data indexed by the write command is completely written to the NVM chip, the storage device sends a write completion message to the host, indicating that the write command has been processed, and also releases the write-on-chip cache occupied by the write command, and can also release the off-chip cache occupied by the write command.

[0046] On the basis of the above, the following steps S118 to S128 are also included:

[0047] Step S118: If the IO command is a read command, check whether there is enough idle on-chip read cache to process the read command.

[0048] If it is determined that the IO command is a read command, check whether there is enough idle on-chip read cache in the storage device to process the read command, wherein the on-chip read cache can also be DTCM or other cache devices with higher access rates. DTCM (DataTCM) is a type of TCM (Tightly Coupled Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can be placed in DTCM to save access time.

[0049] In this step, it is checked whether there is enough idle read-chip cache to be used to process the read command, including the following three situations. In the first situation, there are enough idle read-chip caches, and these idle read-chip caches are enough to process the read command, that is, these idle read-chip caches are larger than the read-chip caches required to process the read command; in the second situation, there are some idle read-chip caches, but these idle read-chip caches are not enough to process the read command, that is, these idle read-chip caches are smaller than the read-chip caches required to process the read command; in the third situation, there is no idle read-chip cache.

[0050] Step S120 : In response to the fact that there is not enough idle on-chip read cache to process the read command, stop receiving the IO command.

[0051] If the free on-chip cache in the storage device is smaller than the on-chip cache required to process the read command, that is, the second situation mentioned above occurs, it means that the free on-chip cache in the storage device is not enough to process the read command, so the read command cannot be processed temporarily; if there is no free on-chip cache in the storage device, that is, the third situation mentioned above occurs, it means that the read command cannot be processed temporarily. Therefore, if there is not enough free on-chip cache in the storage device to process the read command, the IO command is stopped from being received from the host interface of the storage device, and the read command is still placed at the host interface of the storage device, waiting for processing until there is enough free on-chip cache in the storage device to be used to process the read command.

[0052] Step S122: In response to there being an idle on-chip read cache that can be used to process the read command, applying for a corresponding idle on-chip read cache for the read command to process the read command.

[0053] If the free on-chip read cache of the storage device is sufficient to process the write command, and the free on-chip read cache is larger than the on-chip read cache required to process the read command, that is, the first situation mentioned above occurs, the read command is obtained from the host interface, and the corresponding on-chip read cache is allocated for the read command to process the read command.

[0054] Alternatively, as the on-chip read cache is released, the free on-chip read cache of the storage device increases, so that the free on-chip read cache of the storage device is sufficient to process the read command. These free on-chip read caches are larger than the on-chip read cache required to process the read command, which is the first situation mentioned above. In this case, the read command is obtained from the host interface of the storage device, and the corresponding on-chip read cache is allocated to the read command to process the read command.

[0055] Step S124: During processing of the read command, the NVM chip address indicated by the read command is read from the FTL table.

[0056] According to the logic address indicated by the read command, an NVM chip address having a mapping relationship with the logic address is queried from the FTL table, so as to read the data indicated by the read command from the NVM chip according to the NVM chip address.

[0057] Step S126: Read the data indicated by the read command from the NVM chip according to the NVM chip address, and send the data to the host.

[0058] According to the obtained NVM chip address, the data indicated by the read command is read from the NVM chip, and the read data is sent to the host in response to the read command.

[0059] Step S128: Send a read completion message to the host and release the on-chip read cache occupied by the read command.

[0060] After sending the data indexed by the read command to the host, the storage device sends a read completion message to the host, indicating that the read command has been processed and also releases the read chip cache occupied by the read command to facilitate subsequent processing of the read command.

[0061] Embodiment 2

[0062] See also Figure 2 , Figure 2 It is a flowchart of a method for processing IO commands in a mixed read-write scenario provided in Example 2 of the present application.

[0063] The present application provides a method for processing IO commands in a mixed read-write scenario, comprising the following steps:

[0064] Step S210: Determine whether the received IO command is a write command.

[0065] The read and write commands sent from the host to the storage device are cross-mixed, so the IO command obtained from the host interface of the storage device (that is, the interface located in the storage device and used for command transmission between the storage device and the host) may be a read command or a write command. Therefore, it is necessary to determine whether the IO command at the host interface of the storage device is a read command or a write command, so that the read command and the write command are processed in different ways in subsequent processing.

[0066] Step S220: If the IO command is a write command, check whether there is enough free on-chip write cache to process the write command.

[0067] If it is determined that the IO command is a write command, check whether there is enough idle on-chip write cache in the storage device to process the write command, wherein the on-chip write cache can be DTCM or other cache devices with higher access rate. DTCM (DataTCM) is a type of TCM (T i ghtly Coup led Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can be placed in DTCM to save access time.

[0068] In this step, it is checked whether there is enough free write-chip cache to be used to process the write command, including the following three situations. In the first situation, there are enough free write-chip caches, and these free write-chip caches are enough to process the write command, that is, these free write-chip caches are larger than the write-chip caches required to process the write command; in the second situation, there are some free write-chip caches, but these free write-chip caches are not enough to process the write command, that is, these free write-chip caches are smaller than the write-chip caches required to process the write command; in the third situation, there is no free write-chip cache.

[0069] Step S230: In response to the fact that there is not enough idle write-chip cache to process the write command, the write command is stored in a write waiting-to-be-processed resource pool.

[0070] If the free on-chip write cache in the storage device is smaller than the on-chip write cache required to process the write command, that is, the second situation mentioned above occurs, it means that the free on-chip write cache in the storage device is insufficient to process the write command, so the write command cannot be processed temporarily; if there is no free on-chip write cache in the storage device, that is, the third situation mentioned above occurs, it means that the write command cannot be processed temporarily.

[0071] The write command cannot be processed temporarily, which means that the write command still needs to exist in the host interface. Since the read and write commands sent to the host interface of the storage device by the host end are cross-mixed, the read command that the host has submitted to the host interface of the storage device and is located after the write command is always waiting in the host interface and cannot be read and processed in time. The steps for processing a write command are more than those for processing a read command, and the processing time in the firmware of the storage device is longer, the occupied write-chip cache is larger, and the release speed of the write-chip cache is also slower. Therefore, the write command is always waiting in the host interface of the storage device, resulting in the delay of the read command at the storage device end being affected by the write-chip cache released by the write command. Therefore, the read command waits for a long time to be processed, and the processing delay of the read command is increased.

[0072] In order to avoid the delay of the read command caused by the write command that cannot be processed temporarily existing in the host interface and affecting the subsequent reading command processing, the write command is taken out from the host interface of the storage device and temporarily stored in the write waiting processing resource pool of the storage device, so that the write command can be moved from the host interface of the storage device in time, thereby avoiding the delay of the subsequent reading command processing caused by the write command that cannot be processed temporarily in the host interface.

[0073] Among them, the write waiting processing resource pool of the storage device can be an idle write-chip cache of the storage device. Since only the write command is temporarily stored and the data indicated by the write command is not stored, the space resources used for temporarily storing the write command are relatively small, especially compared with the space resources used to process the write command. Therefore, even if the remaining idle write-chip cache in the storage device is smaller than the write-chip cache required to process the write command, many write commands can still be temporarily stored in the idle write-chip cache. Therefore, the write waiting processing resource pool can be an idle write-chip cache; the write waiting processing resource pool of the storage device can also be another storage resource of the storage device, which is different from the write-chip cache in the storage device and is a different component from the write-chip cache in the storage device.

[0074] Step S240: In response to there being enough idle on-chip write cache to be used for processing the write command, process the write command.

[0075] If the free on-chip write cache of the storage device is sufficient to process the write command, and the free on-chip write cache is larger than the on-chip write cache required to process the write command, that is, the first situation mentioned above occurs, the write command is obtained from the host interface, and a corresponding size of on-chip write cache is allocated to the write command to process the write command.

[0076] Alternatively, as the write-chip cache is released, the free write-chip cache of the storage device increases, so that the free write-chip cache of the storage device is sufficient to process the write command. These free write-chip caches are larger than the write-chip cache required to process the write command, which is the first situation mentioned above. In this case, the write command is obtained from the write waiting processing resource pool of the storage device, and a write-chip cache of corresponding size is allocated to the write command to process the write command.

[0077] On the basis of the above, the following steps S250 to S270 are also included:

[0078] Step S250: If the IO command is a read command, check whether there is enough idle on-chip read cache to process the read command.

[0079] If it is determined that the IO command is a read command, check whether there is enough idle on-chip read cache in the storage device to process the read command, wherein the on-chip read cache can also be DTCM or other cache devices with higher access rates. DTCM (DataTCM) is a type of TCM (Tightly Coupled Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can be placed in DTCM to save access time.

[0080] In this step, it is checked whether there is enough idle read-chip cache to be used to process the read command, including the following three situations. In the first situation, there are enough idle read-chip caches, and these idle read-chip caches are enough to process the read command, that is, these idle read-chip caches are larger than the read-chip caches required to process the read command; in the second situation, there are some idle read-chip caches, but these idle read-chip caches are not enough to process the read command, that is, these idle read-chip caches are smaller than the read-chip caches required to process the read command; in the third situation, there is no idle read-chip cache.

[0081] Step S260 : In response to the fact that there is not enough idle on-chip read cache to process the read command, stop receiving the IO command.

[0082] If the free on-chip read cache in the storage device is smaller than the on-chip read cache required to process the read command, that is, the second situation mentioned above occurs, it means that the free on-chip read cache in the storage device is insufficient to process the read command, so the read command cannot be processed temporarily; if there is no free on-chip read cache in the storage device, that is, the third situation mentioned above occurs, it means that the read command cannot be processed temporarily.

[0083] Since the steps for processing a read command are fewer than those for processing a write command, the processing time in the firmware of the storage device is shorter, the occupied read resources are smaller, and the release speed of the read-chip cache is also faster. Therefore, the read command in the host interface of the storage device will not cause delays in the processing of the write command in the host interface. Therefore, if the storage device does not have enough free read-chip cache to process the read command, the storage device stops receiving IO commands from the host interface of the storage device, and still places the read command at the host interface of the storage device, waiting for processing until there is enough free read-chip cache in the storage device that can be used to process the read command.

[0084] Step S270: In response to there being enough idle on-chip read cache to be used for processing the read command, process the read command.

[0085] If the free on-chip read cache of the storage device is sufficient to process the write command, and these free on-chip read caches are larger than the on-chip read caches required to process the read command, that is, the first situation mentioned above occurs, the read command is obtained from the host interface, and the corresponding on-chip read cache is allocated to the read command, so as to process the read command; or as the on-chip read cache is released, the free on-chip read cache of the storage device increases, so that the free on-chip read cache of the storage device is sufficient to process the read command, and these free on-chip read caches are larger than the on-chip read caches required to process the read command, which is also the first situation mentioned above, the read command is obtained from the host interface of the storage device, and the corresponding on-chip read cache is allocated to the read command, so as to process the read command.

[0086] Embodiment 3

[0087] See also Figure 3 , Figure 3 This is a schematic diagram of the processing process of the internal IO commands of the storage device in the read-write hybrid scenario provided in Example 3 of the present application.

[0088] The present application provides a method for processing IO commands in a mixed read-write scenario, comprising the following steps:

[0089] Step S302: Determine whether the received IO command is a write command.

[0090] In a mixed read-write scenario, the read commands and write commands sent by the host to the storage device are cross-mixed, so the IO command obtained from the host interface of the storage device (that is, the interface located in the storage device for command transmission between the storage device and the host) may be a read command or a write command. Therefore, it is necessary to determine whether the IO command at the host interface of the storage device is a read command or a write command, so that the read command and the write command are processed in different ways in subsequent processing.

[0091] Step S304: If the IO command is a write command, check whether the write waiting processing resource pool is empty.

[0092] If it is determined that the IO command is a write command, check whether the write waiting processing resource pool of the storage device is empty. If the write waiting processing resource pool is empty, no write command is stored in the write waiting processing resource pool, which means that the storage device has enough free write-chip cache to process the write command before. If the write waiting processing resource pool is not empty, write commands have been stored in the write waiting processing resource pool, which means that the storage device does not have enough free write-chip cache to process the write command before.

[0093] Step S306: In response to the write waiting processing resource pool being not empty, the write command is stored in the write waiting processing resource pool.

[0094] If it is checked that a write command has been stored in the write waiting processing resource pool, that is, the write waiting processing resource pool is not empty, which means that the storage device does not have enough idle write-chip cache to process the write command before, the write command will be temporarily stored in the write waiting processing resource pool of the storage device, so that the write command can be moved from the host interface of the storage device in time, avoiding the write command waiting in the host interface and causing the read command to be affected by the write-chip cache released by the write command. The delay on the storage device side is avoided, thereby avoiding the read command waiting for too long, and further avoiding increasing the processing delay of the read command.

[0095] Step S308: In response to the write waiting processing resource pool being empty, check whether there is enough idle write on-chip cache to process the write command.

[0096] If it is checked that no write command is stored in the write waiting processing resource pool, that is, the write waiting processing resource pool is empty, this means that before this, the storage device has enough free write-chip cache to process the write command. However, for this write command, it is not yet certain whether the current free write-chip cache of the storage device is sufficient to process the write command. Therefore, in this case, it is necessary to check whether the remaining free write-chip cache in the storage device is sufficient to process the write command.

[0097] Among them, the write-on-chip cache can be DTCM or other cache devices with higher access rates. DTCM (Data TCM) is a type of TCM (Tightly Coupled Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can be placed in DTCM to save access time.

[0098] In this step, it is checked whether there is enough free write-chip cache to be used to process the write command, including the following three situations. In the first situation, there are enough free write-chip caches, and these free write-chip caches are enough to process the write command, that is, these free write-chip caches are larger than the write-chip caches required to process the write command; in the second situation, there are some free write-chip caches, but these free write-chip caches are not enough to process the write command, that is, these free write-chip caches are smaller than the write-chip caches required to process the write command; in the third situation, there is no free write-chip cache.

[0099] Step S310: In response to the fact that there is not enough idle write-chip cache to process the write command, the write command is stored in a write waiting-to-be-processed resource pool.

[0100] If the free on-chip write cache in the storage device is smaller than the on-chip write cache required to process the write command, that is, the second situation mentioned above occurs, then it means that the free on-chip write cache in the storage device is insufficient to process the write command, so the write command cannot be processed temporarily; if there is no free on-chip write cache in the storage device, that is, the third situation mentioned above occurs, then it means that the write command cannot be processed temporarily.

[0101] The write command cannot be processed temporarily, which means that the write command still needs to exist in the host interface of the storage device. Since the read and write commands sent to the host interface of the storage device by the host are cross-mixed, the read command that the host has submitted to the host interface and is located after the write command is always waiting in the host interface and cannot be read and processed in time. The steps for processing a write command are more than those for processing a read command, and the processing time in the firmware of the storage device is longer, the occupied write resources are larger, and the release speed of the write resources is also slower. Therefore, the write command is always waiting in the host interface, resulting in the delay of the read command on the storage device side being affected by the write-chip cache released by the write command. Therefore, the read command waits for a long time to be processed, and the processing delay of the read command is increased.

[0102] In order to avoid the write command that cannot be processed temporarily existing in the host interface of the storage device affecting the processing of subsequent read commands and causing delays in the read commands, the write command is temporarily stored in the write waiting processing resource pool of the storage device, so that the write command can be moved from the host interface in time, thereby avoiding the write command that cannot be processed temporarily affecting the processing of subsequent read commands in the host interface.

[0103] Among them, the write waiting processing resource pool of the storage device can be an idle on-chip write cache of the storage device. Since only the write command is temporarily stored and the data indicated by the write command is not stored, the space resources used for temporarily storing the write command are relatively small, especially compared with the space resources used to process the write command. Therefore, even if the remaining idle on-chip write cache in the storage device is smaller than the on-chip write cache required to process the write command, many write commands can still be temporarily stored in the idle on-chip write cache. Therefore, the write waiting processing resource pool can be an idle on-chip write cache; the write waiting processing resource pool of the storage device can also be another storage resource of the storage device, which is different from the on-chip write cache of the storage device and is a different component from the on-chip write cache of the storage device.

[0104] Step S312: In response to there being enough idle on-chip write cache to be used for processing the write command, apply for a corresponding idle on-chip write cache for the write command to process the write command.

[0105] If the free on-chip write cache of the storage device is sufficient to process the write command, and the free on-chip write cache is larger than the on-chip write cache required to process the write command, that is, the first situation mentioned above occurs, the write command is obtained from the host interface, and a corresponding size of on-chip write cache is allocated to the write command to process the write command.

[0106] Alternatively, as the write-chip cache is released, the free write-chip cache of the storage device increases, so that the free write-chip cache of the storage device is sufficient to process the write command. These free write-chip caches are larger than the write-chip cache required to process the write command, which is the first situation mentioned above. In this case, the write command is obtained from the write waiting processing resource pool of the storage device, and a write-chip cache of corresponding size is allocated to the write command to process the write command.

[0107] Step S314: Apply for a corresponding off-chip flash memory for the write command, so as to write the data indicated by the command into the applied off-chip flash memory during the process of processing the write command.

[0108] In addition, an off-chip flash memory (DRAM, dynamic random access memory) of a corresponding size is applied for the write command, and the data indicated by the write command is written to the applied off-chip flash memory during the process of processing the write command by the write-chip cache of the storage device. Optionally, the data indicated by the write command is written to the off-chip flash memory applied for the write command through DMA (Direct Memory Access).

[0109] Step S316: Allocate an NVM chip address for the data indicated by the write command, and write the data indicated by the write command from the off-chip flash memory to the NVM chip according to the NVM chip address.

[0110] A corresponding NVM (non-volatile memory) chip address is also assigned to the data indicated by the write command, and then the data indicated by the write command is obtained from the off-chip flash memory, and the data indicated by the write command is moved from the off-chip flash memory to the location indicated by the NVM chip address in the NVM chip.

[0111] Step S318: Record the allocated NVM chip address into the FTL table to update the FTL table.

[0112] After the data indicated by the write command is completely moved to the NVM chip, the NVM chip address assigned to the data indicated by the write command is recorded in the FTL table, and the logical address of the write command is also recorded in the FTL table, so that the NVM chip address and the logical address of the data indicated by the write command form a mapping relationship in the FTL table, thereby updating the FTL table.

[0113] Step S320: Send a write completion message to the host and release the write on-chip cache occupied by the write command.

[0114] After the data indexed by the write command is completely written to the NVM chip, the storage device sends a write completion message to the host, indicating that the write command has been processed, and also releases the write-on-chip cache occupied by the write command, and can also release the off-chip cache occupied by the write command.

[0115] See also Figure 4 , Figure 4 This is a flowchart of the background processing of write commands in the write waiting processing buffer pool in the read-write hybrid scenario provided by Example 3 of the present application.

[0116] Based on the above, the background processing writes the write command in the waiting processing buffer pool, and further includes the following steps:

[0117] Step S322: Check whether the write waiting resource pool is empty.

[0118] Check whether the write waiting processing resource pool of the storage device is empty. If the write waiting processing resource pool is empty, no write command is stored in the write waiting processing resource pool. If the write waiting processing resource pool is not empty, write commands are already stored in the write waiting processing resource pool. Then, write commands can be obtained from the write waiting processing resource pool for processing later.

[0119] Step S324: In response to the write waiting processing resource pool being not empty, check whether there is idle write on-chip cache sufficient to be used to process the write commands in the write waiting processing resource pool.

[0120] If it is checked that there is already a write command stored in the write waiting processing resource pool, that is, the write waiting processing resource pool is not empty, and when there is sufficient write-chip cache later, the write command can be obtained from the write waiting processing resource pool for processing. Therefore, it is necessary to check whether the remaining free write-chip cache in the storage device is sufficient to process the write command.

[0121] Check whether there is enough free write-chip cache to be used to process the write command in the write waiting resource pool, including the following three situations. In the first situation, there are enough free write-chip caches, and these free write-chip caches are enough to process the write command, that is, these free write-chip caches are larger than the write-chip caches required to process the write command; in the second situation, there are some free write-chip caches, but these free write-chip caches are not enough to process the write command, that is, these free write-chip caches are smaller than the write-chip caches required to process the write command; in the third situation, there is no free write-chip cache.

[0122] Step S326: In response to there being enough idle on-chip write cache to process the write command, the write command is obtained from the write waiting resource pool, and an on-chip write cache of a corresponding size is allocated to the write command to process the write command.

[0123] If the free on-chip write cache of the storage device is sufficient to process the write command, and the free on-chip write cache is larger than the on-chip write cache required to process the write command, that is, the first situation mentioned above occurs, the write command is obtained from the write waiting processing resource pool of the storage device, and a write-chip cache of corresponding size is allocated to the write command to process the write command.

[0124] Step S314: Apply for a corresponding off-chip flash memory for the write command, so that the data indicated by the command is written to the applied off-chip flash memory during the process of processing the write command.

[0125] In addition, an off-chip flash memory (DRAM, dynamic random access memory) of a corresponding size is applied for the write command, and the data indicated by the write command is written to the applied off-chip flash memory during the process of processing the write command by the on-chip cache of the storage device. Optionally, the data indicated by the write command is written to the applied off-chip flash memory by DMA write.

[0126] Step S316: Allocate an NVM chip address for the data indicated by the write command, and write the data indicated by the write command from the off-chip flash memory to the NVM chip according to the NVM chip address.

[0127] A corresponding NVM (non-volatile memory) chip address is also assigned to the data indicated by the write command, and then the data indicated by the write command is obtained from the off-chip flash memory, and the data indicated by the write command is moved from the off-chip flash memory to the location indicated by the NVM chip address in the NVM chip.

[0128] Step S318: Record the allocated NVM chip address into the FTL table to update the FTL table.

[0129] After the data indicated by the write command is completely moved to the NVM chip, the NVM chip address assigned to the data indicated by the write command is recorded in the FTL table, and the logical address of the write command is also recorded in the FTL table, so that the NVM chip address and the logical address of the data indicated by the write command form a mapping relationship in the FTL table, thereby updating the FTL table.

[0130] Step S320: Send a write completion message to the host and release the write on-chip cache occupied by the write command.

[0131] After the data indexed by the write command is completely written to the NVM chip, the storage device sends a write completion message to the host, indicating that the write command has been processed. In addition, the write on-chip cache occupied by the write command is released, the off-chip cache occupied by the write command is also released, and the space occupied by the write command in the write waiting processing resource pool is also released.

[0132] Please continue reading Figure 3 On the basis of the above, the following steps S328 to S338 are also included:

[0133] Step S328: If the IO command is a read command, check whether there is enough idle on-chip read cache to process the read command.

[0134] If it is determined that the IO command is a read command, check whether there is enough idle on-chip read cache in the storage device to process the read command, wherein the on-chip read cache can also be DTCM or other cache devices with higher access rates. DTCM (DataTCM) is a type of TCM (Tightly Coupled Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can be placed in DTCM to save access time.

[0135] Check whether there is enough free read-chip cache to be used to process the read command, including the following three situations. In the first situation, there are enough free read-chip caches, and these free read-chip caches are enough to process the read command, that is, these free read-chip caches are larger than the read-chip caches required to process the read command; in the second situation, there are some free read-chip caches, but these free read-chip caches are not enough to process the read command, that is, these free read-chip caches are smaller than the read-chip caches required to process the read command; in the third situation, there is no free read-chip cache.

[0136] Step S330 : In response to the fact that there is not enough idle on-chip read cache to process the read command, stop receiving the IO command.

[0137] If the free read-chip cache in the storage device is smaller than the read-chip cache required to process the read command, that is, the second situation mentioned above occurs, it means that the free read-chip cache in the storage device is insufficient to process the read command, so the read command cannot be processed temporarily; if there is no free read-chip cache in the storage device, that is, the third situation mentioned above occurs, it means that the read command cannot be processed temporarily.

[0138] Since the steps for processing a read command are fewer than those for processing a write command, the processing time in the firmware of the storage device is shorter, the occupied read resources are smaller, and the release speed of the read-chip cache is also faster. Therefore, the read command in the host interface of the storage device will not cause delays in the processing of the write command in the host interface. Therefore, if the storage device does not have enough idle read-chip cache to process the read command, it will stop receiving IO commands from the host interface of the storage device, and still place the read command at the host interface of the storage device, waiting for processing.

[0139] Step S332: In response to there being enough idle on-chip read cache to be used for processing the read command, apply for a corresponding idle on-chip read cache for the read command to process the read command.

[0140] If the free on-chip read cache of the storage device is sufficient to process the write command, and the free on-chip read cache is larger than the on-chip read cache required to process the read command, that is, the first situation mentioned above occurs, the read command is obtained from the host interface, and the corresponding on-chip read cache is allocated for the read command to process the read command.

[0141] Alternatively, as the on-chip read cache is released, the free on-chip read cache of the storage device increases, so that the free on-chip read cache of the storage device is sufficient to process the read command. These free on-chip read caches are larger than the on-chip read cache required to process the read command, which is the first situation mentioned above. In this case, the read command is obtained from the host interface of the storage device, and the corresponding on-chip read cache is allocated to the read command to process the read command.

[0142] Step S334: During processing of the read command, the NVM chip address indicated by the read command is read from the FTL table.

[0143] According to the logic address indicated by the read command, an NVM chip address having a mapping relationship with the logic address is queried from the FTL table, so as to read the data indicated by the read command from the NVM chip according to the NVM chip address.

[0144] Step S336: Read the data indicated by the read command from the NVM chip according to the NVM chip address, and send the data to the host.

[0145] According to the obtained NVM chip address, the data indicated by the read command is read from the NVM chip, and the read data is sent to the host in response to the read command.

[0146] Step S338: Send a read completion message to the host and release the read on-chip cache occupied by the read command.

[0147] After sending the data indexed by the read command to the host, the storage device sends a read completion message to the host, indicating that the read command has been processed and also releases the read chip cache occupied by the read command to facilitate subsequent processing of the read command.

[0148] By using the method provided in this embodiment, by caching the write command on the storage device side, the read command from the host can be received and processed as early as possible, avoiding the increased delay caused by long waiting time for the read command. Since the read and write resource pools inside the firmware are separate, when the read and write mixed test is performed, when the write command being processed by the firmware has reached the upper limit, it does not affect the reception of the read command, and the read command delay is as short as possible. The read delay is only related to the processing of the read command itself and is not affected by the write command processing. In addition, in a high-load mixed read and write scenario, by effectively managing resources and optimizing the data processing process, the long tail effect of the read delay can be eliminated or reduced, thereby providing stable and predictable storage performance.

[0149] Embodiment 4

[0150] See also Figure 5 , Figure 5 This is a schematic diagram of the internal logic module of the storage device provided in Example 4 of the present application.

[0151] The present application provides a storage device 500, including: a DRAM 510, an NVM chip 520 and a control component 530; wherein the control component 530 executes the method for processing IO commands in the read-write hybrid scenario described in any one of the above-mentioned embodiments 1 to 3.

[0152] Among them, the control component 530 includes: a front-end module 531 and a back-end module 533; the front-end module 531 includes: a DM (Data Manager) module 5313; the back-end module 533 includes: an SM (Schedule Manager) module 5331 and an FCC (Flash Channel Core) module 5332.

[0153] The DM module 5313 provides read / write on-chip cache, and is responsible for decoding and processing host read / write commands to obtain flash read / write commands, and sends flash read / write commands to the SM module 5331. The SM module 5331 receives the flash read / write commands and sends the flash read / write commands to the FCC module 5332. The FCC module 5332 prioritizes the flash read / write commands and processes them according to the priority.

[0154] Specifically, the processing of the read command is as follows:

[0155] After receiving a read command from the host interface of the storage device, the DM module 5313 checks whether there is any idle on-chip read cache. If there is no idle on-chip read cache used to process the read command, the read command is stored at the host interface. If there is an idle on-chip read cache used to process the read command, a corresponding idle on-chip read cache is applied for the read command, the FTL table is read from the off-chip flash memory, the NVM chip address indicated by the read command is obtained, and the flash memory read command is sent to the SM module 5331.

[0156] The SM module 5331 sends the flash memory read command to the FCC module 5332. The FCC module 5332 schedules the flash memory read command according to the priority and performs read processing according to the priority.

[0157] After the read process is completed, the FCC module 5332 returns a read completion message to the SM module 5331, the SM module 5331 returns a read completion message to the DM module 5313, the DM module 5313 returns a read completion message to the host and releases the read on-chip cache.

[0158] Specifically, the processing of write commands is as follows:

[0159] After receiving a write command from the host interface of the storage device, the DM module 5313 checks whether there is any free on-chip write cache. If there is no free on-chip write cache used to process the write command, the write command is placed in a write waiting processing resource pool. If there is any free on-chip write cache used to process the write command, a corresponding free on-chip write cache is applied for the write command, a corresponding off-chip flash memory is applied for the write command, the data indicated by the command is written to the off-chip flash memory, an NVM chip address is assigned to the data indicated by the write command, and a flash memory write command is sent to the SM module 5331.

[0160] The SM module 5331 sends the flash memory write command to the FCC module 5332, and the FCC module 5332 performs priority scheduling on the flash memory write command and performs write processing according to the priority.

[0161] After the write process is completed, the FCC module 5332 returns a write completion message to the SM module 5331, and the SM module 5331 returns a write completion message to the DM module 5313. The DM module 5313 updates the FTL table, releases the write on-chip cache, and returns a write completion message to the host.

[0162] Since read and write commands need to handle various scenarios, the read-chip buffer allocated when processing read and write commands is larger than the size of the read and write commands received from the host. The read-chip buffer that can be allocated when processing read and write commands is limited, so the number of read and write commands being processed inside the DM module 5313 is limited, and not all read commands sent by the queried host interface can be taken to the DM module 5313 for processing. Although some read commands can be queried by the DM module 5313, they can only be placed in the host interface waiting for processing, and cannot be taken out for processing.

[0163] Both the read-on-chip cache and the write-on-chip cache are on-chip caches. The on-chip cache can be DTCM or other cache devices with higher access rates. DTCM (Data TCM) is a type of TCM (Ti ghtly Coup led Memory, a high-speed cache) that can be directly integrated into the CPU chip. DTCM is the data transmission bus in the cortex core. Data that needs to be accessed frequently can also be placed in DTCM to save access time.

[0164] In addition, the front-end module 531 also includes: a PCIe module 5311 and an Admin management module 5312. The PCIe module 5311 is responsible for processing PCIe events, and the Admin management module 5312 is responsible for executing NVMe Admin management commands.

[0165] The control component 530 further includes: an FTL module 532; the FTL module 532 further includes: a GC (Garbege Collection) module 5321 and a JM (Journey Manager) module 5322. The GC module 5321 is used to effectively manage and recycle all non-volatile memory resources, such as on-chip flash memory, off-chip flash memory, NVM chip, etc.; the JM (Journey Manager) module 5322 is used to record logs during read and write operations.

[0166] See also Figure 1 and Figure 3, use the FIO tool to test the storage device, and output clat to represent completion latency, which refers to the time from submitting the IO command to the kernel to the completion of the IO command. The clat latency includes host-side latency and storage device-side latency. The host-side latency is the time it takes for the IO command to be submitted to the storage device for processing. The storage device-side latency is the time it takes for the host to send the IO command to the host interface of the storage device to the completion of the IO command. The storage device-side latency consists of two parts, namely the time it takes for the IO command to be at the host interface of the storage device (time interval A) + the time it takes for the storage device to receive the IO command to complete the IO command (time interval B).

[0167] During the experiment, we found that the longest time interval B in the storage device is m microseconds, but the longest observed clat delay is still very long compared to m microseconds. This is the long tail phenomenon of QoS. After adding time statistics on the storage device side, we found that in the mixed read-write scenario, write commands are received on the storage device side, and write resources (on-chip cache) need to be occupied on the firmware side to process these write commands. When all write resources are occupied, the storage device will not take new commands from the host interface, which will cause a longer delay in time interval A.

[0168] The latency at the storage device end consists of two parts, namely, the time it takes for the IO command to be sent to the host interface of the storage device (time interval A) + the time it takes for the storage device to receive the IO command and complete the IO command (time interval B). Sometimes, the command sequence found is (write command 1, write command 2, read command), the first of which is a write command. In previous solutions, write resources (on-chip cache) (free resources that can process write commands) are required to process the write command, which results in the read command behind the write command in the host interface being blocked, that is, the read command ranked third cannot be processed, and can only be processed if the previous write command is received by the storage device.

[0169] Since the read and write commands sent by the host end to the host interface of the storage device are cross-mixed, the read command has been waiting at the host interface, resulting in the read command submitted by the host not being taken to the storage device for processing in time, causing the delay of the read command at the host end to be affected by the release of the write command resources (on-chip cache) (that is, the storage device delay of the write command), so the read command waits for a long time. Therefore, the write command submitted by the host is taken from the host interface to the on-chip cache of the storage device (only the cache area of ​​the write command is cached, and the data of the write command is not cached) and stored, without processing, and will be processed after there are write resources (on-chip cache), so that the read command submitted by the host end will not be blocked.

[0170] Based on the above, in a mixed read-write scenario, read commands interspersed among multiple write commands can use corresponding read resources to process read data as early as possible on the firmware side, and the processing of read commands will not be delayed due to resource occupation of processing write commands, thereby reducing the delay in read command processing.

[0171] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0172] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for processing IO commands in a mixed read-write scenario, characterized in that: The steps include: Step S210, determining whether the received IO command is a write command; Step S220: If the IO command is a write command, check whether there is enough free write on-chip cache to process the write command. Step S230: In response to the fact that there is not enough idle write-chip cache to process the write command, the write command is stored in a write waiting-to-process resource pool, and new IO commands continue to be received; Step S240: In response to there being enough idle on-chip write cache to be used for processing the write command, process the write command.

2. The method for processing IO commands in a read-write hybrid scenario according to claim 1, characterized in that: Step S240 also includes: In response to there being enough idle on-chip write buffer to be used for processing the write command, acquiring the write command from the host, and allocating a corresponding size of the on-chip write buffer to the write command to process the write command; Alternatively, in response to the write-on-chip cache being released, if the free write-on-chip cache is sufficient to process the write command, the write command is obtained from the write waiting resource pool, and a write-on-chip cache of a corresponding size is allocated to the write command to process the write command.

3. The method for processing IO commands in a read-write hybrid scenario according to claim 1 or 2, characterized in that: The following steps are also included: Step S250: If the IO command is a read command, check whether there is enough idle on-chip read cache to process the read command; Step S260: In response to the fact that there is not enough idle on-chip read cache to process the read command, stop receiving the IO command; Step S270: In response to there being enough idle on-chip read cache to be used for processing the read command, the read command is processed.

4. The method for processing IO commands in a read-write hybrid scenario according to claim 3, characterized in that: Step S270 also includes: In response to there being enough idle on-chip read cache to be used for processing the write command, allocating a corresponding on-chip read cache to the read command obtained from the host to process the read command; Alternatively, in response to the read on-chip cache being released, if the free read on-chip cache is sufficient to process the read command, the read command is obtained from the host, and a corresponding read on-chip cache is allocated to the read command to process the read command.

5. A method for processing IO commands in a mixed read-write scenario, characterized in that: The steps include: Step S302: determine whether the received IO command is a write command; Step S304: If the IO command is a write command, check whether the write waiting resource pool is empty; Step S306: In response to the write waiting processing resource pool being not empty, the write command is stored in the write waiting processing resource pool, and new IO commands continue to be received; Step S308: In response to the write waiting processing resource pool being empty, checking whether there is idle write on-chip cache sufficient to be used to process the write command; Step S310: In response to the fact that there is not enough idle write-chip cache to process the write command, the write command is stored in a write waiting-to-process resource pool, and new IO commands continue to be received; Step S312: In response to there being enough idle on-chip write cache to be used for processing the write command, apply for a corresponding idle on-chip write cache for the write command to process the write command.

6. The method for processing IO commands in a read-write hybrid scenario according to claim 5, characterized in that: Step S312 also includes: In response to there being enough idle on-chip write buffer to be used for processing the write command, acquiring the write command from the host, and allocating a corresponding size of the on-chip write buffer to the write command to process the write command; Alternatively, in response to the write-on-chip cache being released, if the free write-on-chip cache is sufficient to process the write command, the write command is obtained from the write waiting resource pool, and a write-on-chip cache of a corresponding size is allocated to the write command to process the write command.

7. The method for processing IO commands in a read-write hybrid scenario according to claim 5 or 6, characterized in that: The following steps are also included: Step S322, checking whether the write waiting processing resource pool is empty; Step S324: In response to the write waiting processing resource pool being not empty, checking whether there is idle write on-chip cache sufficient to be used to process write commands in the write waiting processing resource pool; Step S326: In response to there being enough idle on-chip write cache to process the write command, the write command is obtained from the write waiting resource pool, and an on-chip write cache of a corresponding size is allocated to the write command to process the write command.

8. The method for processing IO commands in a read-write hybrid scenario according to claim 5 or 6, characterized in that: The following steps are also included: Step S328: If the IO command is a read command, check whether there is enough idle on-chip read cache to process the read command; Step S330, in response to the fact that there is not enough idle on-chip read cache to process the read command, stop receiving the IO command; Step S332: In response to there being enough idle on-chip read cache to be used for processing the read command, apply for a corresponding idle on-chip read cache for the read command to process the read command.

9. A storage device comprising: DRAM, NVM chip and control component; characterized in that the control component executes the IO command processing method in the read-write hybrid scenario described in any one of claims 1 to 8 above.

10. The storage device according to claim 9, characterized in that: The control component includes: a front-end module and a back-end module; wherein the front-end module includes: a data management module; the back-end module includes: a scheduling management module and a flash channel controller module; Among them, the data management module provides read / write on-chip cache, and is responsible for decoding and processing the host read / write commands to obtain flash memory read / write commands, and sends the flash memory read / write commands to the scheduling management module. The scheduling management module receives the flash memory read / write commands and sends the flash memory read / write commands to the flash memory channel controller module. The flash memory channel controller module performs priority scheduling on the flash memory read / write commands and processes them according to the priority.

Images