Full multi-plane operation enabled

Abstract

The present application relates to full multi-plane operation enablement. A flash memory controller may determine that a first plane in a plane set of a memory die is an invalid plane. The flash memory controller may issue a single descriptor associated with a multi-plane operation for the plane set of the memory die. The single descriptor may contain multiple commands for the multi-plane operation, wherein based on the first plane being the invalid plane, a first command in the multiple commands may be a copy of a second command in the multiple commands. In some cases, a non-NAND controller may receive the single descriptor associated with the multi-plane operation for the plane set of the memory die. The NAND controller may issue multiple commands for the multi-plane operation based on receiving the single descriptor.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on December 24, 2020, with application number 202011547868.5 and title “Fully Multi-Plane Operation Enabling.”

[0003] Cross-references

[0004] This patent application claims priority to U.S. patent application No. 16 / 730,881, filed by Wu et al. on December 30, 2019, entitled “FULL MULTI-PLANE OPERATION ENABLEMENT,” which is assigned to the assignee of this application and is hereby incorporated by reference in its entirety. Technical Field

[0005] The technical field relates to full multi-plane operation enabling. Background Art

[0006] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Typically, a host system may utilize the memory subsystem to store data in the memory devices and retrieve data from the memory devices. Summary of the Invention

[0007] A method is described. The method may include determining that a first plane in a plane set of a memory die is an invalid plane; and issuing a single descriptor associated with a multi-plane operation for the plane set of the memory die based at least in part on the determination, wherein the single descriptor includes a plurality of commands for the multi-plane operation, and wherein based at least in part on the first plane being the invalid plane, a first command in the plurality of commands is a copy of a second command in the plurality of commands, the second command being for a second plane in the plane set.

[0008] A method is described. The method may include receiving a single descriptor associated with a multi-plane operation for a set of planes of a memory die; and issuing a plurality of commands for the multi-plane operation based at least in part on receiving the single descriptor, wherein the single descriptor indicates the plurality of commands for the multi-plane operation, and wherein a first command in the plurality of commands is a copy of a second command in the plurality of commands.

[0009] A system is described. The system may include a plurality of memory components and a processing device operatively coupled to the plurality of memory components to determine that a first plane in a plane set of a memory die is a valid plane; duplicate a first command from a plurality of commands for a multi-plane operation of the plane set based at least in part on a second plane in the plane set being an invalid plane; and issue a single descriptor associated with the multi-plane operation based at least in part on the determination, wherein the single descriptor indicates that the plurality of commands includes the first command and a duplicate of the first command. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be used to limit the present disclosure to specific embodiments, but are only for ease of explanation and understanding.

[0011] Figure 1 An example of a computing system including a memory subsystem according to some examples of the present disclosure is shown.

[0012] Figure 2 is a diagram of an exemplary method for supporting full multi-plane operation enablement for memory according to some examples of the present disclosure.

[0013] Figure 3 is a diagram of an exemplary method for supporting full multi-plane operation enablement for memory according to some examples of the present disclosure.

[0014] Figure 4 is a block diagram of an exemplary system supporting full multi-plane operation enablement for memory according to some examples of the present disclosure.

[0015] Figure 5A is an exemplary memory subsystem that supports full multi-plane operation enablement for memory according to some examples of the present disclosure.

[0016] Figure 5B is an exemplary memory subsystem that supports full multi-plane operation enablement for memory according to some examples of the present disclosure.

[0017] Figure 6 is a block diagram of an exemplary system supporting full multi-plane operation enablement for memory according to some examples of the present disclosure. DETAILED DESCRIPTION

[0018] Aspects of the present disclosure relate to full multi-plane operation enablement. The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. Generally, a host system can utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0019] The memory device may be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. The die in the package can be assigned to one or more channels to communicate with the memory subsystem controller. Each die can be composed of one or more planes. The planes can be grouped into logical units (LUNs). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane is composed of a set of physical blocks, which are a set of memory cells used to store data. A cell is an electronic circuit that stores information. A data block, hereinafter, refers to a unit of a memory device used to store data and can include a group of memory cells, a word line group, a word line, or an individual memory cell.

[0020] Multiple cells can be strung together, and a string can be replicated multiple times in a single block. Each column of cells can be referred to as a "string," and each row can be referred to as a "page." Multiple strings and pages of cells can be collectively referred to as a "block." A data block can contain pages with valid data and pages without data (e.g., pages that have been previously erased but not yet written to). Valid data can then be written (e.g., overwritten) to the memory device (e.g., a different page of the memory device).

[0021] Data operations can be performed by the memory subsystem. Data operations can be host-initiated operations. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem, such as storing data on a memory device at the memory subsystem and reading data from a memory device at the memory subsystem.

[0022] As specified by the host request, the data to be read or written is referred to as "host data" hereinafter. The host request may include logical address information for the host data (e.g., logical block address (LBA), namespace), which is the location that the host system associates with the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., ECC codeword, parity code), data version (e.g., for distinguishing the useful life of the written data), a valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0023] When host data can be written to a memory cell, multiple blocks across multiple memory dies and channels can be used. In some cases, a data block across multiple memory dies and channels may contain pages or planes with invalid data. In response to the occurrence of various events that make the block unreliable, the block can be invalidated. For example, in response to a corresponding bit error rate (BER) exceeding a threshold BER, the block can be invalidated. A data block containing pages or planes with invalid data can be referred to as a bad block. A bad block hereinafter refers to a block that is no longer reliably used to store or retrieve data, for example, due to a defect (e.g., a manufacturing defect) or due to wear. In some cases, the bad block cannot be accessed to replace the invalid data with valid data. For example, the bad block cannot be erased, programmed, or read. In such cases, if at least one of the block groups contains a bad block, the block groups cannot be programmed, erased, or read in parallel.

[0024] In conventional systems, multi-plane operations with at least one bad block can be performed by utilizing one plane operation at a time. In order to implement full multi-plane operations in conventional systems, commands and descriptors for each plane can be issued. For example, because bad blocks cannot be accessed, the memory subsystem controller can issue separate descriptors to avoid bad blocks. The descriptors can contain addresses and command sequences. For example, a descriptor for a bad block can be issued, and a different descriptor for each remaining block (e.g., good blocks, such as those containing valid data) can be issued. In conventional systems, issuing a different descriptor for each command may increase overhead due to the multiple parameters utilized by the controller, reduce the performance of the memory subsystem, and increase the latency of the memory die.

[0025] Aspects of the present disclosure address the above and other deficiencies by having a memory subsystem that enables full multi-plane operation. For example, a controller can issue a single descriptor for multi-plane operation. A single descriptor can contain multiple commands for multi-plane operation. In some cases, the multiple commands can include commands associated with good blocks, and if the commands are associated with bad blocks, the controller can identify the bad blocks, copy the commands associated with the good blocks and replace the commands for the bad blocks with commands for the good blocks. Because the bad blocks cannot be accessed, the command sequence for the bad blocks can be replaced with the command sequence for the good blocks, and by replacing the commands for the bad blocks with the commands for the good blocks, the controller can issue a single descriptor to perform program, erase or read operations in parallel with other groups of blocks (i.e., a single descriptor can be used to perform operations on multiple blocks or groups of blocks).

[0026] By issuing a single descriptor for multiple commands, the overall performance of the memory subsystem can be improved. For example, enabling full multi-plane operation can improve the overall efficiency of the memory subsystem by reducing the resource cost and time associated with accessing multiple descriptors from memory and improving the performance of the memory subsystem. Such techniques may result in the memory subsystem experiencing improved read, write, and erase speeds and / or reduced power consumption, improved processing time, etc.

[0027] First, in the reference Figure 1 The features of the present disclosure are described in the context of the computing environment described. Figure 2 Features of the present disclosure are described in the context of the methods, block diagrams, and exemplary memory dies described in FIG5 . These and other features of the present disclosure are further illustrated by and described with reference to a computer system, the computer system being related to a computer system such as that described with reference to FIG5 . Figure 6 Full multi-plane operation is enabled as described.

[0028] Figure 1 An example of a computing system 100 according to examples disclosed herein is shown. The computing environment can include a host system 105 and a memory subsystem 110. The memory subsystem 110 can include media such as one or more non-volatile memory devices (e.g., memory device 130), one or more volatile memory devices (e.g., memory device 140), or a combination thereof.

[0029] The memory subsystem 110 can be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multi-media controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile DIMMs (NVDIMMs).

[0030] The computing system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked business device), or such a computing device that includes a memory and a processing device.

[0031] Computing system 100 can include a host system 105 coupled to one or more memory subsystems 110. In some examples, host system 105 is coupled to memory subsystems 110 of different types. Figure 1 An example of a host system 105 coupled to a memory subsystem 110 is shown. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0032] The host system 105 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a memory protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 uses, for example, the memory subsystem 110 to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0033] The host system 105 can be coupled to the memory subsystem 110 using a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, Fibre Channel, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM slot interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 105 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 105 via a PCIe interface, the host system 105 can further utilize a Non-Volatile Memory Express (NVMe) interface to access the memory component (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 105 . Figure 1 Memory subsystem 110 is shown as an example. Generally, host system 105 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0034] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM) such as dynamic RAM (DRAM) and synchronous DRAM (SDRAM).

[0035] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can perform bit storage based on bulk resistance changes in combination with a stackable cross-grid data access array. In addition, compared to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without having to erase the non-volatile memory cells in advance. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0036] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cells. In some embodiments, a particular memory device may include an SLC portion and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 may be grouped into pages, which may refer to logical units of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0037] Although nonvolatile memory components such as NAND-type flash memory (e.g., 2D NAND, 3D NAND) and a 3D cross-point array of nonvolatile memory cells are described, the memory device 130 can be based on any other type of nonvolatile memory cell, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), spin-transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable and programmable ROM (EEPROM).

[0038] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data, as well as other such operations, in the memory device 130. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or other suitable processor.

[0039] The memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the illustrated example, the local memory 125 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 105.

[0040] In some instances, local memory 125 may include memory registers that store memory pointers, pre-fetched data, etc. Local memory 125 may also include ROM for storing microcode. Figure 1 The exemplary memory subsystem 110 in has been shown as including a memory subsystem controller 115, but in another example of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0041] Typically, the memory subsystem controller 115 can receive commands or operations from the host system 105 and convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and correction code (ECC) operations, encryption operations, cache operations, and address conversion between logical addresses (e.g., logical block addresses (LBA), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 can further include host interface circuitry to communicate with the host system 105 via a physical host interface. The host interface circuitry can convert commands received from the host system into command instructions for accessing the memory device 130, and convert responses associated with the memory device 130 into information for the host system 105.

[0042] The memory subsystem 110 may also include additional circuits or components not shown. In some examples, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuits (e.g., row decoders and column decoders) that can receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0043] In some examples, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0044] The local media controller 135 may receive a single descriptor associated with a multi-plane operation for a set of planes of a memory die. Based on receiving the single descriptor, the local media controller 135 may issue multiple commands for the multi-plane operation. The single descriptor may indicate multiple commands, and the multiple commands may include a first command and a second command, where the first command may be a copy of the second command.

[0045] The memory subsystem 110 includes a multi-plane operations manager 150 that can determine that a first plane in a plane set is an invalid plane. For example, an invalid plane can be associated with a hardware error, a block error, a memory component error, or a combination thereof. Additionally or alternatively, an invalid plane can include plane corruption, invalid data, an uncorrectable error, or a combination thereof. In some instances, the invalid plane cannot be accessed by the memory subsystem.

[0046] In some instances, the multi-plane operations manager 150 may issue a single descriptor associated with a multi-plane operation. A single descriptor may contain multiple commands for a multi-plane operation. A first command contained in a single descriptor may be a copy of a second command, where the second command corresponds to an active plane (e.g., a second plane). In such cases, the memory subsystem may access the active plane. By issuing a single descriptor, overhead may be reduced by accessing a single command rather than a descriptor for each command, thereby improving performance and reliability.

[0047] In some examples, the memory subsystem controller 115 includes at least a portion of a multi-plane operations manager 150. For example, the memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in the local memory 125 to perform the operations described herein. In some examples, the multi-plane operations manager 150 is part of the host system 105, an application, or an operating system.

[0048] Multi-plane operations manager 150 may replace the address of the invalid plane with the address of a valid plane based on determining that the first plane is an invalid plane. In some cases, multi-plane operations manager 150 may determine that the multiple planes include more than one invalid plane. In such cases, multi-plane operations manager 150 may replace each address of the invalid plane with the address of a valid plane. More details regarding the operation of multi-plane operations manager 150 are described herein.

[0049] Figure 2 is a diagram of an exemplary method 200 for enabling full multi-plane operation according to some examples of the present disclosure. The method 200 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the method 200 is performed by Figure 1 The multi-plane operations manager 150 is executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the examples shown should be understood as examples only, and the processes shown may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in every example. Other process flows are possible.

[0050] At operation 205, a processing device of a flash memory controller may determine that a first plane of a memory die contains a bad block (e.g., an invalid plane). The bad block may be contained in an invalid plane of the memory die. In some instances, the invalid plane may be the result of a hardware error, plane corruption, block error, memory component failure, or a combination thereof. In such cases, the invalid plane may contain uncorrectable errors. In some cases, determining that the first plane is a bad block may be based on the first plane containing a large amount of invalid data, the first plane exceeding a threshold number of invalid pages of the memory die, or both. In some instances, the flash memory controller may be as described in reference Figure 1 In some examples, aspects of operation 205 may be implemented as described with reference to Figure 1 The described multi-plane operations manager 150 is executed.

[0051] At operation 210, a processing device may publish a single descriptor associated with a multi-plane operation for a memory die, wherein the single descriptor includes a first command and a second command, wherein the first command is a copy of the second command based on the first plane containing a bad block. For example, the single descriptor may be published to a local memory controller of the memory die. In some cases, the single descriptor may include multiple commands for a multi-plane operation (e.g., including at least a first command and a second command). In such cases, based on the first plane containing a bad block, the first command may be a copy of the second command. In some cases, the second command may be for a second plane included in the plane set. In such cases, the second command may correspond to a valid plane. In some instances, the second command may correspond to a second plane different from the first plane.

[0052] In some examples, method 200 may include replacing the address of a first plane (e.g., a bad block) with the address of a second plane (e.g., a good block). In such cases, the second plane in the set of planes may be a valid plane. In some cases, a valid plane may contain valid data. In such cases, determining that the second plane is a valid plane is based on the second plane containing a large amount of valid data.

[0053] In some examples, method 200 may include determining a number of invalid planes (e.g., bad blocks) in a plane set and replacing an address of each of the plurality of invalid planes with an address associated with a valid plane. The addresses may be replaced in a multi-plane command sequence indicated by a single descriptor. In some examples, method 200 may include duplicating a second command based on the first plane being an invalid plane. In such cases, the first command (e.g., address) may be replaced with the second command.

[0054] In some instances, a single descriptor may contain only commands for valid planes in a plane set. In some instances, multiple commands may be associated with at least one of a read operation, a write operation, or an erase operation. In some instances, aspects of operation 210 may be as described with reference to Figure 1 The described multi-plane operations manager 150 is executed.

[0055] Figure 3 is a diagram of an exemplary method 300 for enabling full multi-plane operation according to some examples of the present disclosure. The method 300 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the method 300 is performed by Figure 1The multi-plane operations manager 150 is executed. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the examples shown should be understood as examples only, and the processes shown may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in every example. Other process flows are possible.

[0056] At operation 305, a processing device of a NAND controller may receive a single descriptor associated with a multi-plane operation for a plane set of a memory die. In some examples, the NAND controller may be as described in reference Figure 1 In some examples, aspects of operation 305 may be implemented as described with reference to Figure 1 The described multi-plane operations manager 150 is executed.

[0057] At operation 310, a processing device may issue commands for multi-plane operations based on receiving a single descriptor, wherein the single descriptor indicates commands for multi-plane operations and wherein a first command in the commands is a copy of a second command in the commands. In some cases, the commands may be associated with at least one of a read operation, a write operation, or an erase operation.

[0058] In some instances, method 300 may include issuing a first command for a second plane. The first command may correspond to a first plane, wherein the first plane is an invalid plane. In some instances, the second plane may correspond to a second command, wherein the second plane is a valid plane. In such cases, the second instruction may be copied for the first command based on the first plane being an invalid plane, the amount of invalid data contained in the first plane exceeding a threshold number of invalid pages of the memory die, or both. The invalid plane may be the result of a hardware error, plane damage, block error, memory component failure, or a combination thereof. In such cases, the invalid plane may contain uncorrectable errors. In some cases, the invalid plane may contain invalid data (e.g., bad blocks). In some cases, the valid plane may contain invalid data (e.g., good blocks).

[0059] In some cases, the first plane and the second plane may be included in a plane set. In some instances, method 300 may issue a second command for the second plane. In such cases, the first command may be a copy of the second command. In some instances, the second command may correspond to a second plane that is different from the first plane. In some instances, aspects of operation 310 may be performed as described with reference to FIG. Figure 1 The described multi-plane operations manager 150 is executed.

[0060] Figure 4 FIG4 is a block diagram of an exemplary system that supports full multi-plane operation enablement for memory according to some examples of the present disclosure. Block diagram 400 may include a memory subsystem 405. Memory subsystem 405 may include a flash controller 410, a NAND controller 420, and a backend manager 425. Block diagram 400 may also include a host system 430. Flash controller 410 may be as described in reference Figure 1 An example of a memory subsystem controller 115 is described. The NAND controller may be as described with reference to Figure 1 An example of a local media controller 135 is described.

[0061] The memory subsystem 405 can perform multi-plane operations. For example, the memory subsystem 405 can perform 4-plane operations. In some cases, one or more of the four planes may be invalid planes. The flash controller 410 can determine that a plane in the plane set is a valid plane and another different plane in the plane set is an invalid plane. In order to perform a 4-plane operation on a memory tube core with an invalid plane, the flash controller 410 can copy the command sequence of the valid plane and replace the command sequence of the invalid plane with the copied command sequence. For example, the flash controller 410 can replace the address within the command for the invalid plane with the address of the valid plane. In some cases, the flash controller 410 can copy the command sequence for the valid plane the same number of times as the number of invalid planes in the plane set. For example, if the memory tube core contains two invalid planes, the flash controller 410 can copy the command sequence of the valid plane twice and replace each address of the two invalid planes with the address of the valid plane.

[0062] The flash controller 410 can confirm that the copy command sequence for the invalid plane is the same as the command sequence for the valid plane. In such cases, the address (e.g., data) of the invalid plane can be the same as the address of the valid plane. In some cases, the data may be garbled within the row address; however, the flash controller 410 can read back the data, confirm that the data is garbled within the row address, and confirm that the data is the same as the copied data. In some cases, the garbled data can be associated with the row address.

[0063] Flash controller 410 may issue a single descriptor 415 associated with a multi-plane operation (e.g., a 4-plane operation). Descriptor 415 may indicate multiple commands associated with the multi-plane operation. For example, descriptor 415 may indicate commands associated with an active plane and commands associated with an inactive plane. In such cases, the commands associated with the inactive plane may be duplicated commands associated with the active plane.

[0064] In some instances, descriptor 415 may include a command and a row address. For example, descriptor 415 may include the address of a channel and the address of a memory die within the row address. In some instances, descriptor 415 may connect data associated with a buffer to descriptor 415. Descriptor 415 may be used to generate a command sequence (e.g., copying a command sequence for an active plane and replacing a command sequence for an inactive plane with a command sequence for an active plane). In such cases, descriptor 415 includes the syntax of a command that may be sent to NAND controller 420.

[0065] In some cases, descriptors 415 cannot be stored in the memory of flash controller 410, thereby increasing the overhead associated with accessing descriptors 415. For example, descriptors 415 can be stored in SRAM memory. In some memory subsystems, accessing more than one descriptor 415 for a single multi-plane operation may increase the overhead, time, and resources associated with retrieving multiple descriptors from SRAM memory. Rather, accessing a single descriptor 415 for a single multi-plane operation may reduce the overhead, time, and resources associated with retrieving a single descriptor.

[0066] The flash controller 410 can send a single command using a single descriptor 415 that instructs the NAND controller 420 to perform a 4-plane operation. The single command can delineate four planes within the memory die, where at least one of the four planes is an invalid plane. In such a case, the command can include the copied data of at least one of the valid planes and replace the address of the invalid plane with the address of the valid plane.

[0067] The flash controller 410 may send the descriptor 415 to the NAND controller 420. In such cases, the NAND controller 420 may receive the descriptor 415 and issue the command contained in the descriptor 415. The NAND controller 420 may include microcode configured to receive the command sequence contained in the descriptor 415. When the NAND controller 420 receives the command sequence, the microcode may issue the multi-plane operation associated with the command. In some cases, the microcode may utilize a single data plane (e.g., the last data plane in the command sequence) to issue the command associated with the multi-plane operation. In some instances, the NAND controller 420 may issue the command to each plane (e.g., the active plane and the inactive plane). The command may be associated with a read operation, a write operation, or an erase operation.

[0068] Figure 5A1 is an exemplary memory subsystem 500-a that supports full multi-plane operation for memory according to some examples of the present disclosure. Memory subsystem 500-a may include a memory die 505-a, where memory die 505-a may include plane 510-a, plane 515-a, plane 520-a, and plane 525-a. Each plane may include a data block. For example, plane 510-a includes data block 530-a, and plane 515-a includes data block 535-a.

[0069] Memory die 505-a may be an example of a memory die 505-a that includes a single invalid plane (e.g., plane 510-a). Memory die 505-a may include valid planes (e.g., plane 515-a, plane 520-a, and plane 525-a). Plane 510-a may prevent memory die 505-a from performing multi-plane operations using a single descriptor due to the presence of invalid data in data block 530-a. In some cases, at least one data block 530-a containing invalid data may cause plane 510-a to be an invalid plane. An invalid plane may experience a hardware error, a block error, a memory component error, or a combination thereof. In some cases, an invalid plane may include plane corruption, invalid data, an error that cannot be corrected, or a combination thereof.

[0070] In some instances, the flash memory controller may duplicate commands associated with one of the active planes and replace the commands of the inactive plane with the duplicated commands of the active plane. For example, commands of plane 515-a may be duplicated. Commands of plane 510-a may be replaced with commands of plane 515-a. In some cases, commands of plane 520-a and commands of plane 525-a may be duplicated, and commands of plane 510-a may be replaced with commands of plane 520-a or commands of plane 525-a. The table shows the command sequence for a 3-plane programming operation.

[0071] Table 1

[0072]

[0073] In some cases, the command "Publish Program Page Multi-Plane (85h / 80h-11h) with Plane 0 Page Data" may be associated with plane 515-a. In such cases, the command may be duplicated, and the command for plane 510-a may be replaced with "Publish Program Page Multi-Plane (85h / 80h-11h) with Plane 0 Page Data." For example, the command sequence for plane 510-a and the command sequence for plane 515-a may be the same command sequence (e.g., containing the same addresses).

[0074] In some instances, the command "Publish Program Page Multi-Plane (85h / 80h-11h) with Plane 1 Page Data" may be associated with plane 520-a. The command "Publish Program Page Multi-Plane (85h / 80h-10h) with Plane 2 Page Data" may be associated with plane 525-a. In such instances, the commands for plane 520-a and plane 525-a cannot be copied to replace the commands for plane 510-a. In other instances, the commands for plane 520-a and plane 525-a may be copied to replace the commands for plane 510-a.

[0075] When the NAND controller receives the multi-plane sequence of Table 1, the NAND controller may trigger a programming operation after the NAND controller receives the "Publish Program Page Multi-Plane (85h / 80h-10h) with Plane 2 Page Data" command sequence (e.g., the command sequence for plane 525-a). In such cases, the NAND controller may trigger a programming operation using the last command sequence. In some cases, the command sequences for plane 510-a, plane 515-a, and plane 515-c may be queued (e.g., stored in a local buffer) until the command sequence for plane 525-a is received. The NAND controller may decode the addresses within the command sequence to identify the address locations to overwrite the original data of the data block.

[0076] In some cases, a single descriptor can be issued for a programming operation. If the address of plane 515-a, plane 520-a, or plane 525-a is copied to replace the address of plane 510-a, the flash memory controller can issue a single descriptor because each command sequence is associated with the address of a valid plane. If a command sequence can be associated with the address of an invalid plane, the flash memory controller cannot issue a single descriptor; rather, it can issue a separate descriptor for each command sequence. Issuing a separate descriptor for each command sequence may increase processing time and latency of programming operations.

[0077] In some cases, a command sequence may be associated with an erase operation. Table 2 may provide a command sequence for a 3-plane erase operation.

[0078] Table 2

[0079]

[0080] In some cases, the command "Publish Erase Block Multi-Plane (60h-D1h) with Plane 0" may be associated with plane 515-a. In such cases, the command may be duplicated, and the command for plane 510-a may be replaced with "Publish Erase Block Multi-Plane (60h-D1h) with Plane 0." For example, the command sequence for plane 510-a and the command sequence for plane 515-a may be the same command sequence (e.g., containing the same addresses).

[0081] In some examples, the command "Publish Erase Block Multi-Plane (60h-D1h) with Plane 1" may be associated with plane 520-a. The command "Publish Erase Block Multi-Plane (60h-D0h) with Plane 2" may be associated with plane 525-a. In such cases, the commands for plane 520-a and plane 525-a cannot be copied to replace the commands for plane 510-a. In other examples, the commands for plane 520-a and plane 525-a can be copied to replace the commands for plane 510-a.

[0082] When the NAND controller receives the multi-plane sequence of Table 2, the NAND controller can trigger the erase operation after the NAND controller receives the "Issue Erase Block with Plane 2 (60h-D0h)" command sequence (e.g., the command sequence for plane 525-a). In such cases, the NAND controller can use the last command sequence to trigger the erase operation. In some cases, the command sequences for plane 510-a, plane 515-a, and plane 515-c can be queued (e.g., stored on a local buffer) until the command sequence for plane 525-a is received. Copying the command for plane 515-a does not cause a delay because the NAND controller cannot issue the erase operation until the command sequence for plane 525-a is received. The NAND controller can decode the address within the command sequence to identify the address location to erase the data of the data block.

[0083] In some cases, a single descriptor can be issued for an erase operation. If the address of plane 515-a, plane 520-a, or plane 525-a is copied to replace the address of plane 510-a, the flash controller can issue a single descriptor because each command sequence is associated with the address of a valid plane. If a command sequence can be associated with the address of an invalid plane, the flash controller cannot issue a single descriptor; rather, it can issue a separate descriptor for each command sequence. Issuing a separate descriptor for each command sequence may increase processing time and latency of the erase operation.

[0084] Figure 5B1 is an exemplary memory subsystem 500-b that supports full multi-plane operation for memory according to some examples of the present disclosure. Memory subsystem 500-b may include a memory die 505-b, where memory die 505-b may include plane 510-b, plane 515-b, plane 520-b, and plane 525-b. Each plane may include a data block. For example, plane 510-b includes data block 530-b, and plane 515-b includes data block 535-b.

[0085] Memory die 505-b may be an instance of a memory die 505-b that includes more than one invalid plane (e.g., plane 510-b and plane 520-b). Memory die 505-b may include valid planes (e.g., plane 515-b and plane 525-b). Planes 510-b and 520-b may prevent memory die 505-b from performing multi-plane operations using a single descriptor due to the presence of invalid data in data block 530-b and data block 530-c. In some cases, at least one data block 530-b and data block 530-c containing invalid data may cause plane 510-b and plane 520-b, respectively, to be invalid planes.

[0086] In such cases, the flash memory controller may copy the commands associated with the active plane and replace the commands of the inactive plane with the copied commands of the active plane. For example, the commands of plane 515-b may be copied and the commands of plane 510-b may be replaced with the commands of plane 515-b. The commands of plane 525-b may be copied and the commands of plane 520-b may be replaced with the commands of plane 525-b. In some cases, the commands of plane 525-b may be copied and the commands of plane 510-b may be replaced with the commands of plane 525-b. In other instances, the commands of plane 515-b may be copied and the commands of plane 520-b may be replaced with the commands of plane 515-b. Table 3 may provide a command sequence for a 2-plane programming operation.

[0087] Table 3

[0088]

[0089] In some cases, the command "Publish Program Page Multi-Plane (85h / 80h-11h) with Plane 0 Page Data" may be associated with plane 515-b. In such cases, the command may be duplicated, and the command for plane 510-b may be replaced with "Publish Program Page Multi-Plane (85h / 80h-11h) with Plane 0 Page Data." For example, the command sequence for plane 510-b and the command sequence for plane 515-b may be the same command sequence (e.g., containing the same addresses).

[0090] In some cases, the command "Publish Program Page Multi-Plane (85h / 80h-10h) with Plane 2 Page Data" may be associated with plane 525-b. In such cases, the command may be duplicated, and the command for plane 520-b may be replaced with "Publish Program Page Multi-Plane (85h / 80h-10h) with Plane 2 Page Data." For example, the command sequence for plane 520-b and the command sequence for plane 525-b may be the same command sequence (e.g., containing the same addresses).

[0091] When the NAND controller receives the multi-plane sequence of Table 3, the NAND controller may trigger a programming operation after the NAND controller receives the "Publish Program Page Multi-Plane (85h / 80h-10h) with Plane 2 Page Data" command sequence (e.g., the command sequence for plane 525-b). The NAND controller may recognize that the command sequence associated with plane 520-b is the copied command sequence, thereby indicating that the command sequence for plane 520-b cannot be the last command sequence. In such cases, the NAND controller may avoid issuing a programming operation. In some cases, the command sequences for plane 510-b, plane 515-b, and plane 520-b may be queued (e.g., stored on a local buffer) until the command sequence for plane 525-b is received.

[0092] In some cases, a single descriptor can be issued for a programming operation. If the address of plane 515-b is copied to replace the address of plane 510-b and the address of plane 520-b is copied to replace the address of plane 525-b, the flash controller can issue a single descriptor because each command sequence is associated with the address of a valid plane. If at least one command sequence can be associated with the address of an invalid plane, the flash controller cannot issue a single descriptor; rather, it can issue a separate descriptor for each command sequence. Issuing a separate descriptor for each command sequence may increase processing time and latency of programming operations.

[0093] In some cases, a command sequence may be associated with an erase operation. Table 4 may provide a command sequence for a 2-plane erase operation.

[0094] Table 4

[0095]

[0096] In some cases, the command "Publish Erase Block Multi-Plane (60h-D1h) with Plane 0" may be associated with plane 515-b. In such cases, the command may be duplicated, and the command for plane 510-b may be replaced with "Publish Erase Block Multi-Plane (60h-D1h) with Plane 0." For example, the command sequence for plane 510-b and the command sequence for plane 515-b may be the same command sequence (e.g., containing the same addresses).

[0097] In some cases, the command "Publish Erase Block with Plane 2 (60h-D0h)" may be associated with plane 525-b. In such cases, the command may be duplicated, and the command for plane 520-b may be replaced with "Publish Erase Block with Plane 2 (60h-D0h)." For example, the command sequence for plane 520-b and the command sequence for plane 525-b may be the same command sequence (e.g., containing the same addresses).

[0098] When the NAND controller receives the multi-plane sequence of Table 4, the NAND controller may trigger an erase operation after the NAND controller receives the "Issue Erase Block with Plane 2 (60h-D0h)" command sequence (e.g., the command sequence for plane 525-b). The NAND controller may recognize that the command sequence associated with plane 520-b is a copied command sequence, thereby indicating that the command sequence for plane 520-b cannot be the last command sequence. In such cases, the NAND controller may avoid issuing an erase operation. In some cases, the command sequences for plane 510-b, plane 515-b, and plane 520-b may be queued (e.g., stored in a local buffer) until the command sequence for plane 525-b is received.

[0099] In some cases, a single descriptor can be issued for an erase operation. If the address of plane 515-b is copied to replace the address of plane 510-b and the address of plane 520-b is copied to replace the address of plane 525-b, the flash controller can issue a single descriptor because each command sequence is associated with the address of a valid plane. If at least one command sequence can be associated with the address of an invalid plane, the flash controller cannot issue a single descriptor; rather, it can issue a separate descriptor for each command sequence. Issuing a separate descriptor for each command sequence may increase processing time and latency of the erase operation.

[0100] In some instances, the flash controller may determine the number of inactive planes in the plane set of memory die 505-b and replicate commands for active planes based on the number of inactive planes. For example, the flash controller may determine that plane 510-b and plane 520-b may be inactive planes. In such cases, commands for plane 515-b (e.g., an active plane) may be replicated twice, replacing each address of commands associated with plane 510-b and plane 520-b. In other instances, commands for plane 525-b (e.g., an active plane) may be replicated twice, replacing each address of commands associated with plane 510-b and plane 520-b. The average percentage of multi-plane blocks for 4-plane operations may be 94.051%. The average percentage of multi-plane blocks for 3-plane operations may be 5.809%. The average percentage of multi-plane blocks for 2-plane operations may be 0.139%. The average percentage of multi-plane blocks for 2-plane operations may be 0.000661%. Therefore, replicating commands for active planes based on the number of inactive planes may improve the efficiency and performance of memory die 505-b.

[0101] Figure 6 An exemplary machine of a computer system 600 according to examples disclosed herein that supports maintaining a sequential folding scoreboard is shown. The computer system 600 may include an instruction set that enables the machine to perform any one or more of the techniques described herein. In some examples, the computer system 600 may correspond to a host system (e.g., a reference Figure 1 105) that includes, is coupled to, or utilizes a memory subsystem (e.g., reference Figure 1 The memory subsystem 110 described above) or can be used to perform operations of the controller (for example, to execute an operating system to perform operations related to the reference Figure 1 In some examples, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate as a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0102] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be performed by the machine. Furthermore, while a single machine is shown, the term "machine" may also include any collection of machines that individually or jointly execute a set (or multiple sets of instructions) to perform any one or more of the methodologies discussed herein.

[0103] The exemplary computer system 600 may include a processing device 605, a main memory 610 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus RDRAM (RDRAM), etc.), a static memory 615 (e.g., flash memory, static RAM (SRAM), etc.), and a data storage system 625 that communicate with each other via a bus 645.

[0104] The processing device 605 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a combination of instruction sets. The processing device 605 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a DSP, a network processor, or the like. The processing device 605 is configured to execute instructions 635 for performing the operations and steps discussed herein. The computer system 600 may further include a network interface device 620 for communicating via a network 640.

[0105] The data storage system 625 may include a machine-readable storage medium 630 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 635 or software embodying any one or more of the methodologies or functions described herein. The instructions 635 may also reside, completely or at least partially, within the main memory 610 and / or within the processing device 605 during execution of the instructions by the computer system 600, the main memory 610 and the processing device 605 also constituting machine-readable storage media. The machine-readable storage medium 630, the data storage system 625, and / or the main memory 610 may correspond to a memory subsystem.

[0106] In one example, instructions 635 include instructions for implementing a multi-plane operations manager 650 (e.g., referring to Figure 1The multi-plane operations manager 150 described herein may be a multi-plane operations manager 150 that is configured to store instructions for functionality corresponding to the multi-plane operations manager 150 described herein. Although the machine-readable storage medium 630 is shown as a single medium, the term "machine-readable storage medium" may include a single medium or multiple media that store one or more instruction sets. The term "machine-readable storage medium" may also include any medium that can store or encode an instruction set for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0107] Some parts of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of the operations on the data bits in a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing use the most effective means of conveying the essence of their work to others skilled in the art. An algorithm is generally considered to be a self-consistent sequence of operations that results in a desired result. The operations are those that require physical manipulation of physical quantities. Typically, although not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has been shown that, in principle, it is sometimes convenient to refer to such signals as bits, values, elements, symbols, characters, terms, quantities, etc. for general purposes.

[0108] It should be borne in mind, however, that all of these or similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0109] The present disclosure also relates to an apparatus for performing the operations described herein. The apparatus may be specifically constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, a floppy disk, an optical disk, a CD-ROM, a magneto-optical disk, a ROM, a RAM, an EPROM, an EEPROM, a magnetic card, or an optical card, or any other type of medium suitable for storing electronic instructions, all of which are each coupled to a computer system bus.

[0110] The algorithms and displays presented herein are not inherently associated with any particular computer or other device. Various general-purpose systems can be used together with programs according to the teachings herein, or it may prove convenient to construct more specialized equipment to perform the methods. As described below, structures for various of these systems will appear. In addition, the present disclosure is not described with reference to any specific programming language. It should be understood that various programming languages can be used to implement the teachings of the present disclosure as described herein.

[0111] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some instances, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, and the like.

[0112] In the foregoing description, examples of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader scope and spirit of the examples of the present disclosure as set forth in the appended claims. Accordingly, the specification and drawings are to be read in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: determining that a plurality of planes in the set of planes of the memory die are invalid planes; a command to copy one or more valid planes in the set of planes based on determining a plurality of the invalid planes; as well as A single descriptor associated with a multi-plane operation for the set of planes of the memory die is issued based on the command to copy the one or more active planes, wherein the single descriptor includes a command sequence for the multi-plane operation.

2. The method according to claim 1, further comprising: The address of each of the plurality of the invalid planes is replaced with an address associated with a valid plane in the command sequence for the multi-plane operation indicated by the single descriptor.

3. The method according to claim 1, further comprising: replacing the address of the first plane in the plane set with the address of the second plane in the plane set; as well as An address of a third plane in the plane set is replaced with an address of a fourth plane in the plane set, wherein the first plane and the third plane are the invalid planes and the second plane and the fourth plane are valid planes. 4 . The method of claim 1 , wherein a first command in the command sequence is a copy of a second command in the command sequence, and a third command in the command sequence is a copy of a fourth command in the command sequence.

5. The method of claim 1 , wherein determining the plurality of planes in the set of planes to be the invalid planes is based on the plurality of planes containing a large amount of invalid data, the plurality of planes exceeding a threshold number of invalid pages for the memory die, or both.

6. The method of claim 1 , wherein publishing the single descriptor further comprises: The single descriptor is issued to a local memory controller of the memory die.

7. The method of claim 1, wherein the single descriptor includes commands for active planes in the plane set.

8. The method of claim 1, wherein the command sequence is associated with at least one of a read operation, a write operation, or an erase operation.

9. A memory system comprising: A processing circuit associated with one or more memory devices, wherein the processing circuit is configured to cause the memory system to: determining that a plurality of planes in the set of planes of the memory die are invalid planes; a command to copy one or more valid planes in the set of planes based on determining a plurality of the invalid planes; as well as A single descriptor associated with a multi-plane operation for the set of planes of the memory die is issued based on the command to copy the one or more active planes, wherein the single descriptor includes a command sequence for the multi-plane operation.

10. The memory system of claim 9, wherein the processing circuit is further configured to cause the memory system to: The address of each of the plurality of the invalid planes is replaced with an address associated with a valid plane in the command sequence for the multi-plane operation indicated by the single descriptor.

11. The memory system of claim 9, wherein the processing circuit is further configured to cause the memory system to: replacing the address of a first plane in the plane set with the address of a second plane in the plane set; and An address of a third plane in the plane set is replaced with an address of a fourth plane in the plane set, wherein the first plane and the third plane are the invalid planes and the second plane and the fourth plane are valid planes.

12. The memory system of claim 9, wherein a first command in the command sequence is a copy of a second command in the command sequence, and a third command in the command sequence is a copy of a fourth command in the command sequence.

13. The memory system of claim 9 , wherein determining that the plurality of planes in the set of planes are the invalid planes is based on the plurality of planes containing a large amount of invalid data, the plurality of planes exceeding a threshold number of invalid pages for the memory die, or both.

14. The memory system of claim 9, wherein issuing the single descriptor is further configured to cause the memory system to: The single descriptor is issued to a memory controller of the memory die.

15. The memory system of claim 9, wherein the single descriptor includes commands for active planes in the plane set.

16. The memory system of claim 9, wherein the command sequence is associated with at least one of a read operation, a write operation, or an erase operation.

17. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to: determining that a plurality of planes in the set of planes of the memory die are invalid planes; a command to copy one or more valid planes in the set of planes based on determining a plurality of the invalid planes; as well as A single descriptor associated with a multi-plane operation for the set of planes of the memory die is issued based on the command to copy the one or more active planes, wherein the single descriptor includes a command sequence for the multi-plane operation.

18. The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to: The address of each of the plurality of the invalid planes is replaced with an address associated with a valid plane in the command sequence for the multi-plane operation indicated by the single descriptor.

19. The non-transitory computer-readable medium of claim 17, wherein the instructions are further executable by the processor to: replacing the address of a first plane in the plane set with the address of a second plane in the plane set; and An address of a third plane in the plane set is replaced with an address of a fourth plane in the plane set, wherein the first plane and the third plane are the invalid planes and the second plane and the fourth plane are valid planes.

20. The non-transitory computer-readable medium of claim 17, wherein a first command in the command sequence is a copy of a second command in the command sequence, and a third command in the command sequence is a copy of a fourth command in the command sequence.

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