Signal processing detection system based on FPGA architecture

Abstract

The present invention discloses a signal processing detection system based on FPGA architecture, and specifically relates to the technical field of hardware resource management, including a signal processing detection system based on FPGA architecture, including a signal acquisition module, a signal characteristic analysis module, a fluctuation prediction module, an adaptive hardware reconstruction module and a resource scheduling and optimization module; the signal acquisition module acquires signal data in real time, the signal characteristic analysis module extracts characteristic features, the fluctuation prediction module predicts signal fluctuations based on an AR model and determines whether to trigger hardware reconstruction; the adaptive hardware reconstruction module dynamically adjusts the FPGA configuration when the reconstruction mechanism is triggered, monitors the performance improvement effect, and the resource scheduling and optimization module dynamically allocates hardware resources according to the adjustment result, and optimizes the system resource utilization; when the signal fluctuation is large, the present invention still has sufficient guarantee for hardware resource adjustment and task scheduling capabilities, avoiding the problems of reduced processing efficiency and system response delay.

Description

Technical Field

[0001] The present invention relates to the technical field of hardware resource management, and more specifically, to a signal processing detection system based on FPGA architecture. Background Art

[0002] In modern signal processing systems, as application scenarios become more complex and real-time requirements increase, signal processing systems must be able to adapt to the ever-changing external signal environment and task load. Especially in the fields of communications, radar, industrial automation, etc., the frequency, amplitude, phase and other characteristics of the signal may change dramatically in a short period of time. These changes put forward higher dynamic adjustment and resource management requirements for signal processing systems.

[0003] Traditional signal processing systems usually use fixed hardware resource allocation schemes, which cannot adapt to signal fluctuations in real time, resulting in resource waste or performance degradation. In the prior art, when the signal fluctuations are large, the hardware resource adjustment and task scheduling capabilities of FPGA-based signal processing systems are still limited, and the system cannot respond quickly to signal changes, resulting in reduced processing efficiency and system response delays.

[0004] With the development of FPGA (Field Programmable Gate Array) partial reconfiguration technology, FPGA-based signal processing systems can dynamically adjust hardware resources during system operation. However, how to effectively utilize these reconfiguration features to achieve efficient resource management is still a difficult point in current technology. Summary of the invention

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] The signal processing detection system based on FPGA architecture includes signal acquisition module, signal characteristic analysis module, fluctuation prediction module, adaptive hardware reconstruction module, resource scheduling and optimization module;

[0007] The signal acquisition module is used to collect input signal data in real time, obtain the signal acquisition data set and transmit it to the signal characteristic analysis module;

[0008] The signal characteristic analysis module is used to extract characteristic features from the signal acquisition data set, obtain multiple characteristic feature extraction sets and transmit them to the fluctuation prediction module;

[0009] The fluctuation prediction module is used to build the corresponding AR model based on the historical time series of each feature extraction set and deploy the application, and determine whether to trigger the hardware reconstruction mechanism based on the application results;

[0010] The adaptive hardware reconfiguration module is used to adaptively and dynamically adjust the FPGA hardware configuration when the hardware reconfiguration mechanism is triggered, and monitor the adjustment results to monitor whether the preset target performance parameters of signal processing have improved as expected, and decide whether to keep the current configuration or reconfigure;

[0011] The resource scheduling and optimization module is used to dynamically allocate and schedule hardware resources for the final result of reconfiguration to ensure that the system's resource utilization reaches the optimal state.

[0012] In a preferred embodiment, the signal characteristic analysis module performs characteristic feature extraction, which means extracting the amplitude, frequency, phase and power spectrum density of the signal respectively.

[0013] In a preferred embodiment, the logic of establishing the AR model is:

[0014] Obtain the characteristic values ​​of the target characteristic at different time points, perform preprocessing operations and generate a time series data set, then obtain the cycle length s, use the Bayesian information criterion selection standard to select the optimal autoregressive order p and seasonal autoregressive order P, and establish the AR model formula:

[0015] φ i The coefficient of the autoregressive part indicates the influence of the characteristic value x(ti) at time ti in the past on the current characteristic value x(t), θ j represents the coefficient of the seasonal AR part, which represents the influence of the characteristic value x(t-sj) at the past time t-sj on the current characteristic value x(t). c is a constant term, ∈(t) is a white noise term, x(t) represents the characteristic value at time t, and the coefficient φ of the autoregressive part is determined using maximum likelihood estimation i , the coefficient of the seasonal AR part θ j When the performance of the established AR model formula reaches the expected level, it will be deployed and applied.

[0016] In a preferred embodiment, the application result is obtained by the following logic:

[0017] For each characteristic feature, the sliding window average method is used to detect signal fluctuations:

[0018] For each time t, take the window size as N and calculate the average value M in the window k :

[0019] x(i) represents the characteristic value at time i, k is the starting position index of the sliding window, M k is the sliding average at the kth position;

[0020] Then the absolute value of the difference between the current characteristic value and the window average is calculated to obtain the fluctuation value, and then the characteristic feature influence coefficient corresponding to each fluctuation value is assigned, and then all fluctuation values ​​are weighted averaged to obtain the comprehensive fluctuation value.

[0021] In a preferred embodiment, judging whether to trigger the hardware reconstruction mechanism based on the application result refers to:

[0022] The comprehensive fluctuation value is obtained and compared with the preset mechanism trigger threshold. If the comprehensive fluctuation value is greater than the preset mechanism trigger threshold, the hardware reconstruction mechanism is triggered. If the comprehensive fluctuation value is less than or equal to the preset mechanism trigger threshold, the hardware reconstruction mechanism is not triggered.

[0023] In a preferred embodiment, the adaptive dynamic adjustment of the FPGA hardware configuration is based on the partial reconfiguration characteristics of the FPGA to dynamically adjust the hardware configuration parameter combination being used without affecting the normal operation of other hardware parts.

[0024] In a preferred embodiment, the resource scheduling and optimization module is used to dynamically allocate the final result of the reconfiguration, which means:

[0025] A load analysis is performed based on the current resource usage, and a determination is made based on the load analysis result whether to replace the preset static resource allocation table with a dynamic resource allocation table.

[0026] In a preferred embodiment, load analysis refers to:

[0027] The following calculations are performed based on current resource usage:

[0028] R i represents the utilization rate of the i-th resource, R max It represents the maximum allowable load value, n represents the number of resource types, and α represents the load balancing coefficient. If the load balancing coefficient α exceeds the set load imbalance threshold, resources need to be reallocated.

[0029] In a preferred embodiment, when scheduling hardware resources, a preset priority scheduling algorithm or a shortest processing time priority algorithm is used.

[0030] In a preferred embodiment, the scheduling logic when scheduling hardware resources is:

[0031] represents the importance weight of the i-th task, represents the expected completion time of the i-th task, I represents the adjustment factor, SSI iRepresents the scheduling selection index of the i-th task. When the scheduling selection index is greater than the preset scheduling threshold, the task is divided into task set 1 using the priority scheduling algorithm. When the scheduling selection index is less than or equal to the preset scheduling threshold, the task is divided into task set 2 using the shortest processing time first algorithm.

[0032] All tasks in task set one are sorted in descending order according to the values ​​of the scheduling selection index, and all tasks in task set two are sorted in ascending order according to the values ​​of the scheduling selection index.

[0033] Technical effects and advantages of the present invention:

[0034] Through the resource scheduling and optimization module, the present invention can select a preset static resource allocation table or a dynamic resource allocation table based on the results of load analysis to dynamically schedule the hardware resources in the system. This mechanism effectively improves resource utilization, allowing the system to run efficiently under high load conditions, while avoiding excessive resource allocation under low load conditions and reducing power consumption.

[0035] Through the signal characteristic analysis module and the fluctuation prediction module, the present invention can extract and predict the characteristic fluctuation of the signal in real time, and judge whether to trigger the hardware reconstruction mechanism based on the comprehensive fluctuation value. This mechanism ensures that the system can respond quickly when the signal changes greatly, and ensures the real-time and accuracy of signal processing.

[0036] The present invention supports the priority scheduling algorithm based on the scheduling selection index and the shortest processing time priority algorithm, so that the system can flexibly adjust the task execution order according to the importance of the task and the processing time. This scheduling method improves the task execution efficiency of the system, reduces the average waiting time of the task, and avoids the "hunger" phenomenon of resource allocation during the task execution process.

[0037] The present invention introduces an adaptive dynamic adjustment mechanism, which can automatically adjust the hardware configuration when the system performance does not meet the standard, ensure that the signal processing performance always meets the expected target, and avoid the performance degradation caused by system load fluctuations or signal changes. Based on the partial reconfiguration characteristics of FPGA, the hardware resources can be dynamically adjusted during the operation of the system. This adaptive hardware reconstruction mechanism ensures that the system can adjust the resource configuration according to the real-time changes of the signal, avoids the waste of resources caused by fixed resource allocation, and improves the processing efficiency and flexibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to facilitate understanding by those skilled in the art, the present invention is further described below in conjunction with the accompanying drawings;

[0039] Figure 1 It is a schematic diagram of the signal processing detection system based on FPGA architecture in the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Example 1

[0042] The signal processing detection system based on FPGA architecture includes signal acquisition module, signal characteristic analysis module, fluctuation prediction module, adaptive hardware reconstruction module, resource scheduling and optimization module;

[0043] The signal acquisition module is used to collect input signal data in real time, obtain signal acquisition data sets and transmit them to the signal characteristic analysis module; the signal acquisition module continuously collects raw signals from the environment, which may include analog or digital signals, and uses ADC (analog-to-digital converter) to convert analog signals. The collected data will be updated at a certain frequency according to system requirements and transmitted to subsequent analysis modules.

[0044] The signal characteristic analysis module is used to extract characteristic features from the signal acquisition data set, obtain multiple characteristic feature extraction sets and transmit them to the fluctuation prediction module; the signal characteristic analysis module performs multi-dimensional analysis on the input signal data, extracts key characteristics (such as signal amplitude, frequency, phase, power spectral density), and the extracted useful signal information is the basis for subsequent fluctuation prediction.

[0045] The fluctuation prediction module is used to build the corresponding AR model based on the historical time series of each feature extraction set and deploy the application, and determine whether to trigger the hardware reconstruction mechanism based on the application results; the fluctuation prediction module uses the historical time series data of each feature extraction set to build the corresponding autoregressive (AR) model. The AR model predicts the future change trend of the signal by analyzing historical data and tracks the fluctuation of the signal in real time. By predicting the fluctuation amplitude of the signal, the module can evaluate whether there is an abnormality or major change in the signal, so as to decide whether to trigger the subsequent hardware reconstruction mechanism. Through effective fluctuation prediction, it is possible to react in advance before the signal changes, improving the response speed and adaptability of the system.

[0046] The adaptive hardware reconstruction module is used to adaptively and dynamically adjust the FPGA hardware configuration when the hardware reconstruction mechanism is triggered, and monitor the adjustment results to monitor whether the preset target performance parameters of signal processing have improved as expected, and decide whether to keep the current configuration or reconfigure; when the fluctuation prediction module determines that the signal characteristic change exceeds the threshold, the adaptive hardware reconstruction module is started to reallocate the hardware configuration of the FPGA (such as logic units, DSP units, storage resources, etc.). The module's built-in adaptive strategy can adjust the hardware configuration according to real-time signal requirements to improve processing efficiency. For example, when the signal frequency increases, the system may need more DSP units to handle more calculations. The adjusted configuration will evaluate its effect by monitoring the target performance parameters (such as processing delay, throughput, power consumption, etc.). If the performance parameters do not meet expectations, the system will reconfigure again until the optimization effect meets the requirements. The FPGA partial reconfiguration function enables the system to dynamically adjust and optimize the use of hardware resources without stopping work.

[0047] The resource scheduling and optimization module is used to dynamically allocate and schedule hardware resources for the final result of the reconfiguration to ensure that the system's resource utilization is optimal. The resource scheduling and optimization module receives the reconfiguration results from the adaptive hardware reconstruction module and schedules the hardware resources based on information such as the priority and processing time of the task. This module dynamically allocates hardware resources through scheduling algorithms, such as the priority scheduling algorithm or the shortest processing time priority algorithm, to achieve optimal system performance. According to the size of the scheduling selection index, the module can choose to arrange tasks in descending order to prioritize high-priority tasks, or arrange tasks in ascending order to prioritize tasks with a short estimated time, maximizing the system's processing capacity. By reasonably allocating hardware resources, this module can maintain efficient operation of the system under different load conditions and avoid resource waste or processing bottlenecks.

[0048] The signal characteristic analysis module extracts characteristic features by extracting the amplitude, frequency, phase and power spectrum density of the signal. In signal processing, characteristic features refer to key indicators or values ​​in a signal that can reflect its main behavior or attributes. These features are extracted from the original signal data for further analysis, modeling and prediction. The signal characteristic analysis module extracts characteristic features by extracting specific and useful characteristic values, such as amplitude, frequency, phase and power spectrum density, from the time series data of the signal.

[0049] Characteristic features are the core attributes of a signal, which are used to describe the essential characteristics of a signal and can help the system better understand and predict the behavior of the signal. After extracting these features, they can be used for model building, fluctuation prediction, signal classification or decision making.

[0050] Specific examples of characteristic features: Amplitude represents the strength or size of a signal at a certain moment. Amplitude is the most direct feature of a signal and reflects the height of the signal waveform. Through amplitude extraction, the instantaneous strength or change trend of the signal can be determined, and it is often used to analyze the energy level of the signal. Frequency represents the number of vibrations of a signal in a certain period of time, usually in Hertz (Hz). Frequency is a characteristic of the periodicity of a signal, which can indicate the vibration rate of the signal. Frequency extraction is usually performed through Fourier transform (FFT), which can help analyze the time-frequency characteristics of the signal and is suitable for processing periodic signals or detecting frequency changes. Fourier transform is a prior art and will not be described here. Phase represents the position of the signal waveform within its period and is a measure of time offset, usually expressed in angles. Phase extraction is used to analyze the time alignment or offset of a signal, and is particularly suitable for phase difference analysis between multiple signals. For phase modulated signals in communication systems, phase is a critical feature. Power spectral density represents the power distribution of a signal per unit frequency in the frequency domain. It is used to analyze the energy distribution of a signal at different frequencies and can help identify which frequency components dominate the signal. It is widely used in signal noise analysis, filter design, and frequency domain characteristic analysis.

[0051] The main purpose of extracting these characteristic features is to convert complex raw signal data into simple, meaningful numerical representations for subsequent analysis and processing. The extraction of these features is the basis of signal analysis and is usually used for the following purposes: By analyzing these features, the system can predict the future behavior of the signal, such as using an AR model to predict features at future moments. Characteristic feature extraction helps to detect abnormal fluctuations in the signal, thereby triggering adaptive hardware reconstruction. By extracting and analyzing different characteristic features, the system can understand the dynamic changes of the signal in multiple dimensions and improve the accuracy and robustness of the signal processing system.

[0052] It should be noted that the AR model (autoregressive model) is indeed a prediction method based on time series, which predicts future values ​​by analyzing past signal values. Although the AR model is usually used to predict the amplitude or value of the time series, through appropriate data processing and transformation, that is, the preprocessing operations mentioned below, the frequency, phase and power spectral density of the signal can also be predicted by the AR model.

[0053] Signal Amplitude: Amplitude is a straightforward feature of a time series, so it is very suitable for forecasting using an AR model. The AR model predicts the amplitude of the next moment by analyzing the amplitude of the previous moment.

[0054] Signal frequency: Although frequency is a frequency domain feature of a signal, the instantaneous frequency can be extracted from the time domain signal through Fourier transform (FFT), and then the instantaneous frequency is used as a time series to apply the AR model for prediction. For example, the instantaneous frequency series is obtained using short-time Fourier transform (STFT).

[0055] Signal phase: Phase is another feature in the frequency domain. By extracting the phase information of the signal (for example, obtaining the phase angle through Hilbert transform or FFT), a time series can be formed and the AR model can be applied for prediction.

[0056] Power spectral density (PSD): Power spectral density is also a frequency domain feature. Time series power spectral density data can be obtained through FFT or other frequency domain conversion methods. AR modeling is performed on these data.

[0057] Specifically, the logic of establishing the AR model is: obtain the characteristic values ​​of the target characteristic features at different time points, perform preprocessing operations and generate a time series data set, and then obtain the cycle length s, specifically: perform FFT transformation on the time series signal to obtain the frequency domain signal, and in the frequency domain diagram, find the frequency corresponding to the peak value, which represents the main oscillation frequency of the signal, and its product with the cycle length s is one;

[0058] In some complex signals, there may be multiple cycles or the signal noise is large, and a single autocorrelation function or FFT analysis may not be accurate enough. In this case, the maximum likelihood estimation method can be used to determine the cycle length that best matches the signal characteristics.

[0059] Specific steps: Define a hypothetical model, assume that the signal is periodic, and use parameter s (cycle length) to build the model. By maximizing the likelihood function of the model on the given data, estimate the cycle length s that best fits the actual signal. Continuously adjust s to maximize the value of the likelihood function, and the final s value is the optimal cycle length of the signal.

[0060] The Bayesian Information Criterion selection criteria are used to select the optimal autoregressive order p and seasonal autoregressive order P. The Bayesian Information Criterion avoids overfitting problems by considering the likelihood function of the model and the complexity of the model (i.e. the number of parameters). The core idea of ​​BIC is to select a structure with fewer parameters and a simpler model while ensuring that the model can fit the data well. The formula is as follows:

[0061] BIC=-2*ln(R)+Q*ln(N), Q is the number of free parameters in the model, indicating the complexity of the model, R is the maximum likelihood estimate of the model, indicating the degree of fit of the model to the data, N is the number of samples, -2*ln(R) is used to measure the goodness of fit of the model to the data, the better the fit, the smaller the value, Q*ln(N) is used to penalize the complexity of the model, the more parameters, the higher the complexity, and the larger the penalty term. The smaller the BIC value, the better the model is in balancing the goodness of fit and complexity, so the model with the smallest BIC value is selected. In the seasonal autoregressive model, BIC can be used to select the optimal autoregressive order p and seasonal autoregressive order P. By trying different combinations of p and P, calculating the BIC value of each combination, and selecting the combination with the smallest BIC value as the optimal model, it is ensured that the model has both good fitting ability and avoids excessive complexity.

[0062] The AR model (essentially a seasonal autoregressive model) is established because: in the communication system, some signal processing tasks may have a fixed time division multiplexing mode, and the SAR model can better capture the characteristics of signal periodic changes and improve the dynamic adjustment accuracy of hardware resources. Specific formula:

[0063] φ i The coefficient of the autoregressive part indicates the influence of the characteristic value x(ti) at time ti in the past on the current characteristic value x(t), θ j represents the coefficient of the seasonal AR part, which represents the influence of the characteristic value x(t-sj) at the past time t-sj on the current characteristic value x(t). c is a constant term, ∈(t) is a white noise term, x(t) represents the characteristic value at time t, and the coefficient φ of the autoregressive part is determined using maximum likelihood estimation i , the coefficient of the seasonal AR part θ j When the performance of the established AR model formula reaches the expected level, it will be deployed and applied.

[0064] The application results are obtained through the following logic:

[0065] For each characteristic feature, the sliding window average method is used to detect signal fluctuations:

[0066] For each time t, take the window size as N and calculate the average value M in the window k :

[0067] x(i) represents the characteristic value at time i, k is the starting position index of the sliding window, M k is the sliding average at the kth position;

[0068] Then calculate the absolute value of the difference between the current characteristic value and the window average value to get the fluctuation value, and then assign the characteristic feature influence coefficient wi corresponding to each fluctuation value, and then perform weighted average of all fluctuation values ​​to get the comprehensive fluctuation value W avg . Comprehensive fluctuation value W avg The calculation formula is: ΔDi represents the fluctuation value corresponding to characteristic feature type i.

[0069] The sliding window average method can effectively smooth short-term fluctuations of the signal, remove noise, and retain trends. By calculating the sliding window average of the signal characteristics at each time t, the fluctuations within a specific period can be analyzed more smoothly to avoid misleading information caused by instantaneous fluctuations. By calculating the absolute value of the difference between the current characteristic value and the average value in the sliding window, the instantaneous fluctuation of the signal can be obtained. This fluctuation value reflects the difference between the characteristics of the signal at the current moment and the short-term trend, so that the fluctuation amplitude and change trend of the signal can be more intuitively represented. It dynamically reflects the changes of the signal at each moment relative to the past.

[0070] Different characteristic features (such as the amplitude, frequency, phase, and power spectral density of the signal) have different effects on the overall fluctuation of the signal. Therefore, assigning a characteristic feature influence coefficient corresponding to each fluctuation value can reflect the importance of each feature to the overall fluctuation of the signal. For example, if a certain feature is more sensitive to system performance, it can be given a higher weight. The system can calculate the comprehensive fluctuation value by weighted averaging different characteristics. The comprehensive fluctuation value not only considers the fluctuation of each characteristic individually, but also reflects the degree of their impact on the overall system. Through the comprehensive fluctuation value, the system can more accurately evaluate the impact of signal changes and decide whether to perform hardware reconstruction or resource scheduling optimization. Because this method comprehensively considers the fluctuations of multiple characteristic features, it can more reliably determine whether further adjustments are needed, rather than making judgments based on a single characteristic. This method can prevent the reconstruction mechanism from being falsely triggered when a single characteristic fluctuates too much, and can also ensure that when multiple characteristic features fluctuate significantly at the same time, the system can respond quickly and take action.

[0071] By assigning weights to different characteristics, you can adjust the sensitivity of the system according to specific application scenarios. For example, in some cases, the frequency change of the signal may be more important than the amplitude change, so the frequency characteristic can be given a higher influence coefficient. The system can adaptively adjust the sensitivity to changes in different characteristics to better match different signal processing scenarios.

[0072] Judging whether to trigger the hardware reconstruction mechanism based on application results means:

[0073] Obtain the comprehensive fluctuation value and compare it with the preset mechanism trigger threshold. If the comprehensive fluctuation value is greater than the preset mechanism trigger threshold, the hardware reconstruction mechanism is triggered. If the comprehensive fluctuation value is less than or equal to the preset mechanism trigger threshold, the hardware reconstruction mechanism is not triggered. The preset mechanism trigger threshold is a threshold set in the system to determine whether the current comprehensive fluctuation value exceeds the normal fluctuation range. This threshold is usually set based on historical data, experience or the tolerance range of signal fluctuations in a specific application scenario to avoid frequent triggering of hardware reconstruction due to small fluctuations, while ensuring timely response to important fluctuations. By comparing the comprehensive fluctuation value with the preset threshold, it is possible to prevent unnecessary hardware reconstruction caused by small, instantaneous signal fluctuations, reduce frequent system adjustments, and maintain system stability. When the signal fluctuation obviously exceeds the threshold, the system can respond quickly and improve the signal processing capability through hardware reconstruction to avoid a decrease in signal processing quality or an increase in delay. When adaptively and dynamically adjusting the FPGA hardware configuration, based on the partial reconfiguration feature of the FPGA, the hardware configuration parameter combination in use is dynamically adjusted without affecting the normal operation of other hardware parts. The adaptive hardware reconstruction module is dynamically adjusted based on a preset adaptive adjustment strategy, which is a common practice in the prior art, especially for systems using the partial reconfiguration feature of the FPGA. Adaptive adjustment strategy refers to a set of logic preset in the system, which is used to guide the system on how to dynamically adjust the hardware configuration of FPGA when hardware reconstruction is triggered. These strategies are usually based on signal characteristics and changes in real-time requirements, and can adaptively reconfigure specific hardware (such as hardware configuration parameter combinations composed of logic units, DSP units, etc.) to optimize signal processing performance. FPGA partial reconfiguration feature: Partial reconfiguration technology is a key feature in existing FPGA technology. It allows part of the FPGA hardware resources to be reconfigured during system operation without shutting down or restarting other hardware parts. It can dynamically adjust the hardware configuration in use while keeping the rest of the system functioning normally. The adaptive hardware reconstruction module implements the function of dynamic resource adjustment based on these existing partial reconfiguration technologies and adaptive adjustment strategies. Since this is a technology widely used in FPGA applications, the specific strategy details and implementation can be regarded as existing technology and will not be described in detail. This approach ensures that the system can optimize the use of hardware resources in real time when signal processing requirements change, while ensuring the normal execution of other tasks, in line with the design specifications of existing technology.

[0074] Monitor whether the preset target performance parameters of signal processing are improved to meet the expected preset target performance parameters. The preset target performance parameters are set according to different application scenarios and can be indicators such as data throughput and data processing delay value.

[0075] The resource scheduling and optimization module is used to dynamically allocate the final result of the reconfiguration, which means: performing load analysis based on the current resource usage, and determining whether to replace the preset static resource allocation table with a dynamic resource allocation table according to the load analysis result.

[0076] The preset static resource allocation table refers to a fixed, pre-set resource allocation plan. The system allocates and schedules resources according to this table when it starts or in the early stages. The static resource allocation table will not be dynamically adjusted according to the real-time load situation. It is suitable for scenarios where the task load is relatively uniform and does not change much.

[0077] Contents of the static resource allocation table: Hardware resources (such as FPGA logic units, DSP units, and storage resources) are allocated to different tasks or functional modules according to pre-set rules. Each task or module always uses a fixed amount of resources when the system is running, regardless of the current system load and task changes.

[0078] For example: Assume that the system has three tasks (Task A, Task B, Task C), and the FPGA has the following resources: 1000 logic units; 100 DSP units; 200MB of storage resources; in the static resource allocation table, these resources can be fixedly allocated in the following way: Task A: 300 logic units, 30 DSP units, 50MB of storage. Task B: 400 logic units, 40 DSP units, 100MB of storage. Task C: 300 logic units, 30 DSP units, 50MB of storage. In this allocation table, each task always gets fixed resources, and the resources will not adjust as the task load changes. Regardless of whether one task is underloaded or another task is overloaded, the resources are fixedly allocated.

[0079] When the system detects an unbalanced load, it may be necessary to replace the static resource allocation table with a dynamic resource allocation table. Through the dynamic resource allocation mechanism, it can be flexibly adjusted according to the real-time task requirements and load conditions. This dynamic mechanism can better utilize resources and avoid resource waste or insufficient resources. For example, if the load of task A decreases and the load of task B increases, the system can allocate part of the resources of task A to task B through the dynamic allocation mechanism to ensure efficient use of resources. This dynamic mechanism is more suitable for scenarios with high real-time requirements and large load changes in signal processing systems.

[0080] Load analysis refers to:

[0081] The following calculations are performed based on current resource usage:

[0082] R iIndicates the utilization rate of the i-th resource, indicating the current occupancy of a certain type of resource, usually expressed as a percentage, such as processor utilization, memory utilization, etc. max It represents the maximum allowable load value, that is, the maximum allowable load of the resource, such as the highest utilization rate at which the resource can run safely. n represents the number of resource types, indicating the number of different types of resources in the system, such as the number of logic units, DSP units, storage, etc. α represents the load balancing coefficient. If the load balancing coefficient α exceeds the set load imbalance threshold, the resources need to be reallocated. This formula is used to evaluate whether the current resources of the system are used evenly. If the load balancing coefficient exceeds the set threshold, it means that some resources in the system are overloaded or allocated unreasonably, which prompts the system to reallocate resources. The calculation system can promptly discover the bottleneck of resource usage or load imbalance. For example, if some resources are overused and other resources are underused, the system can improve the overall load situation by reallocating resources to ensure maximum system operation efficiency. The calculation of the load balancing coefficient can help the system avoid overloading of certain types of resources, reduce the risk of failure, and improve the stability and reliability of the system.

[0083] When scheduling hardware resources, a preset priority scheduling algorithm or a shortest processing time first algorithm is used. The priority scheduling algorithm determines the order in which tasks are processed based on the priority of each task. Each task is assigned a priority weight, and tasks with higher weights are executed first. The priority of a task can be determined based on the importance of the task, the time limit for task execution, or the impact of the task on the system. In the system, the priority scheduling algorithm processes high-priority tasks first to ensure that these tasks can be completed as soon as possible and avoid being blocked by low-priority tasks.

[0084] Advantages: High flexibility: The priority can be adjusted flexibly according to the importance of the task, so that the key tasks are executed first. Fast response: High-priority tasks can respond quickly, improving the system's ability to handle key tasks. Disadvantages: It may cause the "starvation" phenomenon of low-priority tasks: that is, low-priority tasks may not be executed for a long time, especially when there are many high-priority tasks.

[0085] The shortest processing time first algorithm determines the execution order based on the estimated processing time of the tasks. The system will first execute the tasks with the shortest estimated processing time, and the estimated processing time of the tasks determines their priority execution order. This algorithm aims to minimize the average waiting time of the system, because short tasks can be executed quickly without delays caused by long tasks occupying system resources.

[0086] Advantages: Maximize system throughput: Short tasks can be executed quickly, so that more tasks can be completed in a unit of time. Reduce average waiting time: By giving priority to shorter tasks, short tasks are prevented from waiting for a long time due to the execution of long tasks. Disadvantages: Not suitable for scenarios with dense long tasks: If there are many long tasks in the system, the priority execution of short tasks may delay long tasks for a long time, affecting the real-time performance of the system.

[0087] Priority scheduling algorithm and shortest processing time priority algorithm are both classic categories of scheduling algorithms and belong to the existing technology. In operating systems, real-time control systems and hardware resource scheduling, these two algorithms are widely used in task scheduling and resource allocation. Their basic principles and usage methods have been widely explained and applied in existing literature and technology. Dynamic resource table refers to the resource scheduling scheme of the two algorithms.

[0088] The scheduling logic when scheduling hardware resources is:

[0089] represents the importance weight of the i-th task, represents the expected completion time of the i-th task, I represents the adjustment factor, SSI i Represents the scheduling selection index of the i-th task. When the scheduling selection index is greater than the preset scheduling threshold, the task is divided into task set 1 using the priority scheduling algorithm. When the scheduling selection index is less than or equal to the preset scheduling threshold, the task is divided into task set 2 using the shortest processing time first algorithm.

[0090] All tasks in task set one are sorted in descending order according to the values ​​of the scheduling selection index, and all tasks in task set two are sorted in ascending order according to the values ​​of the scheduling selection index.

[0091] When selecting a priority scheduling algorithm, the scheduling selection index is calculated by the ratio of the priority weight to the estimated processing time, i.e., the expected completion time. The larger the index, the more important the task is, or its estimated processing time is relatively short, so giving priority to the task helps improve the overall efficiency of the system. Prioritizing tasks with high importance ensures that high-priority tasks are not delayed or blocked by low-priority tasks, thus avoiding long waits for critical tasks. By giving priority to tasks with a larger scheduling selection index, the processing time can be optimized while processing high-priority tasks, maximizing the system's response to task priorities. By sorting in descending order, it can be ensured that the system first processes tasks with lower resource consumption requirements but higher priorities, thereby balancing the importance of tasks and the efficiency of system resource utilization.

[0092] When the shortest processing time first algorithm is selected, the scheduling selection index is arranged in ascending order: When the shortest processing time first algorithm is selected, the scheduling selection index is mainly used to weigh the trade-off between the priority of the task and the estimated processing time. The shortest processing time first algorithm pays more attention to the processing time of the task, so the tasks with a shorter estimated processing time should be processed first in the processing order. By processing the tasks with a shorter estimated processing time first, a part of the tasks can be completed quickly, freeing up more resources to process subsequent longer tasks, thereby maximizing the throughput of the system. Short task priority can reduce the average waiting time of tasks in the system and prevent short tasks from being blocked by long tasks. By arranging in ascending order, the system can avoid the delay of shorter tasks by longer tasks and reduce the task accumulation phenomenon in the system.

[0093] By arranging the scheduling selection index in descending order, important tasks are ensured to be processed first, which fully reflects the priority of tasks and helps to improve the efficiency of key task processing. By arranging the scheduling selection index in ascending order, tasks with short processing time are ensured to be completed first, reducing the overall processing delay and waiting time, and optimizing system throughput. The method of sorting tasks based on the scheduling selection index can ensure the maximum efficiency of system operation.

[0094] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0095] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0096] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0097] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0098] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A signal processing detection system based on FPGA architecture, characterized in that: It includes signal acquisition module, signal characteristic analysis module, fluctuation prediction module, adaptive hardware reconstruction module, resource scheduling and optimization module; The signal acquisition module is used to collect input signal data in real time, obtain the signal acquisition data set and transmit it to the signal characteristic analysis module; The signal characteristic analysis module is used to extract characteristic features from the signal acquisition data set, obtain multiple characteristic feature extraction sets and transmit them to the fluctuation prediction module; The fluctuation prediction module is used to build the corresponding AR model based on the historical time series of each feature extraction set and deploy the application, and determine whether to trigger the hardware reconstruction mechanism based on the application result, that is, the comprehensive fluctuation value; Determining whether to trigger the hardware reconstruction mechanism refers to: Obtain the comprehensive fluctuation value and compare it with the preset mechanism trigger threshold. If the comprehensive fluctuation value is greater than the preset mechanism trigger threshold, the hardware reconstruction mechanism is triggered. If the comprehensive fluctuation value is less than or equal to the preset mechanism trigger threshold, the hardware reconstruction mechanism is not triggered. The adaptive hardware reconfiguration module is used to adaptively and dynamically adjust the FPGA hardware configuration when the hardware reconfiguration mechanism is triggered, and monitor the adjustment results to monitor whether the preset target performance parameters of signal processing have improved as expected, and decide whether to keep the current configuration or reconfigure; The resource scheduling and optimization module is used to dynamically allocate and schedule hardware resources for the final result of reconfiguration to ensure that the system's resource utilization reaches the optimal state.

2. The signal processing detection system based on FPGA architecture according to claim 1 is characterized in that: The signal characteristic analysis module performs characteristic feature extraction, which refers to extracting the amplitude, frequency, phase and power spectrum density of the signal respectively.

3. The signal processing detection system based on FPGA architecture according to claim 2 is characterized in that: The logic of establishing the AR model is: Obtain the characteristic values ​​of the target characteristic at different time points, perform preprocessing operations and generate a time series data set, then obtain the cycle length s, use the Bayesian information criterion selection standard to select the optimal autoregressive order p and seasonal autoregressive order P, and establish the AR model formula: ; Represents the coefficient of the autoregressive part, indicating the past Characteristic value at time For the current characteristic value The degree of influence represents the coefficient of the seasonal AR part, indicating the past Characteristic value at time For the current characteristic value The influence of, c is a constant term, is the white noise term, Represents the characteristic value at time t, and uses maximum likelihood estimation to determine the coefficients of the autoregressive part , the coefficient of the seasonal AR part When the performance of the established AR model formula reaches the expected level, it will be deployed and applied.

4. The signal processing detection system based on FPGA architecture according to claim 3 is characterized in that: The application results are obtained through the following logic: For each characteristic feature, the sliding window average method is used to detect signal fluctuations: For each time t, take the window size as N and calculate the average value within the window : ; represents the characteristic value at time i, k is the starting position index of the sliding window, is the sliding average at the kth position; Then the absolute value of the difference between the current characteristic value and the window average is calculated to obtain the fluctuation value, and then the characteristic feature influence coefficient corresponding to each fluctuation value is assigned, and then all fluctuation values ​​are weighted averaged to obtain the comprehensive fluctuation value.

5. The signal processing detection system based on FPGA architecture according to claim 4 is characterized in that: Adaptive dynamic adjustment of FPGA hardware configuration is based on the partial reconfiguration characteristics of FPGA, and the hardware configuration parameter combination in use is dynamically adjusted without affecting the normal operation of other hardware parts.

6. The signal processing detection system based on FPGA architecture according to claim 5, characterized in that: The resource scheduling and optimization module is used to dynamically allocate the final results of the reconfiguration: A load analysis is performed based on the current resource usage, and a determination is made based on the load analysis result whether to replace the preset static resource allocation table with a dynamic resource allocation table.

7. The signal processing detection system based on FPGA architecture according to claim 6 is characterized in that: Load analysis refers to: The following calculations are performed based on current resource usage: ; represents the utilization rate of the i-th resource, Indicates the maximum allowable load value, n indicates the number of resource types, Indicates the load balancing coefficient. If the load balancing coefficient If the load imbalance threshold is exceeded, resources need to be reallocated.

8. The signal processing detection system based on FPGA architecture according to claim 7, characterized in that: When scheduling hardware resources, use the preset priority scheduling algorithm or the shortest processing time first algorithm.

9. The signal processing detection system based on FPGA architecture according to claim 8, characterized in that: The scheduling logic when scheduling hardware resources is: ; represents the importance weight of the i-th task, represents the expected completion time of the i-th task, represents the adjustment factor, Represents the scheduling selection index of the i-th task. When the scheduling selection index is greater than the preset scheduling threshold, the task is divided into task set 1 using the priority scheduling algorithm. When the scheduling selection index is less than or equal to the preset scheduling threshold, the task is divided into task set 2 using the shortest processing time first algorithm. All tasks in task set one are sorted in descending order according to the values ​​of the scheduling selection index, and all tasks in task set two are sorted in ascending order according to the values ​​of the scheduling selection index.

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