Quantum processor

Abstract

The invention provides a quantum processor, which comprises a signal source core particle and a mixed core particle, and is characterized in that the signal source core particle is used for generating an optical signal, and the mixed core particle is used for data processing and storage; and the signal source core particle is connected with the mixed core particle through an optical communication link. According to the quantum processor provided by the embodiment of the invention, the signal source core particle is connected with the mixed core particle through the optical communication link, so that the rate and bandwidth of data transmission between the core particles are improved, and the performance of the quantum processor is further improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a quantum processor. Background Art

[0002] Quantum computing has an exponential acceleration advantage over classical computers in processing certain specific problems, providing solutions to the large-scale computing problems required for cryptanalysis, weather forecasting, oil exploration, drug design, etc.

[0003] The development of quantum core packaging technology is of great significance to fields such as quantum computing, and can improve the performance, stability, and scalability of quantum chips. However, the technology is still under development and improvement, and faces some challenges, such as maintaining the coherence of quantum bits, reducing transmission delays, reducing the impact of noise during the packaging process, and improving the accuracy and reliability of packaging. Therefore, how to improve quantum core packaging technology and obtain quantum processors with better performance has become an important issue that needs to be solved in this field. Summary of the invention

[0004] In view of the problems in the prior art, an embodiment of the present invention provides a quantum processor that can at least partially solve the problems in the prior art.

[0005] The present invention provides a quantum processor, comprising a signal source core particle and a hybrid core particle, wherein:

[0006] The signal source core particle is used to generate an optical signal, and the hybrid core particle is used to process and store data; the signal source core particle is connected to the hybrid core particle via an optical communication link.

[0007] Furthermore, there are multiple hybrid core particles, which are connected in series. The signal source core particle communicates with the first hybrid core particle of the multiple hybrid core particles connected in series through the optical communication link, and adjacent hybrid core particles communicate with each other through the first optical signal transmission link.

[0008] Furthermore, at least two hybrid core particles among the plurality of hybrid core particles share one optical signal output link.

[0009] Furthermore, the signal source core comprises a light source, an optical amplifier and an optical modulator connected in sequence, and the output end of the optical modulator is connected to the input end of the optical communication link.

[0010] Furthermore, there are multiple hybrid core particles, which are connected in parallel. The signal source core particle is optically connected to each hybrid core particle respectively, and the multiple hybrid core particles in parallel communicate with each other through a second optical signal transmission link. Each hybrid core particle corresponds to an optical signal output link.

[0011] Furthermore, the signal source core comprises a light source, an optical amplifier, an optical power distributor and a plurality of optical modulators, wherein:

[0012] The light source, the optical amplifier and the optical power distributor are connected in sequence, the optical power distributor is connected to each optical modulator respectively, each optical modulator corresponds to a hybrid core particle, and each optical modulator is optically communicated with the corresponding hybrid core particle.

[0013] Furthermore, the signal source core comprises a plurality of optical signal generating units, each optical signal generating unit comprises a light source, an optical amplifier and an optical modulator connected in sequence, each optical signal generating unit corresponds to a hybrid core, and the optical modulator of each optical signal generating unit is optically connected to the corresponding hybrid core.

[0014] Furthermore, the hybrid core comprises a first optical engine, a computing core and a second optical engine, and the computing core is electrically connected to the first optical engine and the second optical engine respectively; the first optical engine and the second optical engine are used to convert received optical signals into electrical signals for output, or convert received electrical signals into optical signals for output.

[0015] Furthermore, there are multiple computing core particles, and each computing core particle is electrically connected to the first light engine and the second light engine respectively.

[0016] Further, the first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, and the second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit;

[0017] The first photonic integrated circuit is arranged at a first preset position of the packaging substrate, and the second photonic integrated circuit is arranged at a second preset position of the packaging substrate, and the adapter plate is bonded to the first photonic integrated circuit through a seventeenth electrical bump and bonded to the second photonic integrated circuit through an eighteenth electrical bump;

[0018] The first electronic integrated circuit is bonded to the adapter board through the nineteenth electrical bump and the twentieth electrical bump, and the second electronic integrated circuit is bonded to the adapter board through the twenty-first electrical bump and the twenty-second electrical bump; the first electronic integrated circuit is electrically connected to the first photonic integrated circuit through the nineteenth electrical bump, the first conductive portion and the seventeenth electrical bump; the second electronic integrated circuit is electrically connected to the second photonic integrated circuit through the twenty-second electrical bump, the second conductive portion and the eighteenth electrical bump;

[0019] Each computing core is bonded to the adapter board through the corresponding twenty-third electrical bump and the twenty-fourth electrical bump; the first electrical communication link corresponding to each computing core is connected to the twenty-third electrical bump corresponding to each computing core to realize the electrical connection between each computing core and the first electronic integrated circuit; the second electrical communication link corresponding to each computing core is connected to the twenty-first electrical bump and the twenty-fourth electrical bump corresponding to each computing core to realize the electrical connection between each computing core and the second electronic integrated circuit;

[0020] The first electrical communication link comprises a third conductive portion, a seventh electrical interconnection line and a fourth conductive portion, or an eighth electrical interconnection line, which are connected in sequence; the third conductive portion and the fourth conductive portion penetrate the adapter board, the seventh electrical interconnection line is arranged on a side surface of the adapter board facing the packaging substrate; the eighth electrical interconnection line is arranged on a side surface of the adapter board facing the computing chip;

[0021] The second electrical communication link includes a fifth conductive part, a ninth electrical interconnection line and a sixth conductive part, or a tenth electrical interconnection line, which are connected in sequence; the fifth conductive part and the sixth conductive part pass through the adapter board, and the ninth electrical interconnection line is arranged on a side surface of the adapter board facing the packaging substrate; the tenth electrical interconnection line is arranged on a side surface of the adapter board facing the computing chip.

[0022] Further, the first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, and the second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit;

[0023] The first electronic integrated circuit is bonded to the first surface of the interposer through the twenty-fifth electrical bump and the twenty-sixth electrical bump, and the first photonic integrated circuit is bonded to the second surface of the interposer through the twenty-seventh electrical bump; the second electronic integrated circuit is bonded to the first surface of the interposer through the twenty-eighth electrical bump and the twenty-ninth electrical bump, and the second photonic integrated circuit is bonded to the second surface of the interposer through the thirtieth electrical bump;

[0024] The seventh conductive portion connects the twenty-seventh electrical bump and the twenty-sixth electrical bump to realize the electrical connection between the first electronic integrated circuit and the first photonic integrated circuit, and the seventh conductive portion passes through the adapter board; the eighth conductive portion connects the thirtieth electrical bump and the twenty-eighth electrical bump to realize the electrical connection between the second electronic integrated circuit and the second photonic integrated circuit, and the eighth conductive portion passes through the adapter board; the adapter board is fixed on the packaging substrate through the third support column;

[0025] Each computing core is bonded to the second surface of the adapter board through the corresponding thirty-first electrical bump and thirty-second electrical bump; each computing core is electrically connected to the first electronic integrated circuit through the corresponding thirty-first electrical bump, the ninth conductive portion, the tenth electrical interconnection line, and the twenty-fifth electrical bump; each computing core is electrically connected to the second electronic integrated circuit through the corresponding thirty-second electrical bump, the tenth conductive portion, the eleventh electrical interconnection line, and the twenty-ninth electrical bump.

[0026] Furthermore, the computing core comprises a global control chip and at least one processing module, and the global control chip is electrically connected to each processing module.

[0027] Furthermore, the processing module includes a computing unit and a storage unit, the computing unit includes at least one first control chip and a corresponding quantum chip, and the storage unit includes at least one second control chip and a corresponding memory.

[0028] Furthermore, the processing module includes a third control chip, a quantum chip and at least one memory, the third control chip is electrically connected to the quantum chip, and the third control chip is electrically connected to each memory respectively.

[0029] Furthermore, the processing module includes a plurality of fourth control chips and corresponding quantum chips and memories, and each fourth control chip is electrically connected to the corresponding quantum chip and memory.

[0030] Furthermore, a first optical engine is arranged at a third preset position of the packaging substrate, and a second optical engine is arranged at a fourth preset position of the packaging substrate, the computing core is bonded to the packaging substrate through a thirty-third electrical bump and a thirty-fourth electrical bump, a first electrical interconnection line and a second electrical interconnection line are arranged on the packaging substrate, the first electrical interconnection line connects the thirty-third electrical bump and the first optical engine, and the second electrical interconnection line connects the thirty-fourth electrical bump and the second optical engine.

[0031] Further, the computing core is bonded to the first light engine through a first electrical bump, and bonded to the second light engine through a second electrical bump, the first light engine is bonded to a first coupler disposed on the packaging substrate through a first optical bump, and the second light engine is bonded to a second coupler disposed on the packaging substrate through a second optical bump;

[0032] A first optical waveguide and a second optical waveguide are arranged on the packaging substrate, the first optical waveguide is connected to the first coupler, and the second optical waveguide is connected to the second coupler; the first optical engine performs optical communication through the first optical bump, the first coupler and the first optical waveguide; the second optical engine performs optical communication through the second optical bump, the second coupler and the second optical waveguide;

[0033] An eleventh conductive part is provided on the first light engine, and the eleventh conductive part is connected to the first electrical bump; a twelfth conductive part is provided on the second light engine, and the twelfth conductive part is connected to the second electrical bump.

[0034] Furthermore, the first light engine and the second light engine are arranged on the upper surface of the packaging substrate, the computing core is bonded to the first light engine through a third electrical bump, and is bonded to the second light engine through a fourth electrical bump;

[0035] A thirteenth conductive part is provided on the first light engine, the thirteenth conductive part is connected to the third electrical bump, and the computing core is electrically connected to the first light engine through the third electrical bump and the thirteenth conductive part; a fourteenth conductive part is provided on the second light engine, the fourteenth conductive part is connected to the fourth electrical bump, and the computing core is electrically connected to the second light engine through the fourth electrical bump and the fourteenth conductive part.

[0036] Further, the first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, and the second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit;

[0037] The first photonic integrated circuit is arranged at a fifth preset position of the packaging substrate, and the second photonic integrated circuit is arranged at a sixth preset position of the packaging substrate, the first electronic integrated circuit is bonded to the first photonic integrated circuit through a fifth electrical bump and bonded to the packaging substrate through a sixth electrical bump, and the second electronic integrated circuit is bonded to the second photonic integrated circuit through a seventh electrical bump and bonded to the packaging substrate through an eighth electrical bump;

[0038] The computing core is bonded to the packaging substrate via a ninth electrical bump and a tenth electrical bump, a third electrical interconnection line arranged on the packaging substrate connects the sixth electrical bump and the ninth electrical bump to realize electrical connection between the computing core and the first electronic integrated circuit, and a fourth electrical interconnection line arranged on the packaging substrate connects the eighth electrical bump and the tenth electrical bump to realize electrical connection between the computing core and the second electronic integrated circuit.

[0039] Further, the first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, the first electronic integrated circuit is bonded to the packaging substrate through an eleventh electrical bump, the first photonic integrated circuit is bonded to the first electronic integrated circuit through a twelfth electrical bump, and a first supporting column is arranged between the first photonic integrated circuit and the packaging substrate; the fifteenth conductive portion penetrates the first photonic integrated circuit;

[0040] The second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit, the second electronic integrated circuit is bonded to the packaging substrate through a thirteenth electrical bump, the second photonic integrated circuit is bonded to the second electronic integrated circuit through a fourteenth electrical bump, and a second supporting column is arranged between the second photonic integrated circuit and the packaging substrate; the sixteenth conductive portion penetrates the second photonic integrated circuit;

[0041] The computing core is bonded to the packaging substrate via a fifteenth electrical bump and a sixteenth electrical bump, a fifth electrical interconnection line provided on the packaging substrate connects the fifteenth electrical bump and the eleventh electrical bump, and a sixth electrical interconnection line provided on the packaging substrate connects the sixteenth electrical bump and the thirteenth electrical bump; the computing core is electrically connected to the first photonic integrated circuit via a third electrical communication link, and the computing core is electrically connected to the second photonic integrated circuit via a fourth electrical communication link;

[0042] The third electrical communication link includes the fifteenth electrical bump, the fifth electrical interconnection line, and the eleventh electrical bump connected in sequence; or, the third electrical communication link includes the fifteenth electrical bump, the fifth electrical interconnection line, the eleventh electrical bump, and the fifteenth conductive portion connected in sequence;

[0043] The fourth electrical communication link includes the sixteenth electrical bump, the sixth electrical interconnection line, and the thirteenth electrical bump connected in sequence; or, the fourth electrical communication link includes the sixteenth electrical bump, the sixth electrical interconnection line, the thirteenth electrical bump, and the sixteenth conductive portion connected in sequence.

[0044] A quantum processor provided by an embodiment of the present invention comprises a signal source core particle and a hybrid core particle, wherein the signal source core particle is used to generate an optical signal, and the hybrid core particle is used to process and store data; the signal source core particle is connected to the hybrid core particle via an optical communication link, thereby improving the rate and bandwidth of data transmission between the core particles, thereby improving the performance of the quantum processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 Schematic diagram of the structure of a quantum processor provided by the first embodiment of the present invention.

[0047] Figure 2 Schematic diagram of the structure of a quantum processor provided by the second embodiment of the present invention.

[0048] Figure 3 Schematic diagram of the structure of a quantum processor provided by the third embodiment of the present invention.

[0049] Figure 4 4 is a schematic diagram of the structure of a quantum processor provided by the fourth embodiment of the present invention.

[0050] Figure 5 4 is a schematic diagram of the structure of a quantum processor provided by the fifth embodiment of the present invention.

[0051] Figure 6 Schematic diagram of the structure of a quantum processor provided by the sixth embodiment of the present invention.

[0052] Figure 7 4 is a schematic diagram of the structure of a quantum processor provided by the seventh embodiment of the present invention.

[0053] Figure 8 Schematic diagram of the structure of a quantum processor provided by the eighth embodiment of the present invention.

[0054] Fig. 9 Schematic diagram of the structure of the hybrid core particle provided by the ninth embodiment of the present invention.

[0055] Fig. 10A Schematic diagram of a cross-sectional structure of a hybrid core particle provided in the tenth embodiment of the present invention.

[0056] Fig. 10B 1 is another schematic cross-sectional structure diagram of the hybrid core particle provided in the tenth embodiment of the present invention.

[0057] Fig.11A It is a schematic cross-sectional structure diagram of a hybrid core particle provided in the eleventh embodiment of the present invention.

[0058] Fig. 11B 2 is another schematic cross-sectional structure diagram of the hybrid core particle provided in the twelfth embodiment of the present invention.

[0059] Fig.12It is a schematic diagram of the structure of a computing core particle provided in the twelfth embodiment of the present invention.

[0060] Fig.13 It is a schematic diagram of the structure of a computing core particle provided in the thirteenth embodiment of the present invention.

[0061] Fig.14 It is a schematic diagram of the structure of a computing core particle provided in the fourteenth embodiment of the present invention.

[0062] Fig.15 It is a schematic diagram of the structure of a computing core particle provided in the fifteenth embodiment of the present invention.

[0063] Fig.16 Schematic diagram of the structure of the hybrid core particle provided in the sixteenth embodiment of the present invention.

[0064] Fig.17 Schematic diagram of the structure of the hybrid core particle provided by the seventeenth embodiment of the present invention.

[0065] Fig.18 It is a schematic structural diagram of the first optical protrusion provided in the eighteenth embodiment of the present invention.

[0066] Fig.19 Schematic diagram of the structure of the hybrid core particle provided by the nineteenth embodiment of the present invention.

[0067] Fig. 20 Schematic diagram of the structure of the hybrid core particle provided by the twentieth embodiment of the present invention.

[0068] Fig.21 It is a schematic diagram of the structure of the hybrid core particle provided in the twenty-first embodiment of the present invention.

[0069] Fig. 22 4 is a schematic diagram of the structure of a quantum processor provided in the twenty-second embodiment of the present invention.

[0070] Fig.23 4 is a schematic diagram of the structure of a quantum processor provided in the twenty-third embodiment of the present invention. DETAILED DESCRIPTION

[0071] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail with reference to the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined with each other arbitrarily. The acquisition, storage, use, and processing of data in the technical scheme in this application comply with the relevant provisions of laws and regulations. The user information in the embodiments of the present application is obtained through legal and compliant channels, and the acquisition, storage, use, and processing of user information are authorized and agreed by the customer.

[0072] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0073] As the feature size of integrated circuits continues to shrink, the signal transmission delay of electrical interconnects has become the main factor affecting the operating speed of integrated circuits. The coupling effects of parasitic capacitance and parasitic inductance that are prevalent between electrical interconnects have a significant impact on signal integrity; at the same time, with the increasing demand for large and high-speed data transmission, the bandwidth capacity that electrical interconnects can provide is not strong enough. Increasing the number of I / Os and the overall size of the chip package for parallel transmission will increase the number of I / Os and the overall size of the chip package, and increasing the data transmission frequency will significantly increase the system energy consumption and the mutual interference caused by parasitic effects. According to empirical data, a 20Gbps signal will lose about 1dB for every inch (2.54 cm) of routing on the circuit board. The problems caused by electrical interconnects still exist in the field of quantum computing. At the same time, due to the sensitivity, weakness, volatility of quantum signals and the immaturity of the corresponding error correction schemes, and the large loss over long distances, the hardware bottleneck of electrical interconnects is likely to have a more significant negative impact in the quantum processor scenario. Compared with the signal loss of electrical interconnects, 1310nm wavelength optical cables only lose 0.35dB per kilometer under normal circumstances. Therefore, on-chip optical interconnection, that is, using light as a carrier for signal transmission within and between chips, as an alternative solution, has advantages over electrical interconnection, such as high speed, high bandwidth, low energy consumption and wavelength division multiplexing.

[0074] Figure 1 is a schematic diagram of the structure of a quantum processor provided by the first embodiment of the present invention, such as Figure 1 As shown, the quantum processor provided by the embodiment of the present invention includes a signal source core particle 1 and a hybrid core particle 2, wherein:

[0075] The signal source core particle 1 is used to generate an optical signal, and the hybrid core particle 2 is used to process and store data; the signal source core particle 1 and the hybrid core particle 2 are connected via an optical communication link 3.

[0076] Specifically, the signal source core 1 may include a light source, an optical amplifier and an optical modulator. The light source generates an optical carrier, the optical amplifier is used to enhance the optical signal power of the optical carrier, and the optical modulator can modulate the optical carrier based on an external radio frequency signal to obtain a desired optical signal. The signal source core 1 transmits the optical signal to the hybrid core 2 via an optical communication link 3.

[0077] The hybrid core particle 2 can convert the received optical signal into an electrical signal for processing and data storage. The hybrid core particle 2 may include an optical engine and a computing core particle. The optical engine is used to convert the optical signal into an electrical signal and can also convert the electrical signal into an optical signal. The computing core particle is used for data processing and storage. The computing core particle may include a quantum chip and a memory. Quantum chips include but are not limited to superconducting quantum chips, topological quantum chips, semiconductor quantum dot chips, etc. The memory includes but is not limited to superconducting memory, non-superconducting memory, hybrid memory, etc. Among them, the number of hybrid core particles 2 is selected according to actual needs, and the embodiment of the present invention is not limited. When the number of current hybrid core particles 2 is greater than or equal to 2, multiple hybrid core particles 2 can be connected in series or in parallel, and can be set according to actual needs, which is not limited in the embodiment of the present invention.

[0078] By introducing the optical communication link 3 for data transmission, the delay can be reduced, the interference of the parasitic effect of the electrical interconnection line on the response signal can be avoided, and the bandwidth of data transmission can be improved.

[0079] A quantum processor provided by an embodiment of the present invention comprises a signal source core particle and a hybrid core particle, wherein the signal source core particle is used to generate an optical signal, and the hybrid core particle is used to process and store data; the signal source core particle is connected to the hybrid core particle via an optical communication link, thereby improving the rate and bandwidth of data transmission between the core particles, thereby improving the performance of the quantum processor.

[0080] Figure 2 is a schematic diagram of the structure of a quantum processor provided by the second embodiment of the present invention, such as Figure 2 As shown, on the basis of the above embodiments, further, there are multiple hybrid core particles 2, and the multiple hybrid core particles 2 are connected in series. The signal source core particle 1 communicates with the first hybrid core particle 2 of the multiple hybrid core particles 2 connected in series through an optical communication link 3, and adjacent hybrid core particles communicate with each other through a first optical signal transmission link 4.

[0081] Specifically, the optical signal generated by the signal source core particle 1 is transmitted to the first hybrid core particle 2 through the optical communication link 33, and the first hybrid core particle 2 is a hybrid core particle 2 directly connected to the signal source core particle 1. The first hybrid core particle 2 can process the received optical signal, and can also transmit the received optical signal to the connected hybrid core particle 2 through the first optical signal transmission link 4. Adjacent hybrid core particles 2 in the series of multiple hybrid core particles 2 can communicate through the connected first optical signal transmission link 4. The series hybrid core particle architecture is suitable for short-distance and highly generalized application scenarios.

[0082] It is understandable that each hybrid core 2 may have a corresponding optical signal output link to facilitate output of processing results and stored data.

[0083] Figure 3is a schematic diagram of the structure of a quantum processor provided by the third embodiment of the present invention. Figure 3 As shown, based on the above embodiments, further, at least two hybrid core particles 2 in the plurality of hybrid core particles 2 share one optical signal output link 5. By sharing the optical signal output link, the number of optical signal output links can be reduced, which facilitates integration and reduces manufacturing costs.

[0084] For example, among the plurality of hybrid core particles 2 , every two hybrid core particles 2 share one optical signal output link 5 , and each hybrid core particle 2 corresponds to only one optical signal output link 5 .

[0085] For example, among the plurality of hybrid core particles 2 , there are three hybrid core particles 2 that share one optical signal output link 5 .

[0086] Figure 4 is a schematic diagram of the structure of a quantum processor provided by the fourth embodiment of the present invention. Figure 4 As shown, based on the above embodiments, the signal source core 1 further includes a light source 1-1, an optical amplifier 1-2 and an optical modulator 1-3 connected in sequence, and the output end of the optical modulator 1-3 is connected to the input end of the optical communication link 33.

[0087] Specifically, the light source 1-1 can generate an optical carrier based on an external driving signal, and the light source can be made of compounds such as gallium arsenide and indium phosphide. The optical amplifier 1-2 is used to enhance the optical signal power of the optical carrier, and the optical amplifier 1-2 can be an optical fiber amplifier, a semiconductor optical amplifier, a nonlinear optical fiber amplifier, etc. The optical modulator 1-3 is used to modulate the optical carrier to obtain an optical signal, and the optical modulator 1-3 can be an acousto-optic modulator, an electro-optical modulation, a semiconductor modulator, a laser modulator, etc.

[0088] The light source 1-1 can be connected to the optical amplifier 1-2 through an optical waveguide, and transmit the generated optical carrier to the optical amplifier 1-2. The optical amplifier 1-2 can be connected to the optical modulator 1-3 through an optical waveguide, and transmit the amplified optical carrier to the optical modulator 1-3. The optical signal output by the optical modulator 1-3 is transmitted to the hybrid core 2 through the optical communication link 3.

[0089] Figure 5 is a schematic diagram of the structure of a quantum processor provided by the fifth embodiment of the present invention. Figure 5 As shown, there are multiple hybrid core particles 2, and the multiple hybrid core particles 2 are connected in parallel. The signal source core particle 1 is optically connected to each hybrid core particle 2 respectively, and the multiple hybrid core particles 2 in parallel communicate with each other through the second optical signal transmission link 8. Each hybrid core particle 2 corresponds to an optical signal output link 5.

[0090] Specifically, the signal source core particle 1 can be communicatively connected to each hybrid core particle 2 via an optical communication link 3, multiple hybrid core particles 2 are connected in parallel, any two hybrid core particles 2 can be communicatively connected via a second optical signal transmission link 8, and each hybrid core particle 2 has an optical signal output link 5.

[0091] The second optical signal transmission link 8 may include an optical fiber and two couplers, with one coupler connected to each end of the optical fiber, and each coupler connected to a hybrid core particle 2. The second optical signal transmission link 8 may include an optical waveguide, through which the two hybrid core particles 2 are connected. Furthermore, the second optical signal transmission link 8 may also include an optical amplifier to enhance the optical signal transmitted step by step.

[0092] The optical signal output link 5 may include an optical fiber and a coupler. The coupler is connected to the output end of the hybrid core 2. One end of the optical fiber is connected to the coupler, and the other end of the optical fiber outputs the optical signal.

[0093] When multiple hybrid core particles 2 are connected in parallel, the independence of a single hybrid core particle 2 is stronger, and since each hybrid core particle 2 directly obtains the optical signal from the signal source core particle 1, the optical signal will not produce step-by-step loss and distortion accumulation. The parallel hybrid core particle architecture is suitable for long-distance communication and application scenarios with a high degree of customization.

[0094] Figure 6 is a schematic diagram of the structure of a quantum processor provided by the sixth embodiment of the present invention, such as Figure 6 As shown, based on the above embodiments, the signal source core 1 further includes a light source 1-1, an optical amplifier 1-2, an optical power distributor 1-4 and a plurality of optical modulators 1-3, wherein:

[0095] The light source 1-1, the optical amplifier 1-2 and the optical power distributor 1-4 are connected in sequence, the optical power distributor 1-4 is connected to each optical modulator 1-3 respectively, each optical modulator 1-3 corresponds to a hybrid core particle 2, and each optical modulator 1-3 is optically connected to the corresponding hybrid core particle 2.

[0096] Specifically, the light source 1-1 can generate an optical carrier based on an external driving signal, and the light source can be made of compounds such as gallium arsenide and indium phosphide. The optical amplifier 1-2 is used to enhance the optical signal power of the optical carrier, and the optical amplifier 1-2 can be an optical fiber amplifier, a semiconductor optical amplifier, a nonlinear optical fiber amplifier, etc. The optical power distributor 1-4 is used to distribute the input optical carrier according to a predetermined ratio to multiple output channels for transmission to each optical modulator 1-3, and the optical power distributor 1-4 can be an optical fiber coupler, a grating coupler, a planar waveguide beam splitter array, etc. The optical modulator 1-3 is used to modulate the optical carrier to obtain an optical signal, and the optical modulator 1-3 can be an acousto-optic modulator, an electro-optical modulation, a semiconductor modulator, a laser modulator, etc.

[0097] The light source 1-1 can be connected to the optical amplifier 1-2 through an optical waveguide, and transmit the generated optical carrier to the optical amplifier 1-2. The optical amplifier 1-2 can be connected to the optical power distributor 1-4 through an optical waveguide, and transmit the amplified optical carrier to the optical power distributor 1-4. The optical power distributor 1-4 can be connected to each optical modulator 1-3 through an optical waveguide, and output each optical carrier to the corresponding optical modulator 1-3. Each optical modulator 1-3 is connected to the corresponding hybrid core 2 through the corresponding optical communication link 3, and outputs each optical signal to the corresponding hybrid core 2.

[0098] Figure 7 is a schematic diagram of the structure of a quantum processor provided by the seventh embodiment of the present invention, such as Figure 7 As shown, on the basis of the above embodiments, further, the signal source core particle 1 includes multiple optical signal generating units 101, each optical signal generating unit 101 includes a light source 101-1, an optical amplifier 101-2 and an optical modulator 101-3 connected in sequence, each optical signal generating unit 101 corresponds to a hybrid core particle 2, and the optical modulator 101-3 of each optical signal generating unit 101 is optically connected to the corresponding hybrid core particle 2.

[0099] Specifically, the signal source core 1 includes a plurality of optical signal generating units 101, and the optical signal generating units 101 output the optical signal to the corresponding hybrid core 2 through the corresponding optical communication link 3, and the optical signal generating units 101 correspond one to one with the hybrid core 2. The optical signal generating unit 101 includes a light source 101-1, an optical amplifier 101-2 and an optical modulator 101-3, the light source 101-1 generates an optical carrier based on an external driving signal, the optical amplifier 101-2 is used to enhance the optical signal power of the optical carrier, and the optical modulator 101-3 is used to modulate the optical carrier to obtain an optical signal.

[0100] The light source 101-1 can be connected to the optical amplifier 101-2 through an optical waveguide, and transmit the generated optical carrier to the optical amplifier 101-2. The optical amplifier 101-2 can be connected to the optical modulator 101-3 through an optical waveguide, and transmit the amplified optical carrier to the optical modulator 101-3. The optical modulator 101-3 is connected to the corresponding hybrid core particle 2 through the corresponding optical communication link 3, and outputs the optical signal to the corresponding hybrid core particle 2.

[0101] Figure 8 is a schematic diagram of the structure of a quantum processor provided by the eighth embodiment of the present invention. Figure 8As shown, on the basis of the above embodiments, further, the hybrid core 2 includes a first light engine 2-1, a computing core 2-2 and a second light engine 2-3, and the computing core 2-2 is electrically connected to the first light engine 2-1 and the second light engine 2-3 respectively; the first light engine 2-1 and the second light engine 2-3 are used to convert the received optical signal into an electrical signal output, or convert the received electrical signal into an optical signal output.

[0102] Specifically, the first optical engine 2-1 can be connected to the signal source core 1 through the optical communication link 3 to receive the optical signal output by the signal source core 1. The first optical engine 2-1 converts the received optical signal into an electrical signal and transmits it to the computing core 2-2. The computing core 2-2 can perform data processing and data storage based on the received electrical signal. The second optical engine 2-3 can be connected to the optical signal output link or to other hybrid cores 2. The second optical engine 2-3 can receive the electrical signal from the computing core 2-2 and then convert the electrical signal into an optical signal for output.

[0103] The first optical engine 2-1 includes an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC). The EIC is used to perform necessary processing on the electrical signal, such as providing a driving and amplifying circuit, and the PIC is used to convert the electrical signal into an optical signal or convert the optical signal into an electrical signal. The EIC and the PIC can be processed on the same chip, or the EIC and the PIC can be processed into independent functional components and integrated together to form the first optical engine 2-1. The second optical engine 2-3 can adopt the same structure as the first optical engine 2-1, which will not be described in detail here.

[0104] The computing core particle 2-2 may include a global control chip and at least one processing module. The global control chip is used to control the data processing scheduling of the processing module and can also perform load balancing scheduling on multiple processing modules. The processing module is used to perform specific data processing and data storage.

[0105] Fig. 9 is a schematic diagram of the structure of the hybrid core particle provided by the ninth embodiment of the present invention. Fig. 9 As shown, on the basis of the above embodiments, further, there are multiple computing core particles 2-2, and each computing core particle 2-2 is electrically connected to the first light engine 2-1 and the second light engine 2-3 respectively.

[0106] Specifically, the hybrid core 2 may include a plurality of computing cores 2 - 2 , and the plurality of computing cores 2 - 2 share a first light engine 2 - 1 and a second light engine 2 - 3 .

[0107] Fig. 10Ais a schematic cross-sectional structure diagram of a hybrid core particle provided in the tenth embodiment of the present invention, Fig. 10B FIG. 1 is another cross-sectional structural diagram of a hybrid core particle provided in the tenth embodiment of the present invention. Fig. 10A and Fig. 10B As shown, the first light engine 2-1 includes a first PIC2-1-1 and a first EIC2-1-2, and the second light engine 2-3 includes a second PIC2-3-1 and a second EIC2-3-2;

[0108] A first PIC2-1-1 is set at a first preset position of the packaging substrate 2-4, and a second PIC2-3-1 is set at a second preset position of the packaging substrate 2-4, and the adapter board 2-5 is bonded to the first PIC2-1-1 through the seventeenth electrical bump 2-6 and bonded to the second PIC2-3-1 through the eighteenth electrical bump 2-7; wherein the first preset position and the second preset position are selected according to actual needs, and the embodiment of the present invention is not limited thereto.

[0109] The first EIC2-1-2 is bonded to the adapter board 2-5 through the nineteenth electrical bump 2-8 and the twentieth electrical bump 2-9, and the second EIC2-3-2 is bonded to the adapter board 2-5 through the twenty-first electrical bump 2-10 and the twenty-second electrical bump 2-11; the first EIC2-1-2 is electrically connected to the first PIC2-1-1 through the nineteenth electrical bump 2-8, the first conductive portion 2-12 and the seventeenth electrical bump 2-6; the second EIC2-3-2 is electrically connected to the second PIC2-3-1 through the twenty-second electrical bump 2-11, the second conductive portion 2-13 and the eighteenth electrical bump 2-7;

[0110] Each computing core 2-2 is bonded to the adapter board 2-5 through the corresponding twenty-third electrical bump 2-14 and the twenty-fourth electrical bump 2-15; the first electrical communication link corresponding to each computing core 2-2 connects the twentieth electrical bump 2-9 and the twenty-third electrical bump 2-14 corresponding to each computing core 2-2 to realize the electrical connection between each computing core 2-2 and the first EIC 2-1-2; the second electrical communication link corresponding to each computing core 2-2 connects the twenty-first electrical bump 2-10 and the twenty-fourth electrical bump 2-15 corresponding to each computing core 2-2 to realize the electrical connection between each computing core 2-2 and the second EIC 2-3-2;

[0111] The first electrical communication link includes a third conductive portion 2-16, a seventh electrical interconnection line 2-17 and a fourth conductive portion 2-18, or an eighth electrical interconnection line 2-19 connected in sequence; the third conductive portion 2-16 and the fourth conductive portion 2-18 penetrate the adapter board 2-5, and the seventh electrical interconnection line 2-17 is arranged on a side surface of the adapter board 2-5 facing the package substrate 2-4; the eighth electrical interconnection line 2-19 is arranged on a side surface of the adapter board 2-5 facing the computing core particle 2-2;

[0112] The second electrical communication link includes a fifth conductive part 2-20, a ninth electrical interconnection line 2-21 and a sixth conductive part 2-22, or a tenth electrical interconnection line 2-23 connected in sequence; the fifth conductive part 2-20 and the sixth conductive part 2-22 pass through the adapter board 2-5, and the ninth electrical interconnection line 2-21 is arranged on a side surface of the adapter board 2-5 facing the packaging substrate 2-4; the tenth electrical interconnection line 2-23 is arranged on a side surface of the adapter board 2-5 facing the computing core 2-2.

[0113] The first conductive part 2-12 passes through the adapter board 2-5. A through hole can be made on the adapter board 2-5, and a conductive layer can be made on the side wall of the through hole to obtain the first conductive part 2-12, or a conductive material can be filled in the through hole to obtain the first conductive part 2-12. The second conductive part 2-13 passes through the adapter board 2-5. The structures of the second conductive part 2-13, the third conductive part 2-16, the fourth conductive part 2-18, the fifth conductive part 2-20 and the sixth conductive part 2-22 are similar to those of the first conductive part 2-12, and are not described in detail here.

[0114] Each computing core 2-2 can be electrically connected through corresponding bumps and electrical interconnects. The first PIC2-1-1 can achieve optical communication through an optical waveguide or optical fiber. The second PIC2-3-1 can achieve optical communication through an optical waveguide or optical fiber.

[0115] For example, Fig. 10A and 10B As shown, the two computing cores 2-2 are electrically connected via the twenty-fourth electrical bump 2-15, the electrical interconnection line 2-76 and the twenty-third electrical bump 2-14.

[0116] For example, Fig. 10A and 10B As shown, the first PIC 2-1-1 optically communicates with other components via an optical waveguide 2-77, and the second PIC 2-3-1 optically communicates with other components via an optical waveguide 2-78.

[0117] Fig.11A is a schematic cross-sectional structure diagram of a hybrid core particle provided in the eleventh embodiment of the present invention, Fig. 11B FIG. 1 is another cross-sectional structural diagram of a hybrid core particle provided in the twelfth embodiment of the present invention. Fig.11A and Fig. 11B As shown, based on the above embodiments, further, the first light engine 2-1 includes a first PIC2-1-1 and a first EIC2-1-2, and the second light engine 2-3 includes a second PIC2-3-1 and a second EIC2-3-2;

[0118] The first EIC 2-1-2 is bonded to the first surface of the adapter board 2-5 through the twenty-fifth electrical bump 2-24 and the twenty-sixth electrical bump 2-25, and the first PIC 2-1-1 is bonded to the second surface of the adapter board 2-5 through the twenty-seventh electrical bump 2-26; the second EIC 2-3-2 is bonded to the first surface of the adapter board 2-5 through the twenty-eighth electrical bump 2-27 and the twenty-ninth electrical bump 2-28, and the second PIC 2-3-1 is bonded to the second surface of the adapter board 2-5 through the thirtieth electrical bump 2-29. On the surface; wherein, there may be multiple twenty-sixth electrical bumps 2-25, the specific number of which is set according to actual needs, and the embodiment of the present invention is not limited; there may be multiple twenty-seventh electrical bumps 2-26, the specific number of which is set according to actual needs, and the embodiment of the present invention is not limited; there may be multiple twenty-eighth electrical bumps 2-27, the specific number of which is set according to actual needs, and the embodiment of the present invention is not limited; there may be multiple thirtieth electrical bumps 2-29, the specific number of which is set according to actual needs, and the embodiment of the present invention is not limited;

[0119] The seventh conductive part 2-30 connects the twenty-seventh electrical bump 2-26 and the twenty-sixth electrical bump 2-25 to realize the electrical connection between the first EIC 2-1-2 and the first PIC 2-1-1, and the seventh conductive part 2-30 penetrates the adapter board 2-5; the eighth conductive part 2-31 connects the thirtieth electrical bump 2-29 and the twenty-eighth electrical bump 2-27 to realize the electrical connection between the second EIC 2-3-2 and the second PIC 2-3-1, and the eighth conductive part 2-31 penetrates the adapter board 2-5; the adapter board 2-5 is fixed on the package substrate 2-4 through the third support column 2-79. The number of the third support column 2-79 can be multiple, and the specific number is set according to actual needs, which is not limited in the embodiment of the present invention.

[0120] Each computing core 2-2 is bonded to the second surface of the adapter board 2-5 through the corresponding thirty-first electrical bump 2-32 and the thirty-second electrical bump 2-33; each computing core 2-2 is electrically connected to the first EIC 2-1-2 through the corresponding thirty-first electrical bump 2-32, the ninth conductive part 2-34, the tenth electrical interconnection line 2-35, and the twenty-fifth electrical bump 2-24; each computing core 2-2 is electrically connected to the second EIC 2-3-2 through the corresponding thirty-second electrical bump 2-33, the tenth conductive part 2-36, the eleventh electrical interconnection line 2-37, and the twenty-ninth electrical bump 2-28.

[0121] Each computing core 2-2 can be electrically connected through corresponding bumps and electrical interconnects. The first PIC2-1-1 can achieve optical communication through optical fibers. The second PIC2-3-1 can achieve optical communication through optical fibers.

[0122] For example, Fig.11A and 11B As shown, the two computing core particles 2-2 are electrically connected through the thirty-second electrical bump 2-33 corresponding to one computing core particle 2-2, the electrical interconnection line 2-88 and the thirty-first electrical bump 2-32 corresponding to the other computing core particle 2-2.

[0123] For example, Fig.11A and 11B As shown, a hole is punched in the first PIC2-1-1, and an optical fiber 2-81 is installed. The first PIC2-1-1 optically communicates with other components through the optical fiber 2-81. A hole is punched in the second PIC2-3-1, and an optical fiber 2-80 is installed. The second PIC2-3-1 optically communicates with other components through the optical fiber 2-80.

[0124] Fig.12 is a schematic diagram of the structure of a computing core particle provided by the twelfth embodiment of the present invention, such as Fig.12 As shown, on the basis of the above embodiments, further, the computing core particle 2-2 includes a global control chip 2-2-1 and at least one processing module 2-2-2, and the global control chip 2-2-1 is electrically connected to each processing module 2-2-2.

[0125] Specifically, the computing core particle 2-2 is electrically connected to the first light engine 2-1 and the second light engine 2-3 through the global control chip 2-1-1, and the global control chip 2-1-1 can control the input and output of data. The global control chip 2-2-1 is electrically connected to each processing module 2-2-2, and can provide the received data to each processing module 2-2-2, and can also output the data processed by each processing module 2-2-2. The global control chip 2-2-1 can also load balance multiple processing modules 2-2-2 based on a preset load balancing algorithm. The processing module 2-2-2 is used for data processing and data storage. The global control chip 2-1-1 can use a CMOS control chip, which is a control chip manufactured using complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, referred to as CMOS) technology. The processing module 2-2-2 may include a quantum chip and a memory. Quantum chips include but are not limited to superconducting quantum chips, topological quantum chips, semiconductor quantum dot chips, etc. The memory includes but is not limited to superconducting memory, non-superconducting memory, hybrid memory, etc.

[0126] Fig.13 is a schematic diagram of the structure of a computing core particle provided by the thirteenth embodiment of the present invention, such as Fig.13 As shown, on the basis of the above embodiments, further, the processing module 2-2-2 includes a computing unit 2-2-2-1 and a storage unit 2-2-2-2, the computing unit 2-2-2-1 includes at least one first control chip 2-2-2-1-1 and a corresponding quantum chip (QIC) 2-2-2-1-2, and the storage unit 2-2-2-2 includes at least one second control chip 2-2-2-2-1 and a corresponding memory 2-2-2-2-2.

[0127] Specifically, the first control chip 2-2-2-1-1 corresponds to the quantum chip 2-2-2-1-2 one by one, the first control chip 2-2-2-1-1 is connected to the corresponding quantum chip 2-2-2-1-2, and each first control chip 2-2-2-1-1 is electrically connected to the global control chip 2-2-1. The second control chip 2-2-2-2-1 corresponds to the memory 2-2-2-2-2 one by one, the second control chip 2-2-2-2-1 is connected to the corresponding memory 2-2-2-2-2, and each second control chip 2-2-2-2-1 is electrically connected to the global control chip 2-2-1. The first control chip 2-2-2-1-1 and the second control chip 2-2-2-2-1 can adopt CMOS control chips. When there are multiple first control chips 2-2-2-1-1, each first control chip 2-2-2-1-1 can be electrically connected through electrical interconnection lines; when there are multiple second control chips 2-2-2-2-1, each second control chip 2-2-2-2-1 can be electrically connected through electrical interconnection lines.

[0128] The computing unit 2-2-2-1 and the storage unit 2-2-2-2 are prepared independently, and there is no special requirement for the position distribution of the computing unit 2-2-2-1 and the storage unit 2-2-2-2 during integration. Since the computing unit 2-2-2-1 and the storage unit 2-2-2-2 are manufactured separately, a homogeneous integration method is adopted inside the processing module 2-2-2, which reduces the process difficulty and improves the design flexibility.

[0129] Fig.14 is a schematic diagram of the structure of a computing core particle provided by the fourteenth embodiment of the present invention, such as Fig.14 As shown, on the basis of the above embodiments, further, the processing module 2-2-2 includes a third control chip 2-2-2-3, a quantum chip 2-2-2-4 and at least one memory 2-2-2-5, the third control chip 2-2-2-3 is electrically connected to the quantum chip 2-2-2-4, and the third control chip 2-2-2-3 is electrically connected to each memory 2-2-2-5 respectively.

[0130] Specifically, in the embodiment of the present invention, the processing module 2-2-2 adopts a centralized architecture, pursuing near-memory computing to reduce the distance required for information access in the memory, thereby reducing delays and signal distortion. The third control chip 2-2-2-3 is used to realize data interaction between the quantum chip 2-2-2-4 and the memory 2-2-2-5. When there are multiple third control chips 2-2-2-3, each third control chip 2-2-2-3 can be electrically connected through electrical interconnects.

[0131] Fig.15 is a schematic diagram of the structure of a computing core particle provided by the fifteenth embodiment of the present invention, such as Fig.15As shown, on the basis of the above embodiments, further, the processing module 2-2-2 includes multiple fourth control chips 2-2-2-6 and corresponding quantum chips 2-2-2-7 and memory 2-2-2-8, and each fourth control chip 2-2-2-6 is electrically connected to the corresponding quantum chip 2-2-2-7 and memory 2-2-2-8.

[0132] Specifically, each fourth control chip 2-2-2-6 can be electrically connected through an electrical interconnection line, and the fourth control chip 2-2-2-6 is electrically connected to the global control chip 2-2-1. The fourth control chip 2-2-2-6 has a corresponding quantum chip 2-2-2-7 and a memory 2-2-2-8, and the fourth control chip 2-2-2-6 is electrically connected to the corresponding quantum chip 2-2-2-7 and the memory 2-2-2-8. The number of fourth control chips 2-2-2-6 included in the processing module 2-2-2 is set according to actual needs, and the embodiment of the present invention is not limited. In the embodiment of the present invention, the processing module 2-2-2 adopts a centralized architecture, pursuing near-memory computing to reduce the distance required for information access in the memory, thereby reducing delays and signal distortion.

[0133] Fig.14 The processing modules 2-2-2 and Fig.15 The processing module 2-2-2 shown is applied to different scenarios. Fig.14 The processing module 2-2-2 shown is suitable for a larger quantum chip 2-2-2-4. The same quantum chip 2-2-2-4 requires multiple memories 2-2-2-5 to provide cache support. Fig.15 The processing module 2-2-2 shown is suitable for scenarios where the quantum chip 2-2-2-7 is smaller in scale and only requires one memory 2-2-2-8 to provide cache support. Therefore, a larger number of quantum chips 2-2-2-7 can be integrated in the same processing module 2-2-2.

[0134] Fig.16 is a schematic diagram of the structure of the hybrid core particle provided by the sixteenth embodiment of the present invention. Fig.16 As shown, on the basis of the above embodiments, further, the first light engine 2-1 and the second light engine 2-3 are arranged on a packaging substrate, the computing core 2-2 is bonded to the packaging substrate 2-4, and the packaging substrate 2-4 is provided with a first electrical interconnection line 2-40 for realizing an electrical connection between the computing core 2-2 and the first light engine 2-1 and a second electrical interconnection line 2-41 for realizing an electrical connection between the computing core 2-2 and the second light engine 2-3.

[0135] A first light engine 2-1 is set at a third preset position of the packaging substrate 2-4, and a second light engine 2-3 is set at a fourth preset position of the packaging substrate 2-4. The computing core 2-2 is bonded to the packaging substrate 2-4 through the thirty-third electrical bump 2-38 and the thirty-fourth electrical bump 2-39. A first electrical interconnect 2-40 and a second electrical interconnect 2-41 are set on the packaging substrate 2-4. The first electrical interconnect 2-40 connects the thirty-third electrical bump 2-38 and the first light engine 2-1, and the second electrical interconnect 2-41 connects the thirty-fourth electrical bump 2-39 and the second light engine 2-3.

[0136] Specifically, the first optical engine 2-1 can convert the received optical signal into an electrical signal, and transmit it to the computing core 2-2 through the thirty-third electrical bump 2-38 and the first electrical interconnect 2-40. The second optical engine 2-3 can receive the electrical signal from the computing core 2-2 through the second electrical interconnect 2-41 and the thirty-fourth electrical bump 2-39, and convert the electrical signal into an optical signal for output. The third preset position and the fourth preset position are selected according to actual needs, and the embodiment of the present invention does not limit them.

[0137] The first optical engine 2-1 can realize optical communication through an optical waveguide or an optical fiber. The second optical engine 2-3 can realize optical communication through an optical waveguide or an optical fiber.

[0138] For example, the first optical engine 2-1 may perform optical communication via an optical waveguide 2-83 disposed on the packaging substrate 2-4, and the second optical engine 2-3 may perform optical communication via an optical waveguide 2-82 disposed on the packaging substrate 2-4.

[0139] Fig.17 is a schematic diagram of the structure of the hybrid core particle provided by the seventeenth embodiment of the present invention. Fig.17 As shown, on the basis of the above embodiments, further, the computing core particle 2-2 is bonded to the first light engine 2-1 through the first electrical bump 2-42, and is bonded to the second light engine 2-3 through the second electrical bump 2-43, the first light engine 2-1 is bonded to the first coupler 2-45 provided on the packaging substrate 2-4 through the first optical bump 2-44, and the second light engine 2-3 is bonded to the second coupler 2-47 provided on the packaging substrate 2-4 through the second optical bump 2-46;

[0140] A first optical waveguide 2-48 and a second optical waveguide 2-49 are provided on the packaging substrate 2-4. The first optical waveguide 2-48 is connected to the first coupler 2-45, and the second optical waveguide 2-49 is connected to the second coupler 2-47. The first optical engine 2-1 performs optical communication through the first optical bump 2-44, the first coupler 2-45 and the first optical waveguide 2-48. The second optical engine 2-3 performs optical communication through the second optical bump 2-46, the second coupler 2-47 and the second optical waveguide 2-49.

[0141] An eleventh conductive part 2-50 is arranged on the first light engine 2-1, and the eleventh conductive part 2-50 is connected to the first electrical bump 2-42, and the computing core 2-2 is electrically connected to the first light engine 2-1 through the first electrical bump 2-42 and the eleventh conductive part 2-50; a twelfth conductive part 2-51 is arranged on the second light engine 2-3, and the twelfth conductive part 2-51 is connected to the second electrical bump 2-43, and the computing core 2-2 is electrically connected to the second light engine 2-3 through the second electrical bump 2-43 and the twelfth conductive part 2-51.

[0142] The first optical bump 2-44 and the second optical bump 2-46 are used for optical signal transmission. The first optical bump 2-44 transmits optical signals between the first optical engine 2-1 and the first coupler 2-45; the second optical bump 2-46 transmits optical signals between the second optical engine 2-3 and the second coupler 2-47.

[0143] like Fig.18 As shown, the first optical convex point 2-44 includes a core layer 2-44-1 and a cladding layer 2-44-2, wherein the cladding layer 2-44-2 wraps the core layer 2-44-1, and the refractive index of the core layer 2-44-1 is higher than the refractive index of the cladding layer 2-44-2. The core layer 2-44-1 is located at the center of the first optical convex point 2-44, and the optical signal is transmitted in the core layer 2-44-1 to ensure the transmission quality of the optical signal. The cladding layer 2-44-2 surrounds the core layer 2-44-1, providing a reflection surface and optical isolation for the transmission of the optical signal, and at the same time protecting the core layer from mechanical damage. Among them, the core layer 2-44-1 can be made of indium tin oxide semiconductor material (ITO material), which has both superconducting properties and transparent properties, and helps to significantly reduce signal transmission loss. The cladding layer 2-44-2 can be made of SiO2. The second optical convex point 2-46 can adopt the same structure as the first optical convex point 2-44, which will not be repeated here.

[0144] Fig.19 is a schematic diagram of the structure of the hybrid core particle provided by the nineteenth embodiment of the present invention, such as Fig.19 As shown, on the basis of the above embodiments, further, a first light engine 2-1 and a second light engine 2-3 are arranged on a packaging substrate 2-4, and a computing core 2-2 is bonded to the first light engine 2-1 through a third electrical bump 2-52, and is bonded to the second light engine 2-3 through a fourth electrical bump 2-53;

[0145] A thirteenth conductive part 2-54 is arranged in the first light engine 2-1, and the thirteenth conductive part 2-54 is connected to the third electrical bump 2-52, and the computing core 2-2 is electrically connected to the first light engine 2-1 through the third electrical bump 2-52 and the thirteenth conductive part 2-54; a fourteenth conductive part 2-55 is arranged in the second light engine 2-3, and the fourteenth conductive part 2-55 is connected to the fourth electrical bump 2-53, and the computing core 2-2 is electrically connected to the second light engine 2-3 through the fourth electrical bump 2-53 and the fourteenth conductive part 2-55.

[0146] The first optical engine 2-1 and the second optical engine 2-3 respectively realize optical communication through optical fibers.

[0147] For example, the first light engine 2-1 can perform optical communication through the optical fiber 2-85. The second light engine 2-3 can perform optical communication through the optical fiber 2-84. A hole is punched in the first light engine 2-1, and the optical fiber 2-85 is installed. The first light engine 2-1 performs optical communication with other components through the optical fiber 2-85. A hole is punched in the second light engine 2-3, and the optical fiber 2-84 is installed. The second light engine 2-3 performs optical communication with other components through the optical fiber 2-84.

[0148] Fig. 20 2 is a schematic diagram of the structure of the hybrid core particle provided by the twentieth embodiment of the present invention. Fig. 20 As shown, based on the above embodiments, further, the first light engine 2-1 includes a first PIC2-1-1 and a first EIC2-1-2, and the second light engine 2-3 includes a second PIC2-3-1 and a second EIC2-3-2;

[0149] A first PIC2-1-1 is arranged at a fifth preset position of the package substrate 2-4, and a second PIC2-3-1 is arranged at a sixth preset position of the package substrate 2-4, the first EIC2-1-2 is bonded to the first PIC2-1-1 through a fifth electrical bump 2-56 and bonded to the package substrate 2-4 through a sixth electrical bump 2-57, and the second EIC2-3-2 is bonded to the second PIC2-3-1 through a seventh electrical bump 2-58 and bonded to the package substrate 2-4 through an eighth electrical bump 2-59;

[0150] The computing core 2-2 is bonded to the packaging substrate 2-4 through the ninth electrical bump 2-60 and the tenth electrical bump 2-61. The third electrical interconnection line 2-62 arranged on the packaging substrate 2-4 connects the sixth electrical bump 2-57 and the ninth electrical bump 2-60 to realize the electrical connection between the computing core 2-2 and the first EIC2-1-2. The fourth electrical interconnection line 2-63 arranged on the packaging substrate 2-4 connects the eighth electrical bump 2-59 and the tenth electrical bump 2-61 to realize the electrical connection between the computing core 2-2 and the second EIC2-3-2.

[0151] The first PIC2-1-1 can achieve optical communication through an optical waveguide or an optical fiber. The second PIC2-3-1 can achieve optical communication through an optical waveguide or an optical fiber. The fifth preset position and the sixth preset position are selected according to actual needs, and the embodiment of the present invention does not limit them.

[0152] For example, Fig. 20 As shown, the first PIC 2-1-1 can perform optical communication via the optical waveguide 2-87, and the second PIC 2-3-1 can perform optical communication via the optical waveguide 2-86.

[0153] Fig.21 is a schematic diagram of the structure of the hybrid core particle provided by the twenty-first embodiment of the present invention, such as Fig.21 As shown, on the basis of the above embodiments, further, the first optical engine 2-1 includes a first PIC2-1-1 and a first EIC2-1-2, the first EIC2-1-2 is bonded to the package substrate 2-4 through the eleventh electrical bump 2-64, the first PIC2-1-1 is bonded to the first EIC2-1-2 through the twelfth electrical bump 2-65, and a first support column 2-66 is arranged between the first PIC2-1-1 and the package substrate 2-4; the fifteenth conductive part 2-89 runs through the first EIC2-1-2; wherein, there can be multiple eleventh electrical bumps 2-64, and the specific number of the eleventh electrical bumps 2-64 is set according to actual needs, which is not limited by the embodiment of the present invention. There can be multiple fifteenth conductive parts 2-89, and the specific number of the fifteenth conductive parts 2-89 is set according to actual needs, which is not limited by the embodiment of the present invention. There can be multiple twelfth electrical bumps 2-65, and the specific number of the twelfth electrical bumps 2-65 is set according to actual needs, which is not limited in the embodiment of the present invention. There can be multiple first support columns 2-66, and the specific number of the first support columns 2-66 is set according to actual needs, which is not limited in the embodiment of the present invention.

[0154] The second optical engine 2-3 includes a second PIC2-3-1 and a second EIC2-3-2, the second EIC2-3-2 is bonded to the packaging substrate 2-4 through the thirteenth electrical bump 2-67, the second PIC2-3-1 is bonded to the second EIC2-3-2 through the fourteenth electrical bump 2-68, and a second support column 2-69 is arranged between the second PIC2-3-1 and the packaging substrate 2-4; the sixteenth conductive part 2-90 runs through the second EIC2-3-2; wherein, there can be multiple thirteenth electrical bumps 2-67, and the specific number of the thirteenth electrical bumps 2-67 is set according to actual needs, which is not limited by the embodiment of the present invention. There can be multiple sixteenth conductive parts 2-90, and the specific number of the sixteenth conductive parts 2-90 is set according to actual needs, which is not limited by the embodiment of the present invention. There can be multiple fourteenth electrical bumps 2-68, and the specific number of the fourteenth electrical bumps 2-68 is set according to actual needs, which is not limited by the embodiment of the present invention. There may be multiple second support columns 2-69, and the specific number of the second support columns 2-69 is set according to actual needs, and the embodiment of the present invention does not limit it.

[0155] The computing core particle 2-2 is bonded to the packaging substrate 2-4 through the fifteenth electrical bump 2-70 and the sixteenth electrical bump 2-71, the fifth electrical interconnection line 2-72 arranged on the packaging substrate 2-4 connects the fifteenth electrical bump 2-70 and the eleventh electrical bump 2-64, and the sixth electrical interconnection line 2-73 arranged on the packaging substrate 2-4 connects the sixteenth electrical bump 2-71 and the thirteenth electrical bump 2-67; the computing core particle 2-2 is electrically connected to the first EIC 2-1-2 through the third electrical communication link, and the computing core particle 2-2 is electrically connected to the second EIC 2-3-2 through the fourth electrical communication link;

[0156] The third electrical communication link includes a fifteenth electrical bump 2-70, a fifth electrical interconnection line 2-72, and an eleventh electrical bump 2-64 connected in sequence; or, the third electrical communication link includes a fifteenth electrical bump 2-70, a fifth electrical interconnection line 2-72, an eleventh electrical bump 2-64, and a fifteenth conductive portion 2-89 connected in sequence;

[0157] The fourth electrical communication link includes a sixteenth electrical bump 2-71, a sixth electrical interconnection line 2-73, and a thirteenth electrical bump 2-67 connected in sequence; or, the fourth electrical communication link includes a sixteenth electrical bump 2-71, a sixth electrical interconnection line 2-73, a thirteenth electrical bump 2-67, and a sixteenth conductive portion 2-90 connected in sequence.

[0158] When the active area of ​​the first EIC2-1-2 is located on the side surface facing the first PIC2-1-1, the computing core 2-2 is electrically connected to the active area of ​​the first EIC2-1-2 through the fifteenth electrical bump 2-70, the fifth electrical interconnection line 2-72, the eleventh electrical bump 2-64 and the fifteenth conductive portion 2-89 connected in sequence, and the active area of ​​the first EIC2-1-2 is electrically connected to the first PIC2-1-1 through the twelfth electrical bump 2-65; when When the active area of ​​the first EIC2-1-2 is located on the side surface facing the packaging substrate 2-4, the computing core 2-2 is electrically connected to the active area of ​​the first EIC2-1-2 through the fifteenth electrical bump 2-70, the fifth electrical interconnection line 2-72 and the eleventh electrical bump 2-64 connected in sequence, and the active area of ​​the first EIC2-1-2 is electrically connected to the first PIC2-1-1 through the fifteenth conductive part 2-89 and the twelfth electrical bump 2-65 connected in sequence.

[0159] When the active area of ​​the second EIC2-3-2 is located on the side surface facing the second PIC2-3-1, the computing core 2-2 is electrically connected to the active area of ​​the second EIC2-3-2 through the sixteenth electrical bump 2-71, the sixth electrical interconnection line 2-73, the thirteenth electrical bump 2-67 and the sixteenth conductive portion 2-90 connected in sequence, and the active area of ​​the second EIC2-3-2 is electrically connected to the second PIC2-3-1 through the fourteenth electrical bump 2-68; when When the active area of ​​the second EIC2-3-2 is located on the side surface facing the packaging substrate 2-4, the computing core 2-2 is electrically connected to the active area of ​​the second EIC2-3-2 through the sixteenth electrical bump 2-71, the sixth electrical interconnection line 2-73 and the thirteenth electrical bump 2-67 connected in sequence, and the active area of ​​the second EIC2-3-2 is electrically connected to the second PIC2-3-1 through the sixteenth conductive part 2-90 and the fourteenth electrical bump 2-68 connected in sequence.

[0160] The first PIC2-1-1 can realize optical communication through optical fiber. The second PIC2-3-1 can realize optical communication through optical fiber.

[0161] For example, Fig.21 As shown, a hole is punched in the first PIC2-1-1, and an optical fiber 2-74 is installed. The first PIC2-1-1 optically communicates with other components through the optical fiber 2-74. A hole is punched in the second PIC2-3-1, and an optical fiber 2-75 is installed. The second PIC2-3-1 optically communicates with other components through the optical fiber 2-75.

[0162] Fig. 22 is a schematic diagram of the structure of a quantum processor provided by the twenty-second embodiment of the present invention, such as Fig. 22As shown, on the basis of the above embodiments, further, the optical communication link 3 includes an optical amplifier 3-1, a first end of the optical amplifier 3-1 is connected to the signal source core particle 1 through a third optical waveguide 3-2, and a second end of the optical amplifier 3-1 is connected to the hybrid core particle 2 through a second optical waveguide 3-3.

[0163] Fig.23 is a schematic diagram of the structure of a quantum processor provided by the twenty-third embodiment of the present invention, such as Fig.23 As shown, on the basis of the above embodiments, further, the optical communication link 3 includes an optical amplifier 3-1, a third coupler 3-4 and a fourth coupler 3-5, the third coupler 3-4 is connected to the signal source core 1, the fourth coupler 3-5 is connected to the hybrid core 2, the first end of the optical amplifier 3-1 is connected to the third coupler 3-4 through the first optical fiber 3-6, and the second end of the optical amplifier 3-1 is connected to the fourth coupler 3-5 through the second optical fiber 3-7.

[0164] It should be noted that all inter-chip interconnections are allowed to use solder bumps, copper pillar bumps, nail head bumps, etc. The adapter board can be silicon-based, glass-based, etc., and each conductive part can be made using through silicon via technology (TSV), through glass via technology (TGV), molded through via technology (TMV), etc. If the quantum processor is used in superconducting quantum computing application scenarios, superconducting materials are required for inter-chip interconnections and conductive parts.

[0165] The quantum processor provided by the embodiment of the present invention has the following advantages: (1) By replacing some long-distance electrical links with optical links, the adverse effects of hardware bottlenecks such as electrical interconnection transmission delay, parasitic effects, and bandwidth capacity on the development of large-scale, scalable quantum processors are avoided, and the technical advantages of optical interconnection such as high speed, high bandwidth, low energy consumption, and wavelength division multiplexing are fully utilized to improve data transmission efficiency.

[0166] (2) Based on the definition of signal source core particles and hybrid core particles, this application proposes a parallel and serial overall architecture. The parallel architecture is more suitable for long-distance communication and application scenarios with a high degree of customization, while the serial architecture is more suitable for short-distance communication and application scenarios with a higher degree of generalization.

[0167] (3) Based on the relative distribution of computing units and storage units, this application proposes two computing unit architectures: a distributed architecture and a centralized architecture. In the distributed architecture, the control chip + QIC and the memory are prepared separately. There is no special requirement for the location distribution of the two during integration. They are usually homogeneous integration, which improves the design flexibility. The centralized architecture pursues near-memory computing to reduce the distance required for information access in the memory, significantly reducing delays and signal distortion.

[0168] (4) Each QIC has a local control chip, and different QICs use the corresponding local control chip to interconnect signals within the module. Similarly, different modules are connected across modules through a separate global control chip. The entire computing core realizes signal input / output through the optical engines on both sides of the global control chip, forming a bidirectionally symmetrical hybrid core structure. The optical signal is connected over a long distance between different hybrid cores through the optical waveguide in the packaging substrate or the optical fiber of the plate pole, which is conducive to large-scale expansion.

[0169] (5) Signal source cores, computing cores, and optical engines have a variety of architectures and connection methods and can be combined with each other to achieve highly flexible large-scale quantum processor design.

[0170] (6) The quantum processor of the present application has a complete multi-chip integrated packaging architecture, taking into account the comprehensive requirements of quantum processor cost control, signal transmission performance, and large-scale expansion.

[0171] (7) Through the screening of known good chiplets (KGC), the high yield of the chiplets used in the system integration stage can be guaranteed, thereby solving the problem that the overall yield of the quantum processor decreases rapidly as the integration scale increases. In the prior art, the entire complete graphics are made on a single chip according to the size of the chip. The larger the chip, the lower the yield. Therefore, when the scale of quantum chips continues to increase, the continuous decline in the yield of a single chip will lead to rising costs. The quantum processor of the present application includes signal source chiplets and hybrid chiplets. By manufacturing KGCs of various functions with smaller areas, or dividing a large chip into small KGCs with repeated functions, the yield of each KGC is very high, which reduces the manufacturing cost. In addition, the screening process is conducive to improving the yield after system integration.

[0172] In the description of this specification, the description with reference to the terms "one embodiment", "a specific embodiment", "some embodiments", "for example", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0173] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A quantum processor, characterized in that: It includes signal source core particles and mixed core particles, wherein: The signal source core particle is used to generate an optical signal, and the hybrid core particle is used to process and store data; the signal source core particle is connected to the hybrid core particle via an optical communication link.

2. The quantum processor according to claim 1, characterized in that: There are multiple hybrid core particles, which are connected in series. The signal source core particle communicates with the first hybrid core particle of the multiple hybrid core particles connected in series through the optical communication link, and adjacent hybrid core particles communicate with each other through the first optical signal transmission link.

3. The quantum processor according to claim 2, characterized in that: At least two hybrid cores among the plurality of hybrid cores share one optical signal output link.

4. The quantum processor according to claim 2, characterized in that: The signal source core comprises a light source, an optical amplifier and an optical modulator which are connected in sequence, and the output end of the optical modulator is connected to the input end of the optical communication link.

5. The quantum processor according to claim 1, characterized in that: There are multiple hybrid core particles, which are connected in parallel. The signal source core particle is optically connected to each hybrid core particle respectively. The multiple hybrid core particles connected in parallel communicate with each other through a second optical signal transmission link. Each hybrid core particle corresponds to an optical signal output link.

6. The quantum processor according to claim 5, characterized in that: The signal source core comprises a light source, an optical amplifier, an optical power distributor and a plurality of optical modulators, wherein: The light source, the optical amplifier and the optical power distributor are connected in sequence, the optical power distributor is connected to each optical modulator respectively, each optical modulator corresponds to a hybrid core particle, and each optical modulator is optically communicated with the corresponding hybrid core particle.

7. The quantum processor according to claim 5, characterized in that The signal source core comprises a plurality of optical signal generating units, each of which comprises a light source, an optical amplifier and an optical modulator connected in sequence, each of which corresponds to a hybrid core, and the optical modulator of each optical signal generating unit is optically connected to the corresponding hybrid core.

8. The quantum processor according to claim 1, characterized in that: The hybrid core comprises a first optical engine, a computing core and a second optical engine, wherein the computing core is electrically connected to the first optical engine and the second optical engine respectively; the first optical engine and the second optical engine are used to convert received optical signals into electrical signals for output, or to convert received electrical signals into optical signals for output.

9. The quantum processor according to claim 8, characterized in that: There are a plurality of computing core particles, and each computing core particle is electrically connected to the first light engine and the second light engine respectively.

10. The quantum processor according to claim 9, characterized in that: The first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, and the second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit; The first photonic integrated circuit is arranged at a first preset position of the packaging substrate, and the second photonic integrated circuit is arranged at a second preset position of the packaging substrate, and the adapter plate is bonded to the first photonic integrated circuit through a seventeenth electrical bump and bonded to the second photonic integrated circuit through an eighteenth electrical bump; The first electronic integrated circuit is bonded to the adapter board through the nineteenth electrical bump and the twentieth electrical bump, and the second electronic integrated circuit is bonded to the adapter board through the twenty-first electrical bump and the twenty-second electrical bump; the first electronic integrated circuit is electrically connected to the first photonic integrated circuit through the nineteenth electrical bump, the first conductive portion and the seventeenth electrical bump; the second electronic integrated circuit is electrically connected to the second photonic integrated circuit through the twenty-second electrical bump, the second conductive portion and the eighteenth electrical bump; Each computing core is bonded to the adapter board through the corresponding twenty-third electrical bump and the twenty-fourth electrical bump; the first electrical communication link corresponding to each computing core is connected to the twenty-third electrical bump corresponding to each computing core to realize the electrical connection between each computing core and the first electronic integrated circuit; the second electrical communication link corresponding to each computing core is connected to the twenty-first electrical bump and the twenty-fourth electrical bump corresponding to each computing core to realize the electrical connection between each computing core and the second electronic integrated circuit; The first electrical communication link comprises a third conductive portion, a seventh electrical interconnection line and a fourth conductive portion, or an eighth electrical interconnection line, which are connected in sequence; the third conductive portion and the fourth conductive portion penetrate the adapter board, the seventh electrical interconnection line is arranged on a side surface of the adapter board facing the packaging substrate; the eighth electrical interconnection line is arranged on a side surface of the adapter board facing the computing chip; The second electrical communication link includes a fifth conductive part, a ninth electrical interconnection line and a sixth conductive part, or a tenth electrical interconnection line, which are connected in sequence; the fifth conductive part and the sixth conductive part pass through the adapter board, and the ninth electrical interconnection line is arranged on a side surface of the adapter board facing the packaging substrate; the tenth electrical interconnection line is arranged on a side surface of the adapter board facing the computing chip.

11. The quantum processor according to claim 9, characterized in that The first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, and the second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit; The first electronic integrated circuit is bonded to the first surface of the interposer through the twenty-fifth electrical bump and the twenty-sixth electrical bump, and the first photonic integrated circuit is bonded to the second surface of the interposer through the twenty-seventh electrical bump; the second electronic integrated circuit is bonded to the first surface of the interposer through the twenty-eighth electrical bump and the twenty-ninth electrical bump, and the second photonic integrated circuit is bonded to the second surface of the interposer through the thirtieth electrical bump; The seventh conductive portion connects the twenty-seventh electrical bump and the twenty-sixth electrical bump to realize the electrical connection between the first electronic integrated circuit and the first photonic integrated circuit, and the seventh conductive portion passes through the adapter board; the eighth conductive portion connects the thirtieth electrical bump and the twenty-eighth electrical bump to realize the electrical connection between the second electronic integrated circuit and the second photonic integrated circuit, and the eighth conductive portion passes through the adapter board; the adapter board is fixed on the packaging substrate through the third support column; Each computing core is bonded to the second surface of the adapter board through the corresponding thirty-first electrical bump and thirty-second electrical bump; each computing core is electrically connected to the first electronic integrated circuit through the corresponding thirty-first electrical bump, the ninth conductive portion, the tenth electrical interconnection line, and the twenty-fifth electrical bump; each computing core is electrically connected to the second electronic integrated circuit through the corresponding thirty-second electrical bump, the tenth conductive portion, the eleventh electrical interconnection line, and the twenty-ninth electrical bump.

12. The quantum processor according to claim 8, characterized in that The computing core comprises a global control chip and at least one processing module, and the global control chip is electrically connected to each processing module.

13. The quantum processor according to claim 12, characterized in that: The processing module includes a computing unit and a storage unit. The computing unit includes at least one first control chip and a corresponding quantum chip. The storage unit includes at least one second control chip and a corresponding memory.

14. The quantum processor according to claim 12, characterized in that: The processing module includes a third control chip, a quantum chip and at least one memory, wherein the third control chip is electrically connected to the quantum chip, and the third control chip is electrically connected to each memory respectively.

15. The quantum processor according to claim 12, characterized in that: The processing module includes a plurality of fourth control chips and corresponding quantum chips and memories, and each fourth control chip is electrically connected to a corresponding quantum chip and memory.

16. The quantum processor according to claim 8, characterized in that A first optical engine is arranged at a third preset position of the packaging substrate, and a second optical engine is arranged at a fourth preset position of the packaging substrate, the computing core is bonded to the packaging substrate through a thirty-third electrical bump and a thirty-fourth electrical bump, a first electrical interconnection line and a second electrical interconnection line are arranged on the packaging substrate, the first electrical interconnection line connects the thirty-third electrical bump and the first optical engine, and the second electrical interconnection line connects the thirty-fourth electrical bump and the second optical engine.

17. The quantum processor according to claim 8, characterized in that The computing core is bonded to the first optical engine through a first electrical bump, and bonded to the second optical engine through a second electrical bump, the first optical engine is bonded to a first coupler disposed on the packaging substrate through a first optical bump, and the second optical engine is bonded to a second coupler disposed on the packaging substrate through a second optical bump; A first optical waveguide and a second optical waveguide are arranged on the packaging substrate, the first optical waveguide is connected to the first coupler, and the second optical waveguide is connected to the second coupler; the first optical engine performs optical communication through the first optical bump, the first coupler and the first optical waveguide; the second optical engine performs optical communication through the second optical bump, the second coupler and the second optical waveguide; An eleventh conductive part is provided on the first light engine, and the eleventh conductive part is connected to the first electrical bump; a twelfth conductive part is provided on the second light engine, and the twelfth conductive part is connected to the second electrical bump.

18. The quantum processor according to claim 8, characterized in that The first light engine and the second light engine are arranged on the upper surface of the packaging substrate, the computing core is bonded to the first light engine through a third electrical bump, and is bonded to the second light engine through a fourth electrical bump; A thirteenth conductive part is provided on the first light engine, the thirteenth conductive part is connected to the third electrical bump, and the computing core is electrically connected to the first light engine through the third electrical bump and the thirteenth conductive part; a fourteenth conductive part is provided on the second light engine, the fourteenth conductive part is connected to the fourth electrical bump, and the computing core is electrically connected to the second light engine through the fourth electrical bump and the fourteenth conductive part.

19. The quantum processor according to claim 8, characterized in that The first optical engine includes a first photonic integrated circuit and a first electronic integrated circuit, and the second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit; The first photonic integrated circuit is arranged at a fifth preset position of the packaging substrate, and the second photonic integrated circuit is arranged at a sixth preset position of the packaging substrate, the first electronic integrated circuit is bonded to the first photonic integrated circuit through a fifth electrical bump and bonded to the packaging substrate through a sixth electrical bump, and the second electronic integrated circuit is bonded to the second photonic integrated circuit through a seventh electrical bump and bonded to the packaging substrate through an eighth electrical bump; The computing core is bonded to the packaging substrate via a ninth electrical bump and a tenth electrical bump, a third electrical interconnection line arranged on the packaging substrate connects the sixth electrical bump and the ninth electrical bump to realize electrical connection between the computing core and the first electronic integrated circuit, and a fourth electrical interconnection line arranged on the packaging substrate connects the eighth electrical bump and the tenth electrical bump to realize electrical connection between the computing core and the second electronic integrated circuit.

20. The quantum processor according to claim 8, characterized in that The first optical engine comprises a first photonic integrated circuit and a first electronic integrated circuit, the first electronic integrated circuit is bonded to the packaging substrate through an eleventh electrical bump, the first photonic integrated circuit is bonded to the first electronic integrated circuit through a twelfth electrical bump, a first supporting column is arranged between the first photonic integrated circuit and the packaging substrate; the fifteenth conductive portion penetrates the first photonic integrated circuit; The second optical engine includes a second photonic integrated circuit and a second electronic integrated circuit, the second electronic integrated circuit is bonded to the packaging substrate through a thirteenth electrical bump, the second photonic integrated circuit is bonded to the second electronic integrated circuit through a fourteenth electrical bump, and a second supporting column is arranged between the second photonic integrated circuit and the packaging substrate; the sixteenth conductive portion penetrates the second photonic integrated circuit; The computing core is bonded to the packaging substrate via a fifteenth electrical bump and a sixteenth electrical bump, a fifth electrical interconnection line provided on the packaging substrate connects the fifteenth electrical bump and the eleventh electrical bump, and a sixth electrical interconnection line provided on the packaging substrate connects the sixteenth electrical bump and the thirteenth electrical bump; the computing core is electrically connected to the first photonic integrated circuit via a third electrical communication link, and the computing core is electrically connected to the second photonic integrated circuit via a fourth electrical communication link; The third electrical communication link includes the fifteenth electrical bump, the fifth electrical interconnection line, and the eleventh electrical bump connected in sequence; or, the third electrical communication link includes the fifteenth electrical bump, the fifth electrical interconnection line, the eleventh electrical bump, and the fifteenth conductive portion connected in sequence; The fourth electrical communication link includes the sixteenth electrical bump, the sixth electrical interconnection line, and the thirteenth electrical bump connected in sequence; or, the fourth electrical communication link includes the sixteenth electrical bump, the sixth electrical interconnection line, the thirteenth electrical bump, and the sixteenth conductive portion connected in sequence.

Images