Negative-voltage bit line control circuit for SRAM (Static Random Access Memory) write assist module

Abstract

The invention provides a negative-voltage bit line control circuit for an SRAM (Static Random Access Memory) write assist module. The negative-voltage bit line control circuit comprises a memory unit array; a reverse signal WAEB of a write assist enable signal is equal to 0 in a write cycle and in a write assist function opening state, the pre-charging module triggered by a rising edge of a clock CLK is closed, and all bit lines BLT / BLB are pre-charged to be high and then suspended; after all bit lines BLT / BLB are pre-charged to be high and then suspended, a control signal generated by the write driving module is used for gating a pair of word lines through a column decoding address to be transmitted in so as to write data; the negative voltage bit line module enables the 0 bit line to be reduced to negative voltage in a writing period so as to accelerate data writing; and the control circuit is used for generating a write auxiliary clock WACLK triggered by the negative-voltage bit line module through bit line control, the write auxiliary clock WACLK starts the negative-voltage bit line module to generate a negative-voltage pulse after a certain delay after the word line is gated, and the negative-voltage pulse is generated after the 0 bit line is reduced to 0. According to the invention, the negative voltage module can be adaptively started through the potential of the bit line.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a negative voltage bit line control circuit for a SRAM write assist module. Background Art

[0002] With the development of semiconductor device manufacturing process, the area of ​​SRAM storage cells has gradually shrunk, resulting in a significant reduction in the size of NPG and NPD devices. At the same time, in order to improve the noise tolerance of the storage cell to ensure data reliability, the current capacity of the PPU tube has been strengthened relative to the NPD tube, resulting in the QB node potential being affected by the competition between the PPPU0 and NNPG0 tubes when writing to the storage cell, and unable to quickly drop to a low potential to flip the QT / QB node potential, as shown in Figure 1(a). Therefore, a longer write time is required to ensure the data potential flip in the storage cell, and even the SRAM cannot be written when the process fluctuates, resulting in SRAM failure.

[0003] In order to increase the write speed of the storage unit and reduce the write failure rate, a write assist (WA) module is added to the memory architecture of these storage units. The most commonly used strategy is to connect a negative voltage bit line (NBL) module to the bit line write driver module, as shown in Figure 1(b). This reduces the voltage of the "0" bit line to a negative voltage during the write cycle, increases the current passing through the NNPG0 tube, and thus speeds up data writing.

[0004] In order to save the area of ​​the memory, NBL often generates a negative voltage pulse with a very narrow pulse width through the capacitor pressure difference effect. This pulse takes effect within a certain time after the word line of the memory cell is turned on, ensuring that the negative voltage bit line can be applied to the bit line of the memory cell after the word line of the memory cell is turned on, so that the QB node potential drops further, thereby accelerating the QT / QB node potential flip inside the memory cell.

[0005] The commonly used architecture is Figure 2 As shown, the NMOS source of the bit line driver inverter at the previous stage of the bit line multiplexer (MUX) module is connected to the NBL module, and the write auxiliary clock WACLK generated by the NBL is generated by the control module. After a certain delay after the WPASS signal is selected, WACLK turns on the NBL module to generate a negative voltage.

[0006] In order to solve the above problems, it is necessary to propose a novel negative voltage bit line control circuit for an SRAM write assist module. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a negative voltage bit line control circuit for an SRAM write assist module, so as to solve the problem in the prior art that the negative voltage generation time of SRAMs of different capacities does not match the write cycle control timing.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a negative voltage bit line control circuit for an SRAM write assist module, comprising:

[0009] A memory cell array, wherein each memory cell is connected to a pair of word lines WL, a pair of bit lines BLT / BLB and a power supply line;

[0010] The pre-charging module, in which the inverse signal WAEB of the write assist enable signal is 0 during the write cycle and the write assist function is turned on, the pre-charging module triggered by the rising edge of the clock CLK is turned off, and all the bit lines BLT / BLB are pre-charged to high and then suspended;

[0011] The MUX module, after all bit lines BLT / BLB are precharged to high and then suspended, the control signal generated by the write driver module is input through the column decoding address to select a pair of word lines to write data;

[0012] Negative voltage bit line module, which reduces the voltage of the "0" bit line to negative voltage during the write cycle to speed up data writing;

[0013] The control circuit is used to generate a write auxiliary clock WACLK triggered by a negative voltage bit line module through bit line control. After a certain delay after the word line is selected, the write auxiliary clock WACLK turns on the negative voltage bit line module to generate a negative voltage pulse, so that the negative voltage pulse is generated after the "0" bit line drops to 0.

[0014] Preferably, the memory unit is a 6-transistor memory, which includes: 2 PMOS transistors PPU0, PPU1 and 4 NMOS transistors NPD0, NPD1, NPG0, NPG1; wherein NPD0 and NPD1 are pull-down transistors, PPU0 and PPU1 are rise-up transistors, and NPG0 and NPG1 are transmission transistors; the sources of PPU0 and PPU1 are connected to the storage unit working power supply Vdd, and the drains of PPU0 and PPU1 are connected to the drains of NPD0 and NPD1 respectively; the gate of PPU0 is connected to the gate of NPD0 to form a first storage node QB, and the gate of PPU1 is connected to the gate of NPD1 to form a second storage node QT; the sources of NPD0 and NPD1 are connected to the ground line; the source of NPG0 is connected to the signal BLT, the drain is connected to the first storage node QT, and the gate is connected to the word line WL; the source of NPG1 is connected to the signal BLB, the drain is connected to the second storage node QB, and the gate is connected to the bit line WL.

[0015] Preferably, the control circuit comprises: a first PMOS tube and a first NMOS tube controlled by an inverse signal WAEB of a write assist enable signal; a second NMOS tube controlled by a bit line precharge signal PRCH; 2*n second PMOS tubes whose gates are controlled by bit lines, wherein n is the number of decoding bits of a bit line selector MUX; wherein the substrate terminal and the source terminal of the first PMOS tube are short-circuited and then connected to a power supply voltage VDD, the gate of the first MOS tube is connected to an inverse signal WAEB of a write assist enable signal, and the drain of the first PMOS tube is connected to the source of each second PMOS tube; in two groups of n In the second PMOS tube, the gate of the second PMOS tube is connected to the bit line BLT of the nth column and the bit line BLB of the nth column in sequence respectively; the gate of the first NMOS tube is connected to the inverted signal WAEB of the write auxiliary enable signal, the substrate terminal and the source terminal of the first NMOS tube are short-circuited and then grounded to the terminal VSS, and the drain terminal of the first NMOS is connected to the drain of each second PMOS tube; the gate of the second NMOS tube is connected to the bit line precharge signal PRCH, the substrate terminal and the source terminal of the first NMOS tube are short-circuited and then grounded to the terminal VSS, and the drain terminal of the second NMOS is connected to the drain of each second PMOS tube.

[0016] Preferably, when the write assist is enabled and the bit line is not charged, one of the 2*n bit lines writes "0", controls one of the 2*n second PMOS to be turned on, pulls up the write assist clock WACLK, and turns on the write assist negative voltage bit line module.

[0017] Preferably, the load size of the bit line BLT / BLB is linearly related to the number of mounted storage units. As the memory capacity increases, the falling time of the "0" bit line is prolonged, and the rising edge of the write assist clock WACLK is generated later.

[0018] Preferably, the NMOS source of the bit line driving inverter at the previous stage of the bit line selector module is connected to the negative voltage bit line module.

[0019] Preferably, in the write cycle and when the write assist function is turned on, the inverse signal WAEB of the write assist enable signal is 0, the first PMOS tube is turned on, and the first NMOS tube is turned off; in other cases, the inverse signal WAEB of the write assist enable signal is 1, the first PMOS tube is turned off, and the first NMOS tube is turned on.

[0020] Preferably, after entering the write cycle, the precharge signal PRCH=0, and the second NMOS tube is turned off.

[0021] Preferably, after exiting the write cycle, the precharge signal PRCH=1, the second NMOS tube is turned on, and the write auxiliary clock WACLK is pulled low to turn off the negative voltage bit line module.

[0022] Preferably, the other situation is a read cycle, the inverse signal WAEB of the write assist enable signal is set high, the write assist clock WACLK is always pulled low, and the write assist negative voltage bit line module will not be triggered to work, thereby preventing the negative voltage of the write driver tube from affecting the work of the readout sensitive amplifier.

[0023] Preferably, the write assist clock WACLK signal may be connected to any number of delay modules to fine-tune the generation time of the negative voltage pulse.

[0024] Preferably, the negative pressure pulse is applied locally in a single gate module.

[0025] Preferably, the negative voltage pulse is used as a global potential in a plurality of interconnected gate modules.

[0026] Preferably, the write auxiliary clock WACLK is a local signal in each gate module.

[0027] As described above, the negative voltage bit line control circuit for the SRAM write assist module of the present invention has the following beneficial effects:

[0028] The present invention overcomes the problem of mismatch between the negative voltage generation time and the write cycle control timing of SRAMs with different capacities in the design of an SRAM write assist module. The negative voltage module can be adaptively turned on by the potential of the bit line, which is particularly beneficial for the design of an SRAM compiler with flexible capacity adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1a Shown is a schematic diagram of the internal data of a normal write bit line flip SRAM of the prior art;

[0030] Figure 1b It is a schematic diagram showing the internal data of the negative voltage bit line flipping SRAM in the prior art;

[0031] Figure 2 Shown is a control circuit and module schematic diagram of a prior art write-assist negative voltage bit line module;

[0032] Figure 3 A schematic diagram showing the application of negative voltage pulses under different bit line loads in the prior art;

[0033] Figure 4 It shows a schematic diagram of a negative voltage pulse trigger signal for bit line voltage adaptive control according to the present invention;

[0034] Figure 5 It is a waveform diagram showing the adaptive bit line load control negative voltage pulse start of the present invention. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0036] The present invention provides a negative voltage bit line control circuit for an SRAM write assist module, comprising:

[0037] A memory cell array, wherein each memory cell is connected to a pair of word lines WL, a pair of bit lines BLT / BLB and a power supply line;

[0038] In some embodiments, see Figure 1a and Figure 1b The memory unit is a 6-transistor memory, which includes: 2 PMOS transistors PPU0 and PPU1 and 4 NMOS transistors NPD0, NPD1, NPG0 and NPG1; wherein NPD0 and NPD1 are pull-down transistors, PPU0 and PPU1 are rise-up transistors, and NPG0 and NPG1 are transmission transistors; the sources of PPU0 and PPU1 are connected to the working power supply Vdd of the memory unit, and the drains of PPU0 and PPU1 are connected to the drains of NPD0 and NPD1 respectively; the gate of PPU0 is connected to the gate of NPD0 to form a first storage node QB, and the gate of PPU1 is connected to the gate of NPD1 to form a second storage node QT; the sources of NPD0 and NPD1 are connected to the ground line; the source of NPG0 is connected to the signal BLT, the drain is connected to the first storage node QT, and the gate is connected to the word line WL; the source of NPG1 is connected to the signal BLB, the drain is connected to the second storage node QB, and the gate is connected to the bit line WL. It should be noted that, in other embodiments, the memory cell may also be of other types, such as an 8-transistor memory.

[0039] In some embodiments, the load size of the bit line BLT / BLB is linearly related to the number of mounted memory cells. As the memory capacity increases, the falling time of the "0" bit line is prolonged, and the rising edge of the write assist clock WACLK is generated later.

[0040] In some embodiments, the write assist clock WACLK signal may be followed by any number of delay modules to fine-tune the generation time of the negative voltage pulse.

[0041] The pre-charging module, in which the inverse signal WAEB of the write assist enable signal is 0 during the write cycle and the write assist function is turned on, the pre-charging module triggered by the rising edge of the clock CLK is turned off, and all the bit lines BLT / BLB are pre-charged to high and then suspended;

[0042] The gate module, after all bit lines BLT / BLB are precharged to high and then suspended, the control signal generated by the write driver module is transmitted through the column decoding address to select a pair of word lines to write data;

[0043] Negative voltage bit line module, which reduces the voltage of the "0" bit line to negative voltage during the write cycle to speed up data writing;

[0044] The control circuit is used to generate a write assist clock WACLK triggered by a negative voltage bit line module through bit line control. After a certain delay after the word line is selected, the write assist clock WACLK turns on the negative voltage bit line module to generate a negative voltage pulse, so that the negative voltage pulse is generated after the "0" bit line drops to 0, thereby ensuring that the write assist function is effective.

[0045] In some embodiments, negative pressure pulses are applied locally within a single gate module.

[0046] In some embodiments, the negative voltage pulse is applied as a global potential across multiple interconnected gate modules.

[0047] In some embodiments, the write auxiliary clock WACLK is a local signal in each gate module and will not go through a long line to generate delay. Therefore, it is not necessary to adjust the near-far end delay of WACLK to align with WPASS.

[0048] In some embodiments, see Figure 4 The control circuit includes: a first PMOS tube and a first NMOS tube controlled by an inverse signal WAEB of a write assist enable signal; a second NMOS tube controlled by a bit line precharge signal PRCH; 2*n second PMOS tubes whose gates are controlled by bit lines, wherein n is the number of decoding bits of a bit line selector MUX; wherein the substrate terminal and the source terminal of the first PMOS tube are short-circuited and then connected to a power supply voltage VDD, the gate of the first MOS tube is connected to an inverse signal WAEB of a write assist enable signal, and the drain of the first PMOS tube is connected to the source of each second PMOS tube; in two groups of n first PMOS tubes, In the two PMOS tubes, the gate of the second PMOS tube is connected to the bit line BLT of the nth column and the bit line BLB of the nth column respectively; the gate of the first NMOS tube is connected to the inverse signal WAEB of the write auxiliary enable signal, the substrate terminal and the source terminal of the first NMOS tube are short-circuited and then connected to the ground terminal VSS, and the drain terminal of the first NMOS is connected to the drain of each second PMOS tube; the gate of the second NMOS tube is connected to the bit line precharge signal PRCH, the substrate terminal and the source terminal of the first NMOS tube are short-circuited and then connected to the ground terminal VSS, and the drain terminal of the second NMOS is connected to the drain of each second PMOS tube.

[0049] For example, Figure 4 As shown, this embodiment is a 4-bit column decoding memory, and similarly, it can also be applied to column decoding modes of other bit numbers.

[0050] Four pairs of PMOS tubes for bit line control are added in the selector module, one PMOS tube controlled by the inverse signal WAEB of the write assist enable signal, and two NMOS tubes controlled by the pre-charge signals PRCH and WAEB. The generated write assist enable signal WACLK is used to trigger the negative voltage bit line module to turn on.

[0051] In the write cycle and write assist function is on, WAEB=0, the precharge (PRCH) module triggered by the rising edge of the clock CLK is turned off, all bit lines BLT / BLB are precharged to high and then suspended; then a pair of NMOS tubes selected and controlled by the column decoding address WPASS[3:0] are turned on, and the DT / DB signal generated by the write driver module is input through a pair of word lines selected by the column decoding address. If the written data is 1, the bit line BLT remains at a high potential, and the bit line BLB is reduced to a low potential. At this time, one of the four pairs of bit lines is reduced to turn on the PMOS tube, and the write assist enable signal WACLK is raised. After several levels of short gate delays, the negative voltage pulse is generated just after the "0" bit line drops to 0. The specific waveform is as follows Figure 5 As shown, it can be seen that the negative voltage pulse can be generated normally regardless of the bit line load size.

[0052] In some embodiments, when write assist is enabled and the bit line is not charged, one of the 2*n bit lines is written with "0", controlling one of the 2*n second PMOS to be turned on, thereby pulling up the write assist clock WACLK and turning on the write assist negative voltage bit line module.

[0053] In some embodiments, the NMOS source of the bit line driving inverter at a stage before the gate module of the bit line is connected to the negative voltage bit line module.

[0054] In some embodiments, during a write cycle and when the write assist function is on, the inverse signal WAEB of the write assist enable signal is 0, the first PMOS tube is turned on, and the first NMOS tube is turned off; in other cases, the inverse signal WAEB of the write assist enable signal is 1, the first PMOS tube is turned off, and the first NMOS tube is turned on.

[0055] In some embodiments, after entering the write cycle, the precharge signal PRCH=0, and the second NMOS transistor is turned off.

[0056] In some embodiments, after exiting the write cycle, the precharge signal PRCH=1, the second NMOS tube is turned on, the write auxiliary clock WACLK is pulled low to turn off the negative voltage bit line module, and the negative voltage capacitor is recharged to wait for the next write cycle.

[0057] In some embodiments, other situations are read cycles, the inverse signal WAEB of the write assist enable signal is set high, and the write assist clock WACLK is always pulled low, which will not trigger the write assist negative voltage bit line module to work, thereby avoiding the negative voltage of the write driver tube affecting the operation of the read-out sensitive amplifier, and also saving more power consumption in the read cycle.

[0058] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0059] In summary, the present invention overcomes the problem of the mismatch between the negative voltage generation time and the write cycle control timing of SRAMs of different capacities in the design of SRAM write assist modules, and can adaptively turn on the negative voltage module through the potential of the bit line, which is particularly beneficial for the design of SRAM compilers with flexible capacity adjustment. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0060] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A negative voltage bit line control circuit for an SRAM write assist module, characterized in that: include: A memory cell array, wherein each memory cell is connected to a pair of word lines WL, a pair of bit lines BLT / BLB and a power supply line; The pre-charging module, in which the inverse signal WAEB of the write assist enable signal is 0 during the write cycle and the write assist function is turned on, the pre-charging module triggered by the rising edge of the clock CLK is turned off, and all the bit lines BLT / BLB are pre-charged to high and then suspended; The gate module, after all bit lines BLT / BLB are precharged to high and then suspended, the control signal generated by the write driver module is transmitted through the column decoding address to select a pair of word lines to write data; Negative voltage bit line module, which reduces the voltage of the "0" bit line to negative voltage during the write cycle to speed up data writing; The control circuit is used to generate a write auxiliary clock WACLK triggered by a negative voltage bit line module through bit line control. After a certain delay after the word line is selected, the write auxiliary clock WACLK turns on the negative voltage bit line module to generate a negative voltage pulse, so that the negative voltage pulse is generated after the "0" bit line drops to 0.

2. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The memory unit is a 6-transistor memory, which includes: 2 PMOS transistors PPU0 and PPU1 and 4 NMOS transistors NPD0, NPD1, NPG0 and NPG1; wherein NPD0 and NPD1 are pull-down transistors, PPU0 and PPU1 are rise-up transistors, and NPG0 and NPG1 are transmission transistors; the sources of PPU0 and PPU1 are connected to the working power supply Vdd of the memory unit, and the drains of PPU0 and PPU1 are connected to the drains of NPD0 and NPD1 respectively; the gate of PPU0 is connected to the gate of NPD0 to form a first storage node QB, and the gate of PPU1 is connected to the gate of NPD1 to form a second storage node QT; the sources of NPD0 and NPD1 are connected to the ground line; the source of NPG0 is connected to the signal BLT, the drain is connected to the first storage node QT, and the gate is connected to the word line WL; the source of NPG1 is connected to the signal BLB, the drain is connected to the second storage node QB, and the gate is connected to the bit line WL.

3. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The control circuit comprises: a first PMOS tube and a first NMOS tube controlled by an inverse signal WAEB of a write assist enable signal; a second NMOS tube controlled by a bit line precharge signal PRCH; 2*n second PMOS tubes whose gates are controlled by bit lines, wherein n is the number of decoding bits of a bit line selector MUX; wherein the substrate end and the source end of the first PMOS tube are short-circuited and then connected to a power supply voltage VDD, the gate of the first MOS tube is connected to an inverse signal WAEB of a write assist enable signal, and the drain of the first PMOS tube is connected to the source of each second PMOS tube; in two groups of n second PMOS tubes, In the two PMOS tubes, the gate of the second PMOS tube is connected to the bit line BLT of the nth column and the bit line BLB of the nth column respectively; the gate of the first NMOS tube is connected to the inverse signal WAEB of the write auxiliary enable signal, the substrate terminal and the source terminal of the first NMOS tube are short-circuited and then connected to the ground terminal VSS, and the drain terminal of the first NMOS is connected to the drain of each second PMOS tube; the gate of the second NMOS tube is connected to the bit line precharge signal PRCH, the substrate terminal and the source terminal of the first NMOS tube are short-circuited and then connected to the ground terminal VSS, and the drain terminal of the second NMOS is connected to the drain of each second PMOS tube.

4. The negative voltage bit line control circuit for an SRAM write assist module according to claim 3, characterized in that: When the write assist is enabled and the bit line is not charged, one of the 2*n bit lines is written with "0", and one of the 2*n second PMOS is controlled to be turned on to pull up the write assist clock WACLK and start the write assist negative voltage bit line module.

5. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The load size of the bit line BLT / BLB is linearly related to the number of mounted storage units. As the memory capacity increases, the falling time of the "0" bit line is prolonged, and the rising edge of the write auxiliary clock WACLK is generated later.

6. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The NMOS source of the bit line driving inverter at the previous stage of the bit line selector module is connected to the negative voltage bit line module.

7. The negative voltage bit line control circuit for an SRAM write assist module according to claim 3, characterized in that: In the write cycle and when the write assist function is on, the inverse signal WAEB of the write assist enable signal is 0, the first PMOS tube is turned on, and the first NMOS tube is turned off; in other cases, the inverse signal WAEB of the write assist enable signal is 1, the first PMOS tube is turned off, and the first NMOS tube is turned on.

8. The negative voltage bit line control circuit for an SRAM write assist module according to claim 7, characterized in that: After entering the write cycle, the precharge signal PRCH=0, and the second NMOS tube is turned off.

9. The negative voltage bit line control circuit for an SRAM write assist module according to claim 8, characterized in that: After exiting the write cycle, the precharge signal PRCH=1, the second NMOS tube is turned on, and the write auxiliary clock WACLK is pulled low to turn off the negative voltage bit line module.

10. The negative voltage bit line control circuit for an SRAM write assist module according to claim 9, characterized in that: The other situation is a read cycle, the inverse signal WAEB of the write assist enable signal is set high, and the write assist clock WACLK is always pulled low, which will not trigger the write assist negative voltage bit line module to work, thereby preventing the negative voltage of the write driver tube from affecting the work of the readout sensitive amplifier.

11. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The write auxiliary clock WACLK signal may be connected to any number of delay modules to fine-tune the generation time of the negative voltage pulse.

12. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The negative pressure pulses are applied locally in a single gate module.

13. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The negative voltage pulse is used as a global potential in multiple interconnected gate modules.

14. The negative voltage bit line control circuit for an SRAM write assist module according to claim 1, characterized in that: The write assist clock WACLK is a local signal in each gate module.

Images