Content addressable storage system and addressing method for realizing accurate or fuzzy lookup

Abstract

The invention relates to a content addressable storage system and an addressing method for realizing accurate or fuzzy lookup. In a set of transistors of the memory defined by adjacent bit lines and adjacent source lines, the set of transistors share a common word line. In the addressing stage, a first potential is required to be applied to the previous bit line and a second potential is required to be applied to the next bit line in the adjacent bit lines. The set of transistors is defined in the addressing phase to provide a first state if the current of the previous source line exceeds the current of the latter source line based on the first potential and the second potential being not equal, otherwise they are defined to provide a second state. On the basis that the first potential and the second potential are equal, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the set of transistors are defined to provide a third state in the addressing phase.

Description

Technical Field

[0001] The present invention mainly relates to the technical field of data storage, and more specifically, to a content-addressable storage system in the field of data storage and an addressing method for realizing precise search or fuzzy search. Background Art

[0002] Content addressable memory (CAM) is used to search applications and provide fast and accurate matching. Consumer electronic network devices such as network switches and routers all include addressable memory to provide standards for multiple switching rules for various functional storage. For example, packet parsing, quality of service allocation, security, forwarding, filtering and other necessary switching rules use a lot of addressable storage.

[0003] Content addressable memory is very different from the commonly used random access memory (RAM) in that it uses the input data content to check the corresponding address data and provide output. When using random access memory, the data stored at the address position is read out using the input address. When using content addressable memory, the input data is compared with the data stored in the memory at the same time. If the same content exists, the address information stored by the same data and the search success signal are output. Otherwise, the search success signal cannot be output.

[0004] The main drawback of current content addressable memory is that it requires a lot of additional circuits, such as circuits for matching and estimating all bits in the memory with the input data, and circuits for saving the matching estimation results. Even if no search task is performed, the related additional circuits still have static power consumption in the non-addressing state. Therefore, it is necessary to provide an addressable response strategy based on a simplified circuit structure and meet the current application requirements of big data search. Summary of the invention

[0005] The present application relates to a content-addressable storage system, characterized in that it includes:

[0006] A memory, wherein in a group of transistors defined by adjacent bit lines and adjacent source lines of the memory, the group of transistors share a common word line, and in an addressing phase, a first potential is applied to a preceding bit line and a second potential is applied to a succeeding bit line among the adjacent bit lines;

[0007] Based on the inequality between the first potential and the second potential, if the current of the previous source line exceeds the current of the subsequent source line, the group of transistors are defined to provide the first state in the addressing phase, otherwise, they are defined to provide the second state;

[0008] Based on the first potential and the second potential being equal, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the group of transistors is defined to provide a third state during the addressing phase.

[0009] In the above content-addressable storage system, the first state and the second state are 0 and 1 respectively, or vice versa, the first state and the second state are 1 and 0 respectively, and the third state is a don't care (Do Not Care). This article uses [0] or [1] or [N] don't care to represent the ternary content of the first state, the second state and the third state respectively.

[0010] In the above-mentioned content-addressable storage system, the manner in which the data to be checked (e.g., data used for addressing) is accurately matched with the storage content in the memory includes: the first logical value in the data to be checked is represented by using unequal first potential and second potential, and the first potential is greater than the second potential; and the second logical value in the data to be checked is represented by using unequal first potential and second potential, and the first potential is less than the second potential.

[0011] In the above-mentioned content-addressable storage system, the manner in which the to-be-searched data (eg, data used for addressing) fuzzily matches the storage content in the memory includes: the indefinite value in the to-be-searched data is represented by an equal first potential and a second potential.

[0012] In the above-mentioned content-addressable storage system, the first logic value and the second logic value in the to-be-searched data (eg, data used for addressing) are 1 and 0 respectively, or vice versa.

[0013] In the above content-addressable storage system, when the data to be searched matches the storage content in the memory, the address where the storage content is currently located is used as the output result, i.e. the addressing address. In principle, content addressing works the other way around, i.e. the data is used as a key to search for its address, rather than searching for data based on the address.

[0014] In the above-mentioned content-addressable storage system, in the group of transistors, the floating gate of a transistor determined by the previous bit line and the next source line has charges written in advance, and the floating gates of the remaining transistors have no charges written, which serves as the default first state of the group of transistors.

[0015] In the above-mentioned content-addressable storage system, in the group of transistors, the floating gate of a transistor determined by the latter bit line and the former source line has charge written in advance, and the floating gates of the remaining transistors have no charge written in advance, which serves as the default second state of the group of transistors.

[0016] In the above-mentioned content-addressable storage system, among the group of transistors, charges are written into the floating gates of both a transistor determined by a previous bit line and a previous source line and a transistor determined by a subsequent bit line and a subsequent source line in advance, and charges are not written into the floating gates of the remaining transistors, which serves as the default third state of the group of transistors.

[0017] In the above-mentioned content-addressable storage system, among the group of transistors, charges are written into the floating gates of a transistor determined by a previous bit line and a subsequent source line and a transistor determined by a subsequent bit line and a previous source line in advance, and charges are not written into the floating gates of the remaining transistors, which serves as the default third state of the group of transistors.

[0018] The present application relates to an addressing method for realizing precise or fuzzy search, characterized in that it includes:

[0019] In a memory, a group of transistors is defined by adjacent bit lines and adjacent source lines, and they share a common word line;

[0020] The method of implementing accurate search of the to-be-checked data in the memory includes: a first logic value in the to-be-checked data is represented by a first potential and a second potential that are not equal, and the first potential is greater than the second potential; a second logic value in the to-be-checked data is represented by a first potential and a second potential that are not equal, and the first potential is less than the second potential;

[0021] The method of implementing fuzzy search of the to-be-searched data in the memory includes: an indefinite value in the to-be-searched data is represented by an equal first potential and a second potential;

[0022] A first potential is applied to a preceding bit line and a second potential is applied to a succeeding bit line among adjacent bit lines;

[0023] Based on the inequality between the first potential and the second potential, if the current of the previous source line exceeds the current of the subsequent source line, the group of transistors are defined to provide the first state in the addressing phase, otherwise, they are defined to provide the second state;

[0024] Based on the first potential and the second potential being equal, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the group of transistors is defined to provide a third state during the addressing phase;

[0025] When the data to be checked matches the storage content in the memory, the address where the storage content is currently located is returned as the addressing address.

[0026] In the above-mentioned addressing method for realizing precise or fuzzy search, when the data to be searched matches the storage content in the memory, the address where the storage content is currently located is used as the output result, namely the addressing address.

[0027] In the above-mentioned addressing method for realizing precise or fuzzy search, in the group of transistors, the floating gate of a transistor determined by the previous bit line and the next source line has charge written in advance, and the floating gates of the remaining transistors have no charge written, which serves as the default first state of the group of transistors.

[0028] In the above-mentioned addressing method for realizing precise or fuzzy search, in the group of transistors, the floating gate of a transistor determined by the latter bit line and the former source line has charge written in advance, and the floating gates of the remaining transistors have no charge written, which serves as the default second state of the group of transistors.

[0029] In the above-mentioned addressing method for realizing precise or fuzzy search, among the group of transistors, charges are written into the floating gates of a transistor determined by a previous bit line and a previous source line and a transistor determined by a subsequent bit line and a subsequent source line in advance, and charges are not written into the floating gates of the remaining transistors, which serves as the default third state of the group of transistors; or, charges are written into the floating gates of a transistor determined by a previous bit line and a subsequent source line and a transistor determined by a subsequent bit line and a previous source line in advance, and charges are not written into the floating gates of the remaining transistors, which serves as the default third state of the group of transistors.

[0030] The present application relates to a content-addressable storage system, characterized in that it includes:

[0031] A memory, wherein in a group of transistors defined by adjacent bit lines and adjacent source lines of the memory, the group of transistors share a common word line, and in an addressing phase, a first potential is applied to a preceding bit line and a second potential is applied to a succeeding bit line among the adjacent bit lines;

[0032] When looking for the state of the group of transistors, the currents of two adjacent source lines need to be compared:

[0033] Based on the inequality between the first potential and the second potential, if the current of the previous source line exceeds the current of the subsequent source line, the group of transistors are defined to provide the first state in the addressing phase, otherwise, they are defined to provide the second state;

[0034] Based on the first potential and the second potential being equal, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the group of transistors is defined to provide a third state during the addressing phase.

[0035] The memory used in this application is compatible with existing memories, such as vertical three-dimensional flash memory. Therefore, the power consumption is basically equivalent to that of existing memories, the circuit changes are very small, there are no excessive additional auxiliary circuits, and it has extremely low static power consumption under non-addressing state conditions. In the addressing stage, three states can be provided instead of two states so that the addressing requirements of precise search or fuzzy search can be met at the same time, which meets the mainstream search requirements. The most critical thing is that during the data operation of the memory, a positive voltage will be frequently applied to the gate of the transistor, that is, the word line. This type of operation will accidentally and not intentionally allow the floating gate of the transistor to be slightly programmed, and as a result, the current resolution of the source line of the memory is reduced. When the source line current of the memory is relatively high, the high and low value states of the source line current can still be distinguished. However, when the source line current is low, it is difficult to identify the state that the source line current is intended to express by the source line current, because the difference between any two values ​​of the extremely low source line current is very small and the source line current resolution cannot be infinitely improved. Therefore, the two current values ​​of the source line current intended to express two states are prone to transmit the wrong state due to recognition errors, or the three current values ​​intended to express three states are prone to transmit the wrong state due to recognition errors. One of the considerations of this application is to solve the concerns about state recognition errors caused by the reduction of source line current resolution due to the programming of the floating gate of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to make the above purposes, features and advantages more understandable, the following text will explain the specific implementation methods in detail in conjunction with the drawings. After reading the following description and referring to the following drawings, the features and advantages of the present application will become apparent.

[0037] Figure 1 Explains the difference between content addressable and address addressable in addressable applications.

[0038] Figure 2 It is an explanation of content addressability in terms of achieving precise search or fuzzy search.

[0039] Figure 3 This article uses vertical three-dimensional flash memory as an example to explain content addressability.

[0040] Figure 4 It is used in a group of transistors as the first state of the group of transistors by default.

[0041] Figure 5 It is used in a group of transistors as the second state of the group of transistors by default.

[0042] Figure 6 It is used in a group of transistors as the third state of the group of transistors by default.

[0043] Figure 7It is an example of an addressing method that implements exact or fuzzy search in memory. DETAILED DESCRIPTION

[0044] The technical solutions disclosed in the present application will be clearly and completely described below in conjunction with specific embodiments. However, the embodiments described are only embodiments used for narrative explanation in the present application and are not all embodiments. Based on these embodiments, technicians in this field should realize that any solution obtained without creative work falls within the scope of protection of the present application.

[0045] See also Figure 1 Content addressable is a content-based addressing method. It can be used for high-speed storage, and the stored content remains unchanged. The basic protocol of the currently popular interplanetary file system draws on content addressability. Interplanetary File System (IPFS) is a distributed and peer-to-peer file system protocol. Its goal is to solve the file transfer and storage problems existing in the current Internet and achieve more efficient and secure file transfer and storage.

[0046] See also Figure 1 Let's first explain the difference between content addressable and address addressable. Taking the Internet as an example, the most common addressable application in the industry is address addressable. For example, an IP address can be given, and the user can successfully find the corresponding content stored at this address based on the given address. Another example is that in a computer operating system, the location of the file storage can be found through the path, such as E:\aa\bb\cc.txt, which is a txt file drive letter path. For example, the main drive letter is defined in the E drive, and the main drive letter is the aa folder and the bb folder under the aa folder. Finally, the file named cc and in the txt format is saved in the bb folder.

[0047] See also Figure 1 Content addressability mainly generates content addresses through file content. A typical example is allowing a hash algorithm (HASH algorithm) to be used to find files through content addresses and find files based on addresses.

[0048] See also Figure 1, content addressable is used, for example, between a router and a CPU / cache memory, etc., so that high-speed searches can be performed there. Usually in a general-purpose memory such as RAM (such as SRAM or DRAM), when a specific address is specified or given, the data stored at the address is sent back. On the contrary, when the search data is specified or given, the content addressable memory needs to retrieve the stored data that matches the specified search data from all the content and send back the matching address where the stored data is stored. For example, in addressing applications, when a user enters a data word, another data word associated with the data word can be provided or output.

[0049] See also Figure 1 , and then compare the advantages and disadvantages of content addressability and address addressability. When addressing, according to its addressing characteristics, it can be analyzed that if the content corresponding to the address is deleted or destroyed, or the location of the content is changed, it will cause the failure to access the content through the physical address. In practice, it is common to encounter web pages with 404 failures, or often encounter situations where you click on the network disk link for network download resources and are informed that the link is invalid.

[0050] See also Figure 1 The content-addressable approach can avoid the above situations and ensure the integrity of the file content (not tampered with) because the content address is the result of the inference of the file content by, for example, a HASH algorithm. Once the file content changes, the content address will change accordingly. For example, if an original file is modified actively or accidentally, the original file and the modified file are no longer files with the same pointer. They have different content addresses.

[0051] See also Figure 1 The advantages of content addressing are that files can be stored permanently, file integrity is guaranteed, file content has excellent backup processing capabilities, retrieval speed is fast, and it supplements address addressing.

[0052] See also Figure 1 Because the file is based on content addressing, any identical file address will point to the same content address in the entire content addressing, and the content added later is just a pointer to the first content address. In this way, the file content in the content addressing can be better backed up in actual applications.

[0053] See also Figure 1 In terms of functional complementarity, regarding the scope of application of content addressing, content addressing can actually complement addressing. For example, for files whose contents are not easily changed, such as drafted contracts and various legal documents, content addressing can be used for storage.

[0054] See also Figure 1 , the following part is explained based on content addressability.

[0055] See also Figure 1 , content addressable memory, in addition to binary content addressable memory (CAM) there is also ternary content addressable memory (TCAM). Specifically, the characteristic of binary content addressable memory is that the data type of 0 or 1 is stored in the physical storage unit, and the input content and the stored data are compared to retrieve the address information of the content data stored in the physical device. In contrast, the characteristic of ternary content addressable memory is that 0 or 1 or no fixed value is stored in the physical storage unit, and when retrieving the stored data, the combination of the three must be input, and compared with the input content and the stored data to retrieve the address information of the location where the content data is stored. How to provide an addressable memory with a high retrieval speed while adapting to a large storage capacity is a difficult problem.

[0056] See also Figure 3 , this article will explain the content-addressable storage circuit and the addressing method for achieving precise or fuzzy search by taking the vertical-NAND memory as an example.

[0057] See also Figure 2 , this article uses [0] or [1] or [N] don't care (Do Not Care) to represent ternary content. Ternary content addressable memory TCAM is developed on the basis of CAM. Generally speaking, the traditional binary content addressable memory CAM stipulates that each bit has only two states, namely [0] or [1]. The inherited ternary content addressable memory TCAM stipulates that each bit has three states, namely [0] or [1] or [N], so it is called three states and can be implemented through masks. It is this third state feature of TCAM that enables it to perform both exact match search and fuzzy match search, while CAM does not have a third state and can only perform exact match search.

[0058] See also Figure 2 , Regarding ternary content addressable memory technology, it is essentially a hardware lookup technology that can be used to improve the efficiency of router table lookup. TCAM can be applied to hardware chips dedicated to table lookup operations. For example, hardware-based routing table lookup and packet forwarding technology can be used to quickly classify and route various data packets. Its advantages are reflected in its excellent performance and strong scalability, and it is very suitable for routers in complex scenarios.

[0059] See also Figure 3 , showing the bit lines B1-BN of the flash memory, the positive integers J and N satisfy 0≤J≤N.

[0060] See also Figure 3 , showing the drain select line DS (Drain Sel Line) of the flash memory.

[0061] See also Figure 3 , showing the word lines W0-WM of the flash memory, the positive integers K and M satisfy 0≤K≤M.

[0062] See also Figure 3 , showing the source select line SS (Source Sel Line) of the flash memory.

[0063] See also Figure 3 , showing the source line CS (Cell Source Line) of the flash memory.

[0064] See also Figure 3 The working principle of the memory shown in the figure is basically similar to that of the traditional flash memory (NAND FLASH). For example, a floating gate (Floating Gate) that stores charges such as electrons can be formed between the source and drain of the storage transistor, that is, on the semiconductor where the current is conducted in one direction. The floating gate is wrapped with a layer of silicon oxide film insulator. Above it is the selection / control gate (Control Gate) that controls the conduction current between the source and the drain. The charges in the gate, such as electrons, will not disappear due to power failure, so the flash memory is a non-volatile memory. The write operation is to apply a positive voltage to the control electrode so that the charges, such as electrons, pass through the insulating layer into the floating gate. The erase operation is just the opposite, which is to apply a positive voltage to the substrate to separate electrons from the floating gate to achieve erasure. The data operation of the flash memory belongs to the prior art and will not be described separately in this article.

[0065] See also Figure 3 Based on the working principle of flash NAND reading, when reading a page, the control gates of the unselected pages in the entire block will be positively voltageed to ensure that the unselected transistors are turned on. The problem is that frequent application of voltage to the control gate of the transistor may cause charge to be sucked into the floating gate, forming a slight passive programming and ultimately causing the bit state of the body tube to flip.

[0066] See also Figure 3 For the time being, let's take the two transistors defined by word line W0 and bit lines B1-B2 as an example. During the data operation of the memory, for example, the two transistors defined by word line W0 and bit lines B1-B2 are read objects, and at the same time, positive voltage (called pass voltage) is frequently applied to other transistors such as word line W0, which may accidentally and unintentionally cause the floating gates of the transistors defined by word line W0 and bit lines B1-B2 to be slightly passively programmed, such as charging the floating gates.

[0067] See also Figure 3, we can still take the two transistors defined by the word line W0 and the bit lines B1-B2 as an example. If they are used to program two states (or three states) of a content addressable memory, assume that the two transistors are passively programmed. When a voltage is applied to the word line W0 during addressing, the current on the source line CS is assumed to be ICS. When the source line current is high, it is still possible to distinguish the high and low value states of the source line current ICS. For example, if a threshold value is set, the source line current ICS above the threshold value can represent one state [0] and below the threshold value can represent another state [1]. After the transistor is passively programmed in a hidden or imperceptible manner, when the same voltage is applied to the word line W0 during addressing, the source line current ICS that can flow to the source line CS is greatly reduced compared to the original value due to the accidental programming of the transistor. This result causes the current resolution of the source line of the memory to be significantly reduced. The smaller the current, the more difficult it is to distinguish, especially after the semiconductor technology node reaches the nanometer level, this trend of reduced current resolution becomes more and more obvious. Furthermore, the current mainstream trend of flash memory operating voltage is gradually decreasing year by year. For example, taking Kioxia BiCS4 96-layer stacked flash memory as an example, its typical operating voltage has been reduced from the early 1.8 / 3.3V to 1.2 / 1.8V. The low voltage further clamps the current resolution. When the source line current is low, it is difficult to identify the state to be expressed by the source line current ICS. For example, any two values ​​of the source line current are recorded as ICS1 and ICS2, which are derived from the voltage changes on the bit lines B1 and B2. Due to the hidden passive programming of the transistor, even if the voltage changes on the bit lines B1 and B2 are large, the current difference between ICS1 and ICS2 will not change proportionally with the change in voltage. The difference between the two values ​​of ICS1 and ICS2 of the extremely low source line current is very small, and the source line current resolution cannot be continuously improved indefinitely. The two current values ​​ICS1 and ICS2 that are originally intended to express two states of the source line current are prone to conveying the wrong state due to misidentification. For example, they currently express the state [0] or the state [1] at the same time, or the two states currently expressed, such as [0] and [1], are opposite to the two states originally intended to be expressed, such as [1] and [0]. The following provides corresponding solutions for how to solve such problems.

[0068] See also Figure 4 , about content-addressable storage systems, including Figure 3 The memory shown includes, but is not limited to, a flash memory or a vertical flash memory.

[0069] See also Figure 4, in a group of transistors T10, T20, T30, T40 shown in the memory defined by adjacent bit lines BJ, BJ+1 and adjacent source lines CSQ, CSQ+1, the group of transistors shares a common word line WK. In addition, if the word line WK+1 shown in the figure is taken as an example, then in a group of transistors T1, T2, T3, T4 shown in the memory defined by bit lines BJ, BJ+1 and adjacent source lines CSQ, CSQ+1, the group of transistors shares a common word line WK+1. Therefore, the so-called group of transistors here should have the same common word line, and transistors located at different word lines cannot be regarded as part of the same group of transistors. This is a setting made by the present application to adapt to the paging structure of the same block of flash memory. It should also be noted that the aforementioned transistors T10-T40 and T1-T4 are two different groups of transistors.

[0070] See also Figure 4 , a group of transistors defined or determined by adjacent bit lines BJ, BJ+1 and adjacent source lines CSQ, CSQ+1 of the memory refers to a group of transistors (such as the first group T10-T40 or the second group T1-T4) coupled between these adjacent bit lines BJ, BJ+1 and adjacent source lines CSQ, CSQ+1. Specifically, for example, transistor T1 is coupled between one of the adjacent bit lines BJ and one of the adjacent source lines CSQ, transistor T2 is coupled between one of the adjacent bit lines BJ and the remaining two adjacent source lines CSQ+1, transistor T3 is coupled between the second adjacent bit line BJ+1 and the first adjacent source line CSQ, and transistor T4 is coupled between the second adjacent bit line BJ+1 and the remaining two adjacent source lines CSQ+1. Therefore, it can be seen that adjacent bit lines and adjacent source lines can only define or determine a group of four transistors at a time. If the transistor group is defined or determined without adjacent bit lines and adjacent source lines, for example, the transistor group is defined by spaced bit lines and spaced source lines, the number of transistors used in the transistor group is greater, which is more conducive to determining each state, but the storage density is also reduced. Therefore, defining four transistors at a time is the best choice. If only two transistors are selected at a time, the above-mentioned situation will occur, where one or two transistors are passively programmed in a hidden and imperceptible manner, and are prone to transmitting the wrong state due to recognition errors.

[0071] See also Figure 4, a solution follows: when the data to be checked is performing the addressing query process, a read voltage or query voltage can be applied to the word line WK first, and the single state information represented by the first group T10-T40 is matched with a corresponding bit data in the data to be checked. The two have a match or mismatch result. Note that in this process, the word line WK+1 is applied with a pass voltage to ensure that the second group T1-T4 is turned on. After that, the data to be checked continues to perform the addressing query, and WK is given a pass voltage and the word line WK+1 is a read voltage or query voltage, thereby switching to matching the single state represented by the second group T1-T4 with the corresponding bit data in the data to be checked. The two have a match or mismatch result. It is found that data query or addressing is transferred from T10-T40 to T1-T4.

[0072] See also Figure 3 Based on the addressing described above, the query or addressing is passed from word line W0 to WM until all pages are queried one by one. However, it is worth noting that if the data to be queried matches the storage content in the memory, the query needs to be stopped, for example, stopping at the position or address of word line WK, and the address where the matching storage content is currently located is used as the output result, that is, the addressing address, which belongs to the return value of the addressing.

[0073] See also Figure 4 , taking transistors T10, T20, T30, and T40 as examples, the addressing stage requires that the first bit line in the adjacent bit lines, such as BJ, be applied with a first potential V_pro1 and the second bit line, such as BJ+1, be applied with a second potential V_pro2. Note that the adjacent bit lines require that they are arranged as two bit lines one after the other, and no other bit lines are allowed in the middle of their arrangement. Now, for example, BJ and BJ+1 are arranged as two bit lines one after the other and are adjacent bit lines. The arrangement of BJ and BJ+2 does not belong to the two bit lines one after the other and does not belong to adjacent bit lines, and B3 and B5 do not belong to adjacent bit lines. Similarly, the adjacent source lines, such as CSQ and CSQ+1, are arranged as two source lines one after the other and are adjacent. The arrangement of CSQ and CSQ+2 does not belong to the two source lines one after the other and does not belong to adjacent source lines, and CSQ0 and CSQ2 do not belong to adjacent source lines.

[0074] See also Figure 4 Among the adjacent bit lines, there is a preceding bit line and a succeeding bit line. All bit lines are divided according to the preceding and succeeding adjacent bit lines, and the query of each bit data is performed in units of two adjacent bit lines.

[0075] See also Figure 4 Among the adjacent source lines, there is a preceding source line and a following source line. All source lines are divided according to the preceding and following adjacent source lines, and the query of each bit data is performed in units of two adjacent source lines.

[0076] See also Figure 4 Based on the inequality between the first potential V_pro1 and the second potential V_pro2, the current of the previous source line CSQ exceeds the current of the subsequent source line CSQ+1, and the group of transistors T10, T20, T30, and T40 are defined to provide a first state or a first state [state_1] during the addressing phase.

[0077] See also Figure 5 Based on the inequality between the first potential V_pro1 and the second potential V_pro2, the current of the previous source line CSQ is lower than the current of the subsequent source line CSQ+1, and the group of transistors T10, T20, T30, and T40 are defined to provide a second state or a second state [state_2] during the addressing phase.

[0078] See also Figure 6 , based on the first potential V_pro1 and the second potential V_pro2 being equal, the difference between the current of the previous source line CSQ and the current of the next source line CSQ+1 (such as the difference between the two currents) is within a preset range (such as the preset range is a current range with a lower current limit and an upper current limit specified in advance), then at this time, the group of transistors T10, T20, T30, T40 is defined to provide a third state or a third state [state_3] in the addressing stage.

[0079] See also Figure 4 , optionally, the first state [state_1] and the second state [state_2] are [0] and [1] respectively.

[0080] See also Figure 5 , optionally, the first state [state_1] and the second state [state_2] are [1] and [0] respectively.

[0081] See also Figure 6 , optional, the third state [state_3] corresponds to the optional [N] or irrelevant item (Do Not Care).

[0082] See also Figure 4 , among the transistor groups defined by adjacent bit lines BJ and BJ+1 and adjacent source lines CSQ and CSQ+1 of the memory: a pair of transistors T1-T2 in the group of transistors T1-T4 share the same bit line BJ and the remaining other pair of transistors T3-T4 share the same other bit line BJ+1. One transistor of each of the two pairs of transistors T1-T2, T3-T4, such as T1, T3, share a source line CSQ, and the other transistors of each of the two pairs of transistors T1-T2, T3-T4, such as T2, T4, share another source line CSQ+1.

[0083] See also Figure 4 , the relationship between the current of the previous source line CSQ and the current of the next source line CSQ+1 is compared using a current comparator comp in the embodiment shown in the figure. In an optional example, their currents can also be converted into voltages through a load such as a resistor and then compared using a voltage comparator. The output result out of the comparator comp in the embodiment shown in the figure is based on the first state [state_1] equal to [1] as an example, but can also be [0]. The comparison relationship that the current of the previous source line CSQ exceeds the current of the next source line CSQ+1 is an assumption made in the example in the figure.

[0084] See also Figure 5 , the relationship between the current of the previous source line CSQ and the current of the next source line CSQ+1 is compared using a current comparator comp in the embodiment shown in the figure. In an optional example, their currents can also be converted into voltages through a load such as a resistor and then compared using a voltage comparator. The output result out of the comparator comp in the embodiment shown in the figure is based on the second state [state_2] equal to [0] as an example, but can also be [1]. The comparison relationship that the current of the previous source line CSQ is less than the current of the next source line CSQ+1 is an assumption made in the example in the figure.

[0085] See also Figure 6 , the relationship between the current of the previous source line CSQ and the current of the next source line CSQ+1 is compared using a current comparator comp in the embodiment shown in the figure. In an optional example, their currents can also be converted into voltages through a load such as a resistor and then compared using a voltage comparator. The output result out of the comparator comp in the embodiment shown in the figure is based on the third state [state_3] equal to [N] as an example, and cannot be [1] or [0]. The comparison relationship between the current of the previous source line CSQ and the current of the next source line CSQ+1 is an assumption made in the example in the figure. Note that if the difference between the current of the previous source line and the current of the next source line is within a preset range, in this case, the current of the previous source line CSQ is close to the current of the next source line CSQ+1, which means that they are approximately equal or equal. There may be a small error between the current values ​​of the two (not completely equal), but this is acceptable. For example, a preset range is set and the preset range is predetermined, and it also has a lower limit current value IMIN and an upper limit current value IMAX.

[0086] See also Figure 6, the difference between the current of the previous source line CSQ and the current of the next source line CSQ+1 (such as the difference Ierror between the two currents) is within the preset range, IMIN≤Ierror≤IMAX. This tolerance measure also takes into account the state of the transistor after passive programming in a hidden state. At this time, transistors T10, T20, T30, and T40 are defined to provide a third state or a third state [state_3] in the addressing stage. Otherwise, the address does not match. If the difference Ierror between the two currents is not within the preset range, it is considered that the bit represented by transistors T10, T20, T30, and T40 fails to match, and the value matched with this bit in the data to be checked cannot successfully match this bit. In this case, the data to be checked does not successfully match the address where the bit represented by transistors T10, T20, T30, and T40 is located, so the data to be checked needs to continue to match and query with the content of other addresses (such as the bit line WK+1 where T1-T4 is located). The third state [state_3] of the three states can be used to make a preliminary judgment on whether the transistors such as T10-T40 have reached an unacceptable level due to passive programming. If the transistors have reached an unacceptable level due to passive programming, it is reflected in the difference between the current of the previous source line and the current of the next source line not being within the preset range. In this way, the address mismatch result of the addressing stage can be used to prevent the occurrence of a false match between the data to be checked and the content stored in the memory. For example, there is no suitable state in the three states in the addressing stage to express the state or state of the preset transistor group T10-T40, which indirectly belongs to the result of the address mismatch in the addressing stage. The source of transistor passive programming is closely related to the process of transistors in addition to the inevitable high-frequency data operations of transistors such as reading and writing. Many factors such as the doping concentration of the gate layer material of the floating gate, the thickness of the insulating layer wrapping the floating gate, the thickness of the floating gate, or the critical size of the floating gate will dominate the programming degree of transistor passive programming. Milder passive programming is acceptable, but more severe passive programming usually reaches an unacceptable level and affects the authenticity of the addressing result. The first state and the second state cannot be pre-judged. Passive programming is generated in the floating gate of each transistor of a flash memory during data operations (such as read / write). The main cause of the false match event is that the transistor is passively programmed and the programming level reaches an unacceptable level. If the subsequent precise search or fuzzy search addressing is continued based on the false match event, the addressing result is obviously wrong, but this error is usually not easy to detect, so it is extremely important to implement the above preliminary prediction. The advantage is that hidden errors can be detected in advance to avoid the subsequent addressing tasks being the result of inaccurate state preconditions.

[0087] See also Figure 6In an optional embodiment, based on the equality of the first potential and the second potential, if the difference between the current of the previous source line and the current of the subsequent source line is within a preset range, the group of transistors is defined to provide a third state in the addressing stage, otherwise the group of transistors is a non-third state; thereby utilizing the third state to make a preliminary prediction of whether the transistors have reached an unacceptable level due to passive programming, and if the difference is not within the preset range, the address mismatch result of the addressing stage is used to prevent a false match between the data to be checked and the content stored in the memory.

[0088] See also Figure 4 , the manner in which the to-be-checked data accurately matches the storage content in the memory includes: the first logic value in the to-be-checked data (for example, a logic value assumed to be 1, although it may also be a logic value of 0) is represented by unequal first potentials and second potentials. The first potential is V_pro1 and the second potential is V_pro2. The first potential is applied to the preceding bit line and the second potential is applied to the succeeding bit line in the adjacent bit lines BJ and BJ+1. V_pro1>V_pro2. It can be observed in the figure that the first potential is greater than the second potential, for example, V_pro1 is a portion of the voltage higher than V_pro2.

[0089] See also Figure 5 , the manner in which the data to be checked accurately matches the storage content in the memory includes: the second logic value in the data to be checked (for example, a logic value assumed to be 0, although it can also be a logic value of 1) is represented by unequal first potentials and second potentials. The first potential is V_pro1 and the second potential is V_pro2. The first potential is applied to the previous bit line and the second potential is applied to the next bit line in the adjacent bit lines BJ and BJ+1. V_pro1<V_pro2. It can be observed in the figure that the first potential is less than the second potential, for example, V_pro2 is a portion of the voltage higher than V_pro1.

[0090] See also Figure 6 , the manner in which the to-be-checked data fuzzily matches the storage content in the memory includes: the indefinite values ​​in the to-be-checked data (for example, an indefinite value that is randomly 0, or an indefinite value that is randomly 1) are characterized by using equal first potentials and second potentials. The first potential is V_pro1 and the second potential is V_pro2. The first potential is applied to the preceding bit line and the second potential is applied to the succeeding bit line in the adjacent bit lines BJ and BJ+1. V_pro1≈V_pro2. It can be observed that the first potential is equal to or approximately equal to the second potential, for example, the voltage values ​​of V_pro1 and V_pro2 are equal or approximately the same.

[0091] See also Figure 4In an optional embodiment, if a group of transistors is in the addressing stage, a common word line shared by the group of transistors is applied with a read voltage. For example, the read voltage can be directly equivalent to the voltage value used in the data reading operation of the transistors of the traditional memory. If a group of transistors is in the waiting addressing stage, a common word line shared by the group of transistors is applied with a pass voltage. Figure 5-Figure 6 This embodiment can also be adopted.

[0092] See also Figure 4 In an optional embodiment, during the addressing stage, a read voltage is applied to the common word line of the group of transistors, such as word line WK, and when the data to be checked matches the storage content in the memory, the address where the storage content is currently located (such as the address where word line WK and bit line BJ and bit line BJ+1 are located) is used as the output result, that is, the required addressing address. Figure 5-Figure 6 This embodiment can also be adopted.

[0093] See also Figure 4 Although the first state [state_1] and the second state [state_2] can be identified by comparing the source line current, in a more specific example, it is necessary to fully consider the problem of transmitting the wrong state in the passive programming of the transistor and the accompanying address mismatch problem caused by addressing. Figure 5-Figure 6 This embodiment can also be adopted.

[0094] See also Figure 4 In an optional embodiment, in a group of transistors T10, T20, T30, T40, a floating gate of a transistor such as T20 determined by a previous bit line such as BJ and a subsequent source line such as CSQ+1 is pre-written with charge, and the floating gates of the remaining other transistors T10, T30, T40 are not written with charge, and this setting of the transistor group T10-T40 serves as the default first state [state_1] of the group of transistors T10-T40. The transistor determined by the previous bit line and the subsequent source line means that the position of this transistor is coupled between the previous bit line and the subsequent source line. As shown in the figure, the specific position of a transistor such as T20 determined by the previous bit line such as BJ and the subsequent source line such as CSQ+1 is coupled between the previous bit line BJ and the subsequent source line CSQ+1.

[0095] See also Figure 4In an optional embodiment, it is assumed that any two current values ​​of any single source line current, such as CSQ, are recorded as ICS1 and ICS2 respectively. When the source line current is relatively high, such as when a flash memory uses an extremely high operating voltage or a very large operating current, the high and low value states of the source line current ICS can still be distinguished. By setting a threshold value in advance and the source line current, such as ICS1, being higher than the threshold value, can represent one state [0], while the source line current, such as ICS2, being lower than the threshold value, can represent another state [1]. However, with the low power consumption requirements of electronic devices such as handheld terminals, it is difficult for memories to use extremely high operating voltages or extremely large operating currents, especially for electronic devices such as mobile phones or tablets. Under extremely low operating voltages and extremely low operating currents, the difference between the two current values ​​ICS1 and ICS2 of the source line current is negligible, and even high-precision current sampling circuits such as ADC converters find it difficult to identify this difference. It is difficult to identify the state to be expressed by the source line current by the size of a single source line current. In fact, high-precision ADCs are much more expensive than memories. The more difficult problem is that the transistors T10 or T30 on the source line CSQ are passively programmed. In this way, even if their gates are subjected to a read voltage applied to the word line WK, the voltage of WK will not cause a significant change in the source line current. In other words, the difference between the two current values ​​ICS1 and ICS2 changes even less under passive programming. This is because the read voltage must first be used to offset the influence of the gate charge of the transistor T10 or T30 under passive programming. Therefore, the two current values ​​ICS1 and ICS2 that are intended to express two states using a single source line are prone to transmitting an incorrect state due to low resolution or recognition errors. As the number of data operations such as reading and writing the memory increases, this negative situation becomes more and more obvious, and the passive programming of the transistors will accumulate. Using a single source line to express states has huge defects.

[0096] See also Figure 4, the floating gate of transistor T20 is pre-written with charge, and the floating gates of transistors T10, T30, and T40 are not pre-written with charge. A read voltage needs to be applied to WK during addressing. These transistors are also affected by passive programming. The components of the current of the previous source line, such as CSQ, and the current of the next source line, such as CSQ+1, each include two parts. The first component is a higher voltage, namely the first potential V_pro1, applied to the source line through the read voltage of the word line WK, and the second component is a lower voltage, namely the second potential V_pro2, applied to the source line through the read voltage of the word line WK. The first component dominates the current of the previous source line CSQ to exceed the current of the next source line CSQ+1. Even if these transistors are negatively affected by passive programming, because the second component is simultaneously superimposed on the first component of CSQ and CSQ+1 and is equivalent to raising the resolution of the first component as a whole, the second component does not dominate the current comparison of the first component of CSQ and CSQ+1. This measure can significantly improve the current recognition and resolution scale. Moreover, the first state [state_1] is obtained by comparing the currents of the two source lines, so the first state [state_1] is more robust and less prone to error. There will no longer be a situation where a single source line and its unilateral current easily transmit an erroneous state.

[0097] See also Figure 4 In an optional embodiment, in the group of transistors, a floating gate of a transistor determined by a previous bit line and a subsequent source line is pre-written with charge, and the floating gates of the remaining other transistors are not written with charge, thereby setting a default first state for the group of transistors. It is used to prevent the source line current resolution of each transistor from being reduced under passive programming conditions and the resulting situation of easily transmitting an erroneous state. In an optional embodiment, in the process of comparing the currents of two adjacent source lines, the main current (first component) of each source line for comparison is superimposed with an auxiliary current (second component) to improve the identification and resolution scale of the main current, thereby suppressing the source line current resolution of the transistor from being reduced under passive programming conditions and the resulting situation of easily transmitting an erroneous state.

[0098] See also Figure 5 , among the transistor group of the memory defined by adjacent bit lines BJ and BJ+1 and adjacent source lines CSQ and CSQ+1: the first pair of transistors T1-T2 of the group of transistors T1-T4 share the same bit line BJ and the remaining second pair of transistors T3-T4 share the same other bit line BJ+1. The first pair of transistors and the second pair of transistors each of the two pairs of transistors T1-T2, T3-T4, such as T1, T3, share the source line CSQ, and the first and second pairs of transistors each of the two pairs of transistors T1-T2, T3-T4, such as T2, T4, share the source line CSQ+1.

[0099] See also Figure 5 In an optional embodiment, in a group of transistors T10, T20, T30, T40, a floating gate of a transistor such as T30 determined by a subsequent bit line such as BJ+1 and a previous source line such as CSQ is pre-written with charge, and the floating gates of the remaining transistors T10, T20, T40 are not written with charge, and this setting of the transistor group T10-T40 serves as the default second state [state_2] of the group of transistors T10-T40. The transistor determined by the subsequent bit line and the previous source line means that the position of this transistor is coupled between the subsequent bit line and the previous source line. As shown in the figure, the specific position of a transistor such as T30 determined by a subsequent bit line such as BJ+1 and a previous source line such as CSQ is coupled between the subsequent bit line BJ+1 and the previous source line CSQ.

[0100] See also Figure 5 , the floating gate of transistor T30 is written with charge in advance, and the floating gates of transistors T10, T20, and T40 are not written with charge. A read voltage needs to be applied to WK during addressing. These transistors are also affected by passive programming. The components of the current of the previous source line, such as CSQ, and the current of the next source line, such as CSQ+1, each include two parts. The second component is a lower voltage, namely the first potential V_pro1, applied to the source line through the read voltage of the word line WK, and the first component is a higher voltage, namely the second potential V_pro2, applied to the source line through the read voltage of the word line WK. The first component dominates the current of the previous source line CSQ to be smaller than the current of the next source line CSQ+1. Even if these transistors are negatively affected by passive programming, because the second component is simultaneously superimposed on the first components of CSQ and CSQ+1 and is equivalent to raising the resolution of the first component as a whole, the second component does not dominate the current comparison of the first components of CSQ and CSQ+1. This measure can significantly improve the current recognition and resolution scale. Moreover, the second state [state_2] is obtained by comparing the currents of the two source lines, so the second state [state_2] is more robust and less prone to error. There will no longer be a situation where a single source line and its unilateral current can easily transmit an erroneous state.

[0101] See also Figure 5In an optional embodiment, in the group of transistors, a floating gate of a transistor determined by a subsequent bit line and a previous source line is pre-written with charge, and the floating gates of the remaining other transistors are not pre-written with charge, thereby setting a default second state for the group of transistors. It is used to prevent the source line current resolution of each transistor from being reduced under passive programming conditions and the resulting situation of easily transmitting an erroneous state. In an optional embodiment, in the process of comparing the currents of two adjacent source lines, the main current (first component) of each source line for comparison is superimposed with an auxiliary current (second component) to improve the identification and resolution scale of the main current, thereby suppressing the source line current resolution of the transistor from being reduced under passive programming conditions and the resulting situation of easily transmitting an erroneous state.

[0102] See also Figure 6 In an optional embodiment, in a group of transistors T10, T20, T30, T40, a transistor T10 determined by a previous bit line such as BJ and a previous source line such as CSQ, and a transistor T40 determined by a subsequent bit line such as BJ+1 and a subsequent source line such as CSQ+1, both of which have their floating gates written with charge in advance, and the floating gates of the remaining other transistors such as T20 and T30 are not written with charge, whereby this setting of the group of transistors T10-T40 is used as the default third state [state_3]. The transistor determined by the previous bit line and the previous source line means that the position of this transistor is coupled between the previous bit line and the previous source line. The transistor determined by the subsequent bit line and the subsequent source line means that the position of this transistor is coupled between the subsequent bit line and the subsequent source line. As shown in the figure, the transistor T10 determined by the previous bit line BJ and the previous source line such as CSQ means that the transistor T10 is coupled between the previous bit line BJ and the previous source line such as CSQ. The transistor T40 defined by the next bit line BJ+1 and the next source line CSQ+1 means that the transistor position is coupled between the next bit line BJ+1 and the next source line CSQ+1.

[0103] See also Figure 6 , the floating gates of transistors T10 and T40 are pre-written with charges, while the floating gates of transistors T20 and T30 are not pre-written with charges. A read voltage needs to be applied to WK during addressing. These transistors are also affected by passive programming. The current of the previous source line, such as CSQ, and the current of the next source line, such as CSQ+1, each have two components. The first component is a higher voltage, i.e., the first potential V_pro1, applied to the source line through the read voltage of the word line WK, and the second component is a higher voltage, i.e., the second potential V_pro2, applied to the source line through the read voltage of the word line WK. These two components dominate the current of the previous source line CSQ to be equal to or approximately equal to the current of the next source line CSQ+1.

[0104] See also Figure 6 , based on the first potential V_pro1 and the second potential V_pro2 being equal, the difference between the current of the previous source line CSQ and the current of the next source line CSQ+1 being within a preset range, the transistor group T10-T40 is defined to provide a third state [state_3] in the addressing stage, otherwise the group of transistors is a non-third state non-[state_3], for example, the difference between the currents is not within the preset range. In an optional embodiment, a preliminary pre-judgment can be made based on the third state [state_3] as to whether the transistor has reached an unacceptable level due to passive programming (for example, if the aforementioned difference is not within the preset range, it means that the passive programming has reached an unacceptable level or degree). If the difference is not within the preset range, the address mismatch result of the addressing stage (for example, non-third state non-[state_3] means that the address does not match or does not match) is used to prevent the occurrence of a false match between the data to be checked and the storage content in the memory. If a false match occurs between the data to be checked and the storage content in the memory, an erroneous addressing result will be given or returned.

[0105] See also Figure 6 In an optional embodiment, in a group of transistors T10, T20, T30, T40, a transistor T20 determined by a previous bit line such as BJ and a subsequent source line such as CSQ+1, a transistor T30 determined by a subsequent bit line BJ+1 and a previous source line such as CSQ, both of which have their floating gates written with charge in advance, and the floating gates of the remaining other transistors such as T10 and T40 are not written with charge, whereby this setting of the group of transistors T10-T40 is used as the default third state [state_3]. The transistor determined by the previous bit line and the subsequent source line means that the position of this transistor is coupled between the previous bit line and the subsequent source line. The transistor determined by the subsequent bit line and the previous source line means that the position of this transistor is coupled between the subsequent bit line and the previous source line. As shown in the figure, the transistor T20 determined by the previous bit line BJ and the subsequent source line such as CSQ+1, that is, the position of the transistor T20 is coupled between the previous bit line BJ and the subsequent source line such as CSQ+1. The transistor T30 defined by the next bit line BJ+1 and the previous source line CSQ means that the transistor position is coupled between the next bit line BJ+1 and the previous source line CSQ.

[0106] See also Figure 6, the floating gates of transistors T20 and T30 are pre-written with charges, while the floating gates of transistors T10 and T40 are not pre-written with charges. A read voltage needs to be applied to WK during addressing. These transistors are also affected by passive programming. The current of the previous source line, such as CSQ, and the current of the next source line, such as CSQ+1, each have two components. The first component is a higher voltage, i.e., the first potential V_pro1, applied to the source line through the read voltage of the word line WK, and the second component is a higher voltage, i.e., the second potential V_pro2, applied to the source line through the read voltage of the word line WK. These two components dominate the current of the previous source line CSQ to be equal to or approximately equal to the current of the next source line CSQ+1.

[0107] See also Figure 6 , based on the first potential V_pro1 and the second potential V_pro2 being equal, the difference between the current of the previous source line CSQ and the current of the next source line CSQ+1 being within a preset range, the transistor group T10-T40 is defined to provide a third state [state_3] in the addressing stage, otherwise the group of transistors is a non-third state non-[state_3], for example, the difference between the currents is not within the preset range. In an optional embodiment, a preliminary pre-judgment can be made based on the third state [state_3] as to whether the transistor has reached an unacceptable level due to passive programming (for example, if the aforementioned difference is not within the preset range, it means that the passive programming has reached an unacceptable level or degree). If the difference is not within the preset range, the address mismatch result of the addressing stage (for example, non-third state non-[state_3] means that the address does not match or does not match) is used to prevent the occurrence of a false match between the data to be checked and the storage content in the memory. If a false match occurs between the data to be checked and the storage content in the memory, an erroneous addressing result will be given or returned.

[0108] See also Figure 6 In an optional embodiment, in combination with Figure 3-Figure 5, the addressing method for realizing precise or fuzzy search requires that a group of transistors be defined by adjacent bit lines and adjacent source lines in the memory, and they share a common word line. The method of implementing precise search of the data to be checked in the memory includes: the first logic value in the data to be checked is represented by unequal first potential and second potential, and the first potential is greater than the second potential; the second logic value in the data to be checked is represented by unequal first potential and second potential, and the first potential is less than the second potential. The method of fuzzy search of the data to be checked in the memory is: the indefinite value in the data to be checked is represented by equal first potential and second potential. The first potential is applied to the previous bit line and the second potential is applied to the next bit line in the adjacent bit lines. Based on the inequality of the first potential and the second potential, if the current of the previous source line exceeds the current of the next source line, the group of transistors is defined to provide the first state in the addressing stage, otherwise, the group of transistors are defined to provide the second state. Based on the equality of the first potential and the second potential, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the group of transistors is defined to provide a third state in the addressing stage; when the data to be queried matches the storage content in the memory, the current address of the storage content is returned as the addressing address.

[0109] See also Figure 3 Conventional memory can only access the stored data information when the address where the data is stored is known correctly. Content Addressable Memory (CAM) is a memory that can find the specific location address where the data with relevant content is stored by inputting the data content even if the correct address where the data is stored is unknown. When searching for specific content among multiple data, it has a unique search feature of searching for data related to data consistent with given content, so it can be adopted in network address search scenarios using content addressable memory, and can be regarded as a type of data retrieval engine.

[0110] See also Figure 3 In an optional embodiment, the search criteria include requirements, such as range requirements, exact match requirements and other related search requirements, occupying one or more ternary content addressable memory TCAM entries, and the address of the ternary content addressable memory TCAM entry points to an operation code associated with the standard. When a network device receives a packet, it can extract the attributes of the packet to form a search keyword. The search keyword is compared with multiple ternary content addressable memory entries and generally speaking, the comparison of the search keyword with multiple ternary content addressable memory TCAM entries is performed in parallel in a single clock cycle, and a matching entry can be found from the TCAM entry in a single search operation. The address of the matching entry points to the operation code. According to the operation code, the network device performs a specified operation on the packet.

[0111] See also Figure 3 In an optional embodiment, the TCAM routing table is organized in an address unit format and each address unit includes an IP bit and a mask bit. When establishing the TCAM routing table, the control software writes the destination IP address and the mask corresponding to the IP address into the address unit according to the existing routing table generation algorithm, and in particular, each address unit is also associated with the relevant next IP address. The next IP address refers to the specific and clear IP address of the next router that can lead to the destination routing address. When routing and forwarding a data packet, the destination IP address carried by the data packet searches for the corresponding address unit in the ternary content addressable memory TCAM routing table, and then the next IP address associated with the address unit can be obtained, and the data packet is sent to the next IP address to complete the routing and forwarding of the data packet. The above introduces the subdivided application fields, and of course, TCAM applications include but are not limited to this field.

[0112] See also Figure 3 There are many traditional table item search methods, mainly including linear search, binary tree search, and hash table search. These search methods are software search methods based on SRAM / DRAM, and their common feature is that the search speed is relatively slow. The linear search method needs to traverse all table items in the table. The binary tree search method needs to traverse most nodes in the tree and the search speed is greatly affected by the depth of the tree. Among all software searches, the hash table search method is a relatively fast search method in software searches. The hash is to map a set of keywords to a limited address range according to the set hash function H (key) and the conflict handling method, and use the image of the keyword in the address range as the storage location recorded in the table. This table is called a hash table or hash, and the resulting location is called a hash address or hash address.

[0113] See also Figure 3 Although the hash table search method is relatively fast in software search, it still cannot meet the extremely fast search requirements in high-speed real-time communication systems (such as up to 40G / 100G). Hardware-based TCAM search can be used as a search method that meets the requirements in this context. When using this method for search, all data in the entire table space is queried at the same time, and the search speed is not affected by the size of the table space data. One search is completed per clock cycle and the average search speed is several times, or even up to 100 times, that of SRAM / DRAM-based search.

[0114] See also Figure 2 In the optional example, CAM retrieval is explained by taking four addresses of address addr1, four sets of data of storage content cont1, and four results of search result res1 as examples.

[0115] See also Figure 2In the optional example, the data to be searched is 00100. Search operation: input the data to be searched and return the address where the data is stored. This is the main purpose of CAM. It can quickly search from a huge database and return the best matching address. The fastest search speed can reach more than 100 million times per second.

[0116] See also Figure 2 In the optional example, the storage contents cont1 corresponding to 0x0001, 0x0010 and 0x0100 at the address addr1 are 10000, 01000 and 00010 respectively, and their results res1 do not match. The situation that the data to be checked does not match the storage content is indicated by match0.

[0117] See also Figure 2 In the optional example, the corresponding content cont1 of 0x0011 under the address addr1 is 00100 and its result res1 matches. The situation where the data to be checked matches the stored content is represented by match1.

[0118] See also Figure 2 In the optional example, the CAM search is explained by taking four addresses of address addr2, four sets of data of storage content cont2, and four results of search result res2 as examples. The data to be searched is 10101.

[0119] See also Figure 2 In the optional example, the storage contents cont2 corresponding to 0x0101, 0x0110 and 0x0111 under the address addr2 are 10001, 01010 and 00100 respectively, and their results res2 do not match. The situation where the data to be checked does not match the storage content is indicated by match0.

[0120] See also Figure 2 In the optional example, the corresponding content cont2 of 0x1000 under the address addr2 is 10100 and its result res2 does not match. Although cont2's 10100 is similar to the data to be checked 10101, the situation that the data to be checked does not match the stored content is still represented by match0.

[0121] See also Figure 2 , storage content cont1 and storage content cont2 belong to exact search. The following describes exact search and fuzzy search. CAM does not have a third state, so it can only perform exact match search. The third state feature of TCAM enables it to perform both exact match search and fuzzy match search.

[0122] See also Figure 2In the optional example, four addresses of address addr3, four sets of data of storage content cont3 and four results of search result res3 are used as examples to explain TCAM search. The data to be searched is 10100.

[0123] See also Figure 7 In an optional example, the transistor group defined by adjacent bit lines B0-B1 and adjacent source lines CS0-CS1 is set to represent bit data bit0. The transistor group defined by adjacent bit lines B2-B3 and adjacent source lines CS0-CS1 is set to represent bit data bit1. The transistor group defined by adjacent bit lines B4-B5 and adjacent source lines CS0-CS1 is set to represent bit data bit2. The transistor group defined by adjacent bit lines B6-B7 and adjacent source lines CS0-CS1 is set to represent bit data bit3. The transistor group defined by adjacent bit lines B8-B9 and adjacent source lines CS0-CS1 is set to represent bit data bit4. These transistors collectively express 5 bits of storage content.

[0124] See also Figure 7 In an alternative example, we can assume that the 5-bit storage content expressed by bit0-bit4 corresponds exactly to Figure 2 The storage content cont3 of the address addr3, or the storage content cont2 of the address addr2, and so on.

[0125] See also Figure 2 In the optional example, the storage content cont2 corresponding to 0x1000 under the address addr2 and the data to be checked are both 10100. At this time, the result res2 of the two changes from the aforementioned mismatch to the current match. The situation where the data to be checked matches the storage content is changed to match1. At this time, there is an exact match between the storage content 10100 and the data to be checked 10100 and an exact match search is achieved. When the data to be checked matches the storage content in the memory, the current address of the storage content, such as 0x1000, is returned as the addressing address. It can be combined with Figure 7 In this example, the data to be checked is exactly matched with the content stored in the memory, and the address where the content is currently stored is returned as the addressing address.

[0126] See also Figure 7In the optional example, the storage contents cont3 corresponding to 0x1001, 0x1010 and 0x1011 under the address addr3 are 10001, 10010 and 1010N respectively. The results res3 of the first two do not match. The mismatch between the data to be checked and the storage content is indicated by match0. However, there is a fuzzy match between 1010N and the data to be checked 10100, so the result res3 matches and is indicated by match1. When the data to be checked matches the storage content in the memory, the address where the storage content is currently located, such as 0x1011, is returned as the addressing address. In this example, the data to be checked and the storage content in the memory are fuzzy matched, and the address where the storage content is currently located is returned as the addressing address.

[0127] See also Figure 7 In the optional example, the corresponding content cont3 of 0x1100 under the address addr3 is 101NN and its result res3 is fuzzy matching. Although the 101NN of cont3 does not exactly match the data to be checked 10100, the fuzzy matching result res3 between the data to be checked and the storage content is still represented by match1. The data to be checked matches the storage content in the memory, and the current address of the storage content, such as 0x1100, is returned as the addressing address. In this example, the data to be checked matches the storage content in the memory, and the address of the storage content is returned as the addressing address.

[0128] See also Figure 7 The example in the figure shows the case where only a single exact search is performed. It also shows the case where both exact search and fuzzy search can be performed compatibly.

[0129] See also Figure 7 For example, addressing methods that implement precise or fuzzy lookups can be used for routing. Routing refers to the process of determining the network scope of the end-to-end path from the source to the destination of a packet. Routing works at the third layer of the OSI reference model, such as the packet forwarding device of the network layer. Routers achieve network interconnection by forwarding packets. When the address to be used is given, for example, when the IP address range of 1.0.1.0 is given, it refers to the entire IP address range from 1.0.1.0 to 1.0.1.255. The first three addresses (such as 1.0.1) are precise, and the latter address is allowed to be a fuzzy indefinite value such as any value between 0-255 (or binary representation). Then the first three IP addresses must achieve an exact match, and the content of the latter IP address is actually not important. In this scenario, the three state characteristics provided by this application (i.e., [0], [1], and [N], etc.) can achieve both precise matching and fuzzy matching.

[0130] The above description and drawings provide typical embodiments of specific structures of specific embodiments. The above invention provides existing preferred embodiments, but these contents are not intended to be limiting. For those skilled in the art, various changes and modifications will undoubtedly be obvious after reading the above description. Therefore, the attached claims should be regarded as covering all changes and modifications of the true intent and scope of the present invention. Any and all equivalent scopes and contents within the scope of the claims should be considered to still be within the intent and scope of the present invention.

Claims

1. A content-addressable storage system, characterized in that: include: A memory, wherein in a group of transistors defined by adjacent bit lines and adjacent source lines of the memory, the group of transistors share a common word line, and in an addressing phase, a first potential is applied to a preceding bit line and a second potential is applied to a succeeding bit line among the adjacent bit lines; Based on the inequality between the first potential and the second potential, if the current of the previous source line exceeds the current of the subsequent source line, the group of transistors are defined to provide the first state in the addressing phase, otherwise, they are defined to provide the second state; Based on the first potential and the second potential being equal, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the group of transistors is defined to provide a third state during the addressing phase.

2. The content-addressable storage system according to claim 1, characterized in that: The first and second states are 0 and 1, respectively, or the first and second states are 1 and 0, respectively, and the third state is a don't care.

3. The content-addressable storage system according to claim 1, characterized in that: Ways to accurately match the stored content in the memory include: A first logic value in the to-be-checked data is represented by using a first potential and a second potential that are not equal, the first potential being greater than the second potential; and The second logic value in the to-be-checked data is represented by a first potential and a second potential that are not equal, and the first potential is smaller than the second potential.

4. The content-addressable storage system according to claim 1, characterized in that: The manner in which the to-be-checked data fuzzily matches the storage content in the memory includes: an indefinite value in the to-be-checked data is represented by using an equal first potential and a second potential.

5. The content-addressable storage system according to claim 3 or 4, characterized in that: In the addressing stage, a read voltage is applied to the common word line of the group of transistors. When the data to be checked matches the storage content in the memory, the address where the storage content is currently located is used as the output result, that is, the addressing address.

6. The content-addressable storage system according to claim 1, characterized in that: In the group of transistors, a floating gate of a transistor determined by a previous bit line and a subsequent source line has charges written in advance, and floating gates of the remaining transistors have no charges written in advance, thereby setting a default first state for the group of transistors.

7. The content-addressable storage system according to claim 1, characterized in that: In the group of transistors, a floating gate of a transistor determined by a later bit line and a previous source line has charges written in advance, and floating gates of the remaining transistors have no charges written in advance, thereby setting a default second state for the group of transistors.

8. The content-addressable storage system according to claim 1, characterized in that: Among the group of transistors, charges are written into the floating gates of a transistor determined by a previous bit line and a previous source line and a transistor determined by a subsequent bit line and a subsequent source line in advance, and charges are not written into the floating gates of the remaining transistors, thereby setting a default third state for the group of transistors.

9. The content-addressable storage system according to claim 1, characterized in that: Among the group of transistors, charges are written into the floating gates of a transistor determined by a previous bit line and a subsequent source line and a transistor determined by a subsequent bit line and a previous source line in advance, and charges are not written into the floating gates of the remaining transistors, thereby setting a default third state for the group of transistors.

10. An addressing method for achieving precise or fuzzy search, characterized in that: include: In a memory, a group of transistors is defined by adjacent bit lines and adjacent source lines, and they share a common word line; The method of implementing accurate search of the to-be-checked data in the memory includes: a first logic value in the to-be-checked data is represented by a first potential and a second potential that are not equal, and the first potential is greater than the second potential; a second logic value in the to-be-checked data is represented by a first potential and a second potential that are not equal, and the first potential is less than the second potential; The method of implementing fuzzy search of the to-be-searched data in the memory includes: an indefinite value in the to-be-searched data is represented by an equal first potential and a second potential; A first potential is applied to a preceding bit line and a second potential is applied to a succeeding bit line among adjacent bit lines; Based on the inequality between the first potential and the second potential, if the current of the previous source line exceeds the current of the subsequent source line, the group of transistors are defined to provide the first state in the addressing phase, otherwise, they are defined to provide the second state; Based on the first potential and the second potential being equal, if the difference between the current of the previous source line and the current of the next source line is within a preset range, the group of transistors is defined to provide a third state during the addressing phase; When the data to be checked matches the storage content in the memory, the address where the storage content is currently located is returned as the addressing address.

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