Operational amplifier biasing circuit with protection function

Abstract

The operational amplifier bias circuit with the overvoltage protection and power-on protection functions is provided, bias current needed by a post-stage operational amplifier can be generated through combination of a hysteresis comparator, an inverter chain, a PTAT current generation circuit and the like, and enable signals can be output through the inverter chain to control whether the operational amplifier works or not, so that the operational amplifier bias circuit has the overvoltage protection and power-on protection functions. And the synchronization of the power-on protection and the PTAT current stabilization process is facilitated. On the basis of a traditional biasing circuit, a protection function is realized, and the problem that the working state of the operational amplifier is abnormal when the operational amplifier is under-voltage and over-voltage is avoided. The biasing circuit can be used in an instrument amplifier and other modules, and the working voltage of the circuit is + / -2.3 V to + / -18V.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an operational amplifier bias circuit with a protection function Background Art

[0002] The core task of the analog front end is to convert analog signals into digital signals for subsequent digital signal processing. This conversion process usually includes steps such as filtering, amplification, and analog-to-digital conversion (ADC). Filtering is used to eliminate unwanted frequency components, amplification is used to increase the amplitude of the signal, and ADC is responsible for converting analog signals into digital signals. The role of the analog front end is to provide high-quality signal processing and conversion functions for electronic systems. In many applications, the analog front end is required to accurately control the signal acquisition, amplification, and conversion process to ensure that the collected signal is accurate and reliable, which is a crucial link in signal processing. As part of the analog front end, the amplifier not only amplifies the collected tiny signals, but also needs to ensure the stability and reliability of the signal.

[0003] The instrumentation amplifier is the front end of the acquisition system. On the one hand, it amplifies the weak differential signal to a level suitable for the subsequent analog-to-digital conversion circuit to process. On the other hand, it can suppress common-mode interference and prevent common-mode interference from being converted into differential-mode signals, so that the subsequent ADC can better process the amplified electrical signal. Both industry and academia have conducted extensive and in-depth research on instrumentation amplifiers, but most of the research focuses on improving the performance of the amplifier itself, such as reducing noise density and offset voltage, improving common-mode rejection ratio, and increasing bandwidth. The bias circuit used is relatively simple. However, as part of the analog front end, if the amplifier experiences abnormal conditions such as undervoltage or overvoltage during the signal processing process, it may not be able to correctly process the input signal, which will also affect the subsequent system.

[0004] Therefore, it is necessary to improve the existing bias circuit to realize a bias circuit that can provide a relatively high-precision reference current source or voltage source and provide a certain protection function for the amplifier. Summary of the invention

[0005] The present invention aims at the defects and shortcomings in the prior art and proposes an operational amplifier bias circuit with a protection function.

[0006] The technical solution of the present invention is as follows:

[0007] An operational amplifier bias circuit with a protection function, the operational amplifier bias circuit with a protection function at least comprises: a PTAT current generating module, a current mirror module, a bias current providing module under a secondary power supply, a hysteresis comparator module, a power-on protection and enable signal generating module, and a bias current and voltage providing module.

[0008] Optionally, the PTAT current generating module includes a first NPN tube, a second NPN tube, a first resistor, a second resistor, a third resistor, and a fourth resistor. The bases of the first NPN tube and the second NPN tube are both connected to the source of the first NMOS tube, the emitter of the first NPN tube is connected to the negative end of the first resistor, and the collector is connected to the collector of the first PNP tube. The emitter of the second NPN tube is connected to the positive end of the first resistor. The second resistor is connected to the negative end of the first resistor, the third resistor is connected to the negative end of the second resistor, and the fourth resistor is connected to the negative end of the third resistor and connected to V SS .

[0009] Optionally, the current mirror module includes a first PMOS tube, a second PMOS tube, a first PNP tube, a second PNP tube, a third PNP tube, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor. The gate of the first PMOS tube is connected to the collector of the first NPN tube, and the drain is connected to V SS The source is connected to the drain of the fourth PMOS tube. The gate of the second PMOS tube is connected to the collector of the second NPN tube, the drain is connected to the positive end of the fifth resistor, and the source is connected to the collector of the third PNP tube. The negative end of the fifth resistor is connected to V SS The positive ends of the sixth, seventh and eighth resistors are connected to the drain of the fourth PMOS tube. The negative end of the sixth resistor is connected to the emitter of the third PNP tube, the negative end of the seventh resistor is connected to the emitter of the second PNP tube, and the negative end of the eighth resistor is connected to the emitter of the first PNP tube. The bases of the first, second and third PNP tubes are connected to the source of the second PMOS tube. The base of the third PNP tube is connected to the collector.

[0010] Optionally, the bias current module provided under the secondary power supply includes a first NMOS tube, a third PMOS tube, a third PNP tube, a ninth resistor and a tenth resistor. The gate of the first NMOS tube is connected to the drain of the sixth PMOS tube, the drain is connected to the drain of the fourth PMOS tube, and the source is connected to the negative end of the ninth resistor. The source of the third PMOS tube is connected to the drain of the sixth PMOS tube, the gate is connected to the drain and connected to the collector of the third NPN tube. The base of the third NPN tube is connected to the collector, and the emitter is connected to the positive end of the ninth resistor. The tenth resistor is connected to the negative end of the ninth resistor, and the negative end is connected to V SS .

[0011] Optionally, the bias current and voltage providing module includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a fourth NPN tube, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor. The positive end of the eleventh resistor is connected to V DD The sources of the fourth PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, and the eleventh PMOS tube are connected to the negative end of the eleventh resistor, the gate of the fourth PMOS tube is connected to the drain of the eighth PMOS tube, and the gates of the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, and the eleventh PMOS tube are connected to the source of the fifth PMOS tube. The gate and drain of the ninth PMOS tube are connected, the drain of the tenth PMOS tube is connected to the source of the sixth PMOS tube, and the drain of the eleventh PMOS tube is connected to the gate of the seventh PMOS tube. The source of the seventh PMOS tube is connected to V DD , the drain is connected to the source of the twelfth PMOS tube and the thirteenth PMOS tube. The gate and drain of the fifth PMOS tube are connected, and connected to the drain of the third NMOS tube. The gate of the sixth PMOS tube is connected to the gate of the fifth PMOS tube, and the drain is connected to the positive end of the fourteenth resistor. The gates of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are connected to the drain of the fifth NMOS tube, the source of the second NMOS tube is connected to the drain of the sixth NMOS tube, the source of the third NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the fourth NMOS tube is connected to the gate of the seventh PMOS tube, and the source is connected to the drain of the eighth NMOS tube. The source of the fifth NMOS tube is connected to V SS The source electrodes of the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are connected to V SS , the gate is connected to the drain of the seventh NMOS tube. The drain of the seventh NMOS tube is connected to the emitter of the fourth NPN tube. The gate and drain of the ninth NMOS tube are connected, and connected to the negative end of the fifteenth resistor. The gate of the twelfth PMOS tube is connected to the gate of the thirteenth PMOS tube, and connected to the positive end of the fifteenth resistor. The drain of the twelfth PMOS tube is connected to the source of the fourth NMOS tube, and the gate and drain of the thirteenth PMOS tube are connected. The base and collector of the fourth NPN tube are connected, and connected to the negative end of the fourteenth resistor. The positive end of the twelfth resistor is connected to the eleventh resistor, and the negative end is connected to the drain of the fifth NMOS tube. The positive end of the thirteenth resistor is connected to the source of the third NMOS tube.

[0012] Optionally, the power-on protection and enable signal generating module includes a fourteenth PMOS tube, a fifteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a sixteenth resistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter. The source of the fourteenth PMOS tube is connected to the drain of the seventh PMOS tube, the gate is connected to the gate of the thirteenth PMOS tube, and the source is connected to the drain of the tenth NMOS tube. The source of the fifteenth PMOS tube is connected to the drain of the fourth PMOS tube, the gate is connected to the gate of the third PMOS tube, and the drain is connected to the gate of the tenth NMOS tube. The source of the tenth NMOS tube is connected to the drains of the eleventh NMOS tube and the twelfth NMOS tube, and the sources of the eleventh NMOS tube and the twelfth NMOS tube are connected to V SS The gate of the eleventh NMOS tube is connected to the drain, the gate of the twelfth NMOS tube is connected to the output of the sixth inverter. The drain of the thirteenth NMOS tube is connected to the output of the second inverter and the input of the third and fourth inverters, the gate is connected to the drain of the fourteenth PMOS tube, and the source is connected to V SS The positive end of the sixteenth resistor is connected to the drain of the fifteenth PMOS tube, and the negative end is connected to V SS The positive power supply of each inverter is connected to the drain of the seventh PMOS tube, and the negative power supply is connected to V SS The input end of the first inverter is connected to the drain of the eighteenth NMOS tube, and the output end is connected to the input end of the second inverter. The output end of the second inverter is connected to the input ends of the third inverter and the fourth inverter. The output end of the third inverter is connected to the input end of the fifth inverter and the gate of the nineteenth NMOS tube, the output end of the fourth inverter is connected to the subsequent operational amplifier part, the output end of the fifth inverter is connected to the gate of the twenty-fourth PMOS tube, and the input end of the sixth inverter is connected to the drain of the tenth NMOS tube.

[0013] Optionally, the hysteresis comparator module includes a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a fifth NPN tube, a sixth NPN tube, a seventeenth resistor, an eighteenth resistor, and a nineteenth resistor. The gates of the eighteenth PMOS tube, the nineteenth PMOS tube, the twentieth PMOS tube, the twenty-first PMOS tube, and the twenty-second PMOS tube are connected to the gate of the third PMOS tube, and the source is connected to the drain of the fourth PMOS tube. The drain of the eighteenth PMOS tube is connected to the gate of the sixteenth PMOS tube, the drain of the nineteenth PMOS tube is connected to the sources of the sixteenth PMOS tube and the seventeenth PMOS tube, the drain of the twentieth PMOS tube is connected to the drain of the eighteenth NMOS tube, the drain of the twenty-first PMOS tube is connected to the sources of the twenty-third PMOS tube and the twenty-fourth PMOS tube, and the drain of the twenty-second PMOS tube is connected to the gate of the seventeenth PMOS tube. The gate of the twenty-third PMOS tube is connected to the output end of the fifth inverter, and the drain is connected to the positive end of the nineteenth resistor. The drain of the twenty-fourth PMOS tube is connected to the drain of the eighteenth NMOS tube. The drain of the sixteenth PMOS tube is connected to the drain of the sixteenth NMOS tube, and the drain of the seventeenth PMOS tube is connected to the drain of the seventeenth NMOS tube. The drain of the fourteenth NMOS tube is connected to the negative end of the seventeenth resistor, and the source end is connected to V SS The gate and drain of the fifteenth NMOS tube are connected, the drain is connected to the drain of the sixteenth PMOS tube, and the source is connected to the drain of the sixteenth PMOS tube. The sources of the sixteenth NMOS tube, the seventeenth NMOS tube, and the eighteenth NMOS tube are connected to V SS , the gate and drain of the sixteenth NMOS tube are connected, and the drain is connected to the drain of the sixteenth NMOS tube. The gate of the seventeenth NMOS tube is connected to the gate of the sixteenth NMOS tube, and the drain is connected to the drain of the seventeenth PMOS tube. The gate of the eighteenth NMOS tube is connected to the drain of the seventeenth PMOS tube. The positive end of the seventeenth resistor is connected to the gate of the sixteenth PMOS tube, and the negative end is connected to the eighteenth resistor. The negative ends of the eighteenth resistor and the nineteenth resistor are grounded. The base and collector of the fifth NPN tube and the sixth NPN tube are connected, the collector of the fifth NPN tube is connected to the gate of the seventeenth PMOS tube, and the emitter is connected to the collector of the sixth NPN transistor. The emitter of the sixth NPN transistor is connected to V SS .

[0014] The method for implementing bias in the circuit at least includes: providing a certain current to the module and the power-on protection and enable signal generating module through the bias current and voltage providing module, generating a voltage slightly less than 5V for the inverter part and providing a bias voltage for the gate of the first NMOS tube. Providing a constant current to the operational amplifier through the PTAT current generating module. Producing a bias current for the part under the secondary power supply through the bias current providing module under the secondary power supply, and obtaining a determined secondary power supply voltage.

[0015] Optionally, when the power supply voltage increases to a certain value, the second NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, etc. in the bias current and voltage module all work in the saturation region, I DR13 =I DMP9 =I,I DMN5 =I0,I DMP8 =I DMP10 =I DMP11 =I DMP12 =I,I DMN8 =I DMP13 =2I. The gate voltage of the fifth NMOS tube is proportional to I, so I0 is also positively correlated with I. Since the sum of the voltage drops of the fifth NMOS tube and the twelfth resistor is approximately V DD Therefore, the gate voltage of the third NMOS tube can be represented by I0, and finally the bias current generated on the thirteenth resistor and V DD Positive correlation. The drain voltage of the sixth PMOS tube is V1, which serves as the gate voltage of the first NMOS tube; the drain voltage of the seventh PMOS tube is V2, which serves as the positive power supply of the inverter. Both V1 and V2 are determined by the bias current I. When the secondary power supply voltage increases to a certain value, the emitter junctions of the first NPN transistor and the second NPN transistor in the PTAT current generating module are turned on and work in the amplification region. The voltage difference across the first resistor is R1I PTAT I PTAT After normal generation, the secondary power supply voltage and the bias current I1 provided by the third PMOS tube are both stable.

[0016] Optionally, the current I on the thirteenth resistor satisfies The drain voltage V1 of the sixth PMOS tube satisfies V1=IR 14 +V BE_NPN4 +V GS_MN6 in I S is the saturation current of the transistor, is the thermal voltage. β is the process constant of the MOS tube. The I generated by the first resistor PTAT satisfy The bias current I1 provided by the third PMOS tube satisfies The source voltage V3 of the third PMOS tube satisfies V2=I1R9+V BE_NPN3 +V GS_MP3 +V R10 in I S is the saturation current of the transistor, is the thermal voltage. β is the process constant of the MOS tube.

[0017] Optionally, the method for the circuit to provide protection for the operational amplifier at least comprises: DD The bias current I1 provided by the third PMOS tube is relatively small, the bias current I1 provided by the third PMOS tube has not yet reached the maximum, the voltage drop on the sixteenth resistor is relatively small, and when the tenth NMOS tube is in the cut-off region, this is region I, the input of the sixth inverter and the gate voltage of the thirteenth NMOS tube are high level, and the thirteenth NMOS tube is in the linear region; the output of the sixth inverter is low level, and the twelfth NMOS tube is in the cut-off region; after the bias current I1 provided by the third PMOS tube reaches the maximum value, the tenth NMOS tube is turned on and works in the linear region, which is region II, the input of the sixth inverter and the gate voltage of the thirteenth NMOS tube are low level, and the thirteenth NMOS tube is in the cut-off region; the output of the sixth inverter is high level, the twelfth NMOS tube is in the linear region, and the eleventh NMOS tube is in the cut-off region. When the operational amplifier is working normally, the hysteresis comparator is composed of the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube, the sixteenth PMOS tube, and the seventeenth PMOS tube. The gate of the sixteenth PMOS tube is the non-inverting input terminal, and the gate of the seventeenth PMOS tube is the inverting input terminal. When the operational amplifier is working normally, the hysteresis comparator outputs a low level, and the fourteenth NMOS tube works in the linear region, which is state I. When the bias current increases abnormally, making the voltage at the non-inverting input terminal greater than the reference voltage at the inverting input terminal, the hysteresis comparator outputs a high level, and the fourteenth NMOS tube works in the cut-off region, which is state II. Since the fourteenth NMOS tube is connected in parallel with the eighteenth resistor, which is one of the voltage divider resistors, the flip threshold of the comparator is affected, thereby generating a hysteresis effect. When the circuit is working normally, the gate voltage V1 of the first NMOS tube is small and insufficient to turn it on, so the first NMOS tube works in the cut-off region, which is region I; the power supply voltage V DDAfter abnormal increase, V1 will rise to turn on the first NMOS tube and work in the saturation region. This is state II. In this state, the first NMOS tube will divide the bias current originally generated by the third PMOS tube, causing the part under the secondary power supply to no longer work normally, and the inverter chain outputs a low level to protect the op amp.

[0018] As described above, the operational amplifier bias circuit with protection function of the present invention has at least the following beneficial effects:

[0019] By designing the bias current and voltage module, the entire bias circuit of the operational amplifier has a bias current that changes with V during power-on. DD The current increases slowly, thus ensuring that a current not exceeding 5V is provided to the inverter part. By designing the PTAT current generation module, a current that is only affected by temperature can be provided to the op amp, making the bias current stable. By designing the hysteresis comparator module and the power-on protection and enable signal generation module, the circuit can be DD When the power supply voltage V is small, a control signal is generated through the inverter chain, during which the op amp is temporarily not working, realizing the undervoltage protection function; it can also make the circuit flip the state of the hysteresis comparator when the secondary power supply voltage or PTAT current increases abnormally, protect the op amp through the inverter chain, and restore to normal after the secondary power supply voltage or PTAT current drops to a smaller value, which is conducive to avoiding repeated switching of the working state of the op amp. DD When the voltage increases abnormally, the bias current under the secondary power supply is stopped, and the inverter chain generates a protection signal, thus realizing the overvoltage protection function under several abnormal conditions, so that the operational amplifier can always work within the normal current and voltage range. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The figure is a schematic diagram of the overall circuit of the bias circuit with protection function of the present invention.

[0021] Figure 2 R in the present invention 13 The bias current I varies with the supply voltage V DD 's change graph.

[0022] Figure 3 The positive power supply voltage V2 of the inverter in the present invention changes with the power supply voltage V DD 's change graph.

[0023] Figure 4 The PTAT current in the present invention changes with the power supply voltage V DD 's change graph.

[0024] Figure 5 M in the present invention N10 and M N13The working area varies with the supply voltage V DD 's change graph.

[0025] Figure 6 It is an output voltage curve diagram of the hysteresis comparator in the present invention.

[0026] Description of Figure Numbers

[0027] I1 PTAT current generation module

[0028] I2 Current Mirror Module

[0029] I3 provides bias current module under secondary power supply

[0030] I4 Hysteresis Comparator Module

[0031] I5 power-on protection and enable signal generation module

[0032] I6 provides bias current and voltage module DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] See also Figure 1 to Figure 6 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0035] like Figure 1 As shown, this embodiment provides an operational amplifier bias circuit with a protection function, which includes:

[0036] PTAT current generating module I1, current mirror module I2, bias current providing module I3 under secondary power supply, hysteresis comparator module I4, power-on protection and enable signal generating module I5, bias current and voltage providing module I6.

[0037] The PTAT current generating module I1 includes a first NPN transistor N1, a second NPN transistor N2, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The bases of N1 and N2 are connected to M N1The source of N1 is connected to the negative terminal of R1, the emitter of N1 is connected to the negative terminal of R1, and the collector is connected to the collector of N1. The emitter of N2 is connected to the positive terminal of R1. R2 is connected to the negative terminal of R1, R3 is connected to the negative terminal of R2, and R4 is connected to the negative terminal of R3 and connected to V SS .

[0038] The current mirror module I2 includes a first PMOS tube M P1 , the second PMOS tube M P2 , a first PNP transistor P1, a second PNP transistor P2, a third PNP transistor P3, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8. P1 The gate is connected to the collector of N1, and the drain is connected to V SS , source and M P4 The drain of M P2 The gate is connected to the collector of N2, the drain is connected to the positive end of R5, and the source is connected to the collector of P3. The negative end of R5 is connected to V SS The positive terminals of R6, R7, and R8 are connected to M P4 The negative end of R6 is connected to the emitter of P3, the negative end of R7 is connected to the emitter of P2, and the negative end of R8 is connected to the emitter of P1. The bases of P1, P2, and P3 are connected to M P2 The source of M P3 The base is connected to the collector.

[0039] The bias current module I3 provided under the secondary power supply includes a first NMOS tube M N1 , the third PMOS tube M P3 , the third NPN tube N3, the ninth resistor R9 and the tenth resistor R 10 . M N1 The gate and M P6 The drain of P4 The drain of M is connected to the negative terminal of R9. P3 The source and M P6 The gate is connected to the drain and connected to the collector of N3. The base of N3 is connected to the collector, and the emitter is connected to the positive terminal of R9. 10 Connected to the negative terminal of R9, and the negative terminal is connected to V SS .

[0040] The bias current and voltage module I4 includes a fourth PMOS tube M P4 , the fifth PMOS tube M P5 , the sixth PMOS tube M P6 , the seventh PMOS tube M P7 , the eighth PMOS tube M P8 , the ninth PMOS tube M P9 , the tenth PMOS tube MP10 11. PMOS tube M P11 , the twelfth PMOS tube M P12 、Thirteenth PMOS tube M P13 , the second NMOS tube M N2 , the third NMOS tube M N3 , the fourth NMOS tube M N4 , the fifth NMOS tube M N5 , the sixth NMOS tube M N6 , the seventh NMOS tube M N7 , the eighth NMOS tube M N8 , the ninth NMOS tube M N9 , the fourth NPN tube N4, the eleventh resistor R 11 , the twelfth resistor R 12 、Thirteenth resistor R 13 , the fourteenth resistor R 14 , the fifteenth resistor R 15 . R 11 The positive terminal and V DD Connected. P4 、M P8 、M P9 、M P10 、M P11 The source and R 11 The negative terminal of M P4 The gate and M P8 The drain of M P8 、M P9 、M P10 、M P11 The gate and M P5 The source of M P9 The gate and drain are connected, M P10 The drain of the tube is connected to M P6 The source of M P11 The drain and M P7 The gate of M P7 The source is connected to V DD , drain and M P12 and M P13 The source of M P5 The gate and drain are connected to M N3 The drain of the tube. P6 The gate and M P5 The gate is connected to the drain and the R 14 The positive end of M N2 、M N3 、M N4 The gate and M N5 The drain of M N2 The source and M N6The drain of M N3 The source and M N5 The gate of M N3 The drain and M P7 The gate is connected to the source of M N8 The drain of M N5 The source is connected to V SS , M N6 、M N7 、M N8 The source is connected to V SS , gate and M N7 The drain of M N7 The drain of M is connected to the emitter of N4. N9 The gate and drain are connected and connected to R 15 The negative terminal of M P12 and M P13 The gate of 15 The positive end, M P12 The drain and M N4 The source of M P13 The gate and drain of N4 are connected. The base and collector of N4 are connected and connected to R 14 The negative terminal of R 12 The positive end and R 11 Connected, the negative terminal to M N5 The drain of R 13 Positive end and M N3 The source is connected.

[0041] The power-on protection and enable signal generating module I5 includes a fourteenth PMOS transistor M P14 , the fifteenth PMOS tube M P15 , the tenth NMOS tube M N10 11th NMOS tube M N11 , the twelfth NMOS tube M N12 , Thirteenth NMOS tube M N13 , the sixteenth resistor R 16 , a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter. P14 The source and M P7 The drain is connected to the gate and the P13 The gate is connected to the source of M N10 The drain of M P15 The source and M P4 The drain is connected to the gate and the P3 The gate is connected to the M N10 The gate of M N10 The source and M N11 and M N12 The drain of MN11 and M N12 The source of the tube is connected to V SS , M N11 The gate and drain of the tube are connected, M N12 The gate of M is connected to the output terminal of the sixth inverter. N13 The drain is connected to the output of the second inverter and the input of the third and fourth inverters, and the gate is connected to M P14 The drain is connected to the source and the source is connected to V SS . R 16 The positive end of P15 The negative terminal is connected to V SS The positive power supply of each inverter is connected to M P7 The drain of the tube, the negative power supply is connected to V SS The input terminal of the first inverter is connected to M N18 The output end of the second inverter is connected to the input end of the third inverter and the fourth inverter. The output end of the third inverter is connected to the input end of the fifth inverter and the input end of the M N19 The output end of the fourth inverter is connected to the gate of M, the output end of the fourth inverter is connected to the subsequent operational amplifier part, and the output end of the fifth inverter is connected to the gate of M P24 The gate of the sixth inverter is connected to the input terminal of M N10 The drain is connected.

[0042] The hysteresis comparator module I6 includes a sixteenth PMOS transistor M P16 17th PMOS tube M P17 , Eighteenth PMOS tube M P18 19th PMOS tube M P19 20th PMOS tube M P20 21st PMOS tube M P21 22nd PMOS tube M P22 、23rd PMOS tube M P23 、24th PMOS tube M P24 , the fourteenth NMOS tube M N14 , the fifteenth NMOS tube M N15 , the sixteenth NMOS tube M N16 , the seventeenth NMOS tube M N17 , the eighteenth NMOS tube M N18 , the fifth NPN tube N5, the sixth NPN tube N6, the seventeenth resistor R 17 , Eighteenth resistor R 18 19th resistor R 19 . M P18 、M P19 、M P20 、M P21 、M P22The gate and M P3 The gate is connected to the source of M P4 The drain of M P18 The drain of the tube is connected to M P16 The gate of the tube is connected, M P19 The drain and M P16 and M P17 The source of M P20 The drain and M N18 The drain of M P21 The drain and M P23 Tube and M P24 The source of M P22 The drain and M P17 The gate of M P23 The gate is connected to the output of the fifth inverter, and the drain is connected to R 19 The positive end of M P24 The drain and M N18 The drain of M P16 The drain and M N16 The drain of M P17 The drain and M N17 The drain of M N14 The drain and R 17 The negative terminal is connected to the source terminal and the V SS . M N15 The gate and drain are connected to M P16 The drain is connected to the source and the P16 The drain of M N16 、M N17 、M N18 The source is connected to V SS , M N16 The gate and drain are connected to M N16 The drain of M N17 The gate and M N16 The gate is connected to the M N17 The drain of M N18 The gate and M P17 The drain of R 17 The positive end of P16 The gate is connected to the negative terminal of R 18 Connected, R 18 , R 19 The negative end of N5 and N6 is connected to the base and collector, and the collector of N5 is connected to M P17 The gate of N6 is connected to the gate of N6, and the emitter is connected to the collector of N6. The emitter of N6 is connected to V SS .

[0043] By providing a bias current and voltage module I4 to provide a certain current to the module and the power-on protection and enable signal generation module I5, a voltage slightly less than 5V is generated for the inverter part and a voltage slightly less than 5V is generated for the M N1 The gate of the circuit is provided with a bias voltage. A constant current is provided to the operational amplifier through the PTAT current generating module I1. A bias current module I3 is provided under the secondary power supply to generate a bias current for the part under the secondary power supply, and a determined secondary power supply voltage is obtained.

[0044] Specifically, when the power supply voltage increases to a certain value, the bias current and voltage module I4 is provided. N2 、M N3 、M N5 、M N6 When all work in the saturation region, I DR13 =I DMP9 =I,I DMN5 =I0,I DMP8 =I DMP10 =I DMP11 =I DMP12 =I,I DMN8 =I DMP13 =2I.M N5 The gate voltage is proportional to I, so I0 is also positively correlated with I. N5 With R 12 The sum of the voltage drops is approximately V DD , so M N3 The gate voltage can be expressed as I0, and finally R 13 The bias current generated on the DD Positive correlation. P6 The drain voltage is V1, as M N1 The gate voltage of P7 The drain voltage of R is V2, which serves as the positive power supply of the inverter. Both V1 and V2 are determined by the bias current I. 13 The bias current generated on the DD The change curve of Figure 2 As shown, V2 changes with V DD The change curve of Figure 3 When the secondary power supply voltage increases to a certain value, the emitter junctions of N1 and N2 in the PTAT current generating module I1 are turned on and work in the amplification region. The voltage difference between the two ends of R1 is R1I PTAT I PTAT After normal generation, the secondary power supply voltage and M P3 The bias current I1 provided is stable. PTAT With V DD The change curve of Figure 4 shown.

[0045] As an example, a reasonable setting of MP15 、M P18 、M P19 、M P20 、M P21 、M P22 and M P3 The size of and Reasonable setting of M P8 、M P9 、M P10 、M P20 、M P21 、M P22 and M P11 The size of and The proportions of the remaining pipes are Figure 3 Marking instructions.

[0046] In this embodiment, R 13 The current I satisfies M P6 The drain voltage V1 satisfies V1=IR 14 +V BE_NPN4 +V GS_MN6 in I S is the saturation current of the transistor, is the thermal voltage. β is the process constant of the MOS tube. I generated on R1 PTAT satisfy M P3 The bias current I1 provided satisfies M P3 The source voltage V2 satisfies V2=I1R9+V BE_NPN3 +V GS_MP3 +V R10 in I S is the saturation current of the transistor, is the thermal voltage. β is the process constant of the MOS tube.

[0047] At the power supply voltage V DD Smaller, M P3The bias current I1 provided has not yet reached its maximum value, R 16 The pressure drop on M is small. N10 In the cut-off region, this is region I, the input of the sixth inverter and M N13 The gate voltage is high, M N13 In the linear region; the output of the sixth inverter is low level, M N12 The tube is in the cut-off region; M P3 After the bias current I1 reaches its maximum value, M N10 Turn on and work in the linear region, which is region II. The input of the sixth inverter and M N13 The gate voltage of the tube is low level, M N13 In the cut-off region; the output of the sixth inverter is high level, M N12 In the linear region, M N11 In the cut-off region. N10 and M N13 The working area varies with V DD The change curve is as follows Figure 5 When the op amp is working normally, M N15 、M N16 、M N17 、M P16 、M P17 The tube forms a hysteresis comparator, M P16 The gate is the non-inverting input terminal, M P17 The gate of the amplifier is the inverting input terminal. When the op amp is working normally, the hysteresis comparator outputs a low level. N14 Working in the linear region, this is state I. When the bias current increases abnormally, making the voltage at the non-inverting input terminal greater than the reference voltage at the inverting input terminal, the hysteresis comparator outputs a high level, M N14 Working in the cut-off region, this is state II. N15 As one of the voltage divider resistors, R 18 The parallel connection affects the comparator's flip threshold, thus producing a hysteresis effect. When the voltage of the hysteresis comparator rises and falls, the output curve obtained is as follows Figure 6 When the circuit is working normally, M N1 The gate voltage V1 is too small to turn it on, so M N1 Working in the cut-off region, this is region I; the power supply voltage V DD After abnormal increase, V1 will rise to make M N1 Turn on and work in the saturation region, which is state II. In this state, M N1 will take away the original M P3 The bias current generated causes the part under the secondary power supply to no longer work normally, and the inverter chain outputs a low level to protect the operational amplifier.

[0048] V1 follows V DD The change curve of is shown in the figure. Figure 6 It can be seen that the value of V1 will not change dramatically during the power-on process, which can ensure that the voltage of the logic signal generating part does not exceed 5V and prevent the drain-source voltage of the tube from being too high. PTAT With V DD The change curve of is shown in the figure. After normal generation, it will no longer change with V DD It can be seen that the present invention can provide appropriate bias current and voltage according to the needs of different parts, so that the circuit is at a suitable DC operating point. N10 and M N13 The working area varies with V DD The change curve is as follows Figure 5 The output curve of the hysteresis comparator is shown in Figure 6 As shown. It can be seen that M N10 and M N13 Wait for the tube to be in V DD When the voltage or current increases abnormally, the hysteresis comparator realizes undervoltage protection. The present invention can ensure the normal operation of the operational amplifier and avoid abnormal conditions caused by various situations, thereby transmitting erroneous signals to the subsequent stages in the system.

[0049] In summary, the operational amplifier bias circuit with protection function of the present invention provides suitable bias current and bias voltage for the circuit itself and the operational amplifier through the PTAT current generating module, the current mirror module, the bias current providing module under the secondary power supply, and the bias current and voltage providing module. The undervoltage protection and overvoltage protection functions are provided for the operational amplifier through the hysteresis comparator module, the power-on protection and the enable signal generating module, thereby realizing a circuit with both bias and protection functions, and improving the stability and accuracy of the operation of the operational amplifier.

[0050] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A bias circuit capable of providing a protection function for an operational amplifier, characterized in that: The operational amplifier bias circuit with protection function at least includes: a PTAT current generating module, a current mirror module, a bias current providing module under a secondary power supply, a hysteresis comparator module, a power-on protection and enable signal generating module, and a bias current and voltage providing module.

2. The operational amplifier bias circuit with protection function according to claim 1, characterized in that The PTAT current generating module includes a first NPN tube, a second NPN tube, a first resistor, a second resistor, a third resistor, and a fourth resistor. The bases of the first NPN tube and the second NPN tube are both connected to the source of the first NMOS tube, the emitter of the first NPN tube is connected to the negative end of the first resistor, and the collector is connected to the collector of the first PNP tube. The emitter of the second NPN tube is connected to the positive end of the first resistor. The second resistor is connected to the negative end of the first resistor, the third resistor is connected to the negative end of the second resistor, and the fourth resistor is connected to the negative end of the third resistor and connected to V SS .

3. The operational amplifier bias circuit with protection function according to claim 1, characterized in that The current mirror module includes a first PMOS tube, a second PMOS tube, a first PNP tube, a second PNP tube, a third PNP tube, a fifth resistor, a sixth resistor, a seventh resistor, and an eighth resistor. The gate of the first PMOS tube is connected to the collector of the first NPN tube, and the drain is connected to V SS The source is connected to the drain of the fourth PMOS tube. The gate of the second PMOS tube is connected to the collector of the second NPN tube, the drain is connected to the positive end of the fifth resistor, and the source is connected to the collector of the third PNP tube. The negative end of the fifth resistor is connected to V SS The positive ends of the sixth, seventh and eighth resistors are connected to the drain of the fourth PMOS tube. The negative end of the sixth resistor is connected to the emitter of the third PNP tube, the negative end of the seventh resistor is connected to the emitter of the second PNP tube, and the negative end of the eighth resistor is connected to the emitter of the first PNP tube. The bases of the first, second and third PNP tubes are connected to the source of the second PMOS tube. The base of the third PNP tube is connected to the collector.

4. The operational amplifier bias circuit with protection function according to claim 1, characterized in that The module for providing bias current under the secondary power supply includes a first NMOS tube, a third PMOS tube, a third PNP tube, a ninth resistor and a tenth resistor. The gate of the first NMOS tube is connected to the drain of the sixth PMOS tube, the drain is connected to the drain of the fourth PMOS tube, and the source is connected to the negative end of the ninth resistor. The source of the third PMOS tube is connected to the drain of the sixth PMOS tube, the gate is connected to the drain and connected to the collector of the third NPN tube. The base of the third NPN tube is connected to the collector, and the emitter is connected to the positive end of the ninth resistor. The tenth resistor is connected to the negative end of the ninth resistor, and the negative end is connected to V SS .

5. The operational amplifier bias circuit with protection function according to claim 1, characterized in that The bias current and voltage providing module includes a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a fourth NPN tube, an eleventh resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor. The positive end of the eleventh resistor is connected to V DD The sources of the fourth PMOS tube, the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, and the eleventh PMOS tube are connected to the negative end of the eleventh resistor, the gate of the fourth PMOS tube is connected to the drain of the eighth PMOS tube, and the gates of the eighth PMOS tube, the ninth PMOS tube, the tenth PMOS tube, and the eleventh PMOS tube are connected to the source of the fifth PMOS tube. The gate and drain of the ninth PMOS tube are connected, the drain of the tenth PMOS tube is connected to the source of the sixth PMOS tube, and the drain of the eleventh PMOS tube is connected to the gate of the seventh PMOS tube. The source of the seventh PMOS tube is connected to V DD , the drain is connected to the source of the twelfth PMOS tube and the thirteenth PMOS tube. The gate and drain of the fifth PMOS tube are connected, and connected to the drain of the third NMOS tube. The gate of the sixth PMOS tube is connected to the gate of the fifth PMOS tube, and the drain is connected to the positive end of the fourteenth resistor. The gates of the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are connected to the drain of the fifth NMOS tube, the source of the second NMOS tube is connected to the drain of the sixth NMOS tube, the source of the third NMOS tube is connected to the gate of the fifth NMOS tube, the drain of the fourth NMOS tube is connected to the gate of the seventh PMOS tube, and the source is connected to the drain of the eighth NMOS tube. The source of the fifth NMOS tube is connected to V SS The source electrodes of the sixth NMOS tube, the seventh NMOS tube, and the eighth NMOS tube are connected to V SS , the gate is connected to the drain of the seventh NMOS tube. The drain of the seventh NMOS tube is connected to the emitter of the fourth NPN tube. The gate and drain of the ninth NMOS tube are connected, and connected to the negative end of the fifteenth resistor. The gate of the twelfth PMOS tube is connected to the gate of the thirteenth PMOS tube, and connected to the positive end of the fifteenth resistor. The drain of the twelfth PMOS tube is connected to the source of the fourth NMOS tube, and the gate and drain of the thirteenth PMOS tube are connected. The base and collector of the fourth NPN tube are connected, and connected to the negative end of the fourteenth resistor. The positive end of the twelfth resistor is connected to the eleventh resistor, and the negative end is connected to the drain of the fifth NMOS tube. The positive end of the thirteenth resistor is connected to the source of the third NMOS tube.

6. The operational amplifier bias circuit with protection function according to claim 1, characterized in that The power-on protection and enable signal generating module includes a fourteenth PMOS tube, a fifteenth PMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a sixteenth resistor, a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter, and a sixth inverter. The source of the fourteenth PMOS tube is connected to the drain of the seventh PMOS tube, the gate is connected to the gate of the thirteenth PMOS tube, and the source is connected to the drain of the tenth NMOS tube. The source of the fifteenth PMOS tube is connected to the drain of the fourth PMOS tube, the gate is connected to the gate of the third PMOS tube, and the drain is connected to the gate of the tenth NMOS tube. The source of the tenth NMOS tube is connected to the drains of the eleventh NMOS tube and the twelfth NMOS tube, and the sources of the eleventh NMOS tube and the twelfth NMOS tube are connected to V SS The gate of the eleventh NMOS tube is connected to the drain, the gate of the twelfth NMOS tube is connected to the output of the sixth inverter. The drain of the thirteenth NMOS tube is connected to the output of the second inverter and the input of the third and fourth inverters, the gate is connected to the drain of the fourteenth PMOS tube, and the source is connected to V SS The positive end of the sixteenth resistor is connected to the drain of the fifteenth PMOS tube, and the negative end is connected to V SS The positive power supply of each inverter is connected to the drain of the seventh PMOS tube, and the negative power supply is connected to V SS The input end of the first inverter is connected to the drain of the eighteenth NMOS tube, and the output end is connected to the input end of the second inverter. The output end of the second inverter is connected to the input ends of the third inverter and the fourth inverter. The output end of the third inverter is connected to the input end of the fifth inverter and the gate of the nineteenth NMOS tube, the output end of the fourth inverter is connected to the subsequent operational amplifier part, the output end of the fifth inverter is connected to the gate of the twenty-fourth PMOS tube, and the input end of the sixth inverter is connected to the drain of the tenth NMOS tube.

7. The operational amplifier bias circuit with protection function according to claim 1, characterized in that The hysteresis comparator module includes a sixteenth PMOS tube, a seventeenth PMOS tube, an eighteenth PMOS tube, a nineteenth PMOS tube, a twentieth PMOS tube, a twenty-first PMOS tube, a twenty-second PMOS tube, a twenty-third PMOS tube, a twenty-fourth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a fifth NPN tube, a sixth NPN tube, a seventeenth resistor, an eighteenth resistor, and a nineteenth resistor. The gates of the eighteenth PMOS tube, the nineteenth PMOS tube, the twentieth PMOS tube, the twenty-first PMOS tube, and the twenty-second PMOS tube are connected to the gate of the third PMOS tube, and the source is connected to the drain of the fourth PMOS tube. The drain of the eighteenth PMOS tube is connected to the gate of the sixteenth PMOS tube, the drain of the nineteenth PMOS tube is connected to the sources of the sixteenth PMOS tube and the seventeenth PMOS tube, the drain of the twentieth PMOS tube is connected to the drain of the eighteenth NMOS tube, the drain of the twenty-first PMOS tube is connected to the sources of the twenty-third PMOS tube and the twenty-fourth PMOS tube, and the drain of the twenty-second PMOS tube is connected to the gate of the seventeenth PMOS tube. The gate of the twenty-third PMOS tube is connected to the output end of the fifth inverter, and the drain is connected to the positive end of the nineteenth resistor. The drain of the twenty-fourth PMOS tube is connected to the drain of the eighteenth NMOS tube. The drain of the sixteenth PMOS tube is connected to the drain of the sixteenth NMOS tube, and the drain of the seventeenth PMOS tube is connected to the drain of the seventeenth NMOS tube. The drain of the fourteenth NMOS tube is connected to the negative end of the seventeenth resistor, and the source end is connected to V SS The gate and drain of the fifteenth NMOS tube are connected, the drain is connected to the drain of the sixteenth PMOS tube, and the source is connected to the drain of the sixteenth PMOS tube. The sources of the sixteenth NMOS tube, the seventeenth NMOS tube, and the eighteenth NMOS tube are connected to V SS , the gate and drain of the sixteenth NMOS tube are connected, and the drain is connected to the drain of the sixteenth NMOS tube. The gate of the seventeenth NMOS tube is connected to the gate of the sixteenth NMOS tube, and the drain is connected to the drain of the seventeenth PMOS tube. The gate of the eighteenth NMOS tube is connected to the drain of the seventeenth PMOS tube. The positive end of the seventeenth resistor is connected to the gate of the sixteenth PMOS tube, and the negative end is connected to the eighteenth resistor. The negative ends of the eighteenth resistor and the nineteenth resistor are grounded. The base and collector of the fifth NPN tube and the sixth NPN tube are connected, the collector of the fifth NPN tube is connected to the gate of the seventeenth PMOS tube, and the emitter is connected to the collector of the sixth NPN transistor. The emitter of the sixth NPN transistor is connected to V SS .

8. The operational amplifier bias circuit with protection function according to claim 2-7, characterized in that: The method for implementing bias in the circuit at least includes: providing a certain current to the module and the power-on protection and enable signal generating module through the bias current and voltage providing module, generating a voltage slightly less than 5V for the inverter part and providing a bias voltage for the gate of the first NMOS tube. Providing a constant current to the operational amplifier through the PTAT current generating module. Producing a bias current for the part under the secondary power supply through the bias current providing module under the secondary power supply, and obtaining a determined secondary power supply voltage.

9. The method for providing bias according to claim 8, characterized in that: When the power supply voltage increases to a certain value, the second NMOS transistor, the third NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, etc. in the bias current and voltage module all work in the saturation region, I DR13 =I DMP9 =I,I DMN5 =I0,I DMP8 =I DMP10 =I DMP11 =I DMP12 =I,I DMN8 =I DMP13 =2I. The gate voltage of the fifth NMOS tube is proportional to I, so I0 is also positively correlated with I. Since the sum of the voltage drops of the fifth NMOS tube and the twelfth resistor is approximately V DD Therefore, the gate voltage of the third NMOS tube can be represented by I0, and finally the bias current generated on the thirteenth resistor and V DD Positive correlation. The drain voltage of the sixth PMOS tube is V1, which serves as the gate voltage of the first NMOS tube; the drain voltage of the seventh PMOS tube is V2, which serves as the positive power supply of the inverter. Both V1 and V2 are determined by the bias current I. When the secondary power supply voltage increases to a certain value, the emitter junctions of the first NPN transistor and the second NPN transistor in the PTAT current generating module are turned on and work in the amplification region. The voltage difference between the two ends of the first resistor is I PTAT I PTAT After normal generation, the secondary power supply voltage and the bias current I1 provided by the third PMOS tube are both stable.

10. The method for providing bias according to claim 8-9, characterized in that: The current I on the thirteenth resistor satisfies The drain voltage V1 of the sixth PMOS tube satisfies V1=IR 14 +V BE_NPN4 +V GS_MN6 in I S is the saturation current of the transistor, is the thermal voltage. β is the process constant of the MOS tube. The I generated by the first resistor PTAT satisfy The bias current I1 provided by the third PMOS tube satisfies The source voltage V2 of the third PMOS tube satisfies <h2 style=";text-align:left;direction:ltr">V2 = I1 R9 + V<h2 style=";text-align:left;direction:ltr"> BE_NPN3 <h2 style=";text-align:left;direction:ltr"> +V<h2 style=";text-align:left;direction:ltr"> GS_MP3 <h2 style=";text-align:left;direction:ltr"> +V<h2 style=";text-align:left;direction:ltr"> R10 in I S is the saturation current of the transistor, is the thermal voltage. β is the process constant of the MOS tube.

11. The operational amplifier bias circuit with protection function according to claim 2-7, characterized in that: The method for providing protection for the operational amplifier by the circuit at least comprises: DD The bias current I1 provided by the third PMOS tube is relatively small, the bias current I1 provided by the third PMOS tube has not yet reached the maximum, the voltage drop on the sixteenth resistor is relatively small, and when the tenth NMOS tube is in the cut-off region, this is region I, the input of the sixth inverter and the gate voltage of the thirteenth NMOS tube are high level, and the thirteenth NMOS tube is in the linear region; the output of the sixth inverter is low level, and the twelfth NMOS tube is in the cut-off region; after the bias current I1 provided by the third PMOS tube reaches the maximum value, the tenth NMOS tube is turned on and works in the linear region, which is region II, the input of the sixth inverter and the gate voltage of the thirteenth NMOS tube are low level, and the thirteenth NMOS tube is in the cut-off region; the output of the sixth inverter is high level, the twelfth NMOS tube is in the linear region, and the eleventh NMOS tube is in the cut-off region. When the operational amplifier is working normally, the hysteresis comparator is composed of the fifteenth NMOS tube, the sixteenth NMOS tube, the seventeenth NMOS tube, the sixteenth PMOS tube, and the seventeenth PMOS tube. The gate of the sixteenth PMOS tube is the non-inverting input terminal, and the gate of the seventeenth PMOS tube is the inverting input terminal. When the operational amplifier is working normally, the hysteresis comparator outputs a low level, and the fourteenth NMOS tube works in the linear region, which is state I. When the bias current increases abnormally, making the voltage at the non-inverting input terminal greater than the reference voltage at the inverting input terminal, the hysteresis comparator outputs a high level, and the fourteenth NMOS tube works in the cut-off region, which is state II. Since the fourteenth NMOS tube is connected in parallel with the eighteenth resistor, which is one of the voltage divider resistors, the flip threshold of the comparator is affected, thereby generating a hysteresis effect. When the circuit is working normally, the gate voltage V1 of the first NMOS tube is small and insufficient to turn it on, so the first NMOS tube works in the cut-off region, which is region I; the power supply voltage V DD After abnormal increase, V1 will rise to turn on the first NMOS tube and work in the saturation region. This is state II. In this state, the first NMOS tube will divide the bias current originally generated by the third PMOS tube, causing the part under the secondary power supply to no longer work normally, and the inverter chain outputs a low level to protect the op amp.

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