Semiconductor device and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, and the semiconductor device comprises a substrate; the active strips and the first grooves are located on the surface of the substrate, extend in the first direction and are alternately arranged in the second direction, and the active columns are located on the surfaces of the active strips and are arranged at intervals in the first direction. The first isolation layer extends along the first direction and is positioned at the bottom of the first groove; the bit line structure is located on the top surface of the first isolation layer and covers the side wall of a part of the active strip; the first isolation structures are located between the adjacent bit line structures in the first grooves; an air gap in the first isolation structure; wherein the first direction and the second direction intersect and are located in the plane where the substrate is located.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor device and a method for preparing the same. Background Art

[0002] Currently, a dynamic random access memory (DRAM) having a buried bit line structure is formed to improve the integration of the DRAM and achieve miniaturization.

[0003] However, the buried bit line structures in the related art have serious coupling between them, and the parasitic capacitance is large, which affects the sensing margin of the sense amplifier (SA). In addition, the buried bit line structures in the related art have serious leakage, which affects the working performance of the DRAM. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0006] substrate;

[0007] Active strips and first grooves extending along a first direction on the surface of the substrate and arranged alternately along a second direction, and a plurality of active pillars arranged at intervals along the first direction on the surface of the active strips;

[0008] a first isolation layer extending along the first direction and located at the bottom of the first trench;

[0009] A bit line structure, located on the top surface of the first isolation layer and covering a portion of the sidewall of the active strip;

[0010] a first isolation structure located between adjacent bit line structures in the first trench;

[0011] an air gap located in the first isolation structure;

[0012] The first direction intersects with the second direction and is located in the plane where the substrate is located.

[0013] In some embodiments, it also includes:

[0014] The second isolation layer is located between the bit line structure and the first isolation structure.

[0015] In some embodiments, the active strip includes a first semiconductor layer, a first insulating layer, and an ohmic contact layer located on the surface of the substrate;

[0016] The first isolation layer is located in the first trench between the first semiconductor layers, and the bottom surface of the first insulating layer along the third direction exceeds the top surface of the first isolation layer along the third direction; the third direction intersects with the plane where the substrate is located;

[0017] The bit line structure covers the first insulating layer, the ohmic contact layer, and a portion of the first semiconductor layer sidewall not covered by the first isolation layer.

[0018] In some embodiments, the method further includes: a second trench located between the active pillars and extending along the second direction;

[0019] A second isolation structure, located at the bottom of the second trench;

[0020] The gate structure is located on the top surface of the second isolation structure and covers a portion of the sidewall of the active column; wherein the top surface of the active column exceeds the top surface of the gate structure.

[0021] In some embodiments, the material of the first isolation layer includes silicon nitride;

[0022] The material of the second isolation layer includes a low dielectric constant material;

[0023] The material of the first isolation structure includes silicon dioxide.

[0024] In a second aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor device, comprising:

[0025] Providing a substrate, the substrate comprising initial active strips and first grooves extending along a first direction and alternately arranged along a second direction;

[0026] forming a first isolation layer extending along the first direction at the bottom of the first trench;

[0027] A bit line structure is formed on the top surface of the first isolation layer and a part of the inner wall of the first trench; wherein a gap exists between two adjacent bit line structures located in the same first trench;

[0028] forming a first isolation structure in the gap, and an air gap in the first isolation structure;

[0029] The first direction intersects with the second direction and is located in the plane where the base is located.

[0030] In some embodiments, before forming the first isolation structure and the air gap, the method further includes:

[0031] A second isolation layer is formed on the surface of the bit line structure.

[0032] In some embodiments, providing a substrate comprises:

[0033] Providing a substrate and a semiconductor layer; the semiconductor layer comprises a first semiconductor layer, a first insulating layer, and a second semiconductor layer sequentially stacked along a third direction; the third direction intersects with the plane where the substrate is located;

[0034] The semiconductor layer is patterned until the substrate is exposed to form the initial active strip and the first trench; wherein the initial active strip includes the first semiconductor layer, the first insulating layer and the second semiconductor layer sequentially stacked along the third direction.

[0035] In some embodiments, providing the semiconductor layer includes:

[0036] providing an initial semiconductor structure;

[0037] Performing oxygen ion implantation on the initial semiconductor structure to form a buried layer inside the initial semiconductor structure;

[0038] The initial semiconductor structure and the buried layer are annealed to form the first insulating layer; wherein the first insulating layer material includes silicon dioxide, and the initial semiconductor structure located below the first insulating layer constitutes the first semiconductor layer; and the initial semiconductor structure located above the first insulating layer constitutes the second semiconductor layer.

[0039] In some embodiments, forming a first isolation layer extending along the first direction at the bottom of the first trench includes:

[0040] forming a first initial isolation layer in the first trench;

[0041] The first initial isolation layer is etched back, and the portion of the first initial isolation layer that is retained and located below the first insulating layer and between the first semiconductor layers constitutes the first isolation layer; wherein the bottom surface of the first insulating layer along the third direction exceeds the top surface of the first isolation layer along the third direction.

[0042] In some embodiments, before forming the bit line structure, the method further includes:

[0043] Forming a metal layer on the surface of the first isolation layer in the first trench; a top surface of the metal layer is located between the second semiconductor layers;

[0044] Performing heat treatment on the metal layer and the second semiconductor layer to form an ohmic contact layer located at the bottom of the second semiconductor layer;

[0045] The first semiconductor layer, the first insulating layer and the ohmic contact layer constitute an active strip, and the bit line structure covers a portion of the sidewall of the active strip.

[0046] In some embodiments, forming a bit line structure on a top surface of the first isolation layer and a portion of an inner wall of the first trench includes:

[0047] forming an initial bit line structure on an inner wall of the first trench and a surface of the first isolation layer;

[0048] The initial bit line structure on the side wall of the second semiconductor layer is removed, and the initial bit line structure remaining on the first insulating layer, the ohmic contact layer and the side wall of the first semiconductor layer constitutes the bit line structure.

[0049] In some embodiments, the first isolation structure also fills the first trench; and the method further includes:

[0050] Etching the first isolation structure and the second semiconductor layer to form a plurality of active pillars arranged in an array along the first direction and the second direction, and a second trench extending along the second direction between the active pillars; the second trench exposes the ohmic contact layer and the first isolation structure;

[0051] forming a second isolation structure at the bottom of the second trench;

[0052] A gate structure is formed on the sidewall of the second trench portion having the second isolation structure; wherein the top surface of the active pillar exceeds the top surface of the gate structure.

[0053] In some embodiments, the material of the first isolation layer includes silicon nitride;

[0054] The material of the second isolation layer includes a low dielectric constant material;

[0055] The material of the first isolation structure includes silicon dioxide.

[0056] In some embodiments, the method further comprises:

[0057] A semiconductor isolation layer or a second insulating layer is formed between the substrate and the semiconductor layer.

[0058] The semiconductor device and its preparation method provided by the embodiment of the present disclosure, wherein the semiconductor device includes: a substrate, including active strips and first grooves extending along a first direction and arranged alternately along a second direction, and a plurality of active pillars located on the surface of the active strips and arranged at intervals along the first direction; a first isolation layer extending along the first direction and located at the bottom of the first groove; a bit line structure located on the top surface of the first isolation layer and covering the sidewall of the active strip; a first isolation structure located between adjacent bit line structures in the first groove; and an air gap located in the first isolation structure. Since an air gap is formed in the first isolation structure between the bit line structures, the coupling effect between adjacent bit line structures can be reduced, the parasitic capacitance can be reduced, and thus the sensing margin of the sensing amplifier can be improved; in addition, since the first isolation layer is formed at the bottom of the bit line structure, leakage between the bit line structure and the substrate can be prevented, thereby improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0060] Figure 1 A schematic diagram of a process for preparing a semiconductor device provided by an embodiment of the present disclosure;

[0061] Figures 2 to 21 A schematic diagram of the structure of a semiconductor device during formation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0063] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0064] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0065] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part discussed, it does not mean that the present disclosure necessarily has the first element, component, region, layer or part.

[0066] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] Currently, the coupling between buried bit line structures is serious, the parasitic capacitance is large, and the sensing margin of the sense amplifier is affected. In addition, the leakage between the buried bit line structure and the substrate is serious, which affects the working performance of the semiconductor device.

[0068] Based on this, the embodiment of the present disclosure provides a semiconductor device and a method for preparing the same, wherein the semiconductor device comprises: a substrate, comprising an active strip and a first groove extending in a first direction and arranged alternately in a second direction, and a plurality of active pillars located on the surface of the active strip and arranged at intervals in the first direction; a first isolation layer extending in the first direction and located at the bottom of the first groove; a bit line structure located on the top surface of the first isolation layer and covering the sidewall of the active strip; a first isolation structure located between adjacent bit line structures in the first groove; and an air gap located in the first isolation structure. Since an air gap is formed in the first isolation structure between the bit line structures, the coupling effect between adjacent bit line structures can be reduced, the parasitic capacitance can be reduced, and thus the sensing margin of the sensing amplifier can be improved; in addition, since a first isolation layer is formed at the bottom of the bit line structure, leakage between the bit line structure and the substrate can be prevented, thereby improving the electrical performance of the semiconductor device.

[0069] Hereinafter, the semiconductor device and the manufacturing method thereof in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0070] Before introducing the embodiments of the present disclosure, the following embodiments may use three directions to describe the three-dimensional structure, and take the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis, and Z-axis directions. The thickness direction of the substrate is defined as the third direction. In the plane direction where the substrate is located, two directions intersecting with each other (for example, perpendicular to each other) are defined as the second direction and the third direction. For example, the arrangement direction of the active strip and the first groove may be defined as the second direction. Here, the first direction may be, for example, the X-axis direction, the second direction may be, for example, the Y-axis direction, and the third direction may be, for example, the Z-axis direction.

[0071] Figure 1 A schematic diagram of a process for preparing a semiconductor device according to an embodiment of the present disclosure is provided. Figures 1 to 21 The schematic diagrams of various structures in the semiconductor device manufacturing process provided by the embodiment of the present disclosure are as follows. Figures 1 to 21 The formation process of the semiconductor device is described in detail.

[0072] like Figure 1 As shown, the method for preparing a semiconductor device includes the following steps S101 to S104.

[0073] First, refer to Figures 1 to 7 , performing step S101, providing a substrate, the substrate comprising initial active strips 20b and first grooves 12 extending along a first direction and alternately arranged along a second direction.

[0074] It should be noted that the initial active strip 20 b is used to form the source region, drain region and channel region of the transistor in the semiconductor device, and the bit line structure and word line structure of the semiconductor device will be formed in the first trench 12 .

[0075] In some embodiments, providing a substrate comprises the following steps:

[0076] Step 1: Provide Figure 4 The substrate 10 and the semiconductor layer 20 are shown; the semiconductor layer 20 includes a first semiconductor layer 201, a first insulating layer 202 and a second semiconductor layer 203 which are sequentially stacked along a third direction.

[0077] Here, the substrate 10 may be a silicon substrate, and the substrate 10 may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0078] The main material layer of the semiconductor layer 20 may be the same material as the substrate 10 , or may be a silicon wafer after surface treatment (ie, a single crystal silicon material layer), or may be a material layer containing other semiconductor elements such as polycrystalline silicon.

[0079] In some embodiments, the semiconductor layer 20 may be formed by using SIMOX technology. Specifically, providing the semiconductor layer 20 may include the following steps:

[0080] Step 1: Provide Figure 2 An initial semiconductor structure 20a is shown;

[0081] Step 2: implanting oxygen ions into the initial semiconductor structure 20a to form a Figure 3 The buried layer 202a is shown;

[0082] It should be noted that the buried layer 202 a is a layer doped with high-dose oxygen ions inside the initial semiconductor structure 20 a , and the high-dose oxygen ions can be implanted under high temperature conditions.

[0083] Step 3: Anneal the initial semiconductor structure 20a and the buried layer 202a to form a first insulating layer 202; wherein the material of the first insulating layer 202 includes silicon dioxide, and the initial semiconductor structure 20a located below the first insulating layer 202 constitutes a first semiconductor layer 201; the initial semiconductor structure 20a located above the first insulating layer 202 constitutes a second semiconductor layer 203.

[0084] It should be noted that the semiconductor layer 20 composed of the second semiconductor layer 203, the first insulating layer 202 and the first semiconductor layer 201 can be understood as a silicon-on-insulator (SOI) wafer on an insulating substrate. Among them, the first semiconductor layer 201 is equivalent to the bulk silicon in the SOI wafer, the first insulating layer 202 is equivalent to the silicon dioxide buried layer in the SOI wafer, and the second semiconductor layer 203 is equivalent to the top silicon in the SOI wafer.

[0085] It should also be noted that the first semiconductor layer 201 and the substrate 10 may be made of the same material to form a continuous layer.

[0086] In other embodiments, the semiconductor layer 20 may also be formed by the following steps:

[0087] Depositing a semiconductor material on the surface of the substrate 10 to form a first initial semiconductor layer; wherein the semiconductor material comprises a polycrystalline semiconductor material;

[0088] Depositing an insulating material on the surface of the first semiconductor layer 201 to form a first insulating layer 202; wherein the insulating material may be silicon dioxide;

[0089] Depositing semiconductor material again on the surface of the first insulating layer 202 to form a second initial semiconductor layer;

[0090] The first initial semiconductor layer and the second initial semiconductor layer are subjected to high temperature heat treatment to form a first semiconductor layer 201 and a second semiconductor layer 203 .

[0091] It should be noted that the first initial semiconductor layer and the second initial semiconductor layer formed by deposition are polycrystalline semiconductor materials. The polycrystalline semiconductor materials can be converted into single-crystalline semiconductor materials by high-temperature heat treatment, which can increase the mobility of carriers in the channel structure, thereby increasing the driving current of the formed transistor, and further increasing the response speed of the semiconductor device.

[0092] It should also be noted that the polycrystalline semiconductor material may include polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium.

[0093] The semiconductor layer 20 is patterned until the substrate 10 is exposed, forming an initial active strip 20b and a first trench 12; wherein the initial active strip 20b includes a first semiconductor layer 201, a first insulating layer 202 and a second semiconductor layer 203 sequentially stacked along a third direction.

[0094] During implementation, for example, a layer such as Figures 5 to 7The first photoresist layer 11 having a preset pattern as shown in the figure includes a plurality of sub-patterns arranged at intervals along the Y-axis direction, each sub-pattern extending along the X-axis direction and exposing a portion of the semiconductor layer 20; next, the semiconductor layer 20 is etched through the first photoresist layer 11 to remove the portion of the semiconductor layer 20 exposed by each sub-pattern, thereby forming a semiconductor layer 20 as shown in the figure. Figure 5 and Figure 7 The initial active strips 20 b and the first trenches 12 between the initial active strips 20 b are shown. The bottoms of the first trenches 12 expose the substrate 10 .

[0095] It should be noted that Figure 5 is a three-dimensional view of a semiconductor device. Figure 6 for Figure 5 A top view of Figures 7 to 19 Both Figure 6 The cross-sectional views along a-a', b-b', and c-c' will not be specifically described later.

[0096] It should also be noted that since the initial active strip 20b is formed by patterning the semiconductor layer 20, when the main material of the semiconductor layer 20 is single crystal silicon, since single crystal silicon has high electron mobility, using single crystal silicon as the channel structure can increase the mobility of carriers in the channel structure, thereby increasing the driving current of the formed transistor, and further increasing the response speed of the semiconductor device.

[0097] Next, continue to refer to Figure 1 ,as well as Figures 8 to 10 , performing step S102 to form a first isolation layer 15 extending along a first direction at the bottom of the first trench 12 .

[0098] It should be noted that the first isolation layer 15 is located at the bottom of the first trench 12, and a bit line structure will be subsequently formed on the surface of the first isolation layer 15 in the first trench 12. The first isolation layer 15 is located between the bit line structure and the substrate 10. In this way, the bit line structure can be prevented from leaking electricity to the substrate 10, thereby improving the electrical performance of the semiconductor device.

[0099] It should also be noted that in the embodiment of the present disclosure, the material of the first isolation layer 15 may be silicon nitride. In other embodiments, the material of the first isolation layer 15 may also include silicon dioxide, silicon oxynitride, or a combination thereof, or a combination thereof and silicon nitride.

[0100] In some embodiments, step S102 may include the following steps:

[0101] A first preliminary isolation layer 13 is formed in the first trench 12 .

[0102] During implementation, an isolation material may be deposited in the first trench 12 to form a Figure 8The first initial isolation layer 13 is shown. For example, the isolation material can be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, a coating process or a thin film process to form the first initial isolation layer 13. Here, the isolation material can be silicon nitride.

[0103] The first initial isolation layer 13 is etched back, and the remaining portion of the first initial isolation layer 13 located below the first insulating layer 202 and between the first semiconductor layers 201 constitutes a first isolation layer 15; wherein the bottom surface of the first insulating layer 202 along the third direction exceeds the top surface of the first isolation layer 15 along the third direction.

[0104] During implementation, first, a layer as follows is formed on the surface of the first initial isolation layer 13: Fig. 9 The second photoresist layer 14 shown in FIG. 1 has the same pattern as the first photoresist layer 11, that is, the second photoresist layer 14 exposes the first initial isolation layer 13 in the first groove 12; secondly, the first initial isolation layer 13 is etched to remove the portion of the first initial isolation layer 13 exposed by the second photoresist layer 14, and the remaining first initial isolation layer 13 located at the bottom of the first groove 12 is formed as shown in FIG. Fig.10 The first isolation layer 15 is shown. The bottom surface of the first insulating layer 202 in the Z-axis direction exceeds the top surface of the first isolation layer 15 in the Z-axis direction.

[0105] Please refer to Fig.10 In the process of etching back the first initial isolation layer 13, the first initial isolation layer 13 located on the top surface of the initial active strip 20b is not removed.

[0106] In some embodiments, the method for forming a semiconductor device may further include: forming a semiconductor isolation layer and / or a second insulating layer between the substrate 10 and the semiconductor layer 20 .

[0107] It should be noted that the material of the second insulating layer may be silicon dioxide. The second insulating layer may reduce leakage between the bit line structure and the substrate.

[0108] The semiconductor isolation layer can be an N-type doped layer or a P-type doped layer, and a reverse PN junction is formed between the semiconductor isolation layer and the semiconductor layer 20 (i.e., the first semiconductor layer 201), so that the current of the bit line structure cannot flow to the substrate 10. In this way, the leakage between the bit line structure and the substrate 10 can be further reduced.

[0109] In some embodiments, please refer to Fig.11, the method for preparing the semiconductor device further comprises:

[0110] A metal layer 17 is formed on the surface of the first isolation layer 15 in the first trench 12 ; a top surface of the metal layer 17 is located between the second semiconductor layers 203 .

[0111] During implementation, first, a metal material is deposited on the surface of the first isolation layer 15 and the retained first initial isolation layer 13 to form a Fig.11 Secondly, the initial metal layer 16 is etched back to remove the initial metal layer 16 on the surface of the first initial isolation layer 13, and to remove part of the initial metal layer 16 in the first groove 12, forming Fig.12 The metal layer 17 shown in FIG. The metal material may be at least one of nickel, cobalt or platinum.

[0112] The metal layer 17 and the second semiconductor layer 203 are heat treated to form a Fig.13 The ohmic contact layer 18 is shown.

[0113] It should be noted that the heat treatment process for the metal layer 17 and the second semiconductor layer 203 may be a rapid thermal processing (RTP) process, during which the metal ions in the metal layer 17 diffuse into the second semiconductor layer 203 around it, react with the second semiconductor layer 203 to form a metal silicide as the ohmic contact layer 18. Since a bit line structure will be formed on the sidewall of the ohmic contact layer 18 and in the first trench 12 later, the metal silicide has a lower resistance value, so the contact resistance between the bit line structure and the second semiconductor layer 203 can be reduced, thereby reducing the power consumption of the formed semiconductor device.

[0114] It should also be noted that, in general, the process of heat treating the metal layer 17 and the second semiconductor layer 203 to form metal silicide is likely to induce leakage between the bit line structures, that is, it is likely to form a leakage path between the bit line structures. In the embodiment of the present disclosure, since the first insulating layer 202 is formed at the bottom of the second semiconductor layer 203, the first insulating layer 202 can be used as a stop layer for metal ion doping, which can limit the position of the metal ion doping in the second semiconductor layer 203, and can avoid the formation of a conductive path (i.e., a leakage path) between the bit line structures.

[0115] In addition, the position of the first insulating layer 202 can also control the thickness of the ohmic contact layer 18 in contact with the bit line structure. Due to the presence of the first insulating layer 202, the concentration and energy of the ohmic contact layer 18 (i.e., metal silicide) are relatively unrestricted, which can better reduce the contact resistance between the bit line structure and the semiconductor device, thereby reducing the power consumption.

[0116] In some embodiments, the first semiconductor layer 201, the first insulating layer 202 and the ohmic contact layer 18 constitute Fig.13 Active strip 20c is shown.

[0117] In some embodiments, after forming the ohmic contact layer 18, the method for forming a semiconductor device further includes: removing the metal layer 17. For example, the metal layer 17 may be removed by etching through a dry etching process.

[0118] Next, continue to refer to Figure 1 ,as well as Fig.15 and Fig.16 , executing step S103 , forming a bit line structure 19 on the top surface of the first isolation layer 15 and a portion of the inner wall of the first trench 12 ; wherein a gap exists between two adjacent bit line structures 19 located in the same first trench 12 .

[0119] It should be noted that forming the bit line structure 19 on part of the inner wall of the first trench 12 means that the top surface of the bit line structure 19 is lower than the top surface of the initial active strip 20 b , that is, the bit line structure 19 is formed relatively close to the bottom of the first trench 12 .

[0120] In some embodiments, step S103 may include the following steps:

[0121] An initial bit line structure 19a is formed on the inner wall of the first trench 12 and the surface of the first isolation layer 15;

[0122] When implementing, you can Fig.14 The bit line material is deposited on the first initial isolation layer 13, the inner wall of the first trench 12, and the top surface of the first isolation layer 15 to form a Fig.15 The initial bit line structure 19a is shown. Here, the bit line material can be a single metal, a metal compound or an alloy, wherein the single metal can be copper, aluminum, tungsten, gold or silver, etc.; the metal compound can be tantalum nitride or titanium nitride; the alloy can be an alloy material composed of at least two of copper, aluminum, tungsten, gold or silver.

[0123] The initial bit line structure 19 a on the sidewall of the second semiconductor layer 203 is removed, and the remaining initial bit line structure 19 a located on the first insulating layer 202 , the ohmic contact layer 18 and the sidewall of the first semiconductor layer 201 constitutes a bit line structure 19 .

[0124] During implementation, a portion of the initial bit line structure 19a on the top surface of the first initial isolation layer 13 can be firstly removed by etching or chemical mechanical polishing, and then a portion of the initial bit line structure 19a on the inner wall of the first trench 12 can be removed by dry etching technology. The initial bit line structure 19a remaining on the first insulating layer 202, the ohmic contact layer 18 and the side wall of the first semiconductor layer 201 not covered by the first isolation layer 15 is formed as follows: Fig.16 The bit line structure 19 shown, that is, the bit line structure 19 covers the sidewalls of the active strip 20c.

[0125] Finally, continue to refer to Figure 1 , Fig.17 and Fig.18 , executing step S104 to form a first isolation structure in the gap and an air gap in the first isolation structure.

[0126] During implementation, a first isolation material is deposited between adjacent bit line structures 19 in the first trench 12, and a first isolation structure 23 located between adjacent bit line structures 19 in the first trench 12 and an air gap 22 located in the first isolation structure 23 are formed by controlling the deposition process. Here, the first isolation material of the first isolation structure 23 may be silicon dioxide.

[0127] Please refer to Fig.17 , the first isolation structure 23 also fills the first trench 12 .

[0128] In the disclosed embodiment, the air gap 22 can isolate the bit line structure 19, reduce the coupling effect between adjacent bit line structures 19, and reduce the parasitic capacitance, thereby improving the sensing margin of the sense amplifier.

[0129] In some embodiments, please refer to Fig.18 Before forming the first isolation structure 23 and the air gap 22 , the method for preparing the semiconductor device further includes: forming a second isolation layer 24 on the surface of the bit line structure 19 .

[0130] It should be noted that the material of the second isolation layer 24 includes a low dielectric constant material, that is, a Low-K material. The second isolation layer 24 can be formed by any suitable deposition process, such as ALD or CVD.

[0131] In the embodiment of the present disclosure, the second isolation layer 24 formed of a low dielectric constant material can further reduce the parasitic capacitance between the bit line structures 19, thereby improving the sensing margin of the sense amplifier and the performance of the semiconductor device.

[0132] In some embodiments, see Figures 19 to 21 , the method for preparing the semiconductor device further comprises:

[0133] The first isolation structure 23 and the second semiconductor layer 203 are etched to form a plurality of active pillars 30 arrayed along the first direction and the second direction, and second trenches 31 extending along the second direction between the active pillars 30 ; the second trenches 31 expose the ohmic contact layer 18 and the first isolation structure 23 .

[0134] During implementation, a third photoresist layer (not shown) having a specific pattern may be formed on the surface of the first isolation structure 23 and the second semiconductor layer 203. The specific pattern includes a plurality of sub-patterns arranged at intervals along the X-axis direction, and each sub-pattern extends along the Y-axis direction. The exposed first isolation structure 23 and the second semiconductor layer 203 are etched away through the third photoresist layer to form a Fig.19 and Fig. 20 The active pillars 30 and the second trenches 31 are shown extending along the Y-axis direction and arranged at intervals in the X-axis direction.

[0135] It should be noted that Fig. 20 for Fig.19 A top view of Fig.21 For along Fig.19 Cross-sectional views of a-a', b-b', c-c' and d-d'.

[0136] A second isolation structure 33 is formed at the bottom of the second trench 31 .

[0137] During implementation, a second isolation material is deposited at the bottom of the second trench 31 to form a Fig.21 As shown in the second isolation structure 33 , the second isolation material may be silicon dioxide, silicon nitride, silicon oxynitride or a combination thereof.

[0138] It should be noted that the second isolation structure 33 in the embodiment of the present disclosure is used to isolate adjacent bit line structures 19 and gate structures 32 .

[0139] A gate structure 32 is formed on a portion of the sidewall of the second trench 31 having the second isolation structure 33 ; wherein a top surface of the active pillar 30 exceeds a top surface of the gate structure 32 .

[0140] It should be noted that the gate structure 32 includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer. The material of the gate dielectric layer may be silicon oxide or other suitable materials; the material of the gate conductive layer may be any material with good conductivity, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu). The gate dielectric layer and the gate conductive layer may be formed by any suitable deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, and an atomic layer deposition process.

[0141] It should also be noted that the gate structure in the embodiment of the present disclosure is a double-gate structure. In other embodiments, the gate structure may also be a full-ring gate structure or a single-gate structure.

[0142] It can be understood that the bottom and top active pillars 30 not covered by the gate structure 32 constitute the first source and drain 34 and the second source and drain 35 of the semiconductor device respectively, and the part of the active pillars 30 covered by the gate structure 32 constitutes the channel region of the semiconductor device. The first source and drain 34 is connected to the bit line structure 19 through the ohmic contact layer 18.

[0143] In some embodiments, after forming the gate structure 32, the method for forming a semiconductor device further includes:

[0144] A second isolation material is deposited in the second trench 31 to form a third isolation structure 36, which fills the second trench 31 and is flush with the top surface of the active pillar 30. The second isolation material may be silicon dioxide.

[0145] It should be noted that the third isolation structure 36 in the disclosed embodiment is used to isolate adjacent gate structures 32 to prevent leakage or short circuit. In addition, the third isolation structure 36 fills the second trench 31 to make the semiconductor structure have a flat surface, which is convenient for subsequent formation of other functional structures.

[0146] In some embodiments, the method for forming a semiconductor device further includes: forming a capacitor structure connected to the second source and drain 35. It can be understood that the semiconductor device formed in the embodiment of the present disclosure may be a DRAM.

[0147] In other embodiments, the formed semiconductor device may also be other memory devices or logic devices.

[0148] The semiconductor device in the embodiment of the present disclosure has a vertical channel, which can reduce the size of the semiconductor device and achieve miniaturization; in addition, it can also improve the control ability of the semiconductor device, thereby improving the electrical performance of the semiconductor device.

[0149] The method for forming a semiconductor device provided by the embodiment of the present disclosure forms a first isolation layer at the bottom of the bit line structure, thereby preventing leakage between the bit line structure and the substrate, and improving the electrical performance of the semiconductor device. In addition, since an air gap is formed between adjacent bit line structures, the coupling effect between adjacent bit line structures can be reduced, the parasitic capacitance can be reduced, and the sensing margin of the sensing amplifier can be improved, thereby improving the performance of the formed semiconductor device.

[0150] Another embodiment of the present disclosure provides a Fig.21 The semiconductor structure shown. Fig.21 As shown, the semiconductor device includes:

[0151] Substrate 10;

[0152] Active strips 20c and first grooves extending along the X-axis direction and alternately arranged along the Y-axis direction on the surface of the substrate 10, and a plurality of active pillars 30 arranged at intervals along the first direction on the surface of the active strips 20c;

[0153] A first isolation layer 15 extending along the X-axis direction and located at the bottom of the first trench;

[0154] A bit line structure 19, located on the top surface of the first isolation layer 15 and covering a portion of the sidewall of the active strip 20c;

[0155] A first isolation structure 23, located between adjacent bit line structures 19 in the first trench;

[0156] The air gap 22 is located in the first isolation structure 23 .

[0157] In some embodiments, the material of the first isolation layer 15 includes silicon nitride; and the material of the first isolation structure 23 includes silicon dioxide.

[0158] In the embodiment of the present disclosure, the first isolation layer 15 can prevent the bit line structure 19 from leaking electricity to the substrate 10, thereby improving the electrical performance of the semiconductor device. In addition, the air gap in the first isolation structure 23 between the bit line structures 19 can reduce the coupling effect between adjacent bit line structures 19, reduce parasitic capacitance, thereby improving the sensing margin of the sense amplifier, and further improving the performance of the semiconductor device.

[0159] In some embodiments, please refer to Fig.21 The semiconductor device further includes: a second isolation layer 24 located between the bit line structure 19 and the first isolation structure 23 .

[0160] It should be noted that the second isolation layer 24 can further reduce the parasitic capacitance between the bit line structures 19 , thereby improving the sensing margin of the sense amplifier and the performance of the semiconductor device.

[0161] It should be noted that the material of the second isolation layer 24 includes a low dielectric constant material, ie, a Low-K material.

[0162] In some embodiments, please refer to Fig.21 The active strip 20c includes a first semiconductor layer 201, a first insulating layer 202 and an ohmic contact layer 18 located on the surface of the substrate 10; the first isolation layer 15 is located in the first groove between the first semiconductor layers 201, and the bottom surface of the first insulating layer 202 along the third direction exceeds the top surface of the first isolation layer 15 along the third direction.

[0163] In some embodiments, the bit line structure 19 covering a portion of the sidewalls of the active strip 20 c means that the bit line structure 19 covers the first insulating layer 202 , the ohmic contact layer 18 , and the sidewalls of the first semiconductor layer 201 not covered by the first isolation layer 15 .

[0164] In some embodiments, please refer to Fig.21 The semiconductor device also includes: a second trench located between the active pillars 30 and extending along the second direction; a second isolation structure 33 located at the bottom of the second trench; a gate structure 32 located on the top surface of the second isolation structure 33 and covering a portion of the sidewall of the active pillar 30; wherein the top surface of the active pillar 30 exceeds the top surface of the gate structure 32.

[0165] In some embodiments, the gate structure 32 includes a gate dielectric layer and a gate conductive layer located on the surface of the gate dielectric layer. It should also be noted that the gate structure 32 in the embodiment of the present disclosure is a double-gate structure. In other embodiments, the gate structure 32 can also be a full-ring gate structure or a single-gate structure.

[0166] The material of the second isolation structure 33 includes silicon dioxide.

[0167] In some embodiments, the bottom and top active pillars 30 not covered by the gate structure 32 constitute the first source and drain 34 and the second source and drain 35 of the semiconductor device respectively, and the portion of the active pillars 30 covered by the gate structure 32 constitutes the channel region of the semiconductor device. The first source and drain 34 is connected to the bit line structure 19 through the ohmic contact layer 18.

[0168] In some embodiments, see Fig.21 The semiconductor device further includes: a third isolation structure 36 ; the third isolation structure 36 is located between the gate structures 32 and fills the second trench, and the third isolation structure 36 is flush with the top surface of the active pillar 30 .

[0169] The material of the third isolation structure 36 includes silicon dioxide.

[0170] In some embodiments, the semiconductor device further includes a capacitor structure (not shown); the capacitor structure is connected to the second source and drain 35 .

[0171] It can be understood that the semiconductor device in the embodiment of the present disclosure may be a DRAM. In other embodiments, the semiconductor device may also be other types of memory, such as a NAND flash memory or a phase change memory.

[0172] It should be noted that the semiconductor device formed by the embodiment of the present disclosure is similar to the semiconductor device in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0173] The semiconductor device provided by the embodiment of the present disclosure includes a first isolation layer, and the first isolation layer is at the bottom of the bit line structure. Therefore, leakage between the bit line structure and the substrate can be prevented, thereby improving the electrical performance of the semiconductor device.

[0174] In addition, since the semiconductor device includes an air gap and the air gap is located in the first isolation structure between the bit line structures, the coupling effect between adjacent bit line structures can be reduced, the parasitic capacitance can be reduced, and the sensing margin of the sense amplifier can be improved.

[0175] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0176] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0177] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; Active strips and first grooves extending along a first direction on the surface of the substrate and arranged alternately along a second direction, and a plurality of active pillars arranged at intervals along the first direction on the surface of the active strips; a first isolation layer extending along the first direction and located at the bottom of the first trench; A bit line structure, located on the top surface of the first isolation layer and covering a portion of the sidewall of the active strip; a first isolation structure located between adjacent bit line structures in the first trench; an air gap located in the first isolation structure; The first direction intersects with the second direction and is located in the plane where the substrate is located.

2. The semiconductor device according to claim 1, wherein: Also includes: The second isolation layer is located between the bit line structure and the first isolation structure.

3. The semiconductor device according to claim 1 or 2, characterized in that: The active strip comprises a first semiconductor layer, a first insulating layer and an ohmic contact layer located on the surface of the substrate; The first isolation layer is located in the first trench between the first semiconductor layers, and the bottom surface of the first insulating layer along the third direction exceeds the top surface of the first isolation layer along the third direction; the third direction intersects with the plane where the substrate is located; The bit line structure covers the first insulating layer, the ohmic contact layer, and a portion of the first semiconductor layer sidewall not covered by the first isolation layer.

4. The semiconductor device according to claim 3, characterized in that Also includes: a second trench located between the active pillars and extending along the second direction; A second isolation structure, located at the bottom of the second trench; The gate structure is located on the top surface of the second isolation structure and covers a portion of the sidewall of the active column; wherein the top surface of the active column exceeds the top surface of the gate structure.

5. The semiconductor device according to claim 2, wherein: The material of the first isolation layer includes silicon nitride; The material of the second isolation layer includes a low dielectric constant material; The material of the first isolation structure includes silicon dioxide.

6. A method for preparing a semiconductor device, characterized in that: The method comprises: Providing a substrate, the substrate comprising initial active strips and first grooves extending along a first direction and alternately arranged along a second direction; forming a first isolation layer extending along the first direction at the bottom of the first trench; A bit line structure is formed on the top surface of the first isolation layer and a part of the inner wall of the first trench; wherein a gap exists between two adjacent bit line structures located in the same first trench; forming a first isolation structure in the gap, and an air gap in the first isolation structure; The first direction intersects with the second direction and is located in the plane where the base is located.

7. The method according to claim 6, characterized in that Before forming the first isolation structure and the air gap, the method further includes: A second isolation layer is formed on the surface of the bit line structure.

8. The method according to claim 6 or 7, characterized in that: The providing of a substrate comprises: Providing a substrate and a semiconductor layer; the semiconductor layer comprises a first semiconductor layer, a first insulating layer, and a second semiconductor layer sequentially stacked along a third direction; the third direction intersects with the plane where the substrate is located; The semiconductor layer is patterned until the substrate is exposed to form the initial active strip and the first trench; wherein the initial active strip includes the first semiconductor layer, the first insulating layer and the second semiconductor layer sequentially stacked along the third direction.

9. The method according to claim 8, characterized in that Providing the semiconductor layer, comprising: providing an initial semiconductor structure; Performing oxygen ion implantation on the initial semiconductor structure to form a buried layer inside the initial semiconductor structure; The initial semiconductor structure and the buried layer are annealed to form the first insulating layer; wherein the first insulating layer material includes silicon dioxide, and the initial semiconductor structure located below the first insulating layer constitutes the first semiconductor layer; and the initial semiconductor structure located above the first insulating layer constitutes the second semiconductor layer.

10. The method according to claim 8, characterized in that A first isolation layer extending along the first direction is formed at the bottom of the first trench, comprising: forming a first initial isolation layer in the first trench; The first initial isolation layer is etched back, and the portion of the first initial isolation layer that is retained and located below the first insulating layer and between the first semiconductor layers constitutes the first isolation layer; wherein the bottom surface of the first insulating layer along the third direction exceeds the top surface of the first isolation layer along the third direction.

11. The method according to claim 8, characterized in that Before forming the bit line structure, the method further includes: Forming a metal layer on the surface of the first isolation layer in the first trench; a top surface of the metal layer is located between the second semiconductor layers; Performing heat treatment on the metal layer and the second semiconductor layer to form an ohmic contact layer located at the bottom of the second semiconductor layer; The first semiconductor layer, the first insulating layer and the ohmic contact layer constitute an active strip, and the bit line structure covers a portion of the sidewall of the active strip.

12. The method according to claim 11, characterized in that A bit line structure is formed on a top surface of the first isolation layer and a portion of an inner wall of the first trench, comprising: forming an initial bit line structure on an inner wall of the first trench and a surface of the first isolation layer; The initial bit line structure on the side wall of the second semiconductor layer is removed, and the initial bit line structure remaining on the first insulating layer, the ohmic contact layer and the side wall of the first semiconductor layer constitutes the bit line structure.

13. The method according to claim 11, characterized in that The first isolation structure also fills the first trench; the method further includes: Etching the first isolation structure and the second semiconductor layer to form a plurality of active pillars arranged in an array along the first direction and the second direction, and a second trench extending along the second direction between the active pillars; the second trench exposes the ohmic contact layer and the first isolation structure; forming a second isolation structure at the bottom of the second trench; A gate structure is formed on the sidewall of the second trench portion having the second isolation structure; wherein the top surface of the active pillar exceeds the top surface of the gate structure.

14. The method according to claim 7, characterized in that The material of the first isolation layer includes silicon nitride; The material of the second isolation layer includes a low dielectric constant material; The material of the first isolation structure includes silicon dioxide.

15. The method according to claim 8, characterized in that The method further comprises: A semiconductor isolation layer or a second insulating layer is formed between the substrate and the semiconductor layer.

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