Preparation method of semiconductor memory

Abstract

The invention provides a preparation method of a semiconductor memory, which is applied to the technical field of semiconductors. In the invention, a bit line material layer comprising a first cover layer can be formed on a first region of a substrate and a shallow trench isolation structure, a gate structure is formed in a second region of the substrate, and then part of the first cover layer of the bit line material layer on the shallow trench isolation structure is removed. Forming a first cover layer on the shallow trench isolation structure between the first region and the second region of the substrate, so that the top surface of the bit line material layer on the shallow trench isolation structure between the first region and the second region of the substrate is lower than the top surfaces of the bit line material layers in the first region and the second region (in a groove form), and then forming a second cover layer on the first region and the shallow trench isolation structure with the groove in a conformal manner, therefore, the height of the bit line structure in the first region meets the product design requirement, the height of the bit line structure formed on the shallow trench isolation structure near the edge of the first region is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor memory. Background Art

[0002] Dynamic random access memory (DRAM) is a type of volatile memory, including an array area consisting of multiple memory cells and a peripheral area consisting of a control circuit. Each memory cell is composed of a transistor and a capacitor electrically connected to the transistor. The transistor controls the storage or release of charge in the capacitor to achieve the purpose of storing data. The control circuit can address each memory cell to control the access of data to each memory cell through word lines (WL) and bit lines (BL) that span the array area and are electrically connected to each memory cell.

[0003] In order to reduce the size of memory cells and manufacture chips with higher density, the structure of memory cells has been developed towards three-dimensionality, such as using buried wordline connections and stacked capacitors. Stacked capacitors are vertically arranged above the substrate, thereby saving the substrate area occupied by the capacitor and conveniently increasing the electrode height of the capacitor to obtain a larger capacitance. However, as the height increases, the bit line structure, especially the part near the peripheral area, often has the problem of tilting. Summary of the invention

[0004] The object of the present invention is to provide a method for preparing a semiconductor memory device, which can solve the problem in the prior art that as the height increases, the bit line structure, especially the part adjacent to the peripheral area (near the edge of the first area), often collapses.

[0005] In order to solve the above problems, the present invention provides a method for preparing a semiconductor memory, which may at least include:

[0006] providing a substrate comprising a first region and a second region;

[0007] forming a shallow trench isolation structure in the substrate, located between the first region and the second region, the shallow trench isolation structure defining the first region and the second region;

[0008] Forming a bit line material layer located on the first region of the substrate and the shallow trench isolation structure, the bit line material layer sequentially comprising a semiconductor layer, a metal layer and a first cap layer from bottom to top;

[0009] removing a portion of the first cap layer of the bit line material layer located on the shallow trench isolation structure to form a groove;

[0010] A second capping layer is formed on the remaining bit line material layer.

[0011] In some optional examples, forming the bit line material layer further includes forming the bit line material layer in the second region of the substrate to form a gate structure.

[0012] In some optional examples, after forming the gate structure located on the second region of the substrate, the method further includes:

[0013] An etch stop layer is formed on the first region of the substrate and the bit line material layer on the shallow trench isolation structure and on the gate structure in the second region of the substrate.

[0014] In some optional examples, after forming the etching stop layer, the method further includes:

[0015] An insulating dielectric layer is formed on the second region of the substrate and the etching stop layer on the shallow trench isolation structure, and a portion of the insulating dielectric layer in the second region of the substrate buries the gate structure.

[0016] In some optional examples, after forming the insulating dielectric layer, the method further includes:

[0017] A photoresist layer is formed on the first region and a portion of the shallow trench isolation structure and on the gate structure in the second region of the substrate.

[0018] In some optional examples, the step of forming the groove includes:

[0019] All the first capping layer on the shallow trench isolation structure that is not covered by the photoresist layer is removed to form a groove with a bottom exposing the metal layer below the first capping layer on the shallow trench isolation structure.

[0020] In some optional examples, the step of forming the groove includes:

[0021] A portion of the first cover layer on the shallow trench isolation structure that is not covered by the photoresist layer is removed to form a groove with the bottom exposing the remaining first cover layer on the shallow trench isolation structure, and the upper surface profile of the exposed remaining first cover layer is an arc shape that is concave toward the substrate surface.

[0022] In some optional examples, after the groove is formed, the sidewalls of the remaining bit line material layer are in a step-like shape in a horizontal direction from the first region of the substrate to the shallow trench isolation structure.

[0023] In some optional examples, after the groove is formed, the sidewall of the remaining bit line material layer is in a gradually decreasing slope in the horizontal direction from the first region of the substrate to the shallow trench isolation structure.

[0024] In some optional examples, the step of forming the groove further includes:

[0025] The etch stop layer is removed.

[0026] In some optional examples, a distance between an upper surface and a bottom surface of the second capping layer located on the first region of the substrate is smaller than a distance between an upper surface and a bottom surface of the second capping layer located on the shallow trench isolation structure.

[0027] In some optional examples, a distance between an upper surface and a bottom surface of the second capping layer located on the shallow trench isolation structure is greater than a distance between an upper surface and a bottom surface of the second capping layer located on the gate structure in the second region of the substrate.

[0028] Compared with the prior art, the technical solution provided by the present invention has at least one of the following beneficial effects:

[0029] In the preparation method of the semiconductor memory provided by the present invention, a bit line material layer including a first cap layer is first formed on the first region of the substrate and the shallow trench isolation structure, a gate structure is formed in the second region of the substrate, and then a part of the first cap layer of the bit line material layer located on the shallow trench isolation structure is removed, so that the top surface of the bit line material layer on the shallow trench isolation structure between the first region and the second region of the substrate is lower than the top surface of the bit line material layer in the first region and the second region (reflected in the form of grooves), and then a second cap layer is conformally formed on the first region and the shallow trench isolation structure with grooves, thereby ensuring that the height of the bit line structure in the first region meets the product design requirements while reducing the height of the bit line structure formed on the shallow trench isolation structure near the edge of the first region, avoiding the bit line structure formed on the shallow trench isolation structure from tipping over, and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the present application and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application but do not constitute a limitation to the present application. In the accompanying drawings:

[0031] Figure 1A schematic flow chart of a method for preparing a semiconductor memory device according to an embodiment of the present invention;

[0032] Figure 2 to Figure 8 A schematic diagram of the structure of a method for preparing a semiconductor memory device provided in one embodiment of the present invention during the preparation process;

[0033] Wherein, the accompanying drawings are marked as follows:

[0034] 100-substrate, 101-shallow trench isolation structure, 11-first region of the substrate, 12-second region of the substrate, 251-gate structure in the second region, 110-word line structure, 120-insulating layer, 130-bit line material layer, 131-semiconductor layer, 132-metal layer, 133-interlayer dielectric layer, 134-first cap layer, 102-groove, 141-sidewall structure, 140-etching stop layer, 150-insulating dielectric layer, 160-photoresist layer, 170-second cap layer.

[0035] In the drawings, the same reference numerals are used for the same components, and the drawings are not drawn to scale. DETAILED DESCRIPTION

[0036] The following is a further detailed description of the method for manufacturing a semiconductor device proposed in the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, so the present invention is not limited to the specific embodiments disclosed below.

[0037] See also Figure 1 , Figure 1 FIG. 1 is a flow chart of a method for preparing a semiconductor memory device provided in this embodiment. Figure 1 As shown, the method for preparing a semiconductor memory provided in this embodiment at least includes the following steps:

[0038] Step S101 , providing a substrate, wherein the substrate includes a first region and a second region.

[0039] Step S102 , forming a shallow trench isolation structure in the substrate, located between the first region and the second region, wherein the shallow trench isolation structure defines the first region and the second region.

[0040] Step S103 , forming a bit line material layer located on the first region of the substrate and the shallow trench isolation structure, wherein the bit line material layer includes a semiconductor layer, a metal layer and a first cap layer in sequence from bottom to top.

[0041] Step S104 , removing a portion of the first capping layer of the bit line material layer on the shallow trench isolation structure to form a groove.

[0042] Step S105 , forming a second capping layer on the remaining bit line material layer.

[0043] In order to enable a person skilled in the art to which the present invention relates to easily understand the method for preparing a semiconductor device in an embodiment of the present invention, the method for preparing a semiconductor device proposed in the present invention will be further described below in conjunction with various structural schematic diagrams of the method during the preparation process.

[0044] Figure 2 to Figure 8 The present invention is a schematic structural diagram of a method for manufacturing a semiconductor memory device during the manufacturing process.

[0045] See also Figure 2 , perform the above steps S101 to S102, provide a substrate 100, the substrate 100 includes a plurality of shallow trench isolation structures 101 arranged in sequence, wherein one of the shallow trench isolation structures 101 has a larger width than the other shallow trench isolation structures 101 and is located on one side of all the other shallow trench isolation structures, the shallow trench isolation structure 101 defines the substrate 100 into a first area 11 and a second area 12, the first area 11 of the substrate 100 includes a plurality of word line structures 110, and an insulating layer 120 is formed on the entire surface of the first area 11 and the second area 12 of the substrate 100. In one embodiment, the substrate 100 is any suitable substrate material known in the art, for example, it can be a silicon substrate, a silicon-containing substrate, a silicon-on-insulator substrate, or a substrate composed of other suitable materials, etc., but is not limited thereto. The shallow trench isolation structure 101 may include a single layer or multiple layers of dielectric materials. Applicable dielectric materials may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, nitrogen-doped silicon carbide, low dielectric constant dielectric materials such as fluorinated silicon glass, carbon silicon oxide, spin-on silicon glass, porous low dielectric constant dielectric materials, or a combination of the above materials, but not limited thereto. Exemplarily, the shallow trench isolation structure 101 is in the shape of a long strip. The substrate 100 also includes a plurality of word line structures 110, and the word line structure 110 may include a gate dielectric layer, a work function layer, a conductive layer, and a cap layer, but not limited thereto. The material of the insulating layer 120 may be an oxide or a nitride, but not limited thereto.

[0046] Continue reading Figure 2Then, the above step S103 is performed to form a bit line material layer 130 on the first region 11 of the substrate 100, a portion of the shallow trench isolation structure 101, and the insulating layer 120 of the second region 12 by using a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. In one embodiment, the bit line material layer 130 is a multi-layer material structure, such as the bit line material layer 130 includes a semiconductor layer 131, a barrier layer 132, a metal layer 133, and a first cap layer 134 from bottom to top. The material of the semiconductor layer 131 may include single crystal silicon (crystalline silicon), polycrystalline silicon (polysilicon), amorphous silicon (amorphous silicon), doped silicon (doped silicon), silicon germanium (SiGe), or other suitable semiconductor materials, but is not limited thereto. The material of the barrier layer 132 may include metal, metal silicide or metal nitride, such as titanium (Ti), titanium nitride (TiN), tungsten silicide (WSi), cobalt silicide (CoSi), tungsten nitride (WN), but not limited thereto. The material of the metal layer 133 may include tungsten (W), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or compounds, alloys, and / or composite layers of the aforementioned metal materials, but not limited thereto. The first cap layer 134 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. Preferably, the material of the semiconductor layer 131 in the embodiment of the present invention is polysilicon, the material of the barrier layer 132 is titanium nitride (TiN), the material of the metal layer 133 is tungsten (W), and the material of the first cap layer 134 is silicon nitride (SiN).

[0047] It should be understood that the process of performing the above step S103 also includes etching and removing a portion of the bit line material layer 130 on the second region 12 of the substrate 100 by at least one of a dry etching process or a wet etching process, so as to form at least one discrete gate structure 251 in the second region 12. Subsequently, a sidewall structure 141 is formed on the sidewall of the gate structure 251 and on the sidewall of the bit line material layer 130 located on the shallow trench isolation structure 101. The sidewall structure 141 may include a dielectric material, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but is not limited thereto.

[0048] See also Figure 3, following the above step S103, the above deposition process can be used to conformally form an etching stop layer 140 and an insulating dielectric layer 150 on the first area 11 of the substrate 100 and the bit line material layer 130 on the shallow trench isolation structure 101 and the gate structure 251 in the second area 12 of the substrate 100, and then etching or chemical mechanical polishing processes are used to allow the insulating dielectric layer 150 to be located only on the shallow trench isolation structure 101 and the second area 12 of the substrate 100. Specifically, the insulating dielectric layer 150 is located on the etching stop layer 140 on the shallow trench isolation structure 101, and the gate structure 251 in the second area 12 of the substrate 100 is buried. In one embodiment, the materials of the etch stop layer 140 and the insulating dielectric layer 150 may include dielectric materials, such as silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), or a combination of the above materials, but not limited thereto. Preferably, the material of the etch stop layer 140 is silicon carbide nitride (SiCN), and the material of the insulating dielectric layer 150 is silicon nitride (SiN).

[0049] Afterwards, a photoresist layer 160 is formed on the first area 11 of the substrate 100 and a portion of the shallow trench isolation structure 101 and on the gate structure 251 of the second area 12 of the substrate 100, that is, the photoresist layer 160 has an opening, the bottom of the opening exposes a portion of the etching stop layer 140 and the insulating dielectric layer 150 on the shallow trench isolation structure 101.

[0050] See also Figure 4 and Figure 5 In the above step S104, at least one etching process of dry etching or wet etching can be used, and the photoresist layer 160 can be used as a mask to etch away the etching stop layer 140 and part of the first cap layer 134 of the bit line material layer 130 on the shallow trench isolation structure 101 along the opening of the photoresist layer 160 to form a groove 102. Since the inventive concept of the present invention is to make the top surface of the bit line material layer 130 on the shallow trench isolation structure 101 between the first area 11 and the second area 12 of the substrate 100 lower than the top surface of the bit line material layer 130 in the first area 11 and the second area 12, when the groove 102 is formed by etching in step S104, it can remove part of the height of the first cap layer 134 along the opening, and of course, it can also remove all of the first cap layer 134 along the opening.

[0051] As a preferred example, Figure 4As shown, the etching barrier layer 140 not covered by the photoresist layer 160 (i.e., the opening) and all of the first capping layer 134 on the shallow trench isolation structure 101 can be removed to form a groove 102 whose bottom exposes the metal layer 133 below the first capping layer 134 on the shallow trench isolation structure 101.

[0052] As another preferred example, Figure 5 As shown, the etching stop layer 140 not covered by the photoresist layer 160 (i.e., the opening) and a portion of the first capping layer 134 on the shallow trench isolation structure 101 can be removed to form a groove 102 whose bottom exposes the remaining first capping layer 134 located on the shallow trench isolation structure 101, and the upper surface profile of the exposed remaining first capping layer 134 is an arc shape that is concave toward the surface of the substrate 100, and the arc shape that is concave toward the surface of the substrate 100 includes a gradually decreasing slope in the horizontal direction from the first area 11 of the substrate 100 to the shallow trench isolation structure 101.

[0053] It should be understood that, since the photoresist layer 160 is also simultaneously formed in the second region 12 of the substrate 100 during the etching process of forming the groove 102 in step S104 of the embodiment of the present invention, the etching process of this step S104 will not cause loss in the height of the gate structure 251 in the second region 12.

[0054] See also Figure 6 or Figure 7 In the above step S104, a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. can be used to form the Figure 4 or Figure 5A second capping layer 170 is formed conformally on the substrate 100 with the groove 102 shown, wherein the material of the second capping layer 170 is the same as the material of the first capping layer 134 in the bit line material layer 130, for example, the material of the second capping layer 170 may be silicon nitride (SiN). Since the bit line material layer 130 on the shallow trench isolation structure 101 in the embodiment of the present invention has the groove 102, when the second capping layer 170 is conformally formed by a deposition process, the distance between the upper surface and the bottom surface of the second capping layer 170 located on the first area 11 of the substrate 100 is smaller than the distance between the upper surface and the bottom surface of the second capping layer 170 located on the shallow trench isolation structure 101, and the distance between the upper surface and the bottom surface of the second capping layer 170 located on the shallow trench isolation structure 101 is greater than the distance between the gate electrode 134 located in the second area 12 of the substrate 100. The distance between the upper surface and the bottom surface of the second capping layer 170 on the structure 251 makes the top surface of the bit line structure located in the first area 11 of the substrate 100 and composed of the second capping layer 170, the first capping layer 134, the metal layer 133, the barrier layer 132 and the semiconductor layer 131 higher than the top surface of the bit line structure composed of the second capping layer 170, the first capping layer 134 (this film layer may not be present), the metal layer 133, the barrier layer 132 and the semiconductor layer 131 on the shallow trench isolation structure 101 located near the first area 11 of the substrate 100, thereby achieving the purpose of the invention.

[0055] It should be understood that after executing the above step S104 to form the groove 102 and before executing the above step S105 to form the second cover layer 170, the embodiment of the present invention may also include the step of removing the photoresist layer 160 and the etching stop layer 140 located below the photoresist layer 160 in the first area 11 and the second area 12 of the substrate 100, but is not limited to this.

[0056] It should be understood that Figure 2 to Figure 7 In the illustrated embodiment, the top surface of the bit line material layer 130 located in the first region 11 of the substrate 100 is flush with the top surface of the gate structure 251 located in the second region 12 of the substrate 100. In other embodiments, those skilled in the art should easily understand that before forming the bit line material layer 130 on the first region 11 of the substrate 100, part of the shallow trench isolation structure 101 and the insulating layer 120 of the second region 12 by a deposition process in the above step S103, an ONO stacked structure composed of an oxide layer, a nitride layer and an oxide layer may be formed on the first region 11 of the substrate 100 and part of the shallow trench isolation structure 101, and a single-layer material structure, such as silicon oxide, may be formed on the second region 12 of the substrate 100. Figure 8As shown, under this setting, the height of the ONO stacked structure is greater than that of the single-layer material structure, so that the top surface of the bit line material layer 130 formed on the first region 11 of the substrate 100 and the shallow trench isolation structure 101 is higher than the top surface of the gate structure 251 (formed by etching the bit line material layer) in the second region 12 of the substrate 100, that is, the height is as shown in FIG. Figure 8 In the subsequent process, due to the height difference D1, the etching stop layer 140 located on the first area 11 will be etched away, while the etching stop layer 140 located in the second area 12 will remain, as shown in FIG. Figure 6 shown.

[0057] Afterwards, the above steps S104 to S105 can be performed based on the bit line material layer 130 and the gate structure 251 having the height difference D1, that is, the etching stop layer 140, the insulating dielectric layer 150, the photoresist layer 160 are formed, at least a portion of the first cap layer 134 is etched to form the groove 102, and the second cap layer 170 is formed. The details are as described above. Figure 3 to Figure 7 Corresponding to the above description, the present invention will not be repeated here.

[0058] It should be understood that the "conformal" formation in this article refers to the shape along the surface of the film layer, such as "conformal" covering means that one film layer is attached along the shape of the surface of another film layer, and the surface shapes of the two film layers are consistent.

[0059] To summarize, in the method for preparing a semiconductor memory provided by the present invention, a bit line material layer including a first cap layer is first formed on the first region of the substrate and the shallow trench isolation structure, a gate structure is formed in the second region of the substrate, and then a portion of the first cap layer of the bit line material layer located on the shallow trench isolation structure is removed, so that the top surface of the bit line material layer on the shallow trench isolation structure between the first region and the second region of the substrate is lower than the top surface of the bit line material layer in the first region and the second region (reflected in the form of a groove), and then a second cap layer is formed conformally on the first region and the shallow trench isolation structure with the groove, thereby ensuring that the height of the bit line structure in the first region meets the product design requirements while reducing the height of the bit line structure formed on the shallow trench isolation structure near the edge of the first region, thereby avoiding the tipping of the bit line structure on the shallow trench isolation structure, that is, improving the performance of the semiconductor device.

[0060] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor memory, characterized in that: include: providing a substrate comprising a first region and a second region; forming a shallow trench isolation structure in the substrate, located between the first region and the second region, the shallow trench isolation structure defining the first region and the second region; Forming a bit line material layer located on the first region of the substrate and the shallow trench isolation structure, the bit line material layer sequentially comprising a semiconductor layer, a metal layer and a first cap layer from bottom to top; removing a portion of the first cap layer of the bit line material layer located on the shallow trench isolation structure to form a groove; A second capping layer is formed on the remaining bit line material layer.

2. The method for preparing a semiconductor memory according to claim 1, wherein: The forming of the bit line material layer further comprises forming the bit line material layer in the second region of the substrate to form a gate structure.

3. The method for preparing a semiconductor memory according to claim 2, wherein: After forming the gate structure on the second region of the substrate, the method further comprises: An etch stop layer is formed on the first region of the substrate and the bit line material layer on the shallow trench isolation structure and on the gate structure in the second region of the substrate.

4. The method for preparing a semiconductor memory according to claim 3, wherein: After forming the etching stop layer, the method further comprises: An insulating dielectric layer is formed on the second region of the substrate and the etching stop layer on the shallow trench isolation structure, and a portion of the insulating dielectric layer in the second region of the substrate buries the gate structure.

5. The method for preparing a semiconductor memory according to claim 4, wherein: After forming the insulating dielectric layer, the method further comprises: A photoresist layer is formed on the first region and a portion of the shallow trench isolation structure and on the gate structure in the second region of the substrate.

6. The method for preparing a semiconductor memory according to claim 5, wherein: The steps of forming the groove include: All the first capping layer on the shallow trench isolation structure that is not covered by the photoresist layer is removed to form a groove with a bottom exposing the metal layer below the first capping layer on the shallow trench isolation structure.

7. The method for preparing a semiconductor memory according to claim 5, wherein: The steps of forming the groove include: A portion of the first cover layer on the shallow trench isolation structure that is not covered by the photoresist layer is removed to form a groove with the bottom exposing the remaining first cover layer on the shallow trench isolation structure, and the upper surface profile of the exposed remaining first cover layer is an arc shape that is concave toward the substrate surface.

8. The method for preparing a semiconductor memory according to claim 6, wherein: After the groove is formed, the sidewall of the remaining bit line material layer is in a step-like shape in a horizontal direction from the first region of the substrate to the shallow trench isolation structure.

9. The method for preparing a semiconductor memory according to claim 7, wherein: After the groove is formed, the sidewall of the remaining bit line material layer is in a gradually decreasing slope in the horizontal direction from the first region of the substrate to the shallow trench isolation structure.

10. The method for preparing a semiconductor memory according to claim 4 or 5, characterized in that: The step of forming the groove further includes: The etch stop layer is removed.

11. The method for preparing a semiconductor memory according to claim 8 or 9, characterized in that: A distance between an upper surface and a bottom surface of the second capping layer located on the first region of the substrate is smaller than a distance between an upper surface and a bottom surface of the second capping layer located on the shallow trench isolation structure.

12. The method for preparing a semiconductor memory according to claim 8 or 9, characterized in that: A distance between an upper surface and a bottom surface of the second capping layer located on the shallow trench isolation structure is greater than a distance between an upper surface and a bottom surface of the second capping layer located on the gate structure in the second region of the substrate.

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