Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel is provided with an opening area, an isolation area and a display area. The isolation region is arranged around the opening region, and the isolation region comprises a first gate layer and an isolation column; the isolation column is arranged on one side, far away from the substrate, of the first gate layer; the first gate layer comprises a first gate electrode, and the first gate electrode is electrically connected with a cathode voltage. The first gate electrode below the isolation column is negatively charged, and hole black spots caused by electrochemical corrosion are avoided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) display technology does not require a backlight, but uses a very thin organic material coating and a glass substrate (or flexible organic substrate). When current passes through, these organic materials will emit light. OLED screens have the advantages of high contrast, wide viewing angle, and low power consumption, and are currently widely used in mobile electronic products, such as mobile phones. Summary of the invention

[0003] The purpose of the embodiments of the present invention is to provide a display panel and a display device to improve the problem of hole black spots on the display panel. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a display panel having an opening area, an isolation area and a display area; the isolation area is arranged around the opening area, and the isolation area includes: a first gate layer, an isolation column;

[0005] The isolation column is arranged on a side of the first gate layer away from the substrate;

[0006] The first gate layer includes a first gate electrode, and the first gate electrode of the isolation region is electrically connected to a cathode voltage.

[0007] In a possible implementation, the isolation region further includes: a touch film layer, which is disposed on a side of the isolation column away from the substrate; the touch film layer includes a plurality of touch lines, and the touch lines in the isolation region are electrically connected to a cathode voltage.

[0008] In a possible implementation, the display area includes:

[0009] A first gate insulating layer, a first source-drain electrode, a first flat layer, a second source-drain electrode, a second flat layer, a third source-drain electrode, a third flat layer, and a first gate electrode; the first gate insulating layer is arranged on a side of the first gate layer away from the substrate; the first source-drain electrode is arranged on a side of the first gate insulating layer away from the substrate; the first flat layer is arranged on a side of the first source-drain electrode away from the substrate; the second source-drain electrode is arranged on a side of the first flat layer away from the substrate; the second flat layer is arranged on a side of the second source-drain electrode away from the substrate; the third source-drain electrode is arranged on a side of the second flat layer away from the substrate; the third flat layer is arranged on a side of the third source-drain electrode away from the substrate;

[0010] At least one third source-drain electrode is electrically connected to at least one second source-drain electrode, the at least one second source-drain electrode is electrically connected to at least one first source-drain electrode, and the at least one third source-drain electrode is electrically connected to a cathode voltage; the at least one first source-drain electrode is electrically connected to at least one first gate electrode in the display area, and the at least one first gate electrode is electrically connected to the first gate electrode in the isolation area.

[0011] In a possible implementation, the target third source-drain electrode is electrically connected to the cathode voltage, the target second source-drain electrode is electrically connected to the target third source-drain electrode through a via, the target first source-drain electrode is electrically connected to the target second source-drain electrode through a via, the target first gate electrode is electrically connected to the target first source-drain electrode through a via, and the target first gate electrode is connected to the first gate electrode of the isolation region;

[0012] Among them, the target third source-drain electrode is the third source-drain electrode closest to the isolation region in the display area; the target second source-drain electrode is the second source-drain electrode closest to the isolation region in the display area; the target first source-drain electrode is the first source-drain electrode closest to the isolation region in the display area; the target first gate electrode is the first gate electrode closest to the isolation region in the display area, or the target first gate electrode and the first gate electrode of the isolation region are the same electrode.

[0013] In a possible implementation, the display area further includes: an on-board negative power supply wiring, the on-board negative power supply wiring is electrically connected to the cathode voltage, and the on-board negative power supply wiring is also electrically connected to the at least one third source-drain electrode.

[0014] In a possible implementation manner, the display panel further includes a first power negative electrode wiring, and the touch film layer in the isolation area includes a first touch line, a touch insulating layer, and a second touch line;

[0015] The touch insulating layer is arranged on a side of the first touch line away from the substrate; the second touch line is arranged on a side of the touch insulating layer away from the substrate; the first touch line is electrically connected to the second touch line through a via;

[0016] The first negative power line is arranged in the frame of the display panel, one end of the first negative power line is electrically connected to at least one second touch line, and the other end of the first negative power line is connected to the negative power pin in the logic board.

[0017] In a possible implementation manner, the first gate electrode in the isolation region is a ring structure; and the centers of the multiple first gate electrodes in the isolation region are the same.

[0018] In a possible implementation manner, the first gate electrodes in the isolation region are connected in parallel.

[0019] In a possible embodiment, the second touch line is a mesh wiring, and the second touch line passes through the isolation area and the display area, and is led out from a side of the display area close to the opening area to be connected to the first end of the first negative power line in the display panel frame; the first negative power line is arranged along the frame of the display panel for half a circle, and the other end thereof is connected to the negative power pin in the logic board.

[0020] In a second aspect, an embodiment of the present application provides a display device, which includes a display panel as described in any one of the present application.

[0021] The display panel provided in the embodiment of the present application has an opening area, an isolation area and a display area; the isolation area is arranged around the opening area, and the isolation area includes: a first gate layer and an isolation column; the isolation column is arranged on a side of the first gate layer away from the substrate; the first gate layer includes a first gate electrode, and the first gate electrode is connected to a cathode voltage. The first gate electrode below the isolation column is negatively charged to avoid electrochemical corrosion to produce hole black spots.

[0022] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0024] Figure 1 It is a schematic diagram of the conductive structure of the isolation column;

[0025] Figure 2 It is a schematic diagram of the existing isolation column structure and charge distribution;

[0026] Figure 3 It is a schematic diagram of the electric field of the equivalent model of the existing isolation column;

[0027] Figure 4a A first schematic diagram of a display panel provided in an embodiment of the present application;

[0028] Figure 4b A second schematic diagram of a display panel provided in an embodiment of the present application;

[0029] Figure 4c A third schematic diagram of a display panel provided in an embodiment of the present application;

[0030] Figure 4d A fourth schematic diagram of a display panel provided in an embodiment of the present application;

[0031] Figure 5 Design a top view of the TMA / TMB ring in the opening area;

[0032] Figure 6 This is the schematic diagram of the winding for connecting TMA & TMB to cathode voltage;

[0033] Figure 7 A schematic diagram of the electric field of an equivalent model of an isolation column in a display panel provided in this application;

[0034] Figure 8 This is a schematic diagram of the SIP and Gate1 wiring. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0036] OLED (Organic Light-Emitting Diode) display technology does not require a backlight, but uses a very thin coating of organic materials and a glass substrate (or flexible organic substrate). When current passes through, these organic materials emit light. OLED screens have the advantages of high contrast, wide viewing angle, and low power consumption, and are currently widely used in mobile electronic products, such as mobile phones.

[0037] Screen-to-body ratio refers to the proportion of a device's screen area to its overall front panel area, usually expressed as a percentage. The higher the screen-to-body ratio, the larger the screen takes up on the front of the device, and the smaller the relative bezel or other area that does not display content. For example, if a phone's screen area takes up 85% of the entire front panel, then its screen-to-body ratio is 85%. A high screen-to-body ratio generally results in a more immersive visual experience and makes the device more modern and stylish in appearance. In pursuit of the ultimate screen-to-body ratio, OLED hole-punch screens have gradually become mainstream. OLED hole-punch screens refer to a hole in the operable area of ​​the screen for placing a camera, but if the hole area is not well encapsulated, the electroluminescent layer in the operable area will be exposed to water vapor during the reliability process. In addition, the design of the isolation column cannot completely block electrical conduction, such as Figure 1As shown in the figure, when the panel is powered on, the cathode layer CTD will form a "cathode-isolation column (Al)-cathode" current channel through the aluminum (Al) material part under the isolation column titanium (Ti), and the hole area isolation column will become a negative electrode. The K+ in the polarizer will be transported laterally into the panel under the attraction of negative charges. At the same time, water vapor in the environment will enter the panel along the cutting edge, as shown in the figure. Figure 2 As shown, it is a schematic diagram of the existing isolation column structure and charge distribution. It can be seen that the metal residue above the isolation column and the first gate electrode Gate1 below are positive relative to the cathode layer and carry positive charge, and an electric field is formed above and below the isolation column. Figure 3 The electric field of the isolation column equivalent model is given schematically, TMA / TMB and Gate are 0V, CTD and SD3 are -4V, and then an electrochemical reaction occurs: e-+H2O→OH-+H2↑, K++OH- forms a strong alkaline environment, and the insulating layer is corroded by SiO2+2OH-→SiO3(2-)+H2O, resulting in voids in the insulating layer, which causes package failure and produces black spots.

[0038] In order to improve the problem of black spots on the display panel, firstly, see Figure 4a and Figure 4b The embodiment of the present application provides a display panel, comprising an opening area 101, an isolation area 102 and a display area 103; the isolation area 102 is arranged around the opening area 101, and the isolation area 102 includes:

[0039] First gate layer 01, isolation column 02;

[0040] The isolation column 02 is arranged on a side of the first gate layer 01 away from the substrate PI;

[0041] The first gate layer 01 includes a first gate electrode Gate1 , and the first gate electrode Gate1 in the isolation region is electrically connected to a cathode voltage.

[0042] The opening area 101 is used to place the camera, which is generally a circular area. The Cutting Line refers to the cutting line cut out for placing the camera. The display area 103 generally refers to the AA (Active Area). The first gate electrode Gate1 of the isolation area is electrically connected to the cathode voltage to achieve negative charge. The number of isolation columns in the isolation area can be multiple.

[0043] The display panel provided in the embodiment of the present application has an opening area, an isolation area and a display area; the isolation area is arranged around the opening area, and the isolation area includes: a first gate layer and an isolation column; the isolation column is arranged on a side of the first gate layer away from the substrate; the first gate layer includes a first gate electrode, and the first gate electrode of the isolation area is electrically connected to a cathode voltage. The first gate electrode under the isolation column is negatively charged, reducing or avoiding electrochemical corrosion to produce hole black spots.

[0044] In some embodiments, see Figure 4a and Figure 4b The isolation region 102 further includes: a touch film layer 03, which is arranged on a side of the isolation column 02 away from the substrate PI; the touch film layer 03 includes a plurality of touch lines, and the touch lines in the isolation region are electrically connected to the cathode voltage.

[0045] The touch film layer 03 may include a first touch line (Thin Metal Array, TMA) and a second touch line (Thin Metal Bus, TMB). The first touch line TMA and / or the second touch line TMB are electrically connected to a cathode voltage to be negatively charged.

[0046] In some embodiments, see Figure 4a and Figure 4b , the display area 103 includes:

[0047] A first gate insulating layer (Gate Insulator1, GI1), a first source and drain electrode (Source & Drain1, SD1), a first planarization layer (Planarization1, PLN1), a second source and drain electrode (Source & Drain2, SD2), a second planarization layer PLN2 (Planarization2, PLN2), a third source and drain electrode (Source & Drain3, SD3), a third planarization layer (Planarization3, PLN3), and a first gate electrode Gate1;

[0048] The first gate insulating layer is arranged on a side of the first gate layer away from the substrate;

[0049] The first source-drain electrode is arranged on a side of the first gate insulating layer away from the substrate; the first planar layer is arranged on a side of the first source-drain electrode away from the substrate;

[0050] The second source-drain electrode is arranged on a side of the first flat layer away from the substrate; the second flat layer is arranged on a side of the second source-drain electrode away from the substrate; the third source-drain electrode is arranged on a side of the second flat layer away from the substrate; the third flat layer is arranged on a side of the third source-drain electrode away from the substrate;

[0051] At least one third source-drain electrode is electrically connected to at least one second source-drain electrode, the at least one second source-drain electrode is electrically connected to at least one first source-drain electrode, and the at least one third source-drain electrode is electrically connected to a cathode voltage; the at least one first source-drain electrode is electrically connected to at least one first gate electrode in the display area, and the at least one first gate electrode is electrically connected to the first gate electrode in the isolation area.

[0052] See also Figure 4d , is a schematic diagram of a display panel provided in an embodiment of the present application. The third source-drain electrode in the display area far away from the isolation area is first electrically connected to the third source-drain electrode close to the isolation area, and then the two third source-drain electrodes are electrically connected to a second source-drain electrode, and the second source-drain electrode is electrically connected to a first source-drain electrode, and the first source-drain electrode is electrically connected to the first gate electrode in the display area. Since the first gate electrode in the display area is to participate in the pixel display, the first gate electrode in the display area cannot be arbitrarily negatively charged; in order to reduce the impact on the normal display of the pixel, the first source-drain electrode can be electrically connected to the first gate electrode in the display area that is closest to the isolation area; then, the first gate electrode in the display area is directly connected to the first gate electrode in the isolation area laterally, so that the first gate electrode in the isolation area is negatively charged.

[0053] In some embodiments, the display area further includes: an on-board negative power supply wiring, the on-board negative power supply wiring is electrically connected to the cathode voltage, and the on-board negative power supply wiring is also electrically connected to the at least one third source-drain electrode.

[0054] The negative power supply trace on the board (SIP, ELVSS In Panel) is electrically connected to the cathode voltage at one end and electrically connected to at least one third source-drain electrode at the other end, so that at least one third source-drain electrode is negatively charged. The at least one third source-drain electrode is electrically connected to at least one second source-drain electrode, the at least one second source-drain electrode is electrically connected to at least one first source-drain electrode, the at least one first source-drain electrode is electrically connected to at least one first gate electrode in the display area, and the at least one first gate electrode in the display area is electrically connected to the first gate electrode in the isolation area, so that the first gate electrode in the isolation area is also negatively charged.

[0055] In some embodiments, the target third source-drain electrode is electrically connected to the cathode voltage, the target second source-drain electrode is electrically connected to the target third source-drain electrode through a via hole, the target first source-drain electrode is electrically connected to the target second source-drain electrode through a via hole, the target first gate electrode is electrically connected to the target first source-drain electrode through a via hole, and the target first gate electrode is connected to the first gate electrode of the isolation region;

[0056] Among them, the target third source-drain electrode is the third source-drain electrode closest to the isolation region in the display area; the target second source-drain electrode is the second source-drain electrode closest to the isolation region in the display area; the target first source-drain electrode is the first source-drain electrode closest to the isolation region in the display area; the target first gate electrode is the first gate electrode closest to the isolation region in the display area, or the target first gate electrode and the first gate electrode of the isolation region are the same electrode.

[0057] Since the first gate electrode in the display area is to participate in the pixel display, the first gate electrode in the display area cannot be arbitrarily charged negatively; in order to reduce the impact on the normal display of the pixel, the target first source-drain electrode can be electrically connected to the target first gate electrode; the target first gate electrode is not responsible for the pixel display, and can be the first gate electrode closest to the isolation area in the display area, or the target first gate electrode and the first gate electrode in the isolation area are the same electrode. When the target first gate electrode is the first gate electrode closest to the isolation area in the display area, the target first gate electrode can be directly connected to the first gate electrode in the isolation area horizontally to realize the first gate electrode in the isolation area to be negatively charged; when the target first gate electrode and the first gate electrode in the isolation area are the same electrode, after the target first source-drain electrode is electrically connected to the target first gate electrode, the first gate electrode in the isolation area can be directly charged negatively. In this way, the pixel display in the display area will not be affected, and there is no need to add an additional wiring layer, so that the connection between the first gate electrode in the display area and the first gate electrode in the isolation area is realized.

[0058] Since the target first gate electrode is the first gate electrode closest to the isolation region in the display area, or the target first gate electrode and the first gate electrode in the isolation region are the same electrode, the target first source-drain electrode electrically connected thereto is also the first source-drain electrode closest to the isolation region in the display area; the target second source-drain electrode electrically connected to the target first source-drain electrode is also the second source-drain electrode closest to the isolation region in the display area; and the target third source-drain electrode electrically connected to the target second source-drain electrode is also the third source-drain electrode closest to the isolation region in the display area.

[0059] In the embodiment of the present application, the first gate layer includes at least one first gate electrode, and the first source-drain electrode, the second source-drain electrode, and the third source-drain electrode may be multiple. In the embodiment of the present application, at the junction of the display area and the isolation area, that is, the edge of the inner isolation column (the isolation column farthest from the opening area), the target third source-drain electrode is electrically connected to the target second source-drain electrode, the target second source-drain electrode is electrically connected to the target first source-drain electrode, and the target first source-drain electrode is electrically connected to the target first gate electrode by punching; the target first gate electrode may be the first gate electrode connected to the first gate electrode of the isolation area, or the first gate electrode closest to the first gate electrode of the isolation area.

[0060] See also Figure 4c , is a schematic diagram of a display panel provided in an embodiment of the present application. A third source-drain electrode in the display area that is not the closest to the isolation area is electrically connected to a second source-drain electrode in the display area that is not the closest to the isolation area through a via hole, and the second source-drain electrode is electrically connected to a first source-drain electrode in the display area that is not the closest to the isolation area through a via hole. The first source-drain electrode is then electrically connected to the first gate electrode 011 in the display area that is not responsible for pixel display. Since the third source-drain electrode, the second source-drain electrode, and the first source-drain electrode that are electrically connected are not the closest to the isolation area, the first gate electrode 011 that is not responsible for pixel display to which the first source-drain electrode is finally connected is not the closest to the isolation area, and there is a first gate electrode responsible for pixel display between the first gate electrode 011 that is not responsible for pixel display and the first gate electrode in the isolation area.

[0061] In order to electrically connect the first gate electrode 011 in the display area with the first gate electrode 013 in the isolation area, the simplest method is to horizontally connect the first gate electrode 011 to the first gate electrode 013 in the isolation area, but this will connect to the first gate electrode 012 used for pixel display in the display area, and the first gate electrode used for pixel display will also be negatively charged, affecting the normal display of the pixel. In order not to affect the normal display of the pixel, only a wiring layer can be added under the first gate electrode to electrically connect the first gate electrode 011 to the first gate electrode 013 through the wiring layer; but doing so will increase the cost and increase the thickness of the screen.

[0062] In some embodiments, a second gate layer is further prepared on the first gate insulating layer GI1, including a second gate electrode Gate2, the number of the second gate electrodes may also be multiple, and a second gate insulating layer (GateInsulator2, GI2) is further prepared on the second gate layer.

[0063] An inorganic insulating layer is also included between the first gate insulating layer and the first source-drain electrode. Through an etching process, a hole can be punched in the layer between the target first gate electrode and the first source-drain electrode so that the target first gate electrode and the first source-drain electrode can be electrically connected through the via. Etching, in English, is an important step in the semiconductor manufacturing process and the microelectronic IC manufacturing process and the micro-nano manufacturing process. Etching is actually photolithography corrosion. The photoresist is first exposed by photolithography, and then the corrosion treatment is carried out by other methods to remove the required part. With the development of micro-manufacturing technology, etching is a general term for stripping and removing materials by solution, reactive ions or other mechanical methods.

[0064] A first organic insulating layer is also included between the first flat layer and the second source-drain electrode. When the first organic insulating layer HPLN1 is exposed and developed, the target first source-drain electrode is punched to overlap the target second source-drain electrode. Among them, exposure and development are steps in the preparation process, which are mainly used to transfer the photolithography pattern to the photoresist. Exposure is to irradiate the light source (such as ultraviolet light) through a mask onto the photoresist to change its chemical properties, and then the developer removes the unexposed or exposed parts to form a pattern.

[0065] A second organic insulating layer is also included between the second planar layer and the third source-drain electrode. When the second organic insulating layer HPLN2 is exposed and developed, the target second source-drain electrode is punched to overlap the target third source-drain electrode.

[0066] In an embodiment of the present application, the display area of ​​the display panel includes a first gate insulating layer, a first source-drain electrode, a first flat layer, a second source-drain electrode, a second flat layer, a third source-drain electrode, a third flat layer, and a first gate electrode. The first gate electrode is connected to the third source-drain electrode through the first source-drain electrode and the second source-drain electrode, and the third source-drain electrode is connected to the cathode voltage, so that the first gate electrode in the isolation area is negatively charged.

[0067] In some embodiments, see Figure 4a and Figure 4b , the display area 103 further includes:

[0068] Cathode layer (CTD), electroluminescent layer (EL), first insulating layer (Chemical Vapor Deposition 1, CVD1), organic layer (Ink Jet Printing, IJP), second insulating layer (Chemical Vapor Deposition 2, CVD2);

[0069] The cathode layer is arranged on a side of the third flat layer away from the substrate; the electroluminescent layer is arranged on a side of the cathode layer away from the substrate; the first insulating layer is arranged on a side of the electroluminescent layer away from the substrate; the organic layer is arranged on a side of the first insulating layer away from the substrate; the second insulating layer is arranged on a side of the organic layer away from the substrate; wherein the organic layer is generated by an inkjet printing process.

[0070] The target third source-drain electrode is connected to the cathode voltage terminal in the frame of the display panel through a wiring. Specifically, it may include: the target third source-drain electrode is electrically connected to the negative power wiring on the board, and the negative power wiring on the board is electrically connected to the cathode voltage.

[0071] The cathode layer and the electroluminescent layer extend from the display area to the isolation area, the first insulating layer extends from the display area to the isolation area, the organic layer exists in the display area and part of the isolation area, and the second insulating layer extends from the display area to the isolation area.

[0072] In an embodiment of the present application, the display area of ​​the display panel also includes a cathode layer, an electroluminescent layer, a first insulating layer, an organic layer, and a second insulating layer from bottom to top, and the target third source and drain electrode is connected to the cathode voltage terminal, thereby ensuring that the target third source and drain electrode is negatively charged.

[0073] In some embodiments, see Figure 4a and Figure 4b , the isolation area 102 further includes:

[0074] A barrier and buffer layer Barrier+Buffer, arranged between the substrate and the first gate layer;

[0075] An inter-layer dielectric and a protection layer (ILD+PVX) are arranged on a side of the first gate layer away from the substrate.

[0076] In some embodiments, a first gate insulating layer GI1 is further prepared on the first gate layer, and a second gate layer is further prepared on the first gate insulating layer GI1: including a second gate electrode, the first gate insulating layer GI1 is used to insulate the first gate electrode Gate1 from the second gate electrode Gate2, and a second gate insulating layer GI2 is further prepared on the second gate layer, and the second gate insulating layer GI2 is used to insulate the second gate electrode Gate2 from others. An interlayer dielectric and a protective layer ILD+PVX are arranged on a side of the second gate insulating layer GI2 away from the substrate.

[0077] A first flat layer PLN1, a second flat layer PLN2, and a third flat layer PLN3.

[0078] The first planar layer is arranged on a side of the interlayer dielectric and the protection layer away from the substrate, the second planar layer is arranged on a side of the first planar layer away from the substrate, and the third planar layer is arranged on a side of the second planar layer away from the substrate.

[0079] A cathode layer and an electroluminescent layer are arranged above the third planar layer, an insulating layer is arranged above the electroluminescent layer, and a dam structure Dam is arranged above the insulating layer.

[0080] The flat layer does not penetrate the entire isolation region. On the side of the flat layer close to the opening region, the isolation column is arranged on the side of the interlayer dielectric and the protective layer away from the substrate, the cathode layer and the electroluminescent layer are arranged on the isolation column, and the insulating layer is arranged on the electroluminescent layer. On the side of the flat layer far from the opening region, the isolation column is arranged on the side of the interlayer dielectric and the protective layer away from the substrate, the cathode layer and the electroluminescent layer are arranged on the isolation column, the first insulating layer is arranged on the electroluminescent layer, the organic layer is arranged on the first insulating layer; and the second insulating layer is arranged on the organic layer.

[0081] In the embodiment of the present application, the isolation area of ​​the display panel also includes a barrier and buffer layer, an interlayer dielectric and a protective layer. The barrier and buffer layer, the interlayer dielectric and the protective layer, like the first gate layer, extend from the isolation area to the display area.

[0082] In some embodiments, the display panel further includes a first power negative electrode wiring, and the touch film layer in the isolation area includes a first touch line TMA, a touch insulating layer (Thermal Laminated Dielectric, TLD) and a second touch line TMB;

[0083] The first touch line is arranged on a side of the second insulating layer away from the substrate;

[0084] The touch insulating layer is arranged on a side of the first touch line away from the substrate;

[0085] The second touch control line is arranged on a side of the touch control insulating layer away from the substrate;

[0086] The first touch line is electrically connected to the second touch line through a via hole;

[0087] The first negative power line is arranged in the frame of the display panel, one end of the first negative power line is electrically connected to at least one second touch line, and the other end of the first negative power line is connected to the negative power pin in the logic board.

[0088] In the embodiment of the present application, the touch film layer includes a first touch line TMA, a touch insulating layer TLD and a second touch line TMB. It can be seen that the touch film layer adopts a double-layer wiring structure.

[0089] The display area also includes touch control lines, which are arranged on the second insulating layer.

[0090] like Figure 5 The figure shows a top view of the hole area TMA & TMB ring design, and the touch film layer is a ring structure. Hole Dam refers to the dam structure Dam in the isolation area, and both the inner and outer sides of the Hole Dam are TMA & TMB rings.

[0091] The first touch line is connected to the second touch line through a via hole; and the second touch line is connected to a cathode voltage.

[0092] A touch insulating layer is also included between the first touch wire and the second touch wire. A hole is punched in the touch insulating layer to allow the first touch wire to be connected to the second touch wire through the hole, thereby realizing parallel connection of the first touch wire and the second touch wire. The second touch wire is connected to the cathode voltage, that is, the first touch wire is connected to the cathode voltage.

[0093] In some embodiments, the second touch line is a mesh line, see Figure 6 , the second touch line passes through the isolation area and the display area, and is led out from the side of the display area close to the opening area to connect to the first end of the first negative power line in the frame of the display panel; the first negative power line is arranged along the frame of the display panel for half a circle, and the other end thereof is connected to the negative power pin VSS pin in the logic board. The logic board is located on the side of the display panel far away from the opening area, and the first negative power line is connected to the negative power pin VSS pin in the logic board through the FPC On COP Bonding process. The second touch line is connected to the VSS pin through the first negative power line to achieve connection with ELVSS, where ELVSS refers to the negative power supply.

[0094] In the embodiment of the present application, the second touch line is led out to the frame of the display panel using a mesh wiring and is connected to the negative electrode of the power supply, so that the second touch line is negatively charged.

[0095] Figure 7 Schematic diagram of the electric field of the equivalent model of the isolation column in the display panel provided by the embodiment of the present application. Among them, the second touch line is led out to the frame of the display panel using a mesh routing and connected to the negative electrode of the power supply, so that the second touch line is negatively charged, so TMA / TMB is -4V, and Gate1 is connected to the cathode voltage upward through the first source-drain electrode, the second source-drain electrode, and the third source-drain electrode, so Gate1 is negatively charged, which is -4V.

[0096] In some embodiments, see Figure 8 The first gate electrode of the isolation region is a ring structure; the centers of the multiple first gate electrodes in the isolation region are the same. In the actual production process, there may be errors in the centers of the multiple first gate electrodes in the isolation region, but as long as the difference does not exceed the preset value. The first gate electrodes in the isolation region are connected in parallel.

[0097] V data refers to the data voltage. One end of the SIP wiring is connected to the cathode voltage ELVSS terminal on the panel, and the other end can be connected to the third source-drain electrode SD3, so that the third source-drain electrode is connected to the cathode voltage terminal in the frame of the display panel through the wiring. The SIP uses the gap of the hole area to punch holes downward at the edge of the inner isolation column to connect the third source-drain electrode SD3, the second source-drain electrode SD2, and the first source-drain electrode SD1, and then connect to the first gate electrode Gate1. When there are multiple first gate electrodes, the multiple first gate electrodes adopt a concentric ring structure and are arranged around the opening area. By connecting the first gate electrodes in parallel, multiple first gate electrodes can be connected to the same voltage.

[0098] The display panel provided in the embodiment of the present application includes: a substrate PI, a barrier layer Barrier, a buffer layer Buffer, a first gate layer, the first gate layer includes a plurality of first gate electrodes Gate1, a first gate insulating layer GI1, a second gate layer, the second gate layer includes a plurality of second gate electrodes Gate2, a second gate insulating layer GI2, an interlayer dielectric layer ILD, and a protective layer PVX.

[0099] The display area may further include an inorganic insulating layer, and a hole may be punched on the target first gate electrode by etching, so that the target first gate electrode overlaps the target first source-drain electrode through the via hole.

[0100] The first source-drain electrode SD1 also includes a first planar layer PLN1, and the first planar layer PLN1 also includes a first organic insulating layer HPLN1. When the first organic insulating layer HPLN1 is exposed and developed, the first source-drain electrode is punched to overlap the second source-drain electrode.

[0101] The second source-drain electrode SD2 also includes a second flat layer PLN2, and a second organic insulating layer is also included between the second flat layer and the third source-drain electrode. When the second organic insulating layer HPLN2 is exposed and developed, the second source-drain electrode is punched to overlap the third source-drain electrode. The third source-drain electrode is connected to the cathode voltage terminal in the frame of the display panel through a wiring.

[0102] The third source-drain electrode SD3 also includes a third flat layer PLN3, and the third flat layer PLN3 also includes a cathode layer CTD above the cathode layer. The cathode layer also includes an electroluminescent layer EL above the cathode layer. The cathode layer CTD and the electroluminescent layer EL extend from the display area to the isolation area. The electroluminescent layer EL also includes a first insulating layer CVD1 above the electroluminescent layer EL, and the first insulating layer CVD1 also includes an organic layer IJP above the first insulating layer CVD1, but the organic layer IJP does not cover the entire isolation area and only exists on the side of the isolation area away from the hole area. The organic layer IJP also includes a second insulating layer CVD2 above the organic layer IJP, and the second insulating layer CVD2 also includes a first touch line TMA above the second insulating layer CVD2.

[0103] In the isolation area, multiple isolation columns are included, and the multiple isolation columns are separated by a flat layer. The isolation columns also include a cathode layer CTD above the isolation column, and the cathode layer CTD also includes an electroluminescent layer EL above the electroluminescent layer EL. The insulating layer also includes an organic layer IJP on the side of the isolation area far from the opening area, and the second insulating layer CVD2 is included above the organic layer IJP, and the touch film layer is also included above the second insulating layer CVD2; on the side of the isolation area close to the opening area, the insulating layer does not include the organic layer IJP, but on the side of the isolation area close to the opening area, the insulating layer still includes a touch film layer. The touch film layer also includes a touch overlay component (TOC). The flat layer used to space the isolation columns includes a first flat layer PLN1, a second flat layer PLN2, and a third flat layer PLN3. The cathode layer CTD is also included above the third flat layer PLN3, and the electroluminescent layer EL is also included above the cathode layer CTD. The insulating layer also includes a dam structure Dam above the insulating layer.

[0104] The display panel provided in the embodiment of the present application can eliminate the electric field near the isolation column in the hole area, avoid electrochemical reactions, prevent the thin film packaging layer TFE in the hole area from being corroded, and has a good packaging effect. The risk of failure in the hole area during the reliability process is reduced; moreover, the process follows the existing technical route, does not increase the number of masks, and the cost is comparable to the existing process.

[0105] The second aspect of the present application provides a display device, which includes the display panel described above, wherein the display device can be any product with a display function, such as a mobile phone, a tablet computer, a television, a laptop computer, a digital photo frame, a navigator, etc.

[0106] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0107] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0108] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: It has an opening area, an isolation area and a display area; the isolation area is arranged around the opening area, and the isolation area includes: a first gate layer and an isolation column; The isolation column is arranged on a side of the first gate layer away from the substrate; The first gate layer includes a first gate electrode, and the first gate electrode of the isolation region is electrically connected to a cathode voltage.

2. The display panel according to claim 1, characterized in that: The isolation region further includes: a touch film layer, which is arranged on a side of the isolation column away from the substrate; the touch film layer includes a plurality of touch lines, and the touch lines in the isolation region are electrically connected to a cathode voltage.

3. The display panel according to claim 1, characterized in that: The display area includes: A first gate insulating layer, a first source-drain electrode, a first flat layer, a second source-drain electrode, a second flat layer, a third source-drain electrode, a third flat layer, and a first gate electrode; the first gate insulating layer is arranged on a side of the first gate layer away from the substrate; the first source-drain electrode is arranged on a side of the first gate insulating layer away from the substrate; the first flat layer is arranged on a side of the first source-drain electrode away from the substrate; the second source-drain electrode is arranged on a side of the first flat layer away from the substrate; the second flat layer is arranged on a side of the second source-drain electrode away from the substrate; the third source-drain electrode is arranged on a side of the second flat layer away from the substrate; the third flat layer is arranged on a side of the third source-drain electrode away from the substrate; At least one third source-drain electrode is electrically connected to at least one second source-drain electrode, the at least one second source-drain electrode is electrically connected to at least one first source-drain electrode, and the at least one third source-drain electrode is electrically connected to a cathode voltage; the at least one first source-drain electrode is electrically connected to at least one first gate electrode in the display area, and the at least one first gate electrode is electrically connected to the first gate electrode in the isolation area.

4. The display panel according to claim 3, characterized in that: The target third source-drain electrode is electrically connected to the cathode voltage, the target second source-drain electrode is electrically connected to the target third source-drain electrode through a via hole, the target first source-drain electrode is electrically connected to the target second source-drain electrode through a via hole, the target first gate electrode is electrically connected to the target first source-drain electrode through a via hole, and the target first gate electrode is connected to the first gate electrode of the isolation region; Among them, the target third source-drain electrode is the third source-drain electrode closest to the isolation region in the display area; the target second source-drain electrode is the second source-drain electrode closest to the isolation region in the display area; the target first source-drain electrode is the first source-drain electrode closest to the isolation region in the display area; the target first gate electrode is the first gate electrode closest to the isolation region in the display area, or the target first gate electrode and the first gate electrode of the isolation region are the same electrode.

5. The display panel according to claim 3, characterized in that: The display area further includes: an on-board negative power supply wiring, the on-board negative power supply wiring is electrically connected to the cathode voltage, and the on-board negative power supply wiring is also electrically connected to the at least one third source-drain electrode.

6. The display panel according to claim 2, characterized in that: The display panel further includes a first power negative electrode wiring, and the touch film layer in the isolation area includes a first touch line, a touch insulating layer, and a second touch line; The touch insulating layer is arranged on a side of the first touch line away from the substrate; the second touch line is arranged on a side of the touch insulating layer away from the substrate; the first touch line is electrically connected to the second touch line through a via; The first negative power line is arranged in the frame of the display panel, one end of the first negative power line is electrically connected to at least one second touch line, and the other end of the first negative power line is connected to the negative power pin in the logic board.

7. The display panel according to claim 1, characterized in that: The first gate electrode in the isolation region is a ring structure; the centers of the multiple first gate electrodes in the isolation region are the same.

8. The display panel according to claim 1, characterized in that: The first gate electrodes of the isolation regions are connected in parallel.

9. The display panel according to claim 6, characterized in that: The second touch line is a mesh line, which passes through the isolation area and the display area, and is led out from a side of the display area close to the opening area to be connected to the first end of the first negative power line in the frame of the display panel; the first negative power line is arranged along half a circle along the frame of the display panel, and the other end thereof is connected to the negative power pin in the logic board.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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