Disk array card super capacitor management method and device, equipment and storage medium

Abstract

The invention relates to a disk array card super capacitor management method and device, equipment and a storage medium, and relates to the technical field of disk arrays. According to the method, intelligent management of the super capacitor of the disk array card is realized through authentication management of the super capacitor of the disk array card, capacitor in-place state monitoring and over-temperature protection management, corresponding strategy switching is carried out on the abnormal state of the super capacitor, a user is notified, and user experience is improved while user data integrity is ensured. Wherein the capacitor authentication solves the problem that the standby power supply of the disk array card is abnormal due to the use of a non-compliant super capacitor; due to in-place monitoring, the problem of standby power data loss caused by abnormal plugging and unplugging of a super capacitor of the disk array card is solved; the temperature monitoring can prevent over-temperature of the super capacitor and prevent over-temperature abnormity of the disk array card or the whole server.

Description

Technical Field

[0001] The present application relates to the field of disk array technology, and in particular to a disk array card supercapacitor management method, device, computer equipment and storage medium. Background Art

[0002] Cache is the core function of disk array (RAID) card products. The disk array card greatly improves the performance of the disk array card by storing write requests in the cache of the array card, and then flushes it to the persistent medium through a series of optimization algorithms. The cache medium uses double-rate synchronous dynamic random access memory (DDR), which is a volatile storage medium. Therefore, when the disk array card loses power, the data that has not been flushed in the cache will be lost, causing inconsistent application data and affecting customer business. In order to deal with the problem of cache data loss caused by power outages, the disk array card is equipped with a backup power supply module to provide power support for the cache after power outages, ensuring that the cache data in DDR is saved to the non-volatile memory (NAND Flash) based on NAND technology. After the server resumes power supply, this part of the cache data will be restored and flushed to the persistent medium. This improves the performance of the disk array card while ensuring user data security.

[0003] The disk array card is a disk array card. Its core is the RAID control chip. Its function is to access the data in blocks by striping the data on the disk, reducing the mechanical seek time of the disk and improving the data access speed; by reading several disks in an array at the same time, the mechanical seek time of the disk is reduced and the data access speed is improved; by mirroring or storing parity information, redundant protection of data is achieved. The backup power module commonly used in early disk array cards is lithium battery. The lithium battery backup power method has a high failure rate, high maintenance cost, and the risk of data loss is still high. Therefore, the latest disk array card currently uses a super capacitor + flash memory (Flash) backup power solution to store the data in DDR into Flash in the event of abnormal power failure, which greatly improves data reliability.

[0004] Disk array cards need to use supercapacitors of specific specifications to ensure their backup power function, that is, the voltage, current and power of the power supply required when the power is off must be adapted to the disk array card. Using an unmatched supercapacitor module may cause the backup power function to fail. Manually unplugging or replacing an unmatched supercapacitor module during server operation will also cause the backup power function to be abnormal. In addition, supercapacitors generally have a service life of about five years. When the supercapacitor is low on power, it will also affect the backup power function. Summary of the invention

[0005] Based on this, a disk array card supercapacitor management method, device, computer equipment and storage medium are provided to solve the current technical problem that the supercapacitor reaches the end of its service life and affects the backup power function due to the lack of authentication management, capacitor in-place status monitoring and over-temperature protection management for the disk array card supercapacitor.

[0006] On the one hand, a disk array card supercapacitor management method is provided, wherein the disk array card is provided with a supercapacitor, the disk array card (RAID card) is connected to a disk array card controller (SOC), and the supercapacitor is connected to a capacitor management chip, and the method comprises:

[0007] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0008] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0009] If the handshake is successful, the supercapacitor is authenticated;

[0010] After the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0011] In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0012] Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have a handshake successfully;

[0013] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0014] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0015] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0016] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0017] In one embodiment, before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0018] When the supercapacitor works normally, the pin level of the capacitor management chip is high; when the supercapacitor exceeds the pre-trial working temperature range, the disk array card controller pulls down the pin level of the capacitor management chip;

[0019] When the super capacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

[0020] In one embodiment, the method further comprises:

[0021] When the supercapacitor of the disk array card is connected normally, configuring the cache strategy of the disk array card to be a write-back (WB) mode, and reporting that the supercapacitor is normal;

[0022] When the supercapacitor is unplugged, configuring the cache strategy of the disk array card to be a write-through (WT) mode, and reporting the supercapacitor abnormality;

[0023] When the super capacitor is inserted into the disk array card, the cache strategy of the disk array card is configured as a write-back (WB) mode, and the super capacitor is reported to be normal.

[0024] In one embodiment, before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0025] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0026] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0027] If the handshake is successful, the supercapacitor is authenticated;

[0028] Wherein, authenticating the supercapacitor includes:

[0029] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0030] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0031] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0032] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0033] In one embodiment, the temperature adjustment of the supercapacitor includes:

[0034] Determining whether the temperature of the supercapacitor is higher than a threshold;

[0035] If it is not higher than the threshold, the supercapacitor is authenticated;

[0036] If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold;

[0037] If it is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor;

[0038] If it is higher than the maximum threshold, the use of the super capacitor is stopped, the cache strategy of the disk array card is configured to be a write-through (WT) mode, and the super capacitor abnormality is reported.

[0039] In one embodiment, the step of determining whether the disk array card controller and the capacitor management chip connected to the super capacitor have successfully handshaked includes:

[0040] Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received;

[0041] If the confirmation message replied by the capacitance management chip is received, it is determined that the handshake is successful;

[0042] If the confirmation information replied by the capacitance management chip is not received, it is determined that the handshake fails.

[0043] In one embodiment, the method further comprises:

[0044] Performing periodic capacitance calibration on the supercapacitor;

[0045] Obtaining the total capacity of the calibrated supercapacitor, and determining whether the total capacity satisfies primary backup power;

[0046] If the total capacity is sufficient to complete one backup power supply, continue to perform periodic capacitance calibration on the supercapacitor;

[0047] If the total capacity is insufficient to complete a backup power supply, the cache strategy of the disk array card is configured as a write-through (WT) mode, and a reminder is given to replace the super capacitor.

[0048] On the other hand, a disk array card supercapacitor management device is provided, the device comprising:

[0049] The disk array card access control module is used to perform handshake with the capacitor management chip when the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, and determine whether the handshake is successful;

[0050] A capacitor abnormality cache strategy control module, configured to configure the cache strategy of the disk array card to a write-back (WB) mode if the handshake fails, and report the super capacitor abnormality;

[0051] A capacitor authentication control module, used to authenticate the supercapacitor if the handshake is successful;

[0052] A capacitor pin level monitoring module, used for the disk array card controller to monitor the pin level of the capacitor management chip after the super capacitor works normally;

[0053] A capacitor pin level pull-down judgment module, used for judging that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card in response to detecting that the pin level of the capacitor management chip is pulled down;

[0054] A capacitor status judgment module is used to judge whether the disk array card controller and the capacitor management chip connected to the super capacitor have successfully handshaked;

[0055] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0056] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0057] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0058] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0059] In another aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0060] After the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0061] In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0062] Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have a handshake successfully;

[0063] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0064] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0065] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0066] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0067] In another aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0068] After the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0069] In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0070] Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have a handshake successfully;

[0071] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0072] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0073] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0074] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0075] The above-mentioned disk array card supercapacitor management method, device, computer equipment and storage medium realize intelligent management of disk array card supercapacitors through three aspects: authentication management of disk array card supercapacitors, capacitor in-place status monitoring and over-temperature protection management. It makes corresponding strategy switching and notifies users for abnormal supercapacitor status, thereby improving user experience while ensuring user data integrity. Among them, capacitor authentication solves the problem of abnormal backup power supply of disk array cards caused by the use of non-compliant supercapacitors; in-place monitoring solves the problem of backup power data loss caused by abnormal insertion and removal of disk array card supercapacitors; temperature monitoring can prevent supercapacitors from overheating, and prevent over-temperature abnormalities from occurring in disk array cards or the entire server. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0077] Figure 1 This is an application environment diagram of a disk array card supercapacitor management method in one embodiment of the present application;

[0078] Figure 2 This is a flow chart of a method for managing supercapacitors of a disk array card in one embodiment of the present application;

[0079] Figure 3 This is a judgment logic diagram of a disk array card supercapacitor management method in one embodiment of the present application;

[0080] Figure 4 The schematic diagram of the change of voltage and current over time during the discharge calibration of the capacitance calibration in the prior art;

[0081] Figure 5 This is a schematic diagram of the change of voltage and current over time when the capacitance calibration is all charging calibration in one embodiment of the present application;

[0082] Figure 6 This is a structural block diagram of a disk array card supercapacitor management device in one embodiment of the present application;

[0083] Figure 7This is a diagram of the internal structure of a computer device in one embodiment of the present application. DETAILED DESCRIPTION

[0084] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0085] The disk array card supercapacitor management method provided in this application can be applied to Figure 1 In the application environment shown in the figure, a hardware link consisting of a disk array card controller (SOC), a capacitor management chip and a super capacitor implements the disk array card super capacitor management. The capacitor management chip integrates EEPROM and temperature monitoring functions.

[0086] In one embodiment, Figure 2 , Figure 3 As shown, a disk array card supercapacitor management method is provided, wherein the disk array card is provided with a supercapacitor, the disk array card (RAID card) is connected to a disk array card controller (SOC), and the supercapacitor is connected to a capacitor management chip. Figure 1 The following steps are used as an example to illustrate the disk array card controller in the system:

[0087] Step S4, after the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0088] Step S5, in response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0089] Step S6, determining whether the disk array card controller and the capacitor management chip connected to the supercapacitor have successfully handshaked;

[0090] Step S7, if the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0091] Step S8: If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the super capacitor is obtained to determine whether the temperature of the super capacitor is normal;

[0092] Step S9, if the temperature of the super capacitor is normal, determine to insert the super capacitor into the disk array card;

[0093] Step S10: If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0094] Among them, RAID, the abbreviation of Redundant Arrays of Independent Disks, is a disk array. RAID card, a disk array card, its core is the RAID control chip, its function is to achieve block access to data by striping the data on the disk, reducing the mechanical seek time of the disk and improving the data access speed; by reading several disks in an array at the same time, the mechanical seek time of the disk is reduced and the data access speed is improved; by mirroring or storing parity information, redundant protection of data is achieved.

[0095] Among them, supercapacitors are electrochemical components that store energy through polarized electrolytes. This energy storage process is reversible, so supercapacitors can be repeatedly charged and discharged hundreds of thousands of times.

[0096] Specifically, the intelligent management of the supercapacitor of the disk array card is achieved through the authentication management of the supercapacitor of the disk array card, the monitoring of the capacitor in-place status, and the management of over-temperature protection. The corresponding strategy switching and notification to the user are made for the abnormal state of the supercapacitor, which improves the user experience while ensuring the integrity of the user data. Among them, the capacitor authentication solves the problem of abnormal backup power supply of the disk array card caused by the use of non-compliant supercapacitors; the in-place monitoring solves the problem of backup power data loss caused by abnormal insertion and removal of the supercapacitor of the disk array card; the temperature monitoring can prevent the supercapacitor from overheating, and prevent the disk array card or the entire server from overheating abnormally.

[0097] In this embodiment, before the step of the disk array card controller monitoring the pin level of the capacitor management chip, the method further includes:

[0098] When the supercapacitor works normally, the pin level of the capacitor management chip is high; when the supercapacitor exceeds the pre-trial working temperature range, the disk array card controller pulls down the pin level of the capacitor management chip;

[0099] When the super capacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

[0100] It is understandable that the event notification pin of the temperature monitoring function is physically connected to the disk array card controller, and the pin level is high during normal operation. By reusing this pin, temperature monitoring and in-place status monitoring functions can be implemented. When the temperature is over, the chip pulls the pin down, and when it is unplugged, the power is off, and the pin level must be low. Therefore, in the overtemperature or unplugging scenario, the disk array card controller will receive an overtemperature event. Therefore, based on the pin level of the capacitor management chip being pulled down, the disk array card controller can know that the supercapacitor exceeds the pre-trial operating temperature range or the supercapacitor is unplugged from the disk array card.

[0101] The over-temperature event pin of the capacitor management chip is reused to realize the in-place detection function and report the capacitor in-place status in time, eliminating additional hardware circuits and reducing commercial costs.

[0102] like Figure 3 As shown, in this embodiment, the method further includes:

[0103] When the supercapacitor of the disk array card is connected normally, configuring the cache strategy of the disk array card to be a write-back (WB) mode, and reporting that the supercapacitor is normal;

[0104] When the supercapacitor is unplugged, configuring the cache strategy of the disk array card to be a write-through (WT) mode, and reporting the supercapacitor abnormality;

[0105] When the super capacitor is inserted into the disk array card, the cache strategy of the disk array card is configured as a write-back (WB) mode, and the super capacitor is reported to be normal.

[0106] Among them, WT, write-through: when writing data, the data is directly written to the disk, and the writing is completed only when the data is completely stored in the disk. WB, write-back, uses cache as an intermediary. When writing data, the writing is completed when the data is stored in the cache, and the cache block mark is set. When this cache block is to be swapped out, the data is written from the cache to the disk. The write performance is better than WT, and the execution efficiency is high.

[0107] In this embodiment, before the step of the disk array card controller monitoring the pin level of the capacitor management chip, the method further includes:

[0108] Step S1, when the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0109] Step S2: if the handshake fails, configure the cache policy of the disk array card to a write-back (WB) mode, and report the supercapacitor abnormality;

[0110] Step S3, if the handshake is successful, the supercapacitor is authenticated;

[0111] If the handshake is successful, it means that the capacitor management chip is in place, and this event is triggered by capacitor overheating or capacitor insertion. If the handshake fails, it means that the capacitor management chip is not in place, and this event is triggered by unplugging the capacitor, and the capacitor is abnormal.

[0112] Wherein, authenticating the supercapacitor includes:

[0113] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0114] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0115] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0116] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0117] The capacitor authentication function stores the capacitor SN code in the management chip and matches it with the SN code in the SOC. If the match is successful, the authentication is successful. The SOC implements intelligent management of supercapacitors, switches strategies in time, and improves server performance and reliability.

[0118] like Figure 3 As shown, in this embodiment, the temperature adjustment of the supercapacitor includes:

[0119] Determining whether the temperature of the supercapacitor is higher than a threshold;

[0120] If it is not higher than the threshold, the supercapacitor is authenticated;

[0121] If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold;

[0122] If it is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor;

[0123] If it is higher than the maximum threshold, the use of the super capacitor is stopped, the cache strategy of the disk array card is configured to be a write-through (WT) mode, and the super capacitor abnormality is reported.

[0124] Among them, the capacitor temperature is monitored in real time, and timely processing is taken after overheating to ensure data security and server security.

[0125] Temperature monitoring can prevent supercapacitors from overheating, and prevent the disk array card or the entire server from overheating. If the capacitor temperature is abnormal, this event is triggered by overheating, and the fan power is controlled according to the temperature threshold to achieve the cooling function.

[0126] Similarly, when the temperature of the supercapacitor is not higher than the threshold, the method of authenticating the supercapacitor includes:

[0127] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0128] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0129] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0130] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0131] In this embodiment, the step of determining whether the disk array card controller and the capacitor management chip connected to the supercapacitor have successfully handshaked includes:

[0132] Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received;

[0133] If the confirmation message replied by the capacitance management chip is received, it is determined that the handshake is successful;

[0134] If the confirmation information replied by the capacitance management chip is not received, it is determined that the handshake fails.

[0135] If the handshake is successful, it means that the capacitor management chip is in place, and this event is triggered by capacitor overheating or capacitor insertion. If the handshake fails, it means that the capacitor management chip is not in place, and this event is triggered by unplugging the capacitor, and the capacitor is abnormal.

[0136] like Figure 2 , Figure 3 As shown, in this embodiment, the method further includes:

[0137] Step S11, performing periodic capacitance calibration on the supercapacitor;

[0138] Step S12, obtaining the total capacity of the calibrated supercapacitor, and determining whether the total capacity satisfies the primary backup power;

[0139] Step S13, if the total capacity is sufficient to complete one backup power supply, then continue to perform periodic capacitance calibration on the supercapacitor;

[0140] Step S14: if the total capacity is insufficient to complete a backup power supply, the cache strategy of the disk array card is configured as a write-through (WT) mode, and a reminder is given to replace the supercapacitor.

[0141] Among them, the supercapacitor is calibrated periodically to ensure the backup power function and data security. Periodic calibration can refresh the actual power of the supercapacitor to prevent data loss caused by insufficient backup power. Real-time monitoring and periodic calibration process, notify the host to perform corresponding operations to protect data security. The entire process of capacitor management is implemented using SOC, replacing the capacitor calibration management chip to save resources. Periodic capacitor calibration allows users to obtain capacitor power in a timely manner, replace capacitors in a timely manner, and ensure user data integrity and reliability.

[0142] The capacitor calibration currently used in the industry is discharge calibration. The working voltage of the capacitor is U0. When calibration starts, the capacitor begins to discharge. When it discharges to U1, the current time is recorded, and it continues to discharge to U2. According to the capacitor calculation formula, Among them, I discharge is the current value of cross-current discharge, ΔU is the voltage difference before and after discharge, and Δt is the discharge duration. After the discharge is completed, the capacitor is charged to U0. However, this calibration method has certain risks, that is, the energy stored in the capacitor after discharge cannot be less than the energy required for a backup power supply. Otherwise, if an abnormal power outage occurs during the calibration process, the backup power function of the disk array card will be abnormal, resulting in data loss. Figure 4 shown.

[0143] There are certain risks in the discharge calibration method, that is, the energy stored in the capacitor after discharge cannot be less than the energy required for a backup power supply. Otherwise, if an abnormal power outage occurs during the calibration process, the backup power function of the disk array card will be abnormal, resulting in data loss. Figure 5 As shown, the present application proposes a charging calibration method, in which cross-current charging is used to replace cross-current discharge during calibration, and the current time and voltage U are recorded after the charging is stable. 11 , continue to charge to U 12 After charging, discharge to U 10 And according to the capacitance calculation formula The capacitance value is obtained. This method can ensure that the energy of the capacitor is always greater than the energy required for the backup power supply. Even if an abnormal power outage occurs during the calibration process, the backup power supply function can be guaranteed, and the data reliability and integrity can be guaranteed.

[0144] Therefore, the periodic capacitance calibration of the supercapacitor includes:

[0145] The charging calibration method is used to charge the supercapacitor under test with cross current;

[0146] After charging becomes stable, record the charging stable time and stable voltage U 11 , continue charging to the maximum voltage U 12 and the charging end time, and calculate the difference T between the charging end time and the charging stable time charge , calculate from the stable voltage U 11 Charge to the maximum voltage U 12 The slope of the current I charge ;

[0147] According to the capacitance calculation formula The capacitance value of the supercapacitor under test is obtained.

[0148] This application uses charging calibration to implement the calibration function, which can not only obtain the accurate capacitance value of the capacitor, but also ensure the backup power function when encountering an abnormal power outage during the calibration process.

[0149] In the above-mentioned disk array card supercapacitor management method, intelligent management of the disk array card supercapacitor is achieved through authentication management of the disk array card supercapacitor, capacitor in-place status monitoring and over-temperature protection management. Corresponding strategy switching and notification to the user are made for the abnormal state of the supercapacitor, which improves the user experience while ensuring the integrity of user data. Among them, capacitor authentication solves the problem of abnormal backup power supply of the disk array card caused by the use of non-compliant supercapacitors; in-place monitoring solves the problem of backup power data loss caused by abnormal insertion and removal of the disk array card supercapacitor; temperature monitoring can prevent the supercapacitor from overheating, and prevent the disk array card or the entire server from overheating.

[0150] In one embodiment, Figure 6 As shown, a disk array card super capacitor management device 100 is provided, including: a capacitor pin level monitoring module 4, a capacitor pin level pull-down judgment module 5, a capacitor state judgment module 6 and a temperature adjustment module 7.

[0151] The capacitor pin level monitoring module 4 is used for the disk array card controller to monitor the pin level of the capacitor management chip after the super capacitor works normally.

[0152] The capacitor pin level pull-down judgment module 5 is used for judging that the super capacitor exceeds the pre-trial operating temperature range or the super capacitor is unplugged from the disk array card in response to detecting that the pin level of the capacitor management chip is pulled down.

[0153] The capacitor status judgment module 6 is used to judge whether the disk array card controller and the capacitor management chip connected to the supercapacitor have successfully shaken hands; if the handshake cannot be successful, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged; if the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to judge whether the temperature of the supercapacitor is normal; if the temperature of the supercapacitor is normal, it is determined that the supercapacitor is inserted into the disk array card; if the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated.

[0154] The temperature adjustment module 7 is used to adjust the temperature of the super capacitor when the super capacitor is overheated.

[0155] In this embodiment, if Figure 6 As shown, the disk array card supercapacitor management device 100 includes a capacitor pin level management module 8 .

[0156] The capacitor pin level management module 8 is used before the disk array card controller monitors the pin level of the capacitor management chip: when the super capacitor is working normally, the pin level of the capacitor management chip is high; when the super capacitor exceeds the pre-trial working temperature range, the disk array card controller pulls down the pin level of the capacitor management chip; when the super capacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

[0157] In this embodiment, if Figure 6 As shown, the disk array card supercapacitor management device 100 includes a cache strategy management module 9 .

[0158] The cache policy management module 9 is used to configure the cache policy of the disk array card to the write-back (WB) mode when the supercapacitor of the disk array card is connected normally, and report that the supercapacitor is normal; when the supercapacitor is unplugged, configure the cache policy of the disk array card to the write-through (WT) mode, and report that the supercapacitor is abnormal; when the supercapacitor is inserted into the disk array card, configure the cache policy of the disk array card to the write-back (WB) mode, and report that the supercapacitor is normal.

[0159] In this embodiment, if Figure 6 As shown, the disk array card supercapacitor management device 100 includes: a disk array card access control module 1, a capacitor abnormal cache strategy control module 2, and a capacitor authentication control module 3.

[0160] The disk array card access control module 1 is used to perform a handshake with the capacitor management chip when the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, and determine whether the handshake is successful.

[0161] The capacitor abnormality cache strategy control module 2 is used to configure the cache strategy of the disk array card to a write-back (WB) mode if the handshake fails, and report the super capacitor abnormality.

[0162] The capacitor authentication control module 3 is used to authenticate the super capacitor if the handshake is successful.

[0163] Wherein, authenticating the supercapacitor includes:

[0164] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0165] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0166] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0167] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0168] In this embodiment, the temperature adjustment of the supercapacitor includes:

[0169] Determining whether the temperature of the supercapacitor is higher than a threshold;

[0170] If it is not higher than the threshold, the supercapacitor is authenticated;

[0171] If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold;

[0172] If it is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor;

[0173] If it is higher than the maximum threshold, the use of the super capacitor is stopped, the cache strategy of the disk array card is configured to be a write-through (WT) mode, and the super capacitor abnormality is reported.

[0174] In this embodiment, the step of determining whether the disk array card controller and the capacitor management chip connected to the supercapacitor have successfully handshaked includes:

[0175] Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received;

[0176] If the confirmation message replied by the capacitance management chip is received, it is determined that the handshake is successful;

[0177] If the confirmation information replied by the capacitance management chip is not received, it is determined that the handshake fails.

[0178] In this embodiment, if Figure 6 As shown, the disk array card supercapacitor management device 100 includes a capacitor calibration management module 10 .

[0179] The capacitance calibration management module 10 is used to perform periodic capacitance calibration on the supercapacitor; obtain the total capacity of the calibrated supercapacitor, and determine whether the total capacity satisfies one backup power supply; if the total capacity is sufficient to complete one backup power supply, continue to perform periodic capacitance calibration on the supercapacitor; if the total capacity is insufficient to complete one backup power supply, configure the cache strategy of the disk array card to a write-through (WT) mode, and remind the user to replace the supercapacitor.

[0180] In the above-mentioned disk array card supercapacitor management device, intelligent management of the disk array card supercapacitor is achieved through authentication management of the disk array card supercapacitor, capacitor in-place status monitoring and over-temperature protection management. Corresponding strategy switching and notification to the user are made for the abnormal state of the supercapacitor, which improves the user experience while ensuring the integrity of user data. Among them, capacitor authentication solves the problem of abnormal backup power supply of the disk array card caused by the use of non-compliant supercapacitors; in-place monitoring solves the problem of backup power data loss caused by abnormal plugging and unplugging of the disk array card supercapacitor; temperature monitoring can prevent the supercapacitor from overheating, and prevent the disk array card or the entire server from overheating abnormally.

[0181] For the specific definition of the disk array card supercapacitor management device, please refer to the definition of the disk array card supercapacitor management method above, which will not be repeated here. Each module in the above-mentioned disk array card supercapacitor management device can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0182] In one embodiment, a computer program product is provided, comprising a computer program, which, when executed by a processor, implements the following steps:

[0183] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0184] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0185] If the handshake is successful, the supercapacitor is authenticated;

[0186] After the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0187] In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0188] Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have a handshake successfully;

[0189] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0190] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0191] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0192] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0193] In one embodiment, the computer program further implements the following steps when executed by a processor:

[0194] Before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0195] When the supercapacitor works normally, the pin level of the capacitor management chip is high; when the supercapacitor exceeds the pre-trial working temperature range, the disk array card controller pulls down the pin level of the capacitor management chip;

[0196] When the super capacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

[0197] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0198] When the supercapacitor of the disk array card is connected normally, configuring the cache strategy of the disk array card to be a write-back (WB) mode, and reporting that the supercapacitor is normal;

[0199] When the supercapacitor is unplugged, configuring the cache strategy of the disk array card to be a write-through (WT) mode, and reporting the supercapacitor abnormality;

[0200] When the super capacitor is inserted into the disk array card, the cache strategy of the disk array card is configured as a write-back (WB) mode, and the super capacitor is reported to be normal.

[0201] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0202] Before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0203] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0204] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0205] If the handshake is successful, the supercapacitor is authenticated;

[0206] Wherein, authenticating the supercapacitor includes:

[0207] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0208] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0209] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0210] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0211] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0212] The temperature regulation of the supercapacitor comprises:

[0213] Determining whether the temperature of the supercapacitor is higher than a threshold;

[0214] If it is not higher than the threshold, the supercapacitor is authenticated;

[0215] If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold;

[0216] If it is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor;

[0217] If it is higher than the maximum threshold, the use of the super capacitor is stopped, the cache strategy of the disk array card is configured to be a write-through (WT) mode, and the super capacitor abnormality is reported.

[0218] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0219] The step of judging whether the disk array card controller and the capacitor management chip connected to the super capacitor have successfully handshaked comprises:

[0220] Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received;

[0221] If the confirmation message replied by the capacitance management chip is received, it is determined that the handshake is successful;

[0222] If the confirmation information replied by the capacitance management chip is not received, it is determined that the handshake fails.

[0223] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0224] Performing periodic capacitance calibration on the supercapacitor;

[0225] Obtaining the total capacity of the calibrated supercapacitor, and determining whether the total capacity satisfies primary backup power;

[0226] If the total capacity is sufficient to complete one backup power supply, continue to perform periodic capacitance calibration on the supercapacitor;

[0227] If the total capacity is insufficient to complete a backup power supply, the cache strategy of the disk array card is configured as a write-through (WT) mode, and a reminder is given to replace the super capacitor.

[0228] For specific limitations on the steps implemented when the computer program is executed by the processor, please refer to the above limitations on the method for managing the supercapacitor of the disk array card, which will not be repeated here.

[0229] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 7 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store disk array card supercapacitor management data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a disk array card supercapacitor management method is implemented.

[0230] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0231] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0232] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0233] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0234] If the handshake is successful, the supercapacitor is authenticated;

[0235] After the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0236] In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0237] Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have a handshake successfully;

[0238] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0239] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0240] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0241] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0242] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0243] Before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0244] When the supercapacitor works normally, the pin level of the capacitor management chip is high; when the supercapacitor exceeds the pre-trial working temperature range, the disk array card controller pulls down the pin level of the capacitor management chip;

[0245] When the super capacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

[0246] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0247] When the supercapacitor of the disk array card is connected normally, configuring the cache strategy of the disk array card to be a write-back (WB) mode, and reporting that the supercapacitor is normal;

[0248] When the supercapacitor is unplugged, configuring the cache strategy of the disk array card to be a write-through (WT) mode, and reporting the supercapacitor abnormality;

[0249] When the super capacitor is inserted into the disk array card, the cache strategy of the disk array card is configured as a write-back (WB) mode, and the super capacitor is reported to be normal.

[0250] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0251] Before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0252] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0253] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0254] If the handshake is successful, the supercapacitor is authenticated;

[0255] Wherein, authenticating the supercapacitor includes:

[0256] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0257] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0258] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0259] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0260] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0261] The temperature regulation of the supercapacitor comprises:

[0262] Determining whether the temperature of the supercapacitor is higher than a threshold;

[0263] If it is not higher than the threshold, the supercapacitor is authenticated;

[0264] If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold;

[0265] If it is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor;

[0266] If it is higher than the maximum threshold, the use of the super capacitor is stopped, the cache strategy of the disk array card is configured to be a write-through (WT) mode, and the super capacitor abnormality is reported.

[0267] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0268] The step of judging whether the disk array card controller and the capacitor management chip connected to the super capacitor have successfully handshaked comprises:

[0269] Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received;

[0270] If the confirmation message replied by the capacitance management chip is received, it is determined that the handshake is successful;

[0271] If the confirmation information replied by the capacitance management chip is not received, it is determined that the handshake fails.

[0272] In one embodiment, when the processor executes the computer program, the processor further implements the following steps:

[0273] Performing periodic capacitance calibration on the supercapacitor;

[0274] Obtaining the total capacity of the calibrated supercapacitor, and determining whether the total capacity satisfies primary backup power;

[0275] If the total capacity is sufficient to complete one backup power supply, continue to perform periodic capacitance calibration on the supercapacitor;

[0276] If the total capacity is insufficient to complete a backup power supply, the cache strategy of the disk array card is configured as a write-through (WT) mode, and a reminder is given to replace the super capacitor.

[0277] For specific limitations on the steps implemented when the processor executes the computer program, please refer to the above limitations on the method for managing the supercapacitor of the disk array card, which will not be repeated here.

[0278] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0279] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0280] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0281] If the handshake is successful, the supercapacitor is authenticated;

[0282] After the supercapacitor works normally, the disk array card controller monitors the pin level of the capacitor management chip;

[0283] In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the super capacitor exceeds a pre-trial operating temperature range or the super capacitor is unplugged from the disk array card;

[0284] Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have a handshake successfully;

[0285] If the handshake fails, it means that the capacitor management chip is not in place, and it is determined that the supercapacitor is unplugged;

[0286] If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal;

[0287] If the temperature of the super capacitor is normal, determining to insert the super capacitor into the disk array card;

[0288] If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

[0289] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0290] Before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0291] When the supercapacitor works normally, the pin level of the capacitor management chip is high; when the supercapacitor exceeds the pre-trial working temperature range, the disk array card controller pulls down the pin level of the capacitor management chip;

[0292] When the super capacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

[0293] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0294] When the supercapacitor of the disk array card is connected normally, configuring the cache strategy of the disk array card to be a write-back (WB) mode, and reporting that the supercapacitor is normal;

[0295] When the supercapacitor is unplugged, configuring the cache strategy of the disk array card to be a write-through (WT) mode, and reporting the supercapacitor abnormality;

[0296] When the super capacitor is inserted into the disk array card, the cache strategy of the disk array card is configured as a write-back (WB) mode, and the super capacitor is reported to be normal.

[0297] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0298] Before the disk array card controller monitors the pin level of the capacitor management chip, the method further includes:

[0299] When the disk array card is powered on or detects that the super capacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful;

[0300] If the handshake fails, the cache policy of the disk array card is configured to be a write-back (WB) mode, and the supercapacitor abnormality is reported;

[0301] If the handshake is successful, the supercapacitor is authenticated;

[0302] Wherein, authenticating the supercapacitor includes:

[0303] Burning the production serial number (SN code) of the supercapacitor into an electrically erasable programmable read-only memory (EEPROM), and storing the supercapacitor serial number with matching specifications in the firmware of the disk array card controller;

[0304] Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto;

[0305] If the production serial number in the supercapacitor is in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be write-back (WB) mode, and the supercapacitor is reported to be normal;

[0306] If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to be a write-through (WT) mode, and the supercapacitor abnormality is reported.

[0307] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0308] The temperature regulation of the supercapacitor comprises:

[0309] Determining whether the temperature of the supercapacitor is higher than a threshold;

[0310] If it is not higher than the threshold, the supercapacitor is authenticated;

[0311] If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold;

[0312] If it is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor;

[0313] If it is higher than the maximum threshold, the use of the super capacitor is stopped, the cache strategy of the disk array card is configured to be a write-through (WT) mode, and the super capacitor abnormality is reported.

[0314] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0315] The step of judging whether the disk array card controller and the capacitor management chip connected to the super capacitor have successfully handshaked comprises:

[0316] Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received;

[0317] If the confirmation message replied by the capacitance management chip is received, it is determined that the handshake is successful;

[0318] If the confirmation information replied by the capacitance management chip is not received, it is determined that the handshake fails.

[0319] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0320] Performing periodic capacitance calibration on the supercapacitor;

[0321] Obtaining the total capacity of the calibrated supercapacitor, and determining whether the total capacity satisfies primary backup power;

[0322] If the total capacity is sufficient to complete one backup power supply, continue to perform periodic capacitance calibration on the supercapacitor;

[0323] If the total capacity is insufficient to complete a backup power supply, the cache strategy of the disk array card is configured as a write-through (WT) mode, and a reminder is given to replace the super capacitor.

[0324] For specific limitations on the steps implemented when the computer program is executed by the processor, please refer to the above limitations on the method for managing the supercapacitor of the disk array card, which will not be repeated here.

[0325] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0326] The technical features of the above embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0327] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A disk array card supercapacitor management method, characterized in that: The disk array card is provided with a super capacitor, the disk array card is connected to a disk array card controller, and the super capacitor is connected to a capacitor management chip. The method includes: After the supercapacitor operates normally, the disk array card controller monitors the pin level of the capacitor management chip; In response to detecting that the pin level of the capacitor management chip is pulled low, determining that the supercapacitor exceeds a pre-qualified operating temperature range or the supercapacitor is unplugged from the disk array card; Determine whether the disk array card controller and the capacitor management chip connected to the supercapacitor have successfully handshaked; If the handshake fails, it means that the capacitor management chip is not in place and the supercapacitor is determined to be unplugged; If the handshake is successful, it means that the capacitor management chip is in place, and the temperature of the supercapacitor is obtained to determine whether the temperature of the supercapacitor is normal; If the temperature of the supercapacitor is normal, determining to insert the supercapacitor into the disk array card; If the temperature of the supercapacitor is abnormal, it is determined that the supercapacitor is overheated, and the temperature of the supercapacitor is adjusted.

2. The disk array card supercapacitor management method according to claim 1, characterized in that: Before the step of the disk array card controller monitoring the pin level of the capacitor management chip, the method further includes: When the supercapacitor is working normally, the pin level of the capacitor management chip is high; when the supercapacitor exceeds the pre-qualified operating temperature range, the disk array card controller pulls down the pin level of the capacitor management chip; When the supercapacitor is unplugged from the disk array card, the pin level of the capacitor management chip is low.

3. The disk array card supercapacitor management method according to claim 1, characterized in that: The method further comprises: When the supercapacitor of the disk array card is connected normally, configuring the cache policy of the disk array card to a write-back mode, and reporting that the supercapacitor is normal; When the supercapacitor is unplugged, configuring the cache policy of the disk array card to a write-through mode and reporting the supercapacitor abnormality; When the supercapacitor is inserted into the disk array card, the cache policy of the disk array card is configured to be a write-back mode, and the supercapacitor is reported to be normal.

4. The disk array card supercapacitor management method according to claim 3, characterized in that: Before the step of the disk array card controller monitoring the pin level of the capacitor management chip, the method further includes: When the disk array card is powered on or detects that the supercapacitor is reinserted into the disk array card, a handshake is performed with the capacitor management chip to determine whether the handshake is successful; If the handshake fails, configure the cache policy of the disk array card to a write-back mode and report the supercapacitor abnormality; If the handshake is successful, the supercapacitor is authenticated; The authenticating the supercapacitor includes: Burning the production serial number of the supercapacitor into a electrically erasable programmable read-only memory, and storing the serial number of the supercapacitor with the appropriate specifications in the firmware of the disk array card controller; Matching and comparing the supercapacitor serial number in the firmware of the disk array card controller with the production serial number in the supercapacitor connected thereto; If the production serial number in the supercapacitor is the same as the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication is successful, the cache policy of the disk array card is configured to be in write-back mode, and the supercapacitor is reported to be normal; If the production serial number in the supercapacitor is not in the supercapacitor serial number in the firmware of the disk array card controller, it is determined that the supercapacitor authentication fails, the cache policy of the disk array card is configured to a write-through mode, and the supercapacitor abnormality is reported.

5. The disk array card supercapacitor management method according to claim 1, characterized in that: The temperature adjustment of the supercapacitor includes: Determining whether the temperature of the supercapacitor is higher than a threshold; If it is not higher than the threshold, the supercapacitor is authenticated; If it is higher than the threshold, determining whether the temperature of the supercapacitor is higher than the maximum threshold; If the temperature is not higher than the maximum threshold, increasing the fan power to cool the supercapacitor; If it is higher than the maximum threshold, the supercapacitor is stopped from being used, the cache policy of the disk array card is configured as a write-through mode, and the supercapacitor abnormality is reported.

6. The disk array card supercapacitor management method according to claim 1, characterized in that: The step of determining whether the disk array card controller and the capacitor management chip connected to the supercapacitor have successfully handshaked comprises: Sending an address to the capacitor management chip through the disk array card controller, and determining whether confirmation information replied by the capacitor management chip is received; If the confirmation information returned by the capacitance management chip is received, it is determined that the handshake is successful; If no confirmation information is received from the capacitance management chip, it is determined that the handshake has failed.

7. The disk array card supercapacitor management method according to claim 1, characterized in that: The method further comprises: Performing periodic capacitance calibration on the supercapacitor; Obtaining the total capacity of the calibrated supercapacitor, and determining whether the total capacity satisfies primary backup power requirements; If the total capacity is sufficient to complete one backup power supply, continue to perform periodic capacitance calibration on the supercapacitor; If the total capacity is insufficient to complete one backup power supply, the cache strategy of the disk array card is configured as a write-through mode, and a reminder is given to replace the supercapacitor.

8. A disk array card supercapacitor management device, characterized in that: The device comprises: A capacitor pin level monitoring module, configured to enable the disk array card controller to monitor the pin level of the capacitor management chip after the supercapacitor operates normally; a capacitor pin level low judgment module, configured to, in response to detecting that the pin level of the capacitor management chip is pulled low, determine that the supercapacitor exceeds a pre-qualified operating temperature range or that the supercapacitor is unplugged from the disk array card; a capacitor status judgment module, configured to judge whether a handshake between the disk array card controller and the capacitor management chip connected to the supercapacitor is successful; if the handshake is not successful, it indicates that the capacitor management chip is not in place, and the supercapacitor is determined to be unplugged; if the handshake is successful, it indicates that the capacitor management chip is in place, obtains the temperature of the supercapacitor, and judges whether the temperature of the supercapacitor is normal; if the temperature of the supercapacitor is normal, it is judged that the supercapacitor is inserted into the disk array card; if the temperature of the supercapacitor is abnormal, it is judged that the supercapacitor is overheated; The temperature regulating module is used to regulate the temperature of the super capacitor when the super capacitor is overheated.

9. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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