PCIe resource allocation method and device for server and electronic equipment

Abstract

The embodiment of the invention provides a PCIe resource allocation method and device for a server and electronic equipment. The method comprises the steps that a historical topology mode and first resources distributed for a plurality of PE interfaces in a historical mode are obtained, the topology mode represents the connection mode of a PCIe Switch and a CPU, and the PE interfaces are ports where the CPU is connected with the PCIe Switch; acquiring a second resource required by the current topology mode and a plurality of PE interfaces; according to the current topology mode, the historical topology mode, the first resources and the second resources, idle resources in the first resources are determined, and at least part of the idle resources are recycled to a resource pool; and according to the current topology mode, the historical topology mode, the first resource and the second resource, determining a missing resource in the second resource, and allocating resources to the plurality of PE interfaces from a resource pool. The method is used for achieving plug and play of the external equipment of the computer.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a PCIe resource allocation method, device and electronic device for a server. Background Art

[0002] During the process of starting up a computer system, the basic input and output system is required to initialize the computer hardware and allocate sufficient system resources to the computer hardware so that the computer system can run normally after connecting the computer hardware devices. As external hardware devices used to expand the functions of computer systems are constantly being innovated, it becomes particularly important for the basic input and output system to allocate resources quickly and efficiently.

[0003] In the prior art, a specific version of the basic input / output system can be released to support the topological mode of the connection between the hardware device and the computer; or, for different topological modes of the connection between the hardware device and the computer, the basic input / output system statically reserves the maximum resources required.

[0004] However, as the topology mode changes, the basic input and output system version needs to be continuously updated, and the demand for system resources of hardware devices will only become greater and greater with the development of technology. Statically reserved resources will not only need to be updated periodically, but will also result in a waste of system resources. It cannot meet customers' needs for plug-in and unplug-and-change hardware devices in different scenarios, affecting the efficiency of equipment reconfiguration. Summary of the invention

[0005] The embodiments of the present application provide a PCIe resource allocation method, device and electronic device for a server, so as to achieve a plug-and-play effect when an external hardware device is connected to a computer.

[0006] In a first aspect, an embodiment of the present application provides a PCIe resource allocation method for a server, which is applied to a basic input / output system on a mainboard of the server; the basic input / output system is connected to a hardware device via a PCIe Switch; the method comprises:

[0007] Acquire a historical topology mode and a first resource historically allocated to a plurality of PE interfaces, wherein the topology mode represents a connection mode between a PCIe Switch and a CPU, and the PE interface is a port through which the CPU is connected to the PCIe Switch;

[0008] Acquire the current topology mode and the second resource required by the plurality of PE interfaces;

[0009] Determine idle resources in the first resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and recycle at least part of the idle resources to a resource pool;

[0010] According to the current topology mode and the historical topology mode, the first resources, and the second resources, the missing resources in the second resources are determined, and resources are allocated to the plurality of PE interfaces from a resource pool.

[0011] In a possible implementation manner, obtaining a historical topology mode and a first resource historically allocated to a plurality of PE interfaces includes:

[0012] Determine the historical topology mode and the first resource according to the reserved resource information;

[0013] The reserved resource information includes historical resource information and default resource information. The historical topology mode of the default resource information is empty. The first resource allocated to each PE interface by the default resource information is a preset unit resource.

[0014] In a possible implementation manner, before acquiring the current topology mode and the second resources required by the plurality of PE interfaces, the method further includes:

[0015] Initializing hardware devices connected to the basic input and output system based on the historical topology pattern and the first resource;

[0016] Traverse multiple PCIE devices connected to the CPU through the PCIe Switch to obtain traversal result information.

[0017] In a possible implementation manner, the acquiring the current topology mode and the second resource currently required by the plurality of PE interfaces includes:

[0018] Determine the current topology mode and the second resources required by the plurality of PE interfaces according to the traversal result information.

[0019] In a possible implementation manner, determining idle resources in the first resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and recycling at least part of the idle resources to a resource pool includes:

[0020] A first preset resource is reserved for a first PE interface having the first resource, and a portion of the first resource excluding the first preset resource is recycled into the resource pool; wherein the first PE interface is not currently connected to the PCIeSwitch.

[0021] In a possible implementation manner, determining idle resources in the first resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and recycling at least part of the idle resources to a resource pool includes:

[0022] A second resource is reserved for a second PE interface having the first resource, and a portion of the first resource that exceeds the second resource is recovered into the resource pool; wherein the second PE interface is currently connected to the PCIe Switch, and the second resource of the second PE interface is less than the first resource.

[0023] In a possible implementation manner, determining the missing resources in the second resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and allocating resources to the plurality of PE interfaces from a resource pool includes:

[0024] Reserve a first resource for a third PE interface having the first resource, and remove part of the resources required for the first resource from the second resource allocated to the third PE interface from the resource pool; wherein the third PE interface is currently connected to the PCIe Switch, and the second resource of the third PE interface is greater than the first resource.

[0025] In a possible implementation manner, determining the missing resources in the second resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and allocating resources to the plurality of PE interfaces from a resource pool includes:

[0026] The first preset resource is reserved for a fourth PE interface having the first preset resource, and part of the resources required by the first preset resource is removed from the second resource allocated to the fourth PE interface from the resource pool; wherein the fourth PE interface has not been connected to the PCIe Switch in history.

[0027] In a possible implementation manner, the current topology mode and the historical topology mode are respectively one of the following:

[0028] Cascade mode, general mode, balanced dual uplink mode and balanced single uplink mode; among them,

[0029] The cascade mode represents that two PCIe switches are connected in sequence, wherein one PCIe switch is connected to a PE interface of a CPU;

[0030] The general mode represents that two PCIe switches are connected to one PE interface of the same CPU respectively;

[0031] The balanced dual uplink mode indicates that two PCIe switches are each connected to two PE interfaces of different CPUs;

[0032] The balanced single uplink mode indicates that two PCIe switches are respectively connected to a PE interface of a different CPU.

[0033] In a possible implementation manner, after determining the missing resources in the second resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and allocating resources to the plurality of PE interfaces from a resource pool, the method further includes:

[0034] Updating resource reservation information of the system according to the current topology mode and the second resource;

[0035] Restarting the basic input and output system, and starting the operating system based on the current topology mode and the second resource.

[0036] In a second aspect, an embodiment of the present application provides a PCIe resource allocation device for a server, which is applied to a basic input / output system on a mainboard of the server; the basic input / output system is connected to a hardware device via a PCIe Switch; the device comprises:

[0037] A first acquisition unit is used to acquire a historical topology mode and a first resource historically allocated to a plurality of PE interfaces, wherein the topology mode represents a connection mode between a PCIe Switch and a CPU, and the PE interface is a port through which the CPU is connected to the PCIe Switch;

[0038] A second acquisition unit, configured to acquire a current topology mode and second resources required by the plurality of PE interfaces;

[0039] A first processing unit is configured to determine idle resources in the first resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and recycle at least part of the idle resources to a resource pool;

[0040] The second processing unit is used to determine the missing resources in the second resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and allocate resources to the multiple PE interfaces from the resource pool.

[0041] In a third aspect, an embodiment of the present application provides an electronic device, the electronic device comprising: a processor, and a memory communicatively connected to the processor;

[0042] The memory stores computer-executable instructions;

[0043] The processor executes the computer-executable instructions stored in the memory to implement the first aspect or any implementation manner of the first aspect.

[0044] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, they are used to implement the first aspect or any implementation method in the first aspect.

[0045] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the first aspect or any implementation of the first aspect. Execution instructions cause the processor to execute the first aspect and / or various possible implementations of the first aspect as described above.

[0046] The embodiments of the present application provide a PCIe resource allocation method, device and electronic device for a server. By acquiring a historical topology mode and a first resource historically allocated, as well as a current topology mode and a second resource currently required, and comparing the historical and current resource allocation situations, the resources allocated by the CPU to each PE interface are integrated or split, thereby realizing dynamic allocation of CPU resources. There is no need to update the BIOS as the topology mode changes, thereby improving the reconfiguration efficiency of CPU external devices, and also reducing the low utilization of CPU resources caused by the preset maximum resources, thereby improving the user reconfiguration experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0048] Figure 1 A schematic diagram of a topology scenario provided for this application;

[0049] Figure 2 A schematic diagram of a PCIe resource allocation method for a server provided in this application Figure 1 ;

[0050] Figure 3 A schematic diagram of a PCIe resource allocation method for a server provided in this application Figure 2 ;

[0051] Figure 4 A schematic diagram of the structure of a PCIe resource allocation device for a server provided in the present application;

[0052] Figure 5 A schematic diagram of the structure of an electronic device provided in this application.

[0053] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0054] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0055] First, the terms involved in this application are explained:

[0056] Bus: It is the bus in PCIe technology. It is a communication highway between multiple hardware and is used to connect and coordinate multiple different computer components. BUS allows high-speed serial communication, supports active power management, error reporting, end-to-end reliable transmission, hot plugging, and quality of service. It is an important part of the computer device tree. Most peripheral hardware expansions need to be carried out through the PCIe bus.

[0057] PCIE: It is a high-speed serial computer expansion bus standard used for connecting between hardware components inside a computer, especially for connecting the motherboard and high-performance hardware devices such as graphics processing units (GPUs), network interface cards (NICs), and storage devices.

[0058] NVRAM: (Non-Volatile Random Access Memory) is a special type of computer storage technology that can keep stored data from being lost even in the event of a power outage.

[0059] PCH: (Platform Controller Hub), located on the motherboard, serves as a bridge and hub between BIOS and CPU to ensure stable operation of the system.

[0060] UPI: (Ultra Path Interconnect) is used to connect multiple CPU processors or CPU and chipset, so that CPUs can exchange data directly without going through the traditional north bridge chip.

[0061] During the process of starting up a computer system, the basic input and output system is required to initialize the computer hardware and allocate sufficient system resources to the computer hardware so that the computer system can run normally after connecting the computer hardware devices. As external hardware devices used to expand the functions of computer systems are constantly being innovated, it becomes particularly important for the basic input and output system to allocate resources quickly and efficiently.

[0062] In one example, a specific version of the basic input and output system may be released to support the topology mode of the hardware devices and computer connections.

[0063] However, in the above method, as the topology mode changes, it is necessary to continuously update the version of the basic input and output system, or rewrite the BIOS program, or replace the chip where the BIOS is located. The process is complicated and may easily cause the computer device to fail to start normally.

[0064] In one example, the basic input / output system can statically reserve the maximum resources required for different hardware devices and computer connection topology modes.

[0065] However, in the above method, the demand for system resources of hardware devices will only become greater and greater with the development of technology. The statically reserved resources will not only need to be updated periodically, but there will also be a waste of system resources. It cannot meet the customer's demand for plugging and unplugging hardware devices for immediate use in different situations, which affects the efficiency of equipment reconfiguration.

[0066] The present application provides a PCIe resource allocation method, device and equipment for a server, aiming to solve the above technical problems.

[0067] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0068] Figure 1 A schematic diagram of a topology mode provided in this application, specifically, Figure 1 This is a schematic diagram of the scenario of balanced dual uplink mode.

[0069] Figure 2 A schematic diagram of a PCIe resource allocation method for a server provided in this application Figure 1 ,like Figure 2 As shown, the method includes:

[0070] S201. Acquire a historical topology mode and a first resource historically allocated to a plurality of PE interfaces, wherein the topology mode represents a connection mode between a PCIe Switch and a CPU, and the PE interface is a port through which the CPU is connected to the PCIe Switch.

[0071] For example, PCIe Switch (Peripheral Component Interconnect ExpressSwitch, PCI Express switch) is a hardware device used to connect multiple PCIE devices. Through PCIe Switch, the computer system can expand more devices to connect to the CPU. PCIe Switch allows multiple devices to share a CPU PE port without the need to allocate a separate port to each device, thereby building a more complex and efficient hardware topology.

[0072] The PE interface provides high-speed data transmission rate to the device and supports hot plugging, that is, the device can be added or removed without restarting the computer. Different channel widths can be configured as needed to meet the data transmission requirements of different devices. It is used to connect expansion devices such as PCIe Switch.

[0073] At the same time, the BIOS (Basic Input / Output System) allocates the required CPU resources to the PCIe Switch through the PE interface (CPU Processing Element), including the memory address space (Memory Address Space), I / O address space (I / O Address Space) and possible interrupt request (IRQ) resources, so that the computer system can start up normally and use the external hardware devices normally after connecting the external hardware devices.

[0074] The topological mode of the historical connection between the PCIe Switch and the CPU in the non-volatile storage area of ​​the BIOS is obtained. Because the CPU and the PCIe Switch are connected through the PE interface, different connection modes of the CPU's PE interface and the PCIe Switch constitute different topological modes, and the BIOS allocates CPU resources to the PCIe Switch through the PE interface. Therefore, the first resource allocated to multiple PE interfaces in the historical topological mode is obtained.

[0075] S202: Acquire the current topology mode and second resources required by multiple PE interfaces.

[0076] Exemplarily, the BIOS initializes the hardware devices according to the acquired historical topology pattern and the first resources historically allocated to multiple PE interfaces, and traverses the hardware devices connected to the CPU through the PCIe Switch through a depth-first search traversal algorithm. During the traversal process, a corresponding BDF (Bus-Device-Function) is assigned to each connected hardware device according to the traversal path. The BDF is an address that uniquely identifies the location of the hardware device in the computer system. The BDF of each hardware device is written into the configuration space of the hardware device. The BIOS obtains the CPU resources required by the hardware device by accessing the configuration space of each hardware device.

[0077] After the traversal is completed, the BIOS summarizes the CPU resources required by the hardware devices under each PE interface connected to the PCIe Switch, and obtains the CPU resources required by each PE interface, which is the second resource. At the same time, according to the traversal path, the connection relationship between the CPU through the PE interface and the PCIe Switch can be obtained, which is the current topology mode.

[0078] S203: Determine idle resources in the first resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and recycle at least part of the idle resources to the resource pool.

[0079] For example, if the current topology mode is inconsistent with the historical topology mode, there will be a PE interface connected to the CPU and PCIe Switch in the historical topology mode, which is not connected in the current topology mode. In this case, it is necessary to reserve a unit resource for the disconnected PE interface and recycle the remaining free resources to the CPU internal resource pool for resource redistribution, where a unit resource is a resource unit set in advance according to demand. For example, 1024G storage resources are defined as a unit resource, that is, 1024G storage resources are reserved for the disconnected PE interface and the remaining resources are recycled.

[0080] Alternatively, if the second resource required by the PE interface connecting the CPU and the PCIe Switch in the current topology mode is much smaller than the first resource in the historical topology mode, the second resource needs to be reserved for the PE interface that remains connected, and the remaining free resources are recycled to the CPU internal resource pool for redistribution. In addition, since the CPU resources are allocated to the PE in integer units, the resource size of each unit is set by the user. Therefore, if the CPU resources required by the traversed PE interface are between n unit resources and n+1 unit resources, the second resource allocated to the PE interface should be n+1 unit resources.

[0081] S204: Determine the missing resources in the second resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and allocate resources to the multiple PE interfaces from the resource pool.

[0082] For example, if the current topology mode is inconsistent with the historical topology mode, there will be PE interfaces that are not connected to the CPU and PCIe Switch in the historical topology mode. They remain connected in the current topology mode, and in the unconnected state, each PE interface only retains a default unit resource. When the CPU resources required by the PE interface obtained exceed the original unit resource, it is necessary to reallocate multiple unit resources to the PE interface from the CPU resource pool, so that the sum of the original unit resource and the reallocated multiple unit resources can be greater than or equal to the CPU resources required by the PE interface.

[0083] Alternatively, if the second resource required by the PE interface connecting the CPU and the PCIe Switch in the current topology mode is much greater than the first resource in the historical topology mode, it is necessary to reallocate multiple unit resources from the CPU internal resource pool to the PE interface based on the original first resource, so that the sum of the first resource and the reallocated multiple unit resources can be greater than or equal to the CPU resource required by the PE interface.

[0084] Each hardware device connected to the PCIe Switch can obtain CPU resources to maintain normal startup from the PE interface, so the BIOS can successfully complete the initialization of the computer system's peripheral hardware devices, thereby starting the computer system.

[0085] A PCIe resource allocation method for a server provided in an embodiment of the present application obtains a historical topology mode and a first resource allocated historically, as well as a current topology mode and a second resource currently required, compares the historical and current resource allocation situations, and integrates or splits the resources allocated by the CPU to each PE interface, thereby realizing dynamic allocation of CPU resources. There is no need to update the BIOS as the topology mode changes, thereby improving the reconfiguration efficiency of CPU external devices, and also reducing the low utilization of CPU resources caused by the preset maximum resources, thereby improving the user reconfiguration experience.

[0086] Figure 3 A schematic diagram of a PCIe resource allocation method for a server provided in this application Figure 2 ,like Figure 3 As shown, in this embodiment Figure 2 Based on the embodiment, a PCIe resource allocation method for a server is described in detail, and the method includes:

[0087] S301. Determine a historical topology mode and a first resource according to reserved resource information.

[0088] The reserved resource information includes historical resource information and default resource information. The historical topology mode of the default resource information is empty. The first resource allocated to each PE interface by the default resource information is a preset unit resource.

[0089] For example, each time the BIOS completes resource allocation for the CPU's PE interface, the topology mode and resource allocation status will be stored in a non-volatile storage area as historical resource information, so that when the computer is turned on for the second time and the topology mode has not changed, it can directly boot into the OS according to the original historical resource reservation, shortening the computer system startup process.

[0090] When the computer system is turned on for the first time, since there is no historical startup situation, the reserved resource information saved in the non-volatile storage area of ​​BIOS is the default resource information. The default resource information is pre-written into BIOS by the technician as the initial setting of the computer. The historical topology mode of the default resource information is empty, and the first resource of each PE interface of the CPU is a preset unit of resource.

[0091] S302, based on the historical topology mode and the first resource, initialize the hardware device connected to the basic input and output system; traverse multiple PCIE devices connected to the CPU through the PCIe Switch to obtain traversal result information.

[0092] Exemplarily, the BIOS initializes the hardware devices according to the acquired historical topology mode and the first resources historically allocated to the multiple PE interfaces, and traverses the hardware devices connected to the CPU through the PCIe Switch by using a depth-first search traversal algorithm.

[0093] like Figure 1As shown, taking the traversal of the balanced dual uplink mode as an example, during the traversal process, the BIOS traverses to CPU 0, allocates a Bus resource to CPU 0, marked as Bus 0, continues to traverse the PCIe Switch connected to Bus 0 through the PE 0 interface, allocates a Bus resource to the part of the PCIe Switch that uses the resources from the PE 0 interface, marked as Bus 1, continues to traverse the devices connected under Bus 1, and allocates Bus 2 and Bus 3 to the following two devices in sequence. There are no other devices under Bus 2 and Bus 3. Continue to traverse the PCIe Switch connected to the PE 2 interface under Bus 0, allocates a Bus resource to the part of the PCIe Switch that uses the resources from the PE 2 interface, marked as Bus 4, continues to traverse the devices connected under Bus 4, and allocates Bus 5 and Bus 6 to the following two devices in sequence. The traversal of the devices connected to CPU 0 is completed, and the traversal of CPU 0 is continued in the same way. 1 connected devices until all devices are assigned a unique Bus, which means that each connected hardware device is assigned a corresponding BDF (Bus-Device-Function). BDF is an address that uniquely identifies the location of the hardware device in the computer system. For example, (Bus 7, Bus 11, Bus 13) can uniquely identify the connected hardware device. The BDF of each hardware device is written into the configuration space of the hardware device. The BIOS obtains the CPU resources required by the hardware device by accessing the configuration space of each hardware device. The CPU resources required by each hardware device and the BDF of each hardware device constitute the traversal result information.

[0094] S303: Determine the current topology mode and the second resources required by the multiple PE interfaces according to the traversal result information.

[0095] For example, after the traversal is completed, the BIOS summarizes the CPU resources required by the hardware devices under each PE interface connected to the PCIe Switch, and obtains the CPU resources required by each PE interface, which is the second resource. At the same time, according to the traversal path, the connection relationship between the CPU through the PE interface and the PCIe Switch can be obtained, which is the current topology mode.

[0096] S304: Determine idle resources in the first resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and recycle at least part of the idle resources to the resource pool.

[0097] The current topology mode and historical topology mode are one of the following:

[0098] Cascade mode, general mode, balanced dual uplink mode and balanced single uplink mode; among them, cascade mode represents two PCIe Switches connected in sequence, one PCIe Switch is connected to a PE interface of a CPU; general mode represents two PCIe Switches are connected to a PE interface of the same CPU; balanced dual uplink mode represents two PCIeSwitch are connected to two PE interfaces of different CPUs; balanced single uplink mode represents two PCIe Switch are connected to a PE interface of different CPUs.

[0099] In one example, step S304 includes the following steps:

[0100] In the first step of step S304, a first preset resource is reserved for a first PE interface having a first resource, and a portion of the first resource excluding the first preset resource is recycled to a resource pool; wherein the first PE interface is not currently connected to a PCIe Switch.

[0101] The second step of step S304 is to reserve a second resource for the second PE interface having the first resource, and recycle the portion of the first resource that exceeds the second resource to the resource pool; wherein the second PE interface is currently connected to the PCIe Switch, and the second resource of the second PE interface is less than the first resource.

[0102] For example, Figure 1 The way the CPU is connected through the PE interface and the PCIe Switch is the balanced dual uplink mode. Figure 1 For example, if Switch 0 and Switch 1 are connected, and either Switch 1 or Switch 1 is connected to a PE port, the topology mode is cascade mode;

[0103] If Switch 0 is connected to CPU 0 through a PE port, and Switch 1 is connected to CPU 1 through a PE port, and the two PE ports are different, the topology mode is balanced single uplink mode;

[0104] If Switch 0 is connected to CPU 1 through a PE port, and Switch 1 is connected to CPU 1 through a PE port, and the two PE ports are different, the topology mode is the general mode.

[0105] For the first step of step S304, if the current topology mode and the historical topology mode are inconsistent, there will be a PE interface connecting the CPU and the PCIe Switch in the historical topology mode, which is not connected in the current topology mode. In this case, it is necessary to reserve a unit resource for the disconnected PE interface, and recycle the remaining free resources to the CPU internal resource pool for resource redistribution, wherein a unit resource is a resource unit pre-set according to demand, that is, the first preset resource is a unit resource. For example, 1024G storage resources are defined as a unit resource, that is, the first preset resource reserved for the disconnected PE interface is 1024G storage resources, and the remaining resources are recycled.

[0106] For example, when the historical topology mode is balanced dual uplink mode and the current topology mode is balanced single uplink mode, and in the historical topology mode, Switch 0 is connected to CPU 0 through PE 0 and PE 2, and Switch 1 is connected to CPU 1 through PE 0 and PE 2, and in the current topology mode, Switch 0 is connected to CPU 0 through PE 0, and Switch 1 is connected to CPU 1 through PE 2, then one unit of resource needs to be reserved for the disconnected PE 2 of CPU 0 and PE 0 of CPU 1, and other resources except the first preset resource need to be recovered back to the CPU resource pool.

[0107] For the second step of step S304, if the second resource required by the PE interface connecting the CPU and the PCIe Switch in the current topology mode is much smaller than the first resource in the historical topology mode, the second resource needs to be reserved for the PE interface that remains connected, and the remaining free resources are recycled to the CPU internal resource pool for redistribution. In addition, since the CPU resources are allocated to the PE in integer units, the resource size of each unit is set by the user. Therefore, if the CPU resources required by the traversed PE interface are between n unit resources and n+1 unit resources, the second resource allocated to the PE interface should be n+1 unit resources.

[0108] For example, when the historical topology mode is cascade mode and the current topology mode is balanced single uplink mode, and in the historical topology mode, Switch 0 is connected to CPU 0 through PE 0, and Switch 1 is connected to Switch 0, and in the current topology mode, Switch 0 is connected to CPU 0 through PE 0, and Switch 1 is connected to CPU 1 through PE 2, the resources required by the PE 0 interface of CPU 0 become smaller, then the second resource needs to be reserved for the PE 0 interface of CPU 0, and the remaining free resources need to be recovered to the CPU internal resource pool.

[0109] S305: Determine the missing resources in the second resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and allocate resources to the multiple PE interfaces from the resource pool.

[0110] In one example, step S305 includes the following steps:

[0111] The first step of step S305 is to reserve the first resource for the third PE interface having the first resource, and remove part of the resources required for the first resource from the second resource allocated to the third PE interface in the resource pool; wherein the third PE interface is currently connected to the PCIe Switch, and the second resource of the third PE interface is greater than the first resource.

[0112] The second step of step S305 is to reserve the first preset resource for the fourth PE interface having the first preset resource, and remove part of the resources required by the first preset resource from the second resource allocated to the fourth PE interface in the resource pool; wherein the fourth PE interface has not been connected to the PCIe Switch in history.

[0113] Exemplarily, for the first step of step S305, the second resource required by the PE interface connecting the CPU and the PCIe Switch in the current topology mode is much greater than the first resource in the historical topology mode. It is necessary to reallocate multiple unit resources from the CPU internal resource pool to the PE interface based on the original first resource, so that the sum of the first resource and the reallocated multiple unit resources can be greater than or equal to the CPU resources required by the PE interface.

[0114] For example, if the historical topology mode is general mode and the current topology mode is cascade mode, and in the historical topology mode, Switch 0 is connected to CPU 1 through PE 0, and Switch 1 is connected to CPU 1 through PE 2, and in the current topology mode, Switch 0 is connected to CPU 1 through PE 0, and Switch 1 is connected to Switch 0, then the second resource required by the PE 0 interface of CPU 1 becomes larger, then it is necessary to reallocate multiple unit resources from the internal resource pool of CPU 1 so that the sum of the first resource and the reallocated multiple unit resources can be greater than or equal to the CPU resource required by the PE 0 interface of CPU 1.

[0115] Regarding the second step of step S305, if the current topology mode is inconsistent with the historical topology mode, there will be PE interfaces that are not connected to the CPU and PCIe Switch in the historical topology mode, which remain connected in the current topology mode. In the unconnected state, each PE interface only retains the first preset resource, that is, a default unit resource. When the CPU resources required by the PE interface obtained exceed the original unit resource, it is necessary to reallocate multiple unit resources to the PE interface from the CPU resource pool, so that the sum of the original first preset resource and the reallocated multiple unit resources can be greater than or equal to the CPU resources required by the PE interface.

[0116] For example, when the historical topology mode is balanced single uplink mode and the current topology mode is balanced dual uplink mode, and in the historical topology mode, Switch 0 is connected to CPU 0 through PE 0, and Switch 1 is connected to CPU 1 through PE 2, and in the current topology mode, Switch 0 is connected to CPU 0 through PE 0 and PE 2, and Switch 1 is connected to CPU 1 through PE 0 and PE 2, then it is necessary to reallocate multiple unit resources from the CPU resource pool to the reconnected PE 2 of CPU 0 and PE 0 of CPU 1 based on the original first preset resources, so that the PE port resources in the current topology mode can meet the hardware device requirements.

[0117] S306: Update the resource reservation information of the system according to the current topology mode and the second resource; restart the basic input and output system, and start the operating system based on the current topology mode and the second resource.

[0118] Exemplarily, the resource reservation information of the volatile storage area of ​​the BIOS is updated according to the current topology mode and the second resource, and the BIOS is restarted, so that the BIOS completes initialization based on the resource allocation method that meets the hardware device requirements, thereby starting the computer operating system.

[0119] A PCIe resource allocation method for a server provided in an embodiment of the present application obtains a historical topology mode and a first resource allocated historically, as well as a current topology mode and a second resource currently required, compares the historical and current resource allocation situations, and integrates or splits the resources allocated by the CPU to each PE interface, thereby realizing dynamic allocation of CPU resources. There is no need to update the BIOS as the topology mode changes, thereby improving the reconfiguration efficiency of CPU external devices, and also reducing the low utilization of CPU resources caused by the preset maximum resources, thereby improving the user reconfiguration experience.

[0120] Figure 4A schematic diagram of the structure of a PCIe resource allocation device for a server provided in this application is shown in FIG. Figure 4 As shown, a PCIe resource allocation device 40 for a server provided in this embodiment includes:

[0121] The first acquisition unit 401 is used to acquire a historical topology mode and a first resource historically allocated to a plurality of PE interfaces, wherein the topology mode represents a connection mode between a PCIe Switch and a CPU, and the PE interface is a port through which the CPU is connected to the PCIe Switch;

[0122] The second acquisition unit 402 is used to acquire the second resource required by the current topology mode and multiple PE interfaces;

[0123] The first processing unit 403 is used to determine idle resources in the first resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and recycle at least part of the idle resources to the resource pool;

[0124] The second processing unit 404 is configured to determine the missing resources in the second resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and allocate resources to the multiple PE interfaces from the resource pool.

[0125] In a possible implementation manner, the first acquisition unit 401 includes:

[0126] A first determination module 4011, configured to determine a historical topology mode and a first resource according to the reserved resource information;

[0127] The reserved resource information includes historical resource information and default resource information. The historical topology mode of the default resource information is empty. The first resource allocated to each PE interface by the default resource information is a preset unit resource.

[0128] In a possible implementation manner, before the second acquiring unit 402, the device further includes:

[0129] The third processing unit 405 is used to initialize the hardware device connected to the basic input and output system based on the historical topology mode and the first resource; traverse multiple PCIE devices connected to the CPU through the PCIe Switch to obtain traversal result information.

[0130] In a possible implementation manner, the second obtaining unit 402 includes:

[0131] The second determination module 4021 is used to determine the second resources required by the current topology mode and multiple PE interfaces according to the traversal result information.

[0132] In a possible implementation, the first processing unit 403 includes:

[0133] The second processing module 4031 is used to reserve the first preset resource for the first PE interface having the first resource, and recycle the part of the first resource excluding the first preset resource into the resource pool;

[0134] The first PE interface is not currently connected to the PCIe Switch.

[0135] In a possible implementation manner, the first processing unit 403 further includes:

[0136] The third processing module 4032 is used to reserve the second resource for the second PE interface having the first resource, and recycle the part of the first resource exceeding the second resource to the resource pool;

[0137] The second PE interface is currently connected to the PCIe Switch, and the second resource of the second PE interface is smaller than the first resource.

[0138] In a possible implementation, the second processing unit 404 includes:

[0139] The fourth processing module 4041 is used to reserve the first resource for the third PE interface having the first resource, and remove part of the resources required for the first resource from the second resource allocated to the third PE interface in the resource pool; wherein the third PE interface is currently connected to the PCIe Switch, and the second resource of the third PE interface is greater than the first resource.

[0140] In a possible implementation, the second processing unit 404 includes:

[0141] The fifth processing module 4042 is used to reserve the first preset resource for the fourth PE interface having the first preset resource, and remove part of the resources required by the first preset resource from the second resource allocated to the fourth PE interface in the resource pool; wherein the fourth PE interface has not been connected to the PCIe Switch in history.

[0142] In a possible implementation manner, the current topology mode and the historical topology mode are respectively one of the following:

[0143] Cascade mode, general mode, balanced dual uplink mode and balanced single uplink mode; among them,

[0144] The cascade mode indicates that two PCIe switches are connected in sequence, and one PCIe switch is connected to a PE interface of a CPU;

[0145] The general mode represents two PCIe switches connected to one PE interface of the same CPU;

[0146] The balanced dual uplink mode indicates that two PCIe switches are connected to two PE interfaces of different CPUs.

[0147] The balanced single uplink mode indicates that two PCIe switches are each connected to a PE interface of a different CPU.

[0148] In a possible implementation manner, after the second processing unit 404, the device further includes:

[0149] An updating unit 406, configured to update resource reservation information of the system according to the current topology mode and the second resource;

[0150] The restart unit 407 is used to restart the basic input and output system and start the operating system based on the current topology mode and the second resource.

[0151] The present embodiment provides a PCIe resource allocation device for a server, which can execute the method provided by the above method embodiment. The implementation principle and technical effect are similar, and are not described in detail in the present embodiment.

[0152] Figure 5 This is a schematic diagram of the structure of an electronic device provided in this application. Figure 5 As shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the device 50 also includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected via a bus 504.

[0153] In a specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the above method.

[0154] The specific implementation process of the processor 501 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.

[0155] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.

[0156] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0157] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0158] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.

[0159] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.

[0160] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.

[0161] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.

[0162] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.

[0163] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0164] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0165] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0166] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.

[0167] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A PCIe resource allocation method for a server, characterized in that: A basic input and output system applied to the server motherboard; The basic input and output system is connected to the hardware device via a PCIe Switch; the method comprises: Acquire a historical topology mode and a first resource historically allocated to a plurality of PE interfaces, wherein the topology mode represents a connection mode between a PCIe Switch and a CPU, and the PE interface is a port through which the CPU is connected to the PCIe Switch; Acquire the current topology mode and the second resource required by the plurality of PE interfaces; Determine idle resources in the first resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and recycle at least part of the idle resources to a resource pool; According to the current topology mode and the historical topology mode, the first resources, and the second resources, the missing resources in the second resources are determined, and resources are allocated to the plurality of PE interfaces from a resource pool.

2. The method according to claim 1, characterized in that The acquiring of the historical topology mode and the first resource historically allocated to the plurality of PE interfaces includes: Determine the historical topology mode and the first resource according to the reserved resource information; The reserved resource information includes historical resource information and default resource information. The historical topology mode of the default resource information is empty. The first resource allocated to each PE interface by the default resource information is a preset unit resource.

3. The method according to claim 1, characterized in that Before acquiring the current topology mode and the second resources required by the plurality of PE interfaces, the method further includes: Initializing hardware devices connected to the basic input and output system based on the historical topology pattern and the first resource; Traverse multiple PCIE devices connected to the CPU through the PCIe Switch to obtain traversal result information.

4. The method according to claim 3, characterized in that: The obtaining of the current topology mode and the second resource currently required by the plurality of PE interfaces includes: Determine the current topology mode and the second resources required by the plurality of PE interfaces according to the traversal result information.

5. The method according to claim 1, characterized in that: The determining, according to the current topology mode and the historical topology mode, the first resource, and the second resource, idle resources in the first resource, and recycling at least part of the idle resources to a resource pool, includes: A first preset resource is reserved for a first PE interface having the first resource, and a portion of the first resource excluding the first preset resource is recycled into the resource pool; wherein the first PE interface is not currently connected to the PCIe Switch.

6. The method according to claim 1, characterized in that The determining, according to the current topology mode and the historical topology mode, the first resource, and the second resource, idle resources in the first resource, and recycling at least part of the idle resources to a resource pool, includes: A second resource is reserved for a second PE interface having the first resource, and a portion of the first resource exceeding the second resource is recycled into the resource pool; wherein the second PE interface is currently connected to the PCIe Switch, and the second resource of the second PE interface is less than the first resource.

7. The method according to claim 1, characterized in that The determining, according to the current topology mode and the historical topology mode, the first resource, and the second resource, the missing resource in the second resource, and allocating resources to the plurality of PE interfaces from a resource pool, comprises: Reserve a first resource for a third PE interface having the first resource, and remove part of the resources required for the first resource from the second resource allocated to the third PE interface from the resource pool; wherein the third PE interface is currently connected to the PCIe Switch, and the second resource of the third PE interface is greater than the first resource.

8. The method according to claim 1, characterized in that The determining, according to the current topology mode and the historical topology mode, the first resource, and the second resource, the missing resource in the second resource, and allocating resources to the plurality of PE interfaces from a resource pool, comprises: The first preset resource is reserved for a fourth PE interface having the first preset resource, and part of the resources required by the first preset resource is removed from the second resource allocated to the fourth PE interface from the resource pool; wherein the fourth PE interface has not been connected to the PCIe Switch in history.

9. The method according to claim 1, characterized in that: The current topology mode and the historical topology mode are respectively one of the following: Cascade mode, general mode, balanced dual uplink mode and balanced single uplink mode; among them, The cascade mode represents that two PCIe switches are connected in sequence, wherein one PCIe switch is connected to a PE interface of a CPU; The general mode represents that two PCIe switches are connected to one PE interface of the same CPU respectively; The balanced dual uplink mode indicates that two PCIe switches are each connected to two PE interfaces of different CPUs; The balanced single uplink mode indicates that two PCIe switches are respectively connected to a PE interface of a different CPU.

10. The method according to claim 1, characterized in that After determining the missing resources in the second resource according to the current topology mode and the historical topology mode, the first resource, and the second resource, and allocating resources to the plurality of PE interfaces from a resource pool, the method further includes: Updating resource reservation information of the system according to the current topology mode and the second resource; Restarting the basic input and output system, and starting the operating system based on the current topology mode and the second resource.

11. A PCIe resource allocation device for a server, characterized in that: A basic input and output system applied to the server motherboard; The basic input and output system is connected to the hardware device through a PCIe Switch; the device includes: A first acquisition unit is used to acquire a historical topology mode and a first resource historically allocated to a plurality of PE interfaces, wherein the topology mode represents a connection mode between a PCIe Switch and a CPU, and the PE interface is a port through which the CPU is connected to the PCIe Switch; A second acquisition unit, configured to acquire a current topology mode and second resources required by the plurality of PE interfaces; A first processing unit is configured to determine idle resources in the first resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and recycle at least part of the idle resources to a resource pool; The second processing unit is used to determine the missing resources in the second resources according to the current topology mode and the historical topology mode, the first resources, and the second resources, and allocate resources to the multiple PE interfaces from the resource pool.

12. An electronic device, characterized in that: The electronic device comprises: a processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 10.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, which are used to implement the method according to any one of claims 1 to 10 when executed by a processor.

14. A computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the method according to any one of claims 1 to 10 is implemented.

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