Instruction analysis method and device and computer readable storage medium

Abstract

The invention provides an instruction analysis method and device and a computer readable storage medium, and is applied to the technical field of computers.The method comprises the steps that firstly, an information flow fragment in the process that a processor core runs a software program is obtained, the obtained information flow fragment comprises multiple information flows, and any information flow comprises a PC value and an instruction code corresponding to an instruction; according to the method, on the basis of the principle that the PC value of one instruction corresponds to the unique instruction code, the corresponding relation between the PC value and the instruction code in the information flow segment is compared, and then whether the PC value of each instruction in the information flow segment corresponds to different instruction codes or not is judged, and it is determined that the instruction with the PC value corresponding to the different instruction codes is the abnormal instruction. The abnormal instructions of different instruction codes corresponding to the PC values are determined, effective screening of the abnormal instructions is achieved, the abnormal instruction searching difficulty is reduced, the positioning period is shortened, manpower is saved, and meanwhile the verification efficiency of the processor core is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to an instruction analysis method, device and computer-readable storage medium. Background Art

[0002] The microarchitecture of the processor core includes multiple units for implementing different preset functions, such as instruction fetch units, instruction queues, launch units, and execution units. Each unit cooperates with each other to complete the execution of different instructions of the software program.

[0003] During the functional verification of the processor core, it is necessary to iteratively update the relevant units in the microarchitecture according to the verification results. The update of any unit in the microarchitecture may cause instruction exceptions, and the number of instructions that need to be run for processor core verification reaches billions. Therefore, once an abnormal instruction appears during the operation, it is extremely difficult to find it. Not only is the positioning cycle long, but it also requires a lot of manpower, which seriously affects the verification efficiency of the processor core. Summary of the invention

[0004] In view of this, the present application is committed to providing an instruction analysis method, device and computer-readable storage medium to solve the problem in the prior art that the abnormal instruction positioning cycle is long, consumes a lot of manpower, and seriously affects the efficiency of processor core verification.

[0005] In a first aspect, the present application provides an instruction analysis method, comprising:

[0006] Acquire an information flow segment during the process of the processor core running the software program, wherein the information flow segment includes multiple information flows, and the information flow includes a program counter PC value corresponding to the instruction and an instruction code;

[0007] respectively determining whether the PC value of each instruction in the information stream segment corresponds to a different instruction code;

[0008] Determine that the instructions whose PC values ​​correspond to different instruction codes are abnormal instructions.

[0009] In an optional implementation manner, the respectively determining whether the PC value of each instruction in the information stream segment corresponds to a different instruction code includes:

[0010] Extracting a first information flow and a second information flow from the information flow segment, wherein the first information flow includes any information flow in the information flow segment, and the second information flow includes any information flow in the information flow segment other than the first information flow;

[0011] Determining whether the PC value in the first information flow is the same as the PC value in the second information flow;

[0012] If they are the same, determine whether the instruction code in the first information stream is the same as the instruction code in the second information stream.

[0013] In an optional implementation, determining that instructions whose PC values ​​correspond to different instruction codes are abnormal instructions includes:

[0014] If the PC value in the first information stream is the same as the PC value in the second information stream, and the instruction code in the first information stream is different from the instruction code in the second information stream, it is determined that the instruction corresponding to the PC value in the first information stream is an abnormal instruction.

[0015] In an optional implementation manner, extracting the first information flow from the information flow segment includes:

[0016] According to the sequence of the information flows recorded in the information flow segment, each of the information flows is sequentially used as the first information flow;

[0017] The PC value and instruction code in the first information stream are recorded according to a preset data format.

[0018] In an optional implementation, recording the PC value and the instruction code in the first information stream according to a preset data format includes:

[0019] Create an array of key-value pairs;

[0020] The PC value and instruction code in the first information stream are stored in the key-value pair array.

[0021] In an optional embodiment, the method further includes:

[0022] If the PC value of the first information stream is different from the PC values ​​of each of the second information streams, disassembling the instructions corresponding to the PC values ​​in the first information stream;

[0023] Based on the disassembly processing result, it is determined whether the instruction corresponding to the PC value in the first information flow is abnormal.

[0024] In an optional implementation, determining whether the instruction corresponding to the PC value in the first information flow is abnormal based on the disassembly processing result includes:

[0025] Extract the current instruction code included in the disassembly result;

[0026] Obtaining an initial instruction code in the first information stream;

[0027] If the current instruction code is consistent with the initial instruction code, it is determined that the instruction corresponding to the PC value in the first information stream is normal;

[0028] If the current instruction code is inconsistent with the initial instruction code, it is determined that the instruction corresponding to the PC value in the first information flow is abnormal.

[0029] In an optional implementation, the method further includes: performing a fault analysis on the processor core according to the abnormal instruction.

[0030] In a second aspect, the present application provides an instruction analysis device, including: a loading module and a diagnosis module, wherein:

[0031] The loading module is used to load the processor core and control the processor core to execute the software program;

[0032] The diagnostic module is communicatively connected to the loading module, and is used to execute the instruction analysis method as described in any one of the first aspects of the present application.

[0033] In a third aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the instruction analysis method as described in any one of the first aspects of the present application are implemented.

[0034] Based on the above content, the instruction analysis method provided by the present application first obtains an information flow segment in the process of the processor core running the software program, the obtained information flow segment includes multiple information flows, and any information flow includes the PC value and instruction code corresponding to the instruction, and then judges whether the PC value of each instruction in the information flow segment corresponds to a different instruction code, and determines that the instruction with the PC value corresponding to the different instruction code is an abnormal instruction. The method is based on the principle that the PC value of an instruction corresponds to a unique instruction code. By comparing the correspondence between the PC value and the instruction code in the information flow segment, the abnormal instruction with the PC value corresponding to the different instruction code is determined, thereby realizing effective screening of abnormal instructions, reducing the difficulty of finding abnormal instructions, shortening the positioning cycle, saving manpower, and improving the verification efficiency of the processor core. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 It is a flow chart of an instruction analysis method provided by an embodiment of the present invention.

[0037] Figure 2 It is a flow chart of another instruction analysis method provided by an embodiment of the present invention.

[0038] Figure 3 It is a structural block diagram of an instruction analysis device provided by an embodiment of the present invention.

[0039] Figure 4 It is a structural diagram of a server provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] As mentioned above, the microarchitecture of the processor core includes multiple units for implementing different preset functions, such as an instruction fetch unit, an instruction queue, an arbitration unit, a bus, a transmit unit, and an execution unit. Each unit cooperates with each other to complete the execution of different instructions of the software program. For example, the instruction fetch unit is used for instruction fetching, the instruction queue is used for preprocessing and storage of instructions before transmission, the transmit unit is used for instruction transmission, and the execution unit is used to receive instructions transmitted by the transmit unit and execute them.

[0042] Before the processor is officially delivered, the processor core needs to be functionally verified to determine whether the processor core can meet the expected functional requirements. During the functional verification of the processor core, it is necessary to iteratively update the relevant units in the micro-architecture according to the verification results until the resulting processor core can meet the expected requirements. The update of any unit in the micro-architecture may cause instruction abnormalities. In actual applications, the number of instructions that need to be run for processor core verification reaches billions. Therefore, once an abnormal instruction occurs during operation, it is extremely difficult to find the abnormal instruction. Not only is the positioning cycle long, but it also requires a lot of manpower, which seriously affects the verification efficiency of the processor core.

[0043] In order to solve the above technical problems, the present application provides an instruction analysis method, which is based on the principle that the PC value of an instruction corresponds to a unique instruction code. By comparing the correspondence between the PC value and the instruction code in the information flow segment, it is determined that the instructions with PC values ​​corresponding to different instruction codes are abnormal instructions, thereby achieving effective screening of abnormal instructions, reducing the difficulty of finding abnormal instructions, shortening the positioning cycle, saving manpower, and improving the verification efficiency of the processor core.

[0044] The instruction analysis method provided in the present application is applied to an electronic device, which may be a hardware simulation device specifically used for processor core verification, or an electronic device such as a personal computer or a laptop computer, and in some cases, may also be a remote server.

[0045] See also Figure 1 As shown, the instruction analysis method provided by the present application includes the following steps.

[0046] S100: Obtain information flow fragments during the process of the processor core running the software program.

[0047] In practical applications, the information generated during the execution of instructions can be obtained and recorded. The collection of this information is the information flow mentioned in this application. That is to say, the information flow can fully record the instructions executed in sequence during the execution of a software program by the processor core and all related information generated during the execution of the instructions. The instruction analysis method provided by this application is to complete the analysis of instructions based on the information flow generated during the execution of the software program by the processor core, and locate abnormal instructions therefrom. Considering that the information flow generated by the processor core executing any software program may include a huge amount of information, it is extremely difficult to analyze the entire information flow. Therefore, this application first obtains a part of the information flow during the execution of the software program by the processor core, that is, the information flow fragment, and performs instruction analysis based on the obtained information flow fragment.

[0048] A lot of information is generated during the execution of a software program by a processor core. The instruction analysis method provided in the present application is based on the PC (Program Counter) value and instruction code corresponding to each instruction. Therefore, the information system stream fragment obtained by the present method includes multiple information streams, and each information stream includes the PC value and instruction code corresponding to the execution of an instruction by the processor core.

[0049] In a possible implementation, the processor core is loaded on a hardware simulation device, which can simulate the application scenario of the processor core and provide the processor core with other resources required to run the software program. The information flow generated by the processor core in the process of executing the software program can be obtained through the hardware simulation device. If a fault occurs during the execution of the software program by the processor core, a certain number of instructions before the fault scene, such as millions of instructions, can be intercepted. At the same time, a certain number of instructions after the fault scene can be intercepted to obtain an information flow segment including the fault scene. With such a setting, it is possible to avoid analyzing and processing information flow segments with completely normal execution processes, and only analyze and process information flow segments including the fault scene, that is, including abnormal instructions, effectively improving the execution efficiency of instruction analysis and avoiding wasting human and material resources.

[0050] S110, respectively determining whether the PC value of each instruction in the information stream segment corresponds to a different instruction code.

[0051] In the prior art, the instruction executed by the processor core is a binary number that specifies the processor core to perform a certain operation, and usually includes two components: an instruction code (also called an operation code) and an address code. The instruction code is used to describe the function and operation properties of the instruction, that is, to describe the operation function of the instruction, and is the part of the instruction used to identify and execute specific operations, while the address code is used to indicate the operation object of the instruction.

[0052] For any instruction, the corresponding instruction code is unique, and one instruction code may correspond to multiple PC values. If the same PC value in a software program corresponds to two or more instruction codes, it can be determined that the instruction corresponding to the PC value has an exception during execution. The instruction analysis method provided in this application is implemented based on this premise.

[0053] Based on the above content, after obtaining the information stream segment, it is determined whether the PC value of each instruction in the information stream segment corresponds to a different instruction code. In an optional implementation, it can refer to Figure 2 The method shown determines whether the PC value of each instruction corresponds to a different instruction code.

[0054] S1101. Extract a first information stream and a second information stream from information stream segments.

[0055] The first information flow mentioned in this embodiment can be any information flow in the information flow segment. In practical applications, in order to prevent missing a certain information flow, each information flow can be taken as the first information flow in sequence according to the sequence of each information flow recorded in the information flow segment. Of course, the first information flow can also be extracted from the information flow segment in other ways. As long as the method can ensure that all information flows are traversed, it is optional and also falls within the protection scope of this application without exceeding the core idea of ​​this application.

[0056] Further, any information flow other than the first information flow in the information flow segment is used as the second information flow.

[0057] After determining the first information flow, the other information flows other than the first information flow in the information flow segment can be taken as the second information flow in turn, and the first information flow and the second information flow can be further compared. The screening process of the second information flow can be implemented with reference to the screening process of the first information flow, so as to ensure that all other information flows other than the first information flow are traversed, which will not be repeated here.

[0058] In an optional implementation, if in S1101 each information flow is taken as the first information flow in the order of the information flows recorded in the information flow segment, since any two information flows only need to be compared once, the information flow that has been taken as the first information flow and compared one by one with other information flows may no longer be taken as the second information flow, and may be repeatedly compared with the information flow with an earlier execution order. That is to say, in this case, each information flow in the information flow segment that has not yet been taken as the first information flow may be taken as the second information flow in turn. Such a setting can effectively reduce the number of information flow comparisons and improve the efficiency of instruction analysis.

[0059] S1102: Determine whether the PC value in the first information flow is the same as the PC value in the second information flow.

[0060] After determining the first information flow and the second information flow through the above steps, it is specifically determined whether the instructions included in the first information flow are the same as the PC values ​​included in the second information flow. If they are the same, execute S1103; if not, exit the current comparison process.

[0061] S1103: Determine whether the instruction code in the first information stream is the same as the instruction code in the second information stream.

[0062] As mentioned above, during the execution of the same software program, the same PC value corresponds to a unique instruction code. If any PC value corresponds to a different instruction code, it can be determined that the instruction corresponding to the PC value is abnormal. Based on this, when the PC value in the first information stream is the same as the PC value in the second information stream, it is further determined whether the instruction code in the first information stream is the same as the instruction code in the second information stream.

[0063] S120, determining that the instructions whose PC values ​​correspond to different instruction codes are abnormal instructions.

[0064] After the above steps, if the PC value in the first information stream is the same as the PC value in the second information stream, and the instruction code in the first information stream is different from the instruction code in the second information stream, it can be determined that the instruction corresponding to the PC value in the first information stream is an abnormal instruction.

[0065] To summarize, the instruction analysis method provided by the present application first obtains an information flow segment in the process of the processor core running the software program, the obtained information flow segment includes multiple information flows, and any information flow includes the PC value and instruction code corresponding to the instruction, and then judges whether the PC value of each instruction in the information flow segment corresponds to a different instruction code, and determines that the instruction whose PC value corresponds to different instruction codes is an abnormal instruction. The method is based on the principle that the PC value of an instruction corresponds to a unique instruction code. By comparing the correspondence between the PC value and the instruction code in the information flow segment, the abnormal instruction whose PC value corresponds to different instruction codes is determined, thereby realizing effective screening of abnormal instructions, reducing the difficulty of finding abnormal instructions, shortening the positioning cycle, saving manpower, and improving the verification efficiency of the processor core.

[0066] The following takes the iterative upgrade of the instruction fetch unit in the processor core causing instruction execution exception as an example to illustrate the execution process of the execution analysis method provided by the present application.

[0067] S1. Due to the iterative upgrade of the instruction fetch unit causing the processor core to execute instructions abnormally, an information flow segment in the process of the processor core executing software is obtained through a hardware simulation device, and the information flow segment includes the error site, that is, includes the abnormal instruction.

[0068] S2. Extract the first information stream from the information stream segments.

[0069] In an optional implementation, an information set may be first created, and then each information stream may be taken as the first information stream in the order of the information streams recorded in the information stream segment, and each information stream may be parsed to extract the PC value and instruction code in the information stream. The PC value and instruction code in the information stream may be recorded in a preset data format, and the recording results may be finally stored in the aforementioned information set.

[0070] In an optional implementation, a key-value pair array may be used to record the PC value in any information stream and the instruction code corresponding to the PC value. Based on this, after extracting the PC value and instruction code included in the first information stream, a key-value pair array may be created to store the PC value and the corresponding instruction code in the key-value pair array. For example, the key-value pair array is in the form of {key:value}, where key refers to the PC value and value refers to the instruction code corresponding to the PC value. After obtaining the key-value pair array of the first information stream, the key-value pair array of the first information stream may be stored in the information set.

[0071] S3. Sequentially use other information flows in the information flow segment that are not used as the first information flow as the second information flow.

[0072] S4. Extract the PC value and instruction code in the second information stream, and based on the information set obtained in the previous steps, determine whether the information set includes the same PC value. If not, add the PC value and instruction code in the second information stream to the value information set in the form of a key-value pair array, and continue to determine the next information stream. On the contrary, if the information set includes the same PC value, further determine whether the instruction codes in the first information stream and the second information stream are the same. If they are the same, do not perform any processing on the second information stream, and continue to determine the next information stream. If the instruction codes are different, it can be determined that the PC values ​​carried in the first information stream and the second information stream correspond to different instruction codes, and determine that the instruction corresponding to the PC value in the first information stream is an abnormal instruction.

[0073] Repeat the above steps until all information flows in the information flow segment are compared and the abnormal instructions are determined.

[0074] Based on the above comparison process, it can be seen that if an instruction in a certain information flow in the information flow segment only appears once, since there is no other information flow to compare with it, it cannot be determined whether the instruction corresponds to a different instruction code. In this case, it is difficult to directly determine that the instruction that only appears once is a normal instruction. To solve this problem, the present application also proposes the following solution based on the above embodiment.

[0075] If the PC value of the first information stream is different from the PC value of each second information stream, that is, the PC value of the first information stream only appears once in the obtained information stream segment, then the instruction corresponding to the PC value in the first information stream is further disassembled, and based on the disassembly result, it is determined whether the instruction corresponding to the PC value in the first information stream is abnormal. Specifically, after obtaining the disassembly result, the current instruction code included in the disassembly result is extracted, and at the same time, the initial instruction code in the first information stream is obtained. The initial instruction code is the instruction code set by the software designer in the process of writing the software program, and can be regarded as an absolutely correct instruction code. Based on this, if the current instruction code obtained is consistent with the initial instruction code, it can be determined that the instruction of the PC value in the first information stream is normal; on the contrary, if the current instruction code obtained is inconsistent with the initial instruction code, it is determined that the instruction corresponding to the PC value in the first information stream is abnormal.

[0076] It is understandable that in actual applications, the number of instructions that appear only once in an information flow segment is usually small. Therefore, the time required to complete instruction comparison through disassembly is limited. Compared with the method of manually searching for abnormal instructions in the prior art, this method can still significantly improve the efficiency of determining abnormal instructions, which helps to improve the verification efficiency of the processor core.

[0077] On the basis of any of the above embodiments, after determining the abnormal instruction, the processor core can be further analyzed for faults based on the abnormal instruction. For example, the processor core, especially the RTL (Register Transfer Level) design of the instruction fetch unit, is analyzed based on the abnormal instruction until the design defect is determined and the fault is eliminated. Of course, other fault analyses can also be performed on the processor core based on the abnormal instruction, which will not be listed here one by one. The specific implementation can be referred to the relevant technology, and this application does not make specific limitations on this.

[0078] Furthermore, the present application also provides an instruction analysis device, see Figure 3 As shown, the instruction analysis device provided by the present application includes: a loading module 10 and a diagnosis module 20, wherein:

[0079] The loading module 10 is used to load the processor core and control the processor core to execute the software program;

[0080] The diagnosis module 20 is in communication with the loading module 10 , and is used to execute the instruction analysis method provided in any of the above embodiments.

[0081] Below, reference Figure 4 To describe the electronic device provided by the embodiment of the present invention, the electronic device provided by the embodiment may include: at least one processor 100, at least one communication interface 200, at least one memory 300 and at least one communication bus 400;

[0082] In the embodiment of the present invention, the number of the processor 100, the communication interface 200, the memory 300, and the communication bus 400 is at least one, and the processor 100, the communication interface 200, and the memory 300 communicate with each other through the communication bus 400; obviously, Figure 4 The communication connections shown for the processor 100, the communication interface 200, the memory 300, and the communication bus 400 are merely optional;

[0083] Optionally, the communication interface 200 may be an interface of a communication module, such as an interface of a GSM module; the processor 100 may be a central processing unit CPU, or an application specific integrated circuit ASIC (Application Specific Integrated Circuit), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0084] The memory 300 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0085] The processor 100 is specifically used to execute the application program in the memory to implement the steps of the instruction analysis method described above.

[0086] In some embodiments, this embodiment further provides a computer-readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a USB flash disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., in which one or more instructions for implementing the above steps are stored. When the one or more instructions are executed by one or more processors, the processors execute the instruction analysis method described above. For the relevant specific implementation, please refer to the above description, which will not be repeated here.

[0087] In addition to the above-mentioned methods and devices, an embodiment of the present application may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps of the instruction analysis method according to various embodiments of the present application described in the above content of this specification.

[0088] The computer program product may be written in any combination of one or more programming languages ​​to write program codes for performing the operations of the embodiments of the present application, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0089] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0090] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0091] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0092] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, etc. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0093] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

[0094] The above is an explanation of the present disclosure and should not be considered as a limitation thereof. Although several exemplary embodiments of the present disclosure are described, it will be readily understood by those skilled in the art that many modifications may be made to the exemplary embodiments without departing from the novel teachings and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure as defined in the claims. It should be understood that the above is an explanation of the present disclosure and should not be considered to be limited to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The present disclosure is defined by the claims and their equivalents.

Claims

1. A command analysis method, characterized in that: include: Acquire an information flow segment during the process of the processor core running the software program, wherein the information flow segment includes multiple information flows, and the information flow includes a program counter PC value corresponding to the instruction and an instruction code; respectively determining whether the PC value of each instruction in the information stream segment corresponds to a different instruction code; Determine that the instructions whose PC values ​​correspond to different instruction codes are abnormal instructions.

2. The method according to claim 1, characterized in that The respectively determining whether the PC value of each instruction in the information stream segment corresponds to a different instruction code includes: Extracting a first information flow and a second information flow from the information flow segment, wherein the first information flow includes any information flow in the information flow segment, and the second information flow includes any information flow in the information flow segment other than the first information flow; Determining whether the PC value in the first information flow is the same as the PC value in the second information flow; If they are the same, determine whether the instruction code in the first information stream is the same as the instruction code in the second information stream.

3. The method according to claim 2, characterized in that The step of determining that the instructions whose PC values ​​correspond to different instruction codes are abnormal instructions includes: If the PC value in the first information stream is the same as the PC value in the second information stream, and the instruction code in the first information stream is different from the instruction code in the second information stream, it is determined that the instruction corresponding to the PC value in the first information stream is an abnormal instruction.

4. The method according to claim 2, characterized in that: Extracting the first information stream from the information stream fragments includes: According to the sequence of the information flows recorded in the information flow segment, each of the information flows is sequentially used as the first information flow; The PC value and instruction code in the first information stream are recorded according to a preset data format.

5. The method according to claim 4, characterized in that The PC value and the instruction code in the first information stream are recorded according to a preset data format, including: Create an array of key-value pairs; The PC value and instruction code in the first information stream are stored in the key-value pair array.

6. The method according to claim 2, characterized in that The method further comprises: If the PC value of the first information stream is different from the PC values ​​of each of the second information streams, disassembling the instructions corresponding to the PC values ​​in the first information stream; Based on the disassembly processing result, it is determined whether the instruction corresponding to the PC value in the first information flow is abnormal.

7. The method according to claim 6, characterized in that The determining whether the instruction corresponding to the PC value in the first information flow is abnormal based on the disassembly processing result includes: Extract the current instruction code included in the disassembly result; Obtaining an initial instruction code in the first information stream; If the current instruction code is consistent with the initial instruction code, it is determined that the instruction corresponding to the PC value in the first information stream is normal; If the current instruction code is inconsistent with the initial instruction code, it is determined that the instruction corresponding to the PC value in the first information flow is abnormal.

8. The method according to any one of claims 1 to 7, characterized in that: The method further includes: performing a fault analysis on the processor core according to the abnormal instruction.

9. An instruction analysis device, characterized in that: include: Loading modules and diagnostic modules, where The loading module is used to load the processor core and control the processor core to execute the software program; The diagnostic module is communicatively connected to the loading module, and is used to execute the instruction analysis method according to any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the instruction analysis method according to any one of claims 1 to 8 are implemented.

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