Data cache control method and device, medium, program product and terminal

Abstract

According to the data cache control method and device, the medium, the program product and the terminal, by adding the state field in the cache line and optimizing the control method, unified management of complex requirements of cache operation is achieved, and the management process is simplified. Core functions such as dirty bit write-back, effective cache line setting, multi-path access order preserving and replacement priority control can be realized only by inquiring and configuring a status bit once when an instruction arrives and an operation is finished. And meanwhile, the problems of high complexity, large resource consumption and poor expansibility in traditional cache management are solved. The use of the data handling unit optimizes the data exchange between the cache line and the main memory, reduces unnecessary address translation and main memory access, and improves the overall system performance. The structure is suitable for constructing a multi-level cache, can be widely applied to cache devices of various chips, and provides an efficient and reliable cache solution.

Description

Technical Field

[0001] The present application relates to the field of cache management, and in particular to a data cache control method, device, medium, program product and terminal. Background Art

[0002] The existing cache structure is mainly composed of cache lines. Each cache line contains a fixed-size data block, as well as associated metadata such as valid bits, dirty bits, and recently used timestamps. When the processor accesses the memory, it first checks whether the cache contains the required data. If it exists, it is read directly from the cache, which is called a cache hit; otherwise, the data needs to be read from the main memory and loaded into the cache, which is called a cache miss. The introduction of cache significantly improves the access efficiency of the chip because the data access speed is much faster than the main memory.

[0003] However, with the continuous improvement of performance and space requirements of modern digital systems, existing cache structures face many technical challenges. These challenges mainly stem from the inherent defects of the cache line structure, which leads to the following problems: Since the size of the cache line is fixed, the flexibility of the cache is limited. For example, it is impossible to effectively handle the dynamic changes in data access patterns, it is impossible to flexibly manage cache lines, and it is impossible to effectively solve the data synchronization problem between multi-level caches. Secondly, the access speed of the cache line structure is limited by the hardware design and it is difficult to meet the needs of higher frequencies. Summary of the invention

[0004] In view of the shortcomings of the prior art described above, the purpose of the present application is to provide a data cache control method, device, medium, program product and terminal, which are used to solve the problems of insufficient flexibility and limited access speed in existing cache systems due to inherent defects in the cache line structure.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a method for data cache control, the method comprising: receiving a cache access instruction, performing a cache access operation based on the cache access instruction, and determining whether a target cache line accessed by the cache access instruction is hit, wherein a cache group includes one or more cache lines; in response to the target cache line hit, querying whether the target cache line state is occupied; if the target cache line state is occupied, waiting for a release instruction for indicating the release of the target cache line, and performing a cache access operation after receiving the release instruction; if the target cache line state is not occupied, then Directly perform a cache access operation; in response to a target cache line miss, determine whether the cache group is full; if the cache group is full, perform a cache replacement operation to generate a free cache line; if the cache group is not full, select a free cache line based on a cache allocation strategy; read the to-be-accessed data from the main memory, and transfer the to-be-accessed data from the main memory to the free cache line; while performing a cache access operation on the target cache line, mark the status field of the target cache line as occupied, release the target cache line after the cache access operation is completed, and configure the status field based on the cache access instruction.

[0006] In some embodiments of the first aspect of the present application, the process of configuring the status field based on the cache access instruction includes: based on the cache access instruction, setting the field to a combination of one or more states of locked, occupied, dirty, clean, high priority, low priority and invalid.

[0007] In some embodiments of the first aspect of the present application, the process of performing a cache replacement operation includes: performing a priority judgment operation based on a status field of each cache line included in the cache group, and executing a cache line replacement algorithm based on the priority judgment result to generate a free cache location.

[0008] In some embodiments of the first aspect of the present application, the process of configuring the status field based on the cache access instruction includes one or more combinations of the following operations: if the cache access operation is to perform a write operation, then the status field is configured as a dirty bit after the cache access operation is completed; if the cache access operation is to perform a cache line invalidation operation, then the status field is configured as invalid after the cache access operation is completed; if the cache access instruction includes a priority parameter, then the status field is configured to the priority corresponding to the priority parameter.

[0009] In some embodiments of the first aspect of the present application, the method also includes performing one or more of the following write-back operations: after performing a cache replacement operation, performing a write-back operation on a cache line whose status field is marked as a dirty bit; after performing a cache line invalidation operation, performing a write-back operation on a cache line in a cache group whose status field is set to a dirty bit, and setting the status mark of the corresponding cache line to invalid; automatically traversing each cache line in the cache group, performing a write-back operation on a cache line whose status field contains a dirty bit, and setting the status mark of the corresponding cache line to clean.

[0010] In some embodiments of the first aspect of the present application, the process of waiting for a release instruction used to characterize the release of the target cache line and performing a cache access operation after receiving the release instruction includes: when the hit cache line is occupied by a previously executed access instruction, pausing the current cache access operation until the previous access instruction is executed, and performing the next cache access operation after it is released.

[0011] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a data cache device, including: a cache line control module: used to receive a cache access instruction, perform a cache access operation based on the cache access instruction, and determine whether the target cache line accessed by the cache access instruction is hit, wherein a cache group contains one or more cache lines; in response to the target cache line hit, query whether the target cache line state is occupied; if the target cache line state is occupied, wait for a release instruction used to characterize the release of the target cache line, and perform a cache access operation after receiving the release instruction; if the target cache line state is not occupied, directly execute Cache access operation; in response to a miss of the target cache line, determining whether the cache group is full; if the cache group is full, performing a cache replacement operation to generate a free cache line; if the cache group is not full, selecting a free cache line based on a cache allocation strategy; while performing a cache access operation on the target cache line, marking the status field of the target cache line as occupied, releasing the target cache line after the cache access operation is completed, and configuring the status field based on the cache access instruction; data handling module: used to read the data to be accessed from the main memory, and transfer the data to be accessed from the main memory to the free cache line.

[0012] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and the computer program implements the data cache control method when executed by a processor.

[0013] To achieve the above-mentioned purpose and other related purposes, the fourth aspect of the present application provides a computer program product, which includes a computer program code. When the computer program code runs on a computer, the computer implements the data cache control method.

[0014] To achieve the above-mentioned purpose and other related purposes, the fifth aspect of the present application provides an electronic terminal, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the data cache control method.

[0015] As described above, the data cache control method, device, medium, program product and terminal of the present application have the following beneficial effects: by adding a status field to the cache line, unified management of complex cache operation requirements is achieved. This structure simplifies the management process. It only needs to query and configure the status bit once when the instruction arrives and the operation ends to realize functions such as dirty bit write back, setting cache line validity, multi-way access order preservation and control replacement priority. At the same time, it also has good scalability, and new functional modules can be flexibly added according to the application scenario without increasing additional resource consumption. Through the data handling unit, the data exchange between the cache line and the main memory can be effectively managed to ensure that address conversion and main memory access are only performed when necessary, thereby improving system performance. The invention is suitable for constructing a multi-level cache structure and is widely used in cache devices of various chips, which improves the operating speed and efficiency, reduces system latency, and improves the overall performance of the device while maintaining low power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of an embodiment of a data cache control method of the present application is shown.

[0017] Figure 2 A schematic diagram of the cache line data structure in an embodiment of the data cache control method of the present application is shown.

[0018] Figure 3 A structural diagram showing a multi-level cache structure in an embodiment of a data cache control method of the present application.

[0019] Figure 4 A flow chart of another embodiment of the data cache control method of the present application is shown.

[0020] Figure 5 A structural diagram of an embodiment of a data cache control device of the present application is shown.

[0021] Figure 6 A structural diagram of an embodiment of a data cache control terminal of the present application is shown. DETAILED DESCRIPTION

[0022] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0023] Before further explaining the present application in detail, the nouns and terms involved in the embodiments of the present application are explained. The nouns and terms involved in the embodiments of the present application are subject to the following interpretations:

[0024] <1> Cache access: refers to the process by which the processor reads and writes to high-speed memory while executing a program to speed up data access. The purpose of cache is to reduce data transmission delays with main memory and improve the overall efficiency of the program. By quickly accessing the cache, the processor can significantly improve the response speed of data operations.

[0025] <2> Cache access instructions: Instructions in the computer instruction set that are specifically used to generate cache accesses, which are used to tell the processor to access data at a specific memory address. These instructions usually include data loading and storage operations, which directly affect the execution efficiency of the program. The proper use of these instructions can optimize the data processing process.

[0026] <3> Cache access operation: The specific operation of finding, inserting, updating or deleting data in the cache, involving cache hit and miss processing. When the data is found in the cache, it is called a cache hit; if the data is not in the cache, it needs to be obtained from the main memory, which usually causes access delays and affects system performance.

[0027] <4> Occupancy: refers to the usage of cache storage space. High occupancy indicates effective data storage, while low occupancy may indicate free rows. High occupancy usually means that the cache is fully utilized, which can effectively speed up data recovery, while low occupancy may indicate that cache management is not efficient enough and needs to be optimized.

[0028] <5> Release: Mark cache lines that are no longer needed as free so that they can be overwritten by new data to improve cache utilization. When some data is no longer used, the relevant cache lines can be released, allowing new data to be stored in them, thereby maintaining the dynamic and flexible nature of the cache.

[0029] <6> Cache allocation strategy: Strategies for managing data allocation and replacement in the cache, including direct mapping, fully associative, set associative, and other algorithms. These strategies determine the location of data in the cache, affecting the cache hit rate and overall performance. Different cache strategies are suitable for different types of application requirements.

[0030] <7> Free cache lines: refers to unused lines in the cache. These lines can store new data and are usually used first when loading new data. Cache management uses free lines to reduce the latency when writing new data, ensuring that the system can respond quickly when performing data operations.

[0031] <8> L1 / L2: refers to two levels of cache. The first level is located inside the CPU, with fast speed but small capacity; the second level is usually outside the CPU, with large capacity but slightly slower speed. L1 cache is faster, but due to limited space, it usually only stores the most frequently used data, while L2 cache provides more storage space to supplement the shortcomings of L1 cache.

[0032] <9> Intra-line offset: refers to the way to access specific bytes or data within a cache line, usually through the low-order portion of the address. Intra-line offset allows the processor to quickly locate the specific data location in the cache line, thereby speeding up data access.

[0033] <10> Mapping table: A data structure used to track the mapping relationship between cache blocks and main memory addresses to quickly find cache contents. The mapping table maintains the correspondence between data in main memory and cache, helping to effectively manage storage and access operations.

[0034] <11> DDR: A memory technology that allows double data transfer in the same clock cycle and is widely used to improve memory bandwidth and performance. This technology increases the data transfer rate by utilizing two opportunities of the memory channel, improving overall computing performance, and with the development of technology, DDR has evolved into multiple versions to adapt to the increasing bandwidth requirements.

[0035] This application creatively proposes to add a new status field in the cache line to dynamically control the usage status of the cache line. This application can be applied to a variety of fields and scenarios, especially in high-performance computing and storage systems, such as data processing units (DPUs), graphics processing units (GPUs), multi-core processors, and distributed systems. This mechanism can optimize data access and processing flows, improve system performance and throughput, and ensure that the access order between multiple instructions, threads, or processors is correct, thereby improving system throughput, reliability, and performance. In a variety of scenarios such as data centers, cloud computing environments, graphics rendering, and computing, this mechanism is particularly important and can improve system efficiency and reliability.

[0036] To facilitate understanding of the embodiments of the present application, first Figure 1 Detailed description. Figure 1 The following is a flow chart of a data cache control method in an embodiment of the present application. The data cache control method in this embodiment mainly includes the following steps:

[0037] Step S11: receiving a cache access instruction, performing a cache access operation based on the cache access instruction, and determining whether a target cache line accessed by the cache access instruction is hit, wherein a cache group includes one or more cache lines.

[0038] In one embodiment of the present application, when an instruction to access the cache is received, the corresponding cache group is determined by the address index. At this time, the mark bits and status bits of all cache lines in the cache group are traversed to determine whether a hit occurs. If no cache hit occurs, a new cache line needs to be allocated for the access address. If the cache group is not yet full, one of the empty cache lines in the available state will be selected for allocation.

[0039] It should be noted that this embodiment adopts a cache organization method of set associative structure. Figure 2 As shown in the figure, in the set associative structure, the cache library is divided into multiple cache groups, each of which contains multiple cache lines, and each cache line contains a tag, a status field, and cache data. The access address in the access instruction contains the cache line tag, group index, library index, and line offset. The set associative cache combines the advantages of direct mapped cache and fully associative cache, and can reduce the probability of cache conflicts while improving the cache hit rate.

[0040] Exemplarily, in one embodiment, the cache module includes 8 cache libraries, each library includes 512 groups, each group is 8-way, and can store 8 cache lines. The storage space of each library is 256K Byte, and each cache line occupies 64 Byte, so each library can store 4K cache lines. The fixed 3-bit field in the access address is used as the library index, and the 9-bit field is used as the group index. The cache line consists of a tag bit, a status field, and a data bit, where the status field is 3 bits. The 0 to 7 ways of each cache group can be set to a locked state through a register, and the locked cache line will never be reallocated, even if other cache lines are full.

[0041] In particular, the present application also sets a new field in each cache line, which is used to characterize the cache line status field. Through the status field, various status information of the cache line can be centrally marked, such as dirty bit, validity, replacement priority, and whether it is occupied. This cache control method introduces the status field, allowing the "status bit" to be queried only once when the instruction arrives, and only once when the operation ends, so as to realize multiple complex functions such as dirty bit writeback, setting cache line validity, sequentiality of multi-way access, and control of cache line replacement priority. The innovative cache line structure and control method proposed in the present application effectively and uniformly manage various complex cache operation requirements without adding too many resources and operation processes, and have excellent scalability, and can flexibly add more functions according to specific application scenarios. The operation of reading the "status field" (i.e. checking a specific state or condition) and the mark bit operation required for cache search (i.e. determining whether a certain data exists in the cache) are completed in the same clock cycle.

[0042] In one embodiment of the present application, the access instruction is an operation in an instruction set, which is used to send a request to a cache module and request access to a specific memory address. The information in the access instruction includes but is not limited to: a target address and an access type. The target address refers to the location of the data to be accessed in the main memory. The access type refers to the specific operation to be performed, such as a read operation or a write operation.

[0043] Furthermore, the access instruction in this embodiment also includes priority information for setting the target cache line after the operation is completed, and the priority setting is achieved by setting the status field of the cache line. The priority information carried in the access instruction can be used to determine the priority of the cache line, which is divided into high priority and low priority. Depending on the priority, the cache line eviction strategy will also be different. Specifically, high-priority cache lines: when there are no low-priority cache lines in the cache group, the high-priority cache lines will be evicted and marked as "priority retention"; low-priority cache lines: low-priority cache lines will be evicted first and marked as "priority eviction".

[0044] In addition, the access instruction can also be used to control the marking of the status field of the cache line as invalid and locked. Among them, the working principle of the invalid access instruction is that when a cache group receives an invalid instruction, all unlocked cache lines in the cache group will be marked as invalid. If the cache line still has a dirty bit state, its data will be pushed to the main memory. At the same time, the invalid access instruction can support the batch execution of invalid instructions on a cache group to support the status update of multiple cache lines at the same time. The cache line can also be configured to be locked under the control of the access instruction.

[0045] Step S12: In response to the target cache line hit, query whether the target cache line status is occupied; if the target cache line status is occupied, wait for a release instruction for representing the release of the target cache line, and perform a cache access operation after receiving the release instruction; if the target cache line status is not occupied, directly perform a cache access operation.

[0046] In one embodiment of the present application, the process of waiting for a release instruction for characterizing the release of the target cache line and performing a cache access operation after receiving the release instruction includes: when the hit cache line is occupied by a previously executed access instruction, pausing the current cache access operation until the previous access instruction is executed, and performing the next cache access operation after it is released.

[0047] In one embodiment of the present application, if the status field of a cache line is marked as "occupied", it means that other instructions are accessing or operating the same cache line. At this time, the current instruction needs to wait for the previous instruction to be executed and the cache line to be released before it can continue to execute. When operating on a cache line, whether it is reading, writing, setting invalid or other types of access, the status of the cache line will be set to "occupied". This ensures that other instructions cannot access or modify it while the cache line is being operated, thereby avoiding potential conflicts and data corruption. When the instruction operation is completed, the status of the cache line will be updated, and its status field will change from the "occupied" state to the state of the corresponding instruction, and the occupancy state of the cache line will be released, allowing the next instruction to access it. This mechanism ensures the security and efficiency of the cache system, enabling it to handle highly concurrent instruction access and operations.

[0048] It is worth noting that, compared with the prior art, the innovation of the embodiment is that a status field is added to the cache line, which enables the cache system to dynamically control the usage status of the cache line, thereby realizing multi-way order preservation, which is more flexible and efficient than the traditional static cache control method. The importance of multi-way order preservation lies in the ability to ensure that the access order between multiple instructions is correct, thereby avoiding data conflicts and corruption. This is particularly important in multi-core processors and distributed systems, because it is very common for multiple processors or nodes to access shared data at the same time. By implementing multi-way order preservation, the system can ensure the consistency and correctness of the data, thereby improving the stability and reliability of the system. Combined with the dynamic cache control mechanism of the embodiment, compared with the traditional multi-way order preservation method, it can better adapt to complex concurrent access scenarios and further improve the performance and reliability of the system, because the newly added status field provides more sophisticated cache line control.

[0049] Since the creative point of the present application is to use the status field to mark the status of the cache line, thereby protecting the selection of multi-way access, better controlling the usage status of the cache line, and ensuring that the access order between multiple instructions, threads or processors is correct, it can better realize the establishment and management of the multi-level cache structure. Through the cache structure of the present application, the cache and the main memory can be graded according to the consistency of the data, the cache capacity, and the size of the access delay, thereby forming a multi-level cache structure hierarchy.

[0050] Step S13: In response to a target cache line miss, determine whether the cache group is full; if the cache group is full, perform a cache replacement operation to generate a free cache line; if the cache group is not full, select a free cache line based on a cache allocation strategy; read the data to be accessed from the main memory, and transfer the data to be accessed from the main memory to the free cache line.

[0051] In one embodiment of the present application, the cache allocation strategy refers to a strategy for allocating cache lines to data newly entering the cache, so as to improve the cache hit rate and reduce the number of cache misses. The cache allocation strategy includes, but is not limited to: First-In-First-Out (FIFO), Least Recently Used (LRU), Random, Round-Robin, Dynamic, etc. First-In-First-Out refers to giving priority to allocating the free cache lines that enter the cache the earliest; Least Recently Used refers to giving priority to allocating the free cache lines that are least recently used; First-Allocation refers to randomly allocating free cache lines; Round-Robin refers to allocating free cache lines in a circular order; Dynamic allocation refers to dynamically adjusting the allocation strategy according to the cache usage pattern.

[0052] In one embodiment of the present application, a mapping table is maintained in the data handling unit. Through the mapping table maintained in the data handling unit, efficient correspondence between virtual addresses and physical addresses is achieved, that is, before accessing the memory, the mapping table is configured through a configuration command to establish a one-to-one correspondence between the virtual address and the physical address. When the cache line is replaced or written back, the data handling unit quickly searches the mapping table to convert the virtual address into a physical address, thereby ensuring the efficiency and accuracy of data exchange.

[0053] It is worth mentioning that the method of maintaining the mapping table through the data handling unit avoids the step of searching the page table when the cache hits in the traditional cache access, thereby reducing the memory access delay, improving the memory access efficiency, and optimizing the data exchange between the cache and the external main memory, and ultimately significantly improving the overall performance of the system, which has significant innovative advantages.

[0054] In one embodiment of the present application, the process of performing a cache replacement operation includes: performing a priority determination operation according to a status field of each cache line included in the cache group, and performing a cache line replacement algorithm according to the priority determination result to generate a free cache location.

[0055] In one embodiment of the present application, the process of performing cache replacement based on the status field of the cache line includes: when the cache misses and the cache group is full, the replacement priority is determined by checking the status bit of the cache line. The cache control unit determines which cache lines are swapped out first and which cache line contents are retained first based on the setting of the status bit. The data handling unit is responsible for managing the data exchange between the cache and the external main memory. When the cache line is replaced, the cache line control unit sends the exchange instruction to the data handling unit and completes the correspondence between the virtual address and the physical address by looking up the page table. The page table in this scheme only needs to be maintained in the outermost cache.

[0056] Furthermore, if Figure 3 As shown in the figure, the L1 and L2 caches can flexibly select the space size and cache replacement strategy according to actual needs, including random allocation, least recently used, earliest used and other algorithms. When cache replacement is required, the data handling unit is responsible for executing the data exchange between the cache and the main memory, and the cache line control unit issues the exchange instruction and performs page table lookup to complete the conversion from virtual address to physical address. The mapping page table of the virtual address only needs to be maintained in the outermost cache.

[0057] Compared with the prior art, the advantages of the present application lie in its flexibility. Users can dynamically adjust the space size and replacement strategy of the L1 and L2 caches according to the needs of specific applications, thereby optimizing performance; efficiency is improved by centrally managing the mapping page table to the outermost cache, reducing frequent page table lookups and improving memory access efficiency, especially in scenarios with high-frequency cache access; resource utilization, the introduction of multiple replacement strategies such as random allocation and least recently used can more effectively utilize cache resources and reduce cache miss rates; and the design is simplified by integrating page table maintenance into the outer cache, which simplifies the design and management of multi-level caches and reduces complexity.

[0058] Step S14: marking the status field of the target cache line as occupied while performing a cache access operation on the target cache line, releasing the target cache line after the cache access operation is completed, and configuring the status field based on the cache access instruction.

[0059] In one embodiment of the present application, when performing a cache access operation, the status field of the cache line must be managed to maintain stability and efficiency. First, marking the status field as "occupied" can prevent data inconsistency caused by concurrent access. After the operation is completed, the status needs to be reset to "unoccupied", and if there is any data modification, it needs to be synchronized back to the main memory to maintain consistency. In addition, configuring the status field according to the cache access instruction can optimize cache usage efficiency, reduce waiting and conflicts, and thus improve overall performance. This process ensures stability and efficiency under high concurrency.

[0060] In one embodiment of the present application, the process of configuring the status field based on the cache access instruction includes: based on the cache access instruction, setting the field to a combination of one or more states of locked, occupied, dirty, clean, high priority, low priority and invalid.

[0061] In this embodiment, in the cache access instruction, each bit of the status field represents a different state of the cache line to ensure cache management and data consistency. The main states include: locked indicates that the cache line cannot be modified; occupied indicates that the cache line stores valid data; dirty indicates that the data has been modified and needs to be updated to the main memory when written back; clean indicates that the data is consistent with the main memory and can be safely discarded; high priority and low priority indicate the priority of the access request respectively to optimize request processing; invalid indicates that the data is no longer valid to avoid erroneous access. These status fields help the system efficiently manage the cache, maintain data consistency, and improve overall operating efficiency during the cache read process.

[0062] Specifically, the status field is as shown in Table 1, 0x0 indicates a locked state; 0x1 indicates an occupied state; 0x2 indicates a high priority dirty state; 0x3 indicates a low priority dirty state; 0x4 indicates a high priority clean state; 0x5 indicates a low priority clean state; 0x6 indicates an invalid state.

[0063] Status field data Status field meaning 0x0 Locked state 0x1 Occupied state 0x2 Dirty bit status (high priority) 0x3 Dirty bit status (low priority) 0x4 Clean state (high priority) 0x5 Clean state (low priority) 0x6 Invalid state

[0064] Table 1: Status field data and corresponding meanings

[0065] In one embodiment of the present application, the process of configuring the status field based on the cache access instruction includes one or more combinations of the following operations: if the cache access operation is to perform a write operation, then after the cache access operation is completed, the status field is configured as a dirty bit; if the cache access operation is to perform a cache line invalidation operation, then after the cache access operation is completed, the status field is configured as invalid; if the cache access instruction includes a priority parameter, then the status field is configured to a priority corresponding to the priority parameter.

[0066] In one embodiment of the present application, the method also includes performing one or more of the following write-back operations: after performing a cache replacement operation, performing a write-back operation on a cache line whose status field is marked as a dirty bit; after performing a cache line invalidation operation, performing a write-back operation on a cache line in a cache group that is set to a dirty bit, and setting the status mark of the corresponding cache line to invalid; automatically traversing each cache line in the cache group, performing a write-back operation on a cache line whose status field contains a dirty bit, and setting the status mark of the corresponding cache line to clean.

[0067] In this embodiment, when replacing a dirty bit cache line, the process of writing back to the main memory to maintain consistency includes: when the cache is full and new data needs to be written to the cache, a cache replacement operation occurs. In this process, if there is a dirty bit in the replaced cache line (that is, the data in the cache line has been modified but has not been written back to the main memory), the cache line needs to be written back to the main memory. This ensures that the latest copy of the data is kept in the main memory to avoid data loss.

[0068] In this embodiment, the process of writing the invalid dirty bit cache line back to the main memory and marking it as invalid includes: the cache line invalidation operation usually occurs when the data is no longer needed or the cache needs to be reallocated. If the cache line is marked as dirty, it indicates that its data has been modified. In this case, the cache line needs to be written back to the main memory to maintain data consistency and mark the state of the cache line as invalid to avoid future misuse of expired data.

[0069] In this embodiment, the process of periodically writing back all dirty cache lines and marking them as clean is a periodic cleaning operation, which is used to ensure that dirty data in the cache is written back to the main memory in a timely manner. By traversing each cache line in the cache group, all dirty cache lines can be found and written back to the main memory, and then the state is marked as clean. This helps to maintain data consistency between the cache and the main memory and avoid data loss due to cache write-back delay.

[0070] In hardware, specific register bits are set in the cache module to enable or disable features, especially the cache write-back mechanism. Register configuration can determine whether dirty data is written back to main memory when the cache is replaced, invalidated, or cleaned, control cache behavior (such as size and replacement policy), and optimize system performance according to operating conditions.

[0071] Figure 4 A schematic diagram of a cache control method according to another embodiment of the present application is shown. Figure 4As shown, when an access instruction is received, the corresponding cache group is indexed through the access instruction, and the cache hit is judged. If there is a cache line with the corresponding mark and its status is not invalid, it is determined to be a cache hit, otherwise it is determined to be a cache miss. If the cache hits, it further queries whether the cache line status is occupied. If occupied, wait for the previous instruction to release the cache line, and access the cache after release to perform read and write operations, and set the status field of the current cache line to occupied.

[0072] On the other hand, if the cache misses, it is further determined whether the cache group is full. If the cache group is full, the priority is determined based on the cache line status, and the corresponding replacement algorithm is executed. Otherwise, the physical address is indexed by the data handling unit, and the new cache line is transferred from the main memory to the empty cache location. Then the cache is accessed and the corresponding read and write operations, or other types of cache access operations, are performed. Finally, after the cache access operation is completed, the cache line is released, and the status of the cache line is marked according to the access instruction to end the entire cache access process.

[0073] It should be noted that in the embodiments of the present application, words such as "exemplary" or "for example" represent examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0074] In the embodiments of the present application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple.

[0075] Figure 5 is a schematic block diagram of a data cache device provided in an embodiment of the present application. Figure 5 As shown, the device includes a cache line control module 501 and a data handling module 502 .

[0076] Cache line control module 501: used to receive cache access instructions, perform cache access operations based on the cache access instructions, and determine whether the target cache line accessed by the cache access instruction hits, wherein the cache group contains one or more cache lines; in response to the target cache line hit, query whether the target cache line state is occupied; if the target cache line state is occupied, wait for a release instruction for representing the release of the target cache line, and perform a cache access operation after receiving the release instruction; if the target cache line state is not occupied, directly perform a cache access operation; in response to the target cache line miss, determine whether the cache group is full; if the cache group is full, perform a cache replacement operation to generate a free cache line; if the cache group is not full, select a free cache line based on a cache allocation strategy; while performing a cache access operation on the target cache line, mark the state field of the target cache line as occupied, release the target cache line after the cache access operation is completed, and configure the state field based on the cache access instruction.

[0077] The data handling module 502 is used to read the to-be-accessed data from the main memory, and transfer the to-be-accessed data from the main memory to the free cache line.

[0078] The present application efficiently manages the data exchange between the cache and the external main memory through a data handling unit. When a cache line needs to be replaced or written back, the cache line control unit sends a corresponding exchange instruction to the data handling unit. In this process, the mapping table is responsible for quickly matching the virtual address with the physical address. Specifically, when performing data exchange, the mapping table is searched to determine the physical address to be operated, thereby achieving accurate data positioning.

[0079] Compared with the existing technology, this solution significantly reduces the memory access latency when the cache hits by optimizing the use of mapping tables. In the traditional solution, each cache hit requires a page table search, which introduces additional time overhead. In this solution, the introduction of the mapping table enables direct access to the physical address when the cache hits, avoiding unnecessary page table searches and greatly improving the efficiency of memory access. This innovation not only improves the speed of data exchange, but also lays the foundation for improving the performance of the entire calculation.

[0080] It should be understood that the specific process of each module executing the above corresponding steps has been described in detail in the above method embodiment, and for the sake of brevity, it will not be repeated here.

[0081] It should also be understood that the division of modules in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional module in each embodiment of the present application may be integrated into a processor, or may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated modules may be implemented in the form of hardware or in the form of software functional modules.

[0082] Figure 6 is a schematic block diagram of an electronic terminal provided in an embodiment of the present application. Figure 6 As shown, the electronic terminal includes: at least one processor 601, a memory 602, at least one network interface 603 and a user interface 605. The various components in the device are coupled together through a bus system 604. It can be understood that the bus system 604 is used to realize the connection and communication between these components. In addition to the data bus, the bus system 604 also includes a power bus, a control bus and a status signal bus. However, for the sake of clarity, Figure 6 In the specification, various buses are labeled as bus systems.

[0083] The user interface 605 may include a display, a keyboard, a mouse, a trackball, a click gun, keys, buttons, a touch pad or a touch screen.

[0084] It is understood that the memory 602 can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), which is used as an external cache. By way of exemplary but not limiting explanation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM). The memory described in the embodiments of the present application is intended to include but is not limited to these and any other suitable categories of memory.

[0085] The memory 602 in the embodiment of the present application is used to store various categories of data to support the operation of the electronic terminal 600. Examples of these data include: any executable program for operating on the electronic terminal 600, such as an operating system 6021 and an application 6022; the operating system 6021 includes various system programs, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks. The application 6022 may include various applications, such as a media player (Media Player), a browser (Browser), etc., for implementing various application services. The data cache control method provided in the embodiment of the present application may be included in the application 6022.

[0086] The method disclosed in the above embodiment of the present application can be applied to the processor 601, or implemented by the processor 601. The processor 601 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor 601 or an instruction in the form of software. The above processor 601 may be a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The processor 601 can implement or execute the various methods, steps and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor 601 may be a microprocessor or any conventional processor, etc. In combination with the steps of the accessory optimization method provided in the embodiment of the present application, it can be directly embodied as a hardware decoding processor to execute, or it can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium, which is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0087] In an exemplary embodiment, the electronic terminal 600 may be implemented by one or more application specific integrated circuits (ASIC), DSP, programmable logic device (PLD), complex programmable logic device (CPLD) to execute the aforementioned method.

[0088] According to the method provided in the embodiments of the present application, the present application also provides a computer program product, which includes: computer program code, when the computer program code runs on a computer, the computer executes the data cache control method of any embodiment shown in the above embodiments.

[0089] According to the method provided in the embodiments of the present application, the present application also provides a computer-readable storage medium, which stores a program code. When the program code runs on a computer, the computer executes the data cache control method of any one of the embodiments shown above.

[0090] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process, a processor, an object, an executable file, an execution thread, a program and / or a computer running on a processor. By way of illustration, both applications and computing devices running on a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0091] Those of ordinary skill in the art will appreciate that the various illustrative logical blocks and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0092] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0093] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0094] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0096] In the above embodiments, the functions of each functional unit can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions (programs). When the computer program instructions (programs) are loaded and executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (Digital Subscriber Line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. Available media may be magnetic media (e.g., floppy disks, hard disks, tapes), optical media (e.g., high-density digital video discs (DVDs), or semiconductor media (e.g., solid state disks (SSDs)).

[0097] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program codes.

[0098] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0099] In summary, the present application provides a data cache control method, device, medium, program product and terminal. By adding a status field to the cache line and optimizing the control method, unified management of complex cache operation requirements is achieved, simplifying the management process. Only by querying and configuring the status bit once when the instruction arrives and the operation ends, the core functions such as dirty bit write back, setting cache line validity, multi-way access order preservation and control replacement priority can be realized. At the same time, it solves the problems of high complexity, high resource consumption and poor scalability in traditional cache management. The use of data handling units optimizes the data exchange between cache lines and main memory, reduces unnecessary address conversion and main memory access, and improves the overall system performance. This structure is suitable for building a multi-level cache, and can be widely used in cache devices of various chips, providing an efficient and reliable cache solution. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0100] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A data cache control method, characterized in that: The method comprises: Receiving a cache access instruction, performing a cache access operation based on the cache access instruction, and determining whether a target cache line accessed by the cache access instruction is hit, wherein a cache group includes one or more cache lines; In response to the target cache line hit, query whether the target cache line state is occupied; if the target cache line state is occupied, wait for a release instruction for representing the release of the target cache line, and perform a cache access operation after receiving the release instruction; if the target cache line state is not occupied, directly perform a cache access operation; In response to a target cache line miss, determining whether the cache group is full; if the cache group is full, performing a cache replacement operation to generate a free cache line; if the cache group is not full, selecting a free cache line based on a cache allocation policy; reading to-be-accessed data from a main memory, and transferring the to-be-accessed data from the main memory to the free cache line; The state field of the target cache line is marked as occupied while performing a cache access operation on the target cache line, the target cache line is released after the cache access operation is completed, and the state field is configured based on the cache access instruction.

2. The data cache control method according to claim 1, characterized in that: The process of configuring the status field based on the cache access instruction includes: setting the field to a combination of one or more states of locked, occupied, dirty, clean, high priority, low priority and invalid based on the cache access instruction.

3. The data cache control method according to claim 2, characterized in that: The process of performing a cache replacement operation includes: performing a priority determination operation according to a status field of each cache line included in the cache group, and performing a cache line replacement algorithm according to a priority determination result to generate a free cache position.

4. The data cache control method according to claim 2, characterized in that: The process of configuring the status field based on the cache access instruction includes one or more combinations of the following operations: If the cache access operation is to perform a write operation, then after the cache access operation is completed, the status field is configured as a dirty bit; If the cache access operation is to perform a cache line invalidation operation, then after the cache access operation is completed, the status field is configured to be invalid; If the cache access instruction includes a priority parameter, the status field is configured to have a priority corresponding to the priority parameter.

5. The data cache control method according to claim 2, characterized in that: The method further comprises performing one or more of the following write-back operations: After performing the cache replacement operation, performing a write-back operation on the cache line whose status field is marked as a dirty bit; After the cache line invalidation operation is performed, a write-back operation is performed on the cache line with the dirty bit set in the cache group, and the status flag of the corresponding cache line is set to invalid; Automatically traverse each cache line in the cache group, perform writeback operations on cache lines whose status fields contain dirty bits, and set the status flags of the corresponding cache lines to clean.

6. The data cache control method according to claim 1, characterized in that: The process of waiting for a release instruction for representing the release of the target cache line and performing a cache access operation after receiving the release instruction includes: when the hit cache line is occupied by a previously executed access instruction, pausing the current cache access operation until the previous access instruction is executed, and performing the next cache access operation after it is released.

7. A data cache device, characterized in that: include: A cache line control module: used to receive a cache access instruction, perform a cache access operation based on the cache access instruction, and determine whether a target cache line accessed by the cache access instruction is hit, wherein a cache group includes one or more cache lines; in response to the target cache line hit, query whether the target cache line state is occupied; if the target cache line state is occupied, wait for a release instruction for representing the release of the target cache line, and perform a cache access operation after receiving the release instruction; if the target cache line state is not occupied, directly perform a cache access operation; in response to the target cache line miss, determine whether the cache group is full; if the cache group is full, perform a cache replacement operation to generate a free cache line; If the cache group is not full, selecting a free cache line based on a cache allocation policy; marking a status field of the target cache line as occupied while performing a cache access operation on the target cache line, releasing the target cache line after the cache access operation is completed, and configuring the status field based on the cache access instruction; Data handling module: used for reading the to-be-accessed data from the main memory, and transferring the to-be-accessed data from the main memory into the free cache line.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the data cache control method according to any one of claims 1 to 6 is implemented.

9. A computer program product, characterized in that The computer program product includes computer program codes, and when the computer program codes are executed on a computer, the computer is enabled to implement the data cache control method according to any one of claims 1 to 6.

10. An electronic terminal comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the data cache control method according to any one of claims 1 to 6.

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