Optical memory module and optical computing system including the same

Abstract

The invention relates to an optical memory module and an optical computing system including the same. The optical memory module includes a substrate, a first memory controller on the substrate, and a plurality of first memory devices on the substrate. The first memory controller includes a first transceiver. The first transceiver receives a first optical input signal through the first optical interconnect or outputs a first optical output signal through the first optical interconnect. The first memory controller is optically connected to an optical logic module external to the optical memory module through a first transceiver and a first optical interconnect. The plurality of first memory devices are controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the first transceiver, and the first optical interconnect.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate generally to semiconductor integrated circuits, and more particularly, to optical memory modules and optical computing systems including the optical memory modules. Background Art

[0002] Recently, it has been desired to increase the memory bandwidth for high-performance computing (e.g., artificial intelligence (AI) and graphics processing units (GPUs)). When AI is applied to various fields, AI computing and / or learning requires a large amount of memory resources. For example, a GPU for AI computing can access a large amount of memory at high speed, and AI workloads may continue to require high memory bandwidth to implement a high-density computing structure in the GPU. If the memory capacity is insufficient, the performance may be reduced when executing the process. Therefore, various methods of increasing the memory capacity have been proposed. Summary of the invention

[0003] According to an example embodiment, an optical memory module may include a substrate, a first memory controller on the substrate, and a plurality of first memory devices on the substrate. The first memory controller includes a first transceiver. The first transceiver receives a first optical input signal through a first optical interconnect or outputs a first optical output signal through the first optical interconnect. The first memory controller is optically connected to an optical logic module located outside the optical memory module through the first transceiver and the first optical interconnect. The plurality of first memory devices are controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the first transceiver, and the first optical interconnect.

[0004] According to example embodiments, an optical computing system may include an optical logic module, a first optical memory module, and a first optical interconnect. The first optical memory module optically communicates with the optical logic module. The first optical interconnect optically connects the optical logic module with the first optical memory module. The optical logic module includes a first substrate and a first processing device on the first substrate. The first processing device includes a first transceiver. The first transceiver outputs a first optical signal through the first optical interconnect or receives a second optical signal through the first optical interconnect. The first processing device is optically connected to the first optical memory module through the first transceiver and the first optical interconnect. The first optical memory module includes a second substrate, a first memory controller on the second substrate, and a plurality of first memory devices on the second substrate. The first memory controller includes a second transceiver. The second transceiver receives the first optical signal through the first optical interconnect or outputs the second optical signal through the first optical interconnect. The first memory controller is optically connected to the optical logic module through the second transceiver and the first optical interconnect. The plurality of first memory devices are controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the second transceiver, and the first optical interconnect.

[0005] According to example embodiments, an optical memory module may include a substrate, a first memory controller on the substrate, a plurality of first memory devices on the substrate, a second memory controller on the substrate, and a plurality of second memory devices on the substrate. The first memory controller includes a first transceiver. The first transceiver receives a first optical input signal through a first optical interconnect or outputs a first optical output signal through the first optical interconnect. The first memory controller is optically connected to an optical logic module located outside the optical memory module through the first transceiver and the first optical interconnect. The plurality of first memory devices are controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the first transceiver, and the first optical interconnect. The second memory controller includes a second transceiver. The second transceiver receives a second optical input signal through a second optical interconnect or outputs a second optical output signal through a second optical interconnect. The second memory controller is optically connected to the optical logic module through a second transceiver and a second optical interconnect. The plurality of second memory devices are controlled by the second memory controller and accessed by the optical logic module through the second memory controller, the second transceiver, and the second optical interconnect. The first transceiver includes a photonic integrated circuit (PIC), an electrical integrated circuit (EIC), and a serializer and deserializer (SERDES). The photonic integrated circuit generates a first electrical input signal based on a first optical input signal or generates a first optical output signal based on a first electrical output signal. The electrical integrated circuit generates a first signal based on the first electrical input signal or generates a first electrical output signal based on a second signal. The first signal is provided to a first memory controller and a plurality of first memory devices. The second signal is provided from the first memory controller and the plurality of first memory devices. The serializer and the deserializer perform serial-to-parallel conversion on the first signal or perform parallel-to-serial conversion on the second signal. The optical memory module is a disaggregated package physically separated from the optical logic module and is connected to the optical logic module through a first optical interconnect and a second optical interconnect without an interposer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0007] Figure 1 is a block diagram illustrating an optical memory module and an optical computing system including the optical memory module according to example embodiments.

[0008] Figure 2 is a cross-sectional view of an example of an optical memory module according to example embodiments.

[0009] Figure 3 is a cross-sectional view of an example of an optical logic module according to example embodiments.

[0010] Figure 4A and Figure 4B is a block diagram illustrating an example of a transceiver included in an optical memory module according to example embodiments.

[0011] Figure 5A and Figure 5B is a block diagram illustrating an example of a transceiver included in an optical logic module according to example embodiments.

[0012] Fig. 6A and Figure 6B is a cross-sectional view of an example of an optical memory module according to example embodiments.

[0013] Figure 7 is a block diagram illustrating an example of a memory device included in an optical memory module according to example embodiments.

[0014] Figure 8 is a block diagram illustrating an example of a memory controller included in an optical memory module according to example embodiments.

[0015] Fig. 9 and Fig.10 is a block diagram illustrating an optical memory module and an optical computing system including the optical memory module according to example embodiments.

[0016] Fig.11A and Fig. 11B is a cross-sectional view of an example of an optical logic module according to example embodiments.

[0017] Fig.12 is a block diagram illustrating an optical memory module and an optical computing system including the optical memory module according to example embodiments.

[0018] Fig.13 is a block diagram illustrating an electronic system according to example embodiments.

[0019] Fig.14 is a block diagram illustrating a data center including a storage device according to an example embodiment. DETAILED DESCRIPTION

[0020] Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0021] Figure 1 is a block diagram illustrating an optical memory module and an optical computing system including the optical memory module according to example embodiments.

[0022] refer to Figure 1, the optical computing system 100 may include an optical interconnect 120 , an optical logic module 300 , and an optical memory module 500 .

[0023] The optical interconnect 120 optically connects the optical logic module 300 with the optical memory module 500. For example, the optical interconnect 120 may include a component that transmits an optical signal, such as an optical fiber. The optical interconnect 120 may be referred to as an optical link.

[0024] In integrated circuits, an optical interconnect (or interconnect) refers to any system that uses light to transmit signals from one part of an integrated circuit to another. Optical interconnects have become a subject of research due to the high latency and power consumption caused by traditional metal interconnects in transmitting electrical signals over long distances. In electrical interconnects, nonlinear signals (e.g., digital signals) are typically transmitted over copper wires, and these wires have resistance and capacitance that severely limit the rise time of the signal when the size of the wires is scaled down. Optical solutions can be used to transmit signals over long distances to replace the interconnects between dies within an integrated circuit (IC) package. For example, in order to properly control optical signals within a small IC package, microelectromechanical systems (MEMS) technology can be used to effectively integrate optical components (e.g., optical waveguides, optical fibers, lenses, mirrors, optical actuators, optical sensors, etc.) and electronic components.

[0025] The optical logic module 300 may be optically connected to the optical memory module 500 through the optical interconnect 120 and control the overall operation of the optical computing system 100. The optical memory module 500 may be optically connected to the optical logic module 300 through the optical interconnect 120 and store data used in the operation of the optical computing system 100.

[0026] The optical logic module 300 and the optical storage module 500 may exchange optical signals OS11 and OS12. For example, the optical logic module 300 may output the first optical signal OS11 through the optical interconnect 120, and the optical storage module 500 may receive the first optical signal OS11 transmitted through the optical interconnect 120. For example, the optical storage module 500 may output the second optical signal OS12 through the optical interconnect 120, and the optical logic module 300 may receive the second optical signal OS12 transmitted through the optical interconnect 120.

[0027] Each of the optical signals OS11 and OS12 may be defined as an optical input signal or an optical output signal with respect to one of the optical logic module 300 and the optical storage module 500. For example, from the perspective of the optical logic module 300, the first optical signal OS11 may be defined as an optical output signal, and the second optical signal OS12 may be defined as an optical input signal. For example, from the perspective of the optical storage module 500, the first optical signal OS11 may be defined as an optical input signal, and the second optical signal OS12 may be defined as an optical output signal.

[0028] In some example embodiments, the optical signals OS11 and OS12 may be signals associated or related to a data write / read operation performed on the optical memory module 500. For example, when a data write operation is to be performed on the optical memory module 500, the optical logic module 300 may transmit a first optical signal OS11 including a write request (or command), a write address, and write data to the optical memory module 500. For example, when a data read operation is to be performed on the optical storage module 500, the optical logic module 300 may transmit a first optical signal OS11 including a read request (or command) and a read address to the optical storage module 500, and the optical storage module 500 may transmit a second optical signal OS12 including read data to the optical logic module 300. In another example, the optical signals OS11 and OS12 may be signals associated with at least one of various operations of the optical computing system 100, the optical logic module 300, and / or the optical memory module 500.

[0029] The optical logic module 300 may include a processing device 320. The processing device 320 controls the operation of the optical logic module 300 and performs various functions, calculations, jobs, and / or tasks. For example, the processing device 320 may be one of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), and a system on a chip (SoC). The processing device 320 may operate as a host of the optical memory module 500 and may be referred to as a logic semiconductor device.

[0030] For example, Figure 1 As shown, the optical logic module 300 may include a single processing device 320. In another example, as will be referred to in Fig.10 and Fig.12 As described, an optical logic module may include two or more processing devices.

[0031] The processing device 320 may include a transceiver 321. The transceiver 321 is located or provided in the processing device 320 and is directly connected to the optical interconnect 120. The transceiver 321 outputs the first optical signal OS11 through the optical interconnect 120 or receives the second optical signal OS12 through the optical interconnect 120. The processing device 320 is optically connected to the optical storage module 500 through the transceiver 321 and the optical interconnect 120. The transceiver 321 may be referred to as an optical transceiver.

[0032] Will refer to Figure 3 An example of an optical logic module 300 is described and reference will be made to Figure 5A and Figure 5B An example of the transceiver 321 is described.

[0033] The optical memory module 500 may include a memory controller 520 and a plurality of memory devices 530. The memory controller 520 controls the operation of the optical memory module 500. The plurality of memory devices 530 are controlled by the memory controller 520 and store data. For example, each of the plurality of memory devices 530 may be a memory device disposed adjacent to a logic semiconductor device. For example, each of the plurality of memory devices 530 may be one of a high bandwidth memory (HBM) device and a graphic double data rate (GDDR) memory device.

[0034] For example, Figure 1 As shown, the optical memory module 500 may include a single memory controller 520 and a memory device 530 connected thereto. Fig. 9 As described, an optical memory module may include two or more memory controllers and memory devices connected thereto.

[0035] The memory controller 520 may include a transceiver 521. The transceiver 521 is located or provided in the memory controller 520 and is directly connected to the optical interconnect 120. The transceiver 521 receives the first optical signal OS11 through the optical interconnect 120 or outputs the second optical signal OS12 through the optical interconnect 120. The memory controller 520 is optically connected to the optical logic module 300 through the transceiver 521 and the optical interconnect 120.

[0036] The plurality of memory devices 530 are accessed by the optical logic module 300 through the memory controller 520, the transceiver 521, and the optical interconnect 120. For example, under the control of the optical logic module 300, data write / read operations may be performed on the optical memory module 500 (e.g., on the plurality of memory devices 530).

[0037] Will refer to Figure 2 An example of an optical storage module 500 is described and reference will be made to Figure 4A and Figure 4B An example of the transceiver 521 is described. Figure 7 and Figure 8 An example of the memory device 530 and an example of the memory controller 520 are described.

[0038] In some example embodiments, the optical logic module 300 and the optical memory module 500 may be disaggregated packages that are physically separated from each other. In other words, the optical logic module 300 and the optical memory module 500 may not be included in a single package and may be independently (e.g., separately) manufactured and then optically connected via the optical interconnect 120.

[0039] In the optical memory module 500 and the optical computing system 100 according to the example embodiment, memory disaggregation may be implemented using co-packaged optics (CPO) technology. For example, an optical logic module 300 including a processing device 320 and an optical memory module 500 including a memory device 530 may be implemented in disaggregated or separate packages, rather than implementing the processing device 320 and the memory device 530 in a single package, and the optical logic module 300 and the optical memory module 500 may be optically connected through an optical interconnect 120. In addition, transceivers 321 and 521 for connecting to the optical interconnect 120 may be formed in the processing device 320 and the memory controller 520, respectively. Therefore, the capacity (or density) and bandwidth of a memory device connected to one processing device may be effectively expanded, the manufacturing cost may be reduced by connecting the processing device to the memory device without an interposer, and problems such as heat generation, power consumption, and size constraints may be effectively addressed.

[0040] Figure 2 is a cross-sectional view of an example of an optical memory module according to example embodiments.

[0041] refer to Figure 2 , the optical memory module 500a may include a substrate 510, a memory controller (MC) 520, and a plurality of memory devices (MEM1, MEM2, ..., MEMM) 530. The memory module may be referred to as a memory package, a memory chip, or the like.

[0042] The substrate 510 may have an upper surface and a lower surface opposite to each other. For example, the substrate 510 may be a printed circuit board (PCB). The PCB may be a multilayer circuit board including through holes and various circuits. The substrate 510 may also be referred to as a base substrate or a package substrate, etc.

[0043] The memory controller 520 and the plurality of memory devices 530 may be formed or disposed on the substrate 510. Figure 2In an example, the memory controller 520 and the plurality of memory devices 530 may be sequentially stacked in a vertical direction on the substrate 510. For example, the memory controller 520 may be formed on the substrate 510, and the plurality of memory devices 530 may be sequentially stacked or arranged on the memory controller 520.

[0044] As reference Figure 1 As depicted, the memory controller 520 may include a transceiver (TRX) 521. The transceiver 521 may be directly connected to the optical interconnect 120. The memory controller 520 may be optically connected to the optical logic module 300 through the transceiver 521 and the optical interconnect 120.

[0045] The plurality of memory devices 530 may include first to Mth memory devices sequentially stacked in a vertical direction, where M is a positive integer greater than or equal to 2.

[0046] Each of the memory controller 520 and the plurality of memory devices 530 may include a through silicon via (TSV) 513. For example, each through silicon via 513 may be formed by penetrating a portion or the entirety of a semiconductor substrate included in the memory controller 520 and one of the plurality of memory devices 530. For example, the through silicon via 513 may include a data input / output (I / O) through silicon via, a command through silicon via, an address through silicon via, and the like.

[0047] In some example embodiments, the through silicon vias 513 may be arranged at the same position in the memory controller 520 and each of the plurality of memory devices 530 relative to the memory controller 520 and each of the plurality of memory devices 530. Thus, the memory controller 520 and the plurality of memory devices 530 may be stacked such that the through silicon vias 513 of each of the memory controller 520 and the plurality of memory devices 530 may completely overlap (e.g., be aligned) in the vertical direction (e.g., the arrangement of the through silicon vias 513 may perfectly match in the memory controller 520 and the plurality of memory devices 530). In such a stacked state, the memory controller 520 and the plurality of memory devices 530 may be electrically connected to each other and the substrate 510 through the through silicon vias 513 and the conductive material 515.

[0048] An external connector 511 for electrically connecting to an external device may be provided on the lower surface of the substrate 510. For example, the external connector 511 may be a solder ball (eg, a ball grid array (BGA)). The optical memory module 500a may be mounted on the module substrate through the external connector 511.

[0049] For example, a sealing member may be formed on the substrate 510, the memory controller 520, and the plurality of memory devices 530 so that the memory controller 520 and the plurality of memory devices 530 are fixed by the sealing member. For example, a heat sink may be provided on the substrate 510, the memory controller 520, and the plurality of memory devices 530 so that heat generated from the memory controller 520 and the plurality of memory devices 530 is dissipated by the heat sink.

[0050] Figure 3 is a cross-sectional view of an example of an optical logic module according to an example embodiment. Figure 2 Duplicate description.

[0051] refer to Figure 3 , the optical logic module 300a may include a substrate 310 and a processing device (PRC) 320. The logic module may be referred to as a logic package, a logic chip, etc.

[0052] The substrate 310 may be Figure 2 The substrates 310 and 510 may be physically separated substrates.

[0053] The processing device 320 may be formed or disposed on the substrate 310. Figure 1 As depicted, the processing device 320 may include a transceiver (TRX) 321. The transceiver 321 may be directly connected to the optical interconnect 120. The processing device 320 may be optically connected to the optical storage module 500 through the transceiver 321 and the optical interconnect 120.

[0054] An external connector 311 for electrical connection with an external device may be disposed on a lower surface of the substrate 310 .

[0055] As reference Figure 2 and Figure 3 As described above, the processing device 320 and the plurality of memory devices 530 may be formed on substrates 310 and 510, and the substrates 310 and 510 are physically separated from each other, so the optical logic module 300a and the optical memory module 500a may be implemented as a disaggregated or separated package. In addition, the processing device 320 and the plurality of memory devices 530 may be connected using the optical interconnect 120 and the transceivers 321 and 521 without an interposer.

[0056] Figure 4A and Figure 4B is a block diagram illustrating an example of a transceiver included in an optical memory module according to example embodiments.

[0057] refer to Figure 4A , the transceiver 521 a may include a photonic integrated circuit (PIC) 523 and an electrical integrated circuit (EIC) 525 .

[0058] The photonic integrated circuit 523 may generate a first electrical signal ES11m based on a first optical signal OS11 received through the optical interconnect 120, or may generate a second optical signal OS12 output through the optical interconnect 120 based on a second electrical signal ES12m. In other words, the photonic integrated circuit 523 may perform optical-to-electrical (O / E) conversion and / or electrical-to-optical (E / O) conversion. For example, the photonic integrated circuit 523 may include a light source, such as a light emitting diode (LED), a laser, etc.

[0059] The electrical integrated circuit 525 may generate a first signal S11m provided to the memory controller 520 and the memory device (MEM) 531 based on the first electrical signal ES11m, or may generate a second electrical signal ES12m based on a second signal S12m provided from the memory controller 520 and the memory device 531. The memory device 531 may be one of the plurality of memory devices 530.

[0060] A photonic integrated circuit or integrated optical circuit is a microchip containing two or more photonic components that form a functional circuit. The technology detects, generates, transmits and processes light. Photonic integrated circuits utilize photons (or particles of light) rather than electrons utilized by electrical integrated circuits. The main difference between the two is that photonic integrated circuits provide functionality for information signals applied to optical wavelengths typically in the visible optical spectrum or near infrared (about 850 to 1650 nm). For example, the most commonly used material platform commercially for photonic integrated circuits is indium phosphide (InP), which allows the integration of various optical active and passive functions on the same chip. For example, all modern monolithic tunable lasers, widely tunable lasers, externally modulated lasers and transmitters, integrated receivers, etc. are examples of photonic integrated circuits.

[0061] In some example embodiments, the signals S11m and S12m exchanged between the electrical integrated circuit 525 and the memory controller 520 may be signals based on the Universal Chiplet Interconnect Express (UCIe) protocol. UCIe is an open specification for die-to-die interconnect and serial bus between chiplets. However, signals based on various other protocols may be used.

[0062] refer to Figure 4B , the transceiver 521b may include a photonic integrated circuit 523, an electrical integrated circuit 525, and a serializer and deserializer (SERDES) 527. Figure 4A Duplicate description.

[0063] The transceiver 521b can be used with Figure 4A The transceiver 521a is substantially the same, except that the transceiver 521b also includes a serializer and a deserializer 527.

[0064] The serializer and deserializer 527 may perform serial-to-parallel conversion and / or parallel-to-serial conversion. For example, the serializer and deserializer 527 may perform serial-to-parallel conversion on a first signal S11m to generate a signal S11m' provided to the memory controller 520 and the memory device 531. For example, the serializer and deserializer 527 may perform parallel-to-serial conversion on a signal S12m' provided from the memory controller 520 and the memory device 531 to generate a second signal S12m. In other words, the signals S11m' and S12m' between the serializer and deserializer 527 and the memory controller 520 may be parallel signals, and the signals S11m and S12m between the electrical integrated circuit 525 and the serializer and deserializer 527 may be serial signals.

[0065] Figure 5A and Figure 5B is a block diagram showing an example of a transceiver included in an optical logic module according to an example embodiment. Figure 4A and Figure 4B Duplicate description.

[0066] refer to Figure 5A , the transceiver 321 a may include a photonic integrated circuit 323 and an electrical integrated circuit 325 .

[0067] Photonic integrated circuit 323 can be used with Figure 4A The photonic integrated circuit 323 may generate a first optical signal OS11 output through the optical interconnect 120 based on the first electrical signal ES11p, or may generate a second electrical signal ES12p based on the second optical signal OS12 received through the optical interconnect 120.

[0068] The integrated circuit 325 can be connected with Figure 4A The electrical integrated circuit 325 may generate a first electrical signal ES11p based on a first signal S11p provided from the processing device 320, or may generate a second signal S12p provided to the processing device 320 based on a second electrical signal ES12p.

[0069] refer to Figure 5B , the transceiver 321 b may include a photonic integrated circuit 323 , an electrical integrated circuit 325 , and a serializer and deserializer 327 .

[0070] The transceiver 321b can be used with Figure 5A The transceiver 321a is substantially the same except that the transceiver 321b also includes a serializer and a deserializer 327.

[0071] The serializer and deserializer 327 can be used with Figure 4BThe serializer and deserializer 527 in FIG. 3 is substantially the same. The serializer and deserializer 327 may perform serial-to-parallel conversion and / or parallel-to-serial conversion. For example, the serializer and deserializer 327 may perform parallel-to-serial conversion on a signal S11p' provided from the processing device 320 to generate a first signal S11p. For example, the serializer and deserializer 327 may perform serial-to-parallel conversion on a second signal S12p to generate a signal S12p' provided to the processing device 320.

[0072] In some example embodiments, during a data writing operation, the first optical signal OS11 may include a write request, a write address, and write data, as shown in FIG. Figure 1 Similarly, during a data write operation, each of the signals S11p', S11p, and ES11p used to generate the first optical signal OS11 in the processing device 320 and the transceivers 321a and 321b may include a write request, a write address, and write data. In addition, during a data write operation, each of the signals ES11m, S11m, and S11m' generated based on the first optical signal OS11 in the memory controller 520 and the transceivers 521a and 521b may include a write request, a write address, and write data.

[0073] In some example embodiments, during a data read operation, the first optical signal OS11 may include a read request and a read address, and the second optical signal OS12 may include read data, such as reference 1. Figure 1 As described. Similarly, during a data read operation, each of the signals S11p', S11p, and ES11p used to generate the first optical signal OS11 in the processing device 320 and the transceivers 321a and 321b may include a read request and a read address, and each of the signals ES11m, S11m, and S11m' generated based on the first optical signal OS11 in the memory controller 520 and the transceivers 521a and 521b may include a read request and a read address. In addition, during a data read operation, each of the signals S12m', S12m, and ES12m used to generate the second optical signal OS12 in the memory controller 520 and the transceivers 521a and 521b may include read data, and each of the signals ES12p, S12p, and S12p' generated based on the second optical signal OS12 in the processing device 320 and the transceivers 321a and 321b may include read data.

[0074] Fig. 6A and Figure 6B is a cross-sectional view of an example of an optical memory module according to an example embodiment. Figure 2 Duplicate description.

[0075] refer to Fig. 6A , the optical memory module 500 b may include a substrate 510 , a memory controller 520 , and a plurality of memory devices 530 .

[0076] exist Fig. 6A In the example of , the memory controller 520 and the plurality of memory devices 530 may be spaced apart from each other on the substrate 510 , and the plurality of memory devices 530 may be sequentially stacked in a vertical direction on the substrate 510 .

[0077] Each of the plurality of memory devices 530 may include an input / output (I / O) pad (IOPAD). For example, the IOPAD may include a data input / output pad, a command pad, an address pad, and the like.

[0078] In some example embodiments, a plurality of memory devices 530 may be stacked on the substrate 510 so that the surface on which the input / output pad IOPAD may be disposed faces upward. In some example embodiments, with respect to each of the plurality of memory devices 530, the input / output pad IOPAD may be arranged near one side of each of the plurality of memory devices 530. Therefore, the plurality of memory devices 530 may be stacked in proportion, that is, in a stepped shape, so that the input / output pad IOPAD of each of the plurality of memory devices 530 may be exposed (e.g., the input / output pad IOPAD may be exposed on the edge of each step). In such a stacked state, the plurality of memory devices 530 may be electrically connected to each other and to the memory controller 520 through the input / output pad IOPAD and the bonding wire BW.

[0079] In some example embodiments, the adhesive member 517 may be interposed between the plurality of memory devices 530 .

[0080] refer to Figure 6B , the optical memory module 500 c may include a substrate 510 , a memory controller 520 , and a plurality of memory devices 530 .

[0081] exist Figure 6B In the example of , the memory controller 520 and the plurality of memory devices 530 may be spaced apart from each other on the substrate 510 , and the plurality of memory devices 530 may also be spaced apart from each other on the substrate 510 .

[0082] The internal connection structure 519 may be formed between the substrate 510 and the memory controller 520 and the plurality of memory devices 530. The memory controller 520 and the plurality of memory devices 530 may be electrically connected through connection lines included in the internal connection structure 519.

[0083] In some example embodiments, the internal connection structure 519 may be a redistribution layer. For example, the redistribution layer may include a plurality of vias and a plurality of connection lines, and may include a plurality of insulation layers that electrically insulate at least some of the plurality of connection lines.

[0084] In some example embodiments, the internal connection structure 519 may be an interposer. For example, the interposer may include a plurality of through electrodes and a plurality of connection lines. For example, the interposer may be a silicon interposer including a silicon substrate, the silicon substrate being a semiconductor substrate, and the plurality of through electrodes may be silicon through vias penetrating the silicon substrate.

[0085] Although reference Figure 2 , Fig. 6A and Figure 6B describes the configuration of the optical memory module, but it can be combined Figure 2 , Fig. 6A and Figure 6B Some configurations shown in can be used to implement optical memory modules. For example, the memory device 530 can be stacked on the memory controller 520, such as Figure 2 As shown, the memory controller 520 and the memory device 530 can be Fig. 6A For example, the memory controller 520 and the memory device 530 may be spaced apart from each other on the substrate 510, such as Fig. 6A As shown, the memory device 530 can be Figure 2 The through silicon vias 513 in the embodiment are electrically connected to each other, and the memory controller 520 and the memory device 530 can be electrically connected to each other through the through silicon vias 513 in the embodiment. Fig. 6A The bonding wires BW in the embodiment are electrically connected. Figure 6B As shown, the memory controller 520 and the memory device 530 may be connected via an internal connection structure 519, and as shown in FIG. Figure 2 or Fig. 6A As shown, memory devices 530 may be stacked sequentially.

[0086] Figure 7 is a block diagram illustrating an example of a memory device included in an optical memory module according to example embodiments.

[0087] refer to Figure 7 , the memory device 200 includes a control logic 210, a refresh control circuit 215, an address register 220, a bank control logic 230, a row address multiplexer 240, a column address latch 250, a row decoder, a column decoder, a memory cell array, a sense amplifier unit, an input / output (I / O) gating circuit 290, a data I / O buffer 295, and a data I / O pad 299. For example, the memory device 200 may be one of various volatile memory devices, such as a dynamic random access memory (DRAM).

[0088] The memory cell array may include a plurality of memory cells. The memory cell array may include a plurality of bank arrays, for example, first to fourth bank arrays 280a, 280b, 280c and 280d. The row decoder may include a plurality of bank row decoders, for example, first bank row decoder to fourth bank row decoder 260a, 260b, 260c and 260d, respectively connected to the first bank array to the fourth bank array 280a, 280b, 280c and 280d. The column decoder may include a plurality of bank column decoders, for example, first column decoder to fourth column decoder 270a, 270b, 270c and 270d, respectively connected to the first bank array to the fourth bank array 280a, 280b, 280c and 280d. The sense amplifier unit may include a plurality of bank sense amplifiers, for example, first to fourth bank sense amplifiers 285a, 285b, 285c, and 285d connected to first to fourth bank arrays 280a, 280b, 280c, and 280d, respectively.

[0089] The first bank array 280a to the fourth bank array 280d, the first bank row decoder 260a to the fourth bank row decoder 260d, the first bank column decoder 270a to the fourth bank column decoder 270d, and the first bank sense amplifier 285a to the fourth bank sense amplifier 285d can form the first bank to the fourth bank respectively. For example, the first bank array 280a, the first bank row decoder 260a, the first bank column decoder 270a, and the first bank sense amplifier 285a can form a first bank; the second bank array 280b, the second bank row decoder 260b, the second bank column decoder 270b and the second bank sense amplifier 285b can form a second bank; the third bank array 280c, the third bank row decoder 260c, the third bank column decoder 270c and the third bank sense amplifier 285c can form a third bank; and the fourth bank array 280d, the fourth bank row decoder 260d, the fourth bank column decoder 270d and the fourth bank sense amplifier 285d can form a fourth bank.

[0090] The address register 220 may be received from a memory controller located outside the memory device 200 (e.g., from Figure 1 The memory controller 520 in the memory receives the address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR and the column address COL_ADDR. The address register 220 can provide the received bank address BANK_ADDR to the bank control logic 230, can provide the received row address ROW_ADDR to the row address multiplexer 240, and can provide the received column address COL_ADDR to the column address latch 250.

[0091] The bank control logic 230 may generate a bank control signal in response to receiving the bank address BANK_ADDR. One of the first to fourth bank row decoders 260a to 260d corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signal generated by the bank control logic 230, and one of the first to fourth column decoders 270a to 270d corresponding to the received bank address BANK_ADDR may be activated in response to the bank control signal generated by the bank control logic 230.

[0092] The refresh control circuit 215 may generate a refresh address REF_ADDR in response to receiving a refresh command or entering any self-refresh mode. For example, the refresh control circuit 215 may include a refresh counter configured to sequentially change the refresh address REF_ADDR from the first address of the memory cell array to the last address of the memory cell array. The refresh control circuit 215 may receive a control signal from the control logic 210.

[0093] The row address multiplexer 240 may receive a row address ROW_ADDR from the address register 220, and may receive a refresh address REF_ADDR from the refresh control circuit 215. The row address multiplexer 240 may selectively output a row address ROW_ADDR or a refresh address REF_ADDR. The row address (e.g., row address ROW_ADDR or refresh address REF_ADDR) output from the row address multiplexer 240 may be applied to the first to fourth bank row decoders 260a to 260d.

[0094] An activated one of the first to fourth bank row decoders 260a to 260d may decode the row address output from the row address multiplexer 240 and may activate a word line corresponding to the row address. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address.

[0095] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or received column address COL_ADDR to the first to fourth bank column decoders 270a to 270d.

[0096] An activated one of the first to fourth bank column decoders 270 a to 270 d may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0097] The I / O gating circuit 290 may include a circuit for gating I / O data. For example, although not shown, the I / O gating circuit 290 may include an input data mask logic, a read data latch for storing data output from the first bank array 280a to the fourth bank array 280d, and a write driver for writing data to the first bank array 280a to the fourth bank array 280d.

[0098] Data DQ to be read from one of the first to fourth bank arrays 280a to 280d may be sensed by a sense amplifier coupled to the one bank array and may be stored in a read data latch. The data DQ stored in the read data latch may be provided to a memory controller via a data I / O buffer 295 and a data I / O pad 299. Data DQ to be written to one of the first to fourth bank arrays 280a to 280d received via the data I / O pad 299 may be provided from the memory controller to the data I / O buffer 295. The data DQ received via the data I / O pad 299 and provided to the data I / O buffer 295 may be written to the one bank array via a write driver in the I / O gating circuit 290.

[0099] The control logic 210 may control the operation of the memory device 200. For example, the control logic 210 may generate a control signal for the memory device 200 to perform a data write operation or a data read operation. The control logic 210 may include a command decoder 211 that decodes a command CMD received from a memory controller and a mode register 212 that sets an operation mode of the memory device 200. For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal (e.g., / WE), a row address strobe signal (e.g., / RAS), a column address strobe signal (e.g., / CAS), a chip select signal (e.g., / CS), etc. The control logic 210 may further receive a clock signal (e.g., CLK) and a clock enable signal (e.g., / CKE) for operating the memory device 200 in a synchronous scheme.

[0100] Although the memory device included in the optical memory module according to example embodiments is described based on DRAM, the memory device according to example embodiments may be any volatile memory device and / or any nonvolatile memory device, for example, a static random access memory (SRAM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

[0101] Figure 8 is a block diagram illustrating an example of a memory controller included in an optical memory module according to example embodiments.

[0102] refer to Figure 8 , the memory controller 400 may include at least one processor 410 , a buffer memory 420 , an external interface (EXT I / F) 430 , an error correction code (ECC) engine 440 , and an internal interface (INT I / F) 450 .

[0103] The processor 410 may respond to an optical logic module (eg, Figure 1 300 and / or processing device 320) to control the operation of memory controller 400. For example, processor 410 may control an optical memory module (e.g., Figure 1 The optical memory module 500 in FIG. 1 is used for operating the optical memory module, and each component may be controlled by adopting firmware for operating the optical memory module.

[0104] The buffer memory 420 may store instructions and data executed and processed by the processor 410. For example, the buffer memory 420 may be implemented with a volatile memory (eg, DRAM, SRAM, cache memory, etc.).

[0105] The ECC engine 440 for error correction may perform coding modulation using Bose-Chaudhuri-Hocquenghem (BCH) codes, low-density parity-check (LDPC) codes, turbo codes, Reed-Solomon codes, convolutional codes, recursive systematic codes (RSC), trellis coded modulation (TCM), block coded modulation (BCM), etc., or may perform ECC encoding and ECC decoding using the above codes or other error correction codes.

[0106] The external interface 430 may provide a physical connection between the optical logic module and the memory controller 400. The external interface 430 may provide an interface corresponding to the bus format of the optical logic module for communication between the optical logic module and the memory controller 400. For example, the external interface 430 may include a bus interface for connecting to an optical interconnect (e.g., Figure 1 A transceiver 431 of the optical interconnect 120).

[0107] Internal interface 450 can provide communication between memory controller 400 and multiple memory devices (eg, Figure 1 For example, the internal interface 450 may be configured to conform to a standard protocol, such as a switched or open NAND flash interface (ONFI).

[0108] Fig. 9 and Fig.10 is a block diagram illustrating an optical memory module and an optical computing system including the optical memory module according to example embodiments. Figure 1 Repeated description of .

[0109] refer to Fig. 9 , the optical computing system 101 includes the optical interconnects 120 and 125 , the optical logic module 300 , and the optical memory module 501 .

[0110] The optical computing system 101 can be used with Figure 1 The optical computing system 100 of FIG. 1 is substantially the same as that of FIG. 1 , except that the optical computing system 101 further includes an optical interconnect 125 and the configuration of the optical memory module 501 is partially changed. The optical interconnect 120 and the optical logic module 300 may be the same as those of FIG. Figure 1 Those described are essentially the same.

[0111] As with the optical interconnect 120, the optical interconnect 125 can optically connect the optical logic module 300 with the optical memory module 501. The optical logic module 300 and the optical memory module 501 can exchange optical signals OS13 and OS14. For example, the optical logic module 300 can output the third optical signal OS13 through the optical interconnect 125, and can receive the fourth optical signal OS14 transmitted through the optical interconnect 125. For example, the optical memory module 501 can receive the third optical signal OS13 transmitted through the optical interconnect 125, and can output the fourth optical signal OS14 through the optical interconnect 125.

[0112] The optical memory module 501 may include a memory controller 520 and a memory controller 540 and a plurality of memory devices 530 and a plurality of memory devices 550. The memory controller 520 and the plurality of memory devices 530 may be connected to the reference Figure 1 The memory controller and the plurality of memory devices described are substantially the same.Memory controller 540 and plurality of memory devices 550 may be similar to memory controller 520 and plurality of memory devices 530, respectively.

[0113] The memory controller 540 may include a transceiver 541. The transceiver 541 may be located in the memory controller 540 and may be directly connected to the optical interconnect 125. The transceiver 541 may receive the third optical signal OS13 through the optical interconnect 125, or may output the fourth optical signal OS14 through the optical interconnect 125. The memory controller 540 may be optically connected to the optical logic module 300 through the transceiver 541 and the optical interconnect 125.

[0114] The plurality of memory devices 550 may be controlled by the memory controller 540 and may be accessed by the optical logic module 300 through the memory controller 540 , the transceiver 541 , and the optical interconnect 125 .

[0115] Like the memory controller 520 and the plurality of memory devices 530, the memory controller 540 and the plurality of memory devices 550 may be formed on a substrate. For example, the memory controller 540 and the plurality of memory devices 550 may be formed as shown in FIG. Figure 2 , Fig. 6A and Figure 6B For example, the optical memory module 501 may be implemented as a single package, so the memory controllers 520 and 540 and the plurality of memory devices 530 and 550 may be disposed on the same substrate.

[0116] For example, Fig. 9 As shown, the optical memory module 501 may include two memory controllers 520 and 540 and memory devices 530 and 550 connected thereto. In another example, the optical memory module may include three or more memory controllers and memory devices connected thereto.

[0117] refer to Fig.10 , the optical computing system 103 includes the optical interconnect 120 and the optical interconnect 130 , the optical logic module 303 , and the optical memory modules 500 and 600 .

[0118] The optical computing system 103 can be used with Figure 1 The optical computing system 100 of FIG. 1 is substantially the same as that of FIG. 1 , except that the optical computing system 103 further includes an optical interconnect 130 and an optical memory module 600, and the configuration of the optical logic module 303 is partially changed. The optical interconnect 120 and the optical logic module 303 may be the same as those of FIG. Figure 1 Those described are essentially the same.

[0119] As with the optical interconnect 120, the optical interconnect 130 may optically connect the optical logic module 303 with the optical memory module 600. The optical logic module 303 and the optical memory module 600 may exchange optical signals OS21 and OS22. For example, the optical logic module 303 may output a third optical signal OS21 through the optical interconnect 130, and may receive a fourth optical signal OS22 transmitted through the optical interconnect 130. For example, the optical memory module 600 may receive a third optical signal OS21 transmitted through the optical interconnect 130, and may output a fourth optical signal OS22 through the optical interconnect 130.

[0120] The optical logic module 303 may include a processing device 320 and a processing device 330. The processing device 320 may be connected to a reference Figure 1 The processing devices described are substantially the same. Processing device 330 may be similar to processing device 320.

[0121] The processing device 330 may include a transceiver 331. The transceiver 331 may be located in the processing device 330, and may be directly connected to the optical interconnect 130. The transceiver 331 may output the third optical signal OS21 through the optical interconnect 130, or may receive the fourth optical signal OS22 through the optical interconnect 130. The processing device 330 may be optically connected to the optical memory module 600 through the transceiver 331 and the optical interconnect 130.

[0122] The optical memory module 600 may include a memory controller 620 and a plurality of memory devices 630, and the memory controller 620 may include a transceiver 621. The optical memory module 600, the memory controller 620, the transceiver 621, and the plurality of memory devices 630 may be substantially the same as the optical memory module 500, the memory controller 520, the transceiver 521, and the plurality of memory devices 530, respectively.

[0123] The memory controller 620 and the plurality of memory devices 630 may be formed on a substrate. For example, the memory controller 620 and the plurality of memory devices 630 may be formed as shown in FIG. Figure 2 , Fig. 6A and Figure 6B For example, the optical memory modules 500 and 600 may be implemented as different and separate packages, and thus the memory controllers 520 and 620 and the plurality of memory devices 530 and 630 may be disposed on different substrates.

[0124] For example, Fig.10 As shown, the optical logic module 303 may include two processing devices 320 and 330, and the optical computing system 103 includes two optical memory modules 500 and 600 connected thereto. In another example, the optical logic module may include three or more processing devices, and the optical computing system may include three or more optical memory modules connected thereto.

[0125] Fig.11A and Fig. 11B is a cross-sectional view of an example of an optical logic module according to an example embodiment. Figure 3 Repeated description of .

[0126] refer to Fig.11A , the optical logic module 303 a may include a substrate 310 and processing devices 320 and 330 .

[0127] The processing device 320 and the processing device 330 may be spaced apart from each other on the substrate 310. Fig.11A In the example of FIG. 5 , processing device 320 and processing device 330 may not be electrically connected to each other.

[0128] refer to Fig. 11B , the optical logic module 303 b may include a substrate 310 and processing devices 320 and 330 .

[0129] The processing device 320 and the processing device 330 may be spaced apart from each other on the substrate 310. The internal connection structure 319 may be formed between the substrate 310 and the processing device 320 and the processing device 330. Fig. 11B In the example of FIG. 3 , processing device 320 and processing device 330 may be electrically connected to each other through connection lines included in internal connection structure 319. For example, internal connection structure 319 may be similar to Figure 6B The internal connection structure 519 in the embodiment may be an interposer or a redistribution layer.

[0130] Fig.12 is a block diagram illustrating an optical memory module and an optical computing system including the optical memory module according to example embodiments. Figure 1 , Fig. 9 and Fig.10 Repeated description of .

[0131] refer to Fig.12 The optical computing system 105 includes a switch device 150 , an optical interconnect 155 , an optical logic module 305 , and a plurality of optical memory modules 500 , 600 , and 700 .

[0132] The optical computing system 105 can be used with Figure 1 The optical computing system 105 is substantially the same as that of FIG. 1 , except that the optical computing system 105 further includes a switching device 150 and the configuration of the optical computing system 105 is partially changed.

[0133] The optical logic module 305 may include a plurality of processing devices 320, 330, and 340, and the plurality of processing devices 320, 330, and 340 may include a plurality of transceivers 321, 331, and 341, respectively. For example, the number of processing devices 320, 330, and 340 may be X, where X is a positive integer greater than or equal to 2. In addition to changing the number of processing devices 320, 330, and 340, the optical logic module 305 may be the same as the reference Fig.10 The optical logic modules described are essentially the same.

[0134] The plurality of optical memory modules 500, 600, and 700 may include a plurality of memory controllers 520, 620, and 720 and a plurality of memory devices 530, 630, and 730, respectively. The plurality of memory controllers 520, 620, and 720 may include a plurality of transceivers 521, 621, and 721, respectively. For example, the number of the optical memory modules 500, 600, and 700 may be Y, where Y is a positive integer greater than or equal to 2. Each of the optical memory modules 500, 600, and 700 may be connected to a reference Figure 1 The optical memory modules described are essentially the same.

[0135] The switch device 150 may be located or disposed between the optical logic module 305 and the optical memory modules 500, 600, and 700, and may be connected to the optical logic module 305 and the optical memory modules 500, 600, and 700 through the optical interconnect 155. The switch device 150 may control the connection between the optical logic module 305 and the optical memory modules 500, 600, and 700. For example, through the switch device 150, the processing devices 320, 330, and 340 and the optical memory modules 500, 600, and 700 may be connected in a one-to-one correspondence. For example, through the switch device 150, one processing device may be connected to two or more optical memory modules, and / or two or more processing devices may be connected to one optical memory module. For example, depending on the operating state, condition, and / or environment of the optical computing system 105, the connection between the processing devices 320, 330, and 340 and the optical memory modules 500, 600, and 700 may be dynamically / adaptively changed or adjusted.

[0136] Fig.13 is a block diagram illustrating an electronic system according to example embodiments.

[0137] refer to Fig.13 , the electronic system 1000 may include a processor 1010, a memory 1020, a connection 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic system 1000 may also include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0138] The processor 1010 may control the operation of the electronic system 1000. The processor 1010 may execute an operating system and at least one application to provide an Internet browser, a game, a video, etc. The memory 1020 may store data for the operation of the electronic system 1000. The connection 1030 may communicate with external devices and / or systems. The I / O device 1040 may include an input device (e.g., a keyboard, a keypad, a mouse, a touch pad, a touch screen, a remote controller, etc.) and an output device (e.g., a printer, a speaker, etc.). The power supply 1050 may provide power for the operation of the electronic system 1000. The display device 1060 may display an image provided to a user.

[0139] The processor 1010 and the memory 1020 may respectively include a transceiver 1011 and a transceiver 1021. According to example embodiments, the processor 1010 and the memory 1020 may be implemented in the form of an optical logic module and an optical memory module.

[0140] Fig.14 is a block diagram illustrating a data center including a storage device according to an example embodiment.

[0141] refer to Fig.14 , the data center 3000 may be a facility that collects various types of data and provides various services, and may be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used by a company such as a bank or a government agency. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. According to example embodiments, the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be different from each other.

[0142] The application server 3100 may include at least one processor 3110 and at least one memory 3120, and the storage server 3200 may include at least one processor 3210 and at least one memory 3220. The operation of the storage server 3200 will be described as an example. The processor 3210 may control the overall operation of the storage server 3200, and may access the memory 3220 to execute instructions and / or data loaded in the memory 3220. The memory 3220 may include at least one of a double data rate (DDR) synchronous dynamic random access memory (SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, a non-volatile DIMM (NVDIMM), and the like. According to example embodiments, the number of processors 3210 and the number of memories 3220 included in the storage server 3200 may be selected differently. In some example embodiments, the processor 3210 and the memory 3220 may provide a processor-memory pair. In some example embodiments, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100. The application server 3100 may include at least one storage device 3150, and the storage server 3200 may include at least one storage device 3250. In some example embodiments, the application server 3100 may not include the storage device 3150. According to example embodiments, the number of storage devices 3250 included in the storage server 3200 may be selected in various ways.

[0143] The application servers 3100 to 3100n and the storage servers 3200 to 3200m can communicate with each other through the network 3300. The network 3300 can be implemented using Fibre Channel (FC) or Ethernet. FC can be a medium for relatively high-speed data transmission, and an optical switch that provides high performance and / or high availability can be used. Depending on the access scheme of the network 3300, the storage servers 3200 to 3200m can be provided as file storage, block storage, or object storage.

[0144] In some example embodiments, the network 3300 may be a storage-only network or a network dedicated to storage, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and in accordance with an FC protocol (FCP). For another example, the SAN may be an IP-SAN implemented using a Transmission Control Protocol / Internet Protocol (TCP / IP) network and in accordance with an iSCSI (SCSI or Internet SCSI over TCP / IP) protocol. In other example embodiments, the network 3300 may be a general-purpose network, such as a TCP / IP network. For example, the network 3300 may be implemented in accordance with at least one protocol, such as FC over Ethernet (FCoE), network attached storage (NAS), non-volatile memory express (NVMe) over fabric (NVMe-oF), and the like.

[0145] Hereinafter, an example embodiment will be described based on an application server 3100 and a storage server 3200. The description of the application server 3100 may be applied to another application server 3100n, and the description of the storage server 3200 may be applied to another storage server 3200m.

[0146] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m through the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m through the network 3300. For example, the application server 3100 may be implemented as a network server or a database management system (DBMS).

[0147] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n through the network 3300, and / or may access a memory 3220 to 3220m or a storage device 3250 to 3250m included in the storage servers 3200 to 3200m through the network 3300. Therefore, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute a command for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. Data may be transmitted from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m to the storage 3120 to 3120n of the application servers 3100 to 3100n directly or through the storage 3220 to 3220m of the storage servers 3200 to 3200m. For example, data transmitted through the network 3300 may be encrypted data for security or privacy.

[0148] In the storage server 3200, the interface 3254 may provide a physical connection between the processor 3210 and the controller 3251 and / or a physical connection between the network interface card (NIC) 3240 and the controller 3251. For example, the interface 3254 may be implemented based on a direct attached storage (DAS) scheme, in which the storage device 3250 is directly connected to a dedicated cable. For example, the interface 3254 may be implemented based on at least one of various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCI Express (PCIe), NVMe, Compute Express Link (CXL), IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card interface, Multimedia Card (MMC) interface, Embedded MMC (eMMC) interface, Universal Flash Storage (UFS) interface. Embedded UFS (eUFS) interface, Compact Flash (CF) card interface, etc.

[0149] The storage server 3200 may further include a switch 3230 and a NIC 3240. The switch 3230 may selectively connect the processor 3210 with the storage device 3250, or may selectively connect the NIC 3240 with the storage device 3250 under the control of the processor 3210. Similarly, the application server 3100 may further include a switch 3130 and a NIC 3140.

[0150] In some example embodiments, the NIC 3240 may include a network interface card, a network adapter, and the like. The NIC 3240 may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, and the like. The NIC 3240 may also include an internal memory, a digital signal processor (DSP), a host bus interface, and the like, and may be connected to the processor 3210 and / or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the above examples of the interface 3254. In some example embodiments, the NIC 3240 may be integrated with at least one of the processor 3210, the switch 3230, and the storage device 3250.

[0151] In the storage servers 3200 to 3200m and / or the application servers 3100 to 3100n, the processor may send a command to the storage devices 3150 to 3150n and 3250 to 3250m or the memories 3120 to 3120n and 3220 to 3220m to program or read data. For example, the data may be data corrected by an error correction code (ECC) engine. For example, the data may be processed by a data bus inversion (DBI) or a data mask (DM), and may include cyclic redundancy code (CRC) information. For example, for security or privacy, the data may be encrypted data.

[0152] The storage devices 3150 to 3150m and 3250 to 3250m may send control signals and command / address signals to the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. When reading data from the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal and may be used to output data to the DQ bus. The RE signal may be used to generate a data strobe signal (DQS). The command and address signals may be latched in the page buffer based on the rising edge or falling edge of the write enable (WE) signal.

[0153] The controller 3251 may control the overall operation of the storage device 3250. In some example embodiments, the controller 3251 may include a static random access memory (SRAM). The controller 3251 may write data to the NAND flash memory device 3252 in response to a write command, or may read data from the NAND flash memory device 3252 in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 in the storage server 3200, a processor 3210m in another storage server 3200m, or processors 3110 to 3110n in the application servers 3100 to 3100n. The DRAM 3253 may temporarily store (e.g., may buffer) data to be written to the NAND flash memory device 3252 or data read from the NAND flash memory device 3252. In addition, the DRAM 3253 may store metadata. The metadata may be data generated by the controller 3251 to manage user data or the NAND flash memory device 3252.

[0154] In the processors 3110 to 3110n and 3210 to 3210n and the memories 3120 to 3120n and 3220 to 3220n included in the application servers 3100 to 3100n and the storage servers 3200 to 3200m, according to example embodiments, the processor and the memory included in one server may be implemented in the form of an optical logic module and an optical memory module.

[0155] Example embodiments may be applied to various electronic devices and systems including memory devices. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, etc.

[0156] By way of summary and review, at least one example embodiment of the present disclosure provides an optical memory module capable of effectively communicating with an external optical logic module using an optical interconnect.At least one example embodiment of the present disclosure provides an optical computing system including an optical memory module and an optical logic module.

[0157] That is, in an optical memory module and an optical computing system according to example embodiments, co-packaged optical (CPO) technology can be used to achieve memory disaggregation. For example, an optical logic module including a processing device and an optical memory module including a memory device can be implemented in disaggregated or separate packages, rather than implementing the processing device and the memory device in a single package, and the optical logic module and the optical memory module can be optically connected via an optical interconnect. In addition, transceivers for connecting to optical interconnects can be formed in the processing device and the memory controller, respectively. Therefore, the capacity (or density) and bandwidth of a memory device connected to a processing device can be effectively expanded, the manufacturing cost can be reduced by connecting the processing device to the memory device without an interposer, and problems such as heat generation, power consumption, and size constraints can be effectively solved.

[0158] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be apparent to one of ordinary skill in the art when filing this application, unless otherwise specifically stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. An optical memory module, comprising: substrate; a first memory controller on the substrate, the first memory controller comprising a first transceiver, the first transceiver configured to receive a first optical input signal through a first optical interconnect or to output a first optical output signal through the first optical interconnect, the first memory controller being optically connected to an optical logic module located outside the optical memory module through the first transceiver and the first optical interconnect; as well as A plurality of first memory devices on the substrate, the plurality of first memory devices being controlled by the first memory controller and being accessed by the optical logic module through the first memory controller, the first transceiver, and the first optical interconnect.

2. The optical memory module according to claim 1, wherein: The first transceiver comprises: a photonic integrated circuit configured to generate a first electrical input signal based on the first optical input signal or to generate the first optical output signal based on a first electrical output signal; and An electrical integrated circuit configured to generate a first signal based on the first electrical input signal or to generate the first electrical output signal based on a second signal, the first signal being provided to the first memory controller and the plurality of first memory devices, the second signal being provided from the first memory controller and the plurality of first memory devices.

3. The optical memory module according to claim 2, wherein: The first transceiver also includes a serializer and a deserializer configured to perform serial-to-parallel conversion on the first signal or to perform parallel-to-serial conversion on the second signal.

4. The optical memory module according to claim 1, wherein: The optical memory module is a disaggregated package that is physically separate from the optical logic module.

5. The optical memory module according to claim 1, wherein: The plurality of first memory devices are on the first memory controller.

6. The optical memory module according to claim 5, wherein: The first memory controller and the plurality of first memory devices are connected through through silicon vias.

7. The optical memory module according to claim 1, wherein: The plurality of first memory devices are spaced apart from the first memory controller on the substrate.

8. The optical memory module according to claim 7, wherein: The first memory controller and the plurality of first memory devices are connected by bonding wires.

9. The optical memory module according to claim 1, further comprising: a second memory controller on the substrate, the second memory controller comprising a second transceiver, the second transceiver configured to receive a second optical input signal through a second optical interconnect or to output a second optical output signal through the second optical interconnect, the second memory controller being optically connected to the optical logic module through the second transceiver and the second optical interconnect; as well as A plurality of second memory devices on the substrate, the plurality of second memory devices being controlled by the second memory controller and being accessed by the optical logic module through the second memory controller, the second transceiver, and the second optical interconnect.

10. The optical memory module according to claim 1, wherein: Each of the plurality of first memory devices is one of a high bandwidth memory device and a graphics double data rate memory device.

11. An optical computing system comprising: Optical logic module; a first optical memory module configured to optically communicate with the optical logic module; as well as a first optical interconnect configured to optically connect the optical logic module with the first optical memory module, Wherein, the optical logic module comprises: a first substrate, and a first processing device on the first substrate, the first processing device comprising a first transceiver, the first transceiver configured to output a first optical signal through the first optical interconnect or to receive a second optical signal through the first optical interconnect, the first processing device being optically connected to the first optical memory module through the first transceiver and the first optical interconnect, and Wherein, the first optical memory module comprises: The second substrate, a first memory controller on the second substrate, the first memory controller comprising a second transceiver, the second transceiver configured to receive the first optical signal through the first optical interconnect or output the second optical signal through the first optical interconnect, the first memory controller being optically connected to the optical logic module through the second transceiver and the first optical interconnect, and A plurality of first memory devices on the second substrate, the plurality of first memory devices being controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the second transceiver, and the first optical interconnect.

12. The optical computing system of claim 11, wherein: The first transceiver comprises: a photonic integrated circuit configured to generate the first optical signal based on the first electrical signal or to generate the second electrical signal based on the second optical signal; and An electrical integrated circuit is configured to generate the first electrical signal based on a first signal or to generate a second signal based on the second electrical signal, the first signal being provided from the first processing device and the second signal being provided to the first processing device.

13. The optical computing system of claim 12, wherein: The first transceiver also includes a serializer and a deserializer configured to perform a parallel-to-serial conversion on the first signal or a serial-to-parallel conversion on the second signal.

14. The optical computing system of claim 11, wherein: The optical logic module and the first optical memory module are disaggregated packages that are physically separated from each other.

15. The optical computing system of claim 11, further comprising: a second optical memory module configured to optically communicate with the optical logic module; as well as A second optical interconnect is configured to optically connect the optical logic module with the second optical memory module.

16. The optical computing system of claim 15, wherein: The optical logic module also includes a second processing device on the first substrate, the second processing device including a third transceiver, the third transceiver configured to output a third optical signal through the second optical interconnect or receive a fourth optical signal through the second optical interconnect, the second processing device being optically connected to the second optical memory module through the third transceiver and the second optical interconnect.

17. The optical computing system of claim 16, wherein: The second optical memory module comprises: a third substrate; a second memory controller on the third substrate, the second memory controller comprising a fourth transceiver, the fourth transceiver configured to receive the third optical signal through the second optical interconnect or to output the fourth optical signal through the second optical interconnect, the second memory controller being optically connected to the optical logic module through the fourth transceiver and the second optical interconnect; and A plurality of second memory devices on the third substrate, the plurality of second memory devices being controlled by the second memory controller and accessed by the optical logic module through the second memory controller, the fourth transceiver, and the second optical interconnect.

18. The optical computing system of claim 15, further comprising a switch device between the optical logic module and the first optical memory module and the second optical memory module, the switch device being configured to control the connection of the optical logic module with the first optical memory module and the second optical memory module.

19. The optical computing system of claim 11, wherein: The first processing device is one of a central processing unit, a graphics processing unit, and a neural processing unit.

20. An optical memory module, comprising: substrate; a first memory controller on the substrate, the first memory controller comprising a first transceiver, the first transceiver configured to receive a first optical input signal through a first optical interconnect or to output a first optical output signal through the first optical interconnect, the first memory controller being optically connected to an optical logic module located outside the optical memory module through the first transceiver and the first optical interconnect; a plurality of first memory devices on the substrate, the plurality of first memory devices being controlled by the first memory controller and accessed by the optical logic module through the first memory controller, the first transceiver, and the first optical interconnect; a second memory controller on the substrate, the second memory controller comprising a second transceiver, the second transceiver configured to receive a second optical input signal through a second optical interconnect or to output a second optical output signal through the second optical interconnect, the second memory controller being optically connected to the optical logic module through the second transceiver and the second optical interconnect; as well as a plurality of second memory devices on the substrate, the plurality of second memory devices being controlled by the second memory controller and accessed by the optical logic module through the second memory controller, the second transceiver, and the second optical interconnect, Wherein, the first transceiver includes: a photonic integrated circuit configured to generate a first electrical input signal based on the first optical input signal or to generate the first optical output signal based on the first electrical output signal, an electrical integrated circuit configured to generate a first signal based on the first electrical input signal or to generate the first electrical output signal based on a second signal, the first signal being provided to the first memory controller and the plurality of first memory devices, the second signal being provided from the first memory controller and the plurality of first memory devices, and a serializer and a deserializer configured to perform serial-to-parallel conversion on the first signal or to perform parallel-to-serial conversion on the second signal, and wherein the optical memory module is a disaggregated package physically separated from the optical logic module and connected to the optical logic module through the first optical interconnect and the second optical interconnect without an interposer.

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