Semiconductor package with multiple redistribution layers and

Abstract

A semiconductor package includes two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), an intermediate RDL, and a top RDL. The two or more chips include a first chip and a second chip. The top RDL includes a first copper plate and a second copper plate. A plurality of vias electrically connect the second copper plate to the second chip. A method comprising the steps of preparing two or more chips; forming a chip scale molding layer; forming an intermediate RDL; forming a lower molding layer; forming a bottom RDL; forming a molding layer of the lowest level; forming a top RDL; and forming a top molding layer so as to manufacture the semiconductor package.

Description

Technical Field

[0001] The present invention generally relates to semiconductor packages having multiple redistribution layers and methods of making the same. More particularly, the present invention relates to a semiconductor package having an increased chip surface to package surface ratio. Background Art

[0002] It is challenging to reduce the size of semiconductor packages while improving or maintaining heat dissipation capabilities, reliability performance, efficiency, and power density. In order to maintain thermal performance and efficiency, the size of conventional monolithic quad flat no-lead (QFN) packages cannot be reduced.

[0003] Advantages of the present invention include increased efficiency, reduced package size, reduced cost, a more compact footprint, and improved thermal performance.The ratio of chip surface to package surface is at least 67%. Summary of the invention

[0004] The present invention discloses a semiconductor package, comprising two or more chips, a first molding layer, a second molding layer, a third molding layer, a fourth molding layer, a bottom redistribution layer (RDL), an intermediate RDL and a top RDL. The two or more chips include a first chip and a second chip. The top RDL includes a first copper plate and a second copper plate. A plurality of through holes electrically connect the second copper plate to the second chip.

[0005] The present invention also discloses a method for manufacturing a semiconductor package. The method includes the steps of preparing two or more chips; forming a chip-level molding layer; forming an intermediate RDL; forming a lower molding layer; forming a bottom RDL; forming a lowest-level molding layer; forming a top RDL; and forming a top molding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1A A side view showing a semiconductor package in an example of the present invention.

[0007] Figure 1B A side view showing another semiconductor package in an example of the present invention.

[0008] Figure 2 A bottom perspective view showing a semiconductor package in an example of the present invention.

[0009] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Each of the figures is an example of the present invention. Figure 2 A top view of the corresponding level of the semiconductor package.

[0010] Figure 4 is a flow chart of a process for manufacturing a semiconductor device in an example of the present invention.

[0011] Figure 5A , 5B 5C, 5D, 5E, 5F, 5G, 5H and 5I represent process steps for manufacturing a semiconductor device in an example of the present invention. DETAILED DESCRIPTION

[0012] Figure 1A FIG. 1 shows a side view of a semiconductor package 100A in an example of the present invention. Figure 1B 100B is a side view of a semiconductor package 100B in an example of the present invention. The semiconductor package includes two or more chips 120, a first molding layer 112, a second molding layer 114, a third molding layer 116, and a fourth molding layer 118. The semiconductor package also includes a bottom RDL 320 embedded in the first molding layer 112 and a top surface of the bottom RDL 320 is connected to the second molding layer 114. Figure 3B The bottom redistribution layer (RDL) 320 of the second molding layer 114 is embedded in the second molding layer 114 and the top surface of the middle RDL 340 is connected to the third molding layer 116. Figure 3D The middle RDL 340 and the embedded fourth molding layer 118 Figure 3G The top RDL 380 of the semiconductor package 100A is connected to the bottom surface of the top RDL and the third mold layer 116. Two or more chips 120 are embedded in the third mold layer 116, wherein the corresponding front surface of each of the two or more chips 120 is connected to the second mold layer 114, and the corresponding rear surface of the two or fewer chips 120 is connected to the fourth mold layer 118. The bottom surface of the bottom RDL 320 is exposed from the bottom surface of the first mold layer 112 to provide pin connections for the semiconductor package. In one example, the semiconductor package 100A is a DC-DC buck converter. In another example, the semiconductor package 100A is a quad flat no-lead (QFN) package.

[0013] The two or more chips include a first chip 122 and a second chip 124. The first chip 122 and the second chip 124 are shown in dotted lines because they are surrounded by the third mold layer 116 at each edge. The bottom surface 114B of the second mold layer 114 directly contacts the top surface 112T of the first mold layer 112. The bottom surface 116B of the third mold layer 116 directly contacts the top surface 114T of the second mold layer 114. The bottom surface 118B of the fourth mold layer 118 directly contacts the top surface 116T of the third mold layer 116. In one example, each of the first mold layer 112, the second mold layer 114, the third mold layer 116, and the fourth mold layer 118 includes the same mold compound with the same filler. In another example, each of the first mold layer 112, the second mold layer 114, the third mold layer 116, and the fourth mold layer 118 includes a filling material different from the other mold layers. In another example, each of the first, second, third, and fourth mold layers 112, 114, 116, and 118 include the same mold compound having the same filler but having a different percentage amount of filler than the other mold layers.

[0014] Figure 3B The bottom surface of the bottom RDL 320 is exposed from the bottom surface of the first mold layer 112, and Figure 3B The top surface of the top RDL 320 interfaces with the second mold layer 114. The bottom RDL 320 includes a lower half-etched portion enclosed inside the first mold layer 112, and the total area of ​​the bottom surface of the bottom RDL 320 exposed from the bottom of the first mold layer 112 is smaller than the total area of ​​the top surface of the bottom RDL 320 interfaced with the second mold layer 114 and the plurality of bottom vias passing through the second mold layer 114. Figure 3D The bottom surface of the middle RDL 340 directly contacts the second molding layer 114 and is enclosed inside the second molded body layer 114, and Figure 3D The top surface of the middle RDL 340 interfaces with the third molded body layer 116 . Figure 3G The bottom surface of the top RDL 380 is above the third mold layer 116 and interfaces with the third mold body layer 116. Figure 1A In the semiconductor package 100A, the top surface of the top RDL 380 is exposed and coplanar with the top surface of the fourth molding layer 118. Figure 1B The semiconductor package 100B, Figure 3G A top surface of the top RDL 380 directly contacts the fourth molding layer 118 and is encapsulated therein.

[0015] Each of the plurality of sidewalls 123 of the first chip 122 directly contacts the third mold layer 116. Each of the plurality of sidewalls 125 of the second chip 124 directly contacts the third mold layer 116.

[0016] In an example of the present invention, the two or more chips 120 also include Figure 3F The third chip 126. Figure 3F The rear surface of the third chip 126 directly contacts the fourth molding layer 118 .

[0017] Figure 3G The top RDL 380 includes a first copper plate 182 and a second copper plate 184. Figure 1A In the semiconductor package 100A, the top surface 183 of the first copper plate 182 is exposed from the fourth mold layer 118. The top surface 185 of the second copper plate 184 is exposed from the fourth mold layer 118. Figure 1B In the semiconductor package 100B, the top surface 183B of the first copper plate 182B is covered by the fourth mold layer 119 . The top surface 185B of the second copper plate 184B is covered by the fourth mold layer 119 .

[0018] Figure 2 1 shows a bottom perspective view of a semiconductor package 200 in an example of the present invention. The semiconductor package 200 includes a plurality of integrated circuit (IC) control pins along a first edge of the semiconductor package and a ground pin output 260D along a second edge opposite to the first edge. The additional ground pins include a rectangular central ground pin output 260E parallel to and adjacent to the ground pin 260D, and a plurality of ground pin inputs 260A, 260B, and 260C along a third edge perpendicular to the first and second edges. The plurality of power input pins include a rectangular central power pin Vin pin output 220B, and a plurality of Vin pin inputs 220A and 220C substantially aligned with and parallel to the first edge are arranged adjacent to the plurality of IC control pins. The plurality of switch pins include a rectangular central switch pin SW pin output 240D arranged between the central power pin Vin pin output 220B and the central ground pin output 260E, and a plurality of SW pin outputs 240A, 240B, and SW pin output 240C along a fourth edge opposite to the third edge.

[0019] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Each of the examples in this disclosure is Figure 2 A plan view of the bottom or top surface of a corresponding layer of a semiconductor package. Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F, Figure 3G and Figure 3H The layers (except for vias) are from bottom to top as shown in the order shown.

[0020] Figure 3A The figure shows the bottom surface of the first molding layer 112 having the bottom RDL 320, and the bottom pin pattern, which includes the central power input Vin pin output 220B, the SW pin output 240D, the ground pin output 260E and a plurality of corresponding Figure 2 The edge pins are exposed from the bottom of the first molding layer. Figure 3B The top surface of the first mold layer 112 having the bottom RDL 320 is shown, and the bottom RDL 302 includes a first bottom copper connector 322, a second bottom copper connector 324, a third bottom copper connector 326, and a plurality of IC control pins along the first edge. Each of the bottom copper connector and the plurality of IC control pins includes a half-etched bottom enclosed inside the first mold layer 112, wherein the non-etched portion is exposed from the first mold layer, thereby serving as a corresponding connection pin. The power input pins Vin pin out 220A, Vin pin in 220B, and Vin pin out 220C are integral and interconnected through the first bottom copper connector 322; the SW pin 240A, SW pin 240B, SW pin 240C, and SW pin 240D are integral and interconnected through the second bottom copper connector 324; the ground pin out 260B, the ground pin in 260C, the ground pin out 260D, and the ground pin in 260E are integral and interconnected through the third bottom copper connector 326. Figure 3C Display coverage Figure 3B The bottom surface of the second molding layer 114 of the bottom RDL 320 in the embodiment of the present invention is shown in FIG. 1 , wherein the first plurality of bottom vias 331 are aligned with the first bottom copper connector 322, the second plurality of bottom vias 333 are aligned with the second bottom copper connector 324, and the third plurality of bottom vias 335 are aligned with the third bottom copper connector 326. Figure 3D Shows coverage Figure 3B The top surface of the second molding layer 114 of the bottom RDL 320 in the middle RDL 340, wherein the middle RDL 340 includes a first middle copper connector 342, a second middle copper connector 344, a third middle copper connector 346 and a plurality of connection traces. The first plurality of bottom vias 331 electrically connects the first middle copper connector 342 to the first bottom copper connector 322, the second plurality of bottom vias 333 electrically connects the second middle copper connector 344 to the second bottom copper connector 324, and the third plurality of bottom vias 335 electrically connects the third middle copper connector 346 to the third bottom copper connector 326.

[0021] Figure 3E Shows coverage Figure 3DThe bottom RDL 320 and the middle RDL 340 are formed on the bottom surface of the third mold layer 116 . Each of the two or more chips 120 includes a plurality of middle through holes 351 on the front surface of the semiconductor chip exposed on the bottom surface of the third mold layer 116 . Figure 1A and Figure 3B Shows coverage Figure 3D The top surface of the third mold layer 116 of the bottom RDL 320 and the middle RDL 340 is formed, wherein the rear surface of each chip in the two or more chips 120 is exposed on the top surface of the third mold layer 116. In one example, Figure 3F Two or more chips 120 including a first chip 122, a second chip 124, and a third chip 126 are shown. In an example of the present invention, the first chip 122 is a metal oxide semiconductor field effect transistor (MOSFET) chip. The second chip 124 is a MOSFET chip. The third chip 126 is an IC chip. Alternatively, the first chip and the third IC chip can be integrated into one chip. Figure 3E As shown, the first chip 122 includes a first plurality of intermediate vias 351 connected to the source electrode of the first chip 122 and one or more gate vias 351g connected to the gate electrode of the first chip 122 at the front surface of the first chip 122. The second chip 124 includes a second plurality of intermediate vias 353 connected to the source electrode of the second chip and one or more gate vias 353g connected to the gate electrode of the first chip 122 at the front surface of the second chip 24. The third chip 126 includes a third plurality of contact vias 355 electrically connected to a plurality of IC pads. The contact vias 255 include a first gate drive via connected to the gate via 351g of the first chip 122 through a first conductive trace and a second gate drive via connected to the gate via 353g of the second chip 124 through a second conductive trace.

[0022] Figure 3E and Figure 3F 1 and 2. The diagram shows a first plurality of top through holes 371 formed by the third molding layer 116 and aligned with the first intermediate copper connector 342 and a second plurality of top through holes 373 aligned with the second intermediate copper connector 344. The first plurality of top through holes 371 extend along a first direction (X axis). The second plurality of top through holes 373 extend along a second direction (Y axis) perpendicular to the first direction (X axis). The first plurality of top through holes 371 extend along a second direction (Y axis) perpendicular to the first direction (X axis). Figure 3D The first intermediate copper connector 342, Figure 3C The first plurality of bottom through holes 331 and Figure 3B The first bottom copper connector 322 is electrically connected to the power input pin. A plurality of second top through holes 373 are formed by Figure 3D The third intermediate copper connector 346, Figure 3CA second plurality of bottom through holes 333 and Figure 3B The third bottom copper connector 326 is electrically connected to the SW pin.

[0023] Figure 3G 1 shows a bottom surface of a fourth molding layer having a top RDL 380 including a first copper plate 182 and a second copper plate 184. The first copper plate 182 substantially covers the entire rear surface of the first chip 122 and the first plurality of top vias 371. Thus, the drain electrode of the first chip 122 is connected to the power input pin. The second copper plate 184 substantially covers the entire rear surface of the second chip 124 and the second plurality of top vias 373. Thus, the drain electrode of the second chip 124 is connected to the SW pin. In one example, Figure 3H It showed Figure 1B In another example, the top surface of the fourth mold layer 118 may be ground to expose the top surface of the first copper plate 182 and the top surface of the second copper plate 184. Figure 1A shown.

[0024] Figure 3F The back surface area of ​​the first chip 122 is Figure 3F The back surface area of ​​the second chip 124 and Figure 3F The sum of the backside areas of the third chip 126 is Figure 1A at least 67% of the top surface area of ​​the semiconductor package 100A.

[0025] Figure 4 is a flow chart of a process 400 for fabricating a semiconductor device in an example of the present invention. The process 400 may begin at block 402 . Figures 5A-5I For simplicity, the top view of the corresponding steps is shown in Figures 5A-5I Only one semiconductor package component is shown in FIG. Fig.5I The steps shown are followed by a singulation process.

[0026] In box 402, two or more semiconductor chips 520 are prepared from two or more semiconductor wafers. In one example, the two or more wafers include a first MOSFET wafer, a second MOSFET wafer, and an IC wafer. Each of the first MOSFET wafer and the second MOSFET wafer includes a source electrode and a gate electrode on their respective front surfaces, and a drain region extending to the respective rear surfaces of each of the first MOSFET wafer and the second FET wafer. The IC wafer includes a plurality of electrodes on the front surface of the IC wafer. The preparation process begins with applying a wafer mold film in the range of 10-40 microns on the front surface of each of the two or more MOSFET wafers. The wafer molding film covers the electrodes on each front surface of the two or more MOSFET wafers. Laser drilling is applied to form through holes with a diameter of 15-200 microns through the wafer mold film, thereby exposing the electrodes on each front surface of the two or more MOSFET wafers. Back grinding is applied to reduce the thickness of the two or more MOSFET wafers from 760 microns to a desired thickness between 50-300 microns. Each thinned wafer is then cut into a plurality of semiconductor chips, wherein the front electrodes are exposed from the through holes or through hole arrays through the wafer mold film. Now refer to Figure 5A 4. (Top view) A first MOSFET chip 520A from a first MOSFET wafer, a second MOSFET chip 520B from a second MOSFET wafer, and an IC chip 520C from an IC wafer are placed on a first carrier (not shown) with the front electrodes facing downward. Two or more semiconductor chips are placed on the first carrier with a space of 50-200 microns between each other. Alternatively, the first MOSFET chip and the second MOSFET chip can be formed on the same MOSFET wafer. Block 402 can be followed by block 404.

[0027] In block 404, a chip-level molding layer 516 is formed. The chip-level molding layer 516, which fills the space between the chips, thus surrounds all sidewalls of the semiconductor chip and has a thickness of 50-100 microns above the semiconductor chip. An optional grinding process may be applied to smooth the molding layer surface or reduce the chip-level molding layer to the back side of the chip. The chip-level molding layer 516 becomes Figure 1A Now refer to Figure 5B (bottom view), then in the step of block 402, the assembly of semiconductor chip 520 surrounded by chip-level molding layer 516 is released from the first carrier and then mounted on a second carrier (not shown) with the front surface of the chip facing upward. Block 404 may be followed by block 406.

[0028] In block 406, reference is now made to Figure 5C(bottom view), an intermediate RDL540 with a thickness between 5-40 microns is formed on the front surface of the wafer mold film and the chip-level molding layer 516 surrounding the semiconductor chip 520. The intermediate RDL540 can be formed by applying a seed layer, photolithography, copper plating, stripping and etching standard processes. The intermediate RDL540 provides electrical connection between the IC chip and the gate electrodes of the first and second MOSFET chips, and the large first source region S1 and the large second source region S2 are connected to the first MOSFET chip source electrode and the second MOS field effect transistor chip source electrode through the through holes in the wafer mold film respectively. The first source region S1 covers the source electrode of the first MOSFET chip and extends beyond the first MOSFET wafer to the area adjacent to the second MOSFET chip. The intermediate RDL540 also includes a power input region Vin extending to the area adjacent to the first MOSFET chip, and a plurality of contact pads at the peripheral area of ​​the component outside the IC chip, and the plurality of contact pads are connected to the IC chip electrode through a plurality of connection traces. Block 406 may be followed by block 408.

[0029] In block 408, reference is now made to Figure 5D (bottom view), a lower mold layer 514 is formed to cover the middle RDL 540. The lower mold layer 514 becomes Figure 1A Laser drilling is applied to form vias through the lower mold layer 514 to provide connections to the large first source region S1, the large second source region S2, the power input region V'in, and a plurality of contact pads at the peripheral region of the component. Block 408 may be followed by block 410.

[0030] In block 410, reference is now made to Figure 5E (bottom view), a bottom RDL 521 is formed on the lower mold layer 514. The bottom RDL 521 may include a large ground area GND, a large switch node area SW, a power input area Vin, and a plurality of contact pins at the peripheral area of ​​the component. The bottom RDL 521 may have a thickness of 40-150 microns, wherein the half-etched area is recessed from the top surface of the central portion of the large ground area GND, the large switch node area SW, the power input area Vin, and the plurality of contact pins. The bottom RDL 521 may be formed by applying a seed layer, photolithography, copper plating, stripping, and etching standard processes. The bottom RDL 521 provides connections to the large first source area S1 and the large second source area S2 through the through holes in the lower mold layer 514 and the pins for the component. Block 410 may be followed by block 412.

[0031] In block 412, reference is now made to Fig. 5F(bottom view), a lowest level molding layer 512 covering the bottom RDL 521 is formed. The lowest level molding layer 512 becomes Figure 1A The first molding layer of the bottom RDL 521 is formed by a back grinding process to reduce the thickness of the bottom molding layer 512 to expose the top surface of the large ground area GND, the large switch node area SW, the power input area Vin, and the central portion of the plurality of contact pins. The exposed surface of the bottom RDL 521 is then protected from oxidation by applying chemical plating to form a Ni / Au coating. Block 412 may be followed by block 414.

[0032] In block 414, reference is now made to Figure 5G (Top view), a first plurality of through-holes 571 adjacent to the edge of the first MOSFET chip and a second plurality of through-holes 573 adjacent to the edge of the second MOSFET chip are drilled through the chip-level molding layer 516 to reach the intermediate RDL 540 after the assembly is released from the second carrier of the step in block 404 and back-ground to the target thickness. The first plurality of through-holes 571 are aligned with the power input region Vin, and the second plurality of through-holes 573 are aligned with the first source region S1 extending beyond the first MOSFET chip. After filling the through-holes and singulation, the filled first plurality of through-holes 571 become Figure 3G The first plurality of sub-via holes 371 and the filled second plurality of via holes 573 become Figure 3G The second plurality of sub-vias 373 may be formed. Block 414 may be followed by block 416.

[0033] In block 416, reference is now made to Figure 5H (Top view), forming a top RDL580 with a thickness between 40-150 microns. In the same process, by Figure 5G The first plurality of through-holes 571 are filled with conductors to form the first plurality of through-holes, and the first plurality of through-holes are formed by Figure 5G A second plurality of through-holes 573 is filled with a conductor to form a second plurality of through-holes. Top RDL 580 includes a first copper plate 582 and a second copper plate 586. The first copper plate 582 covers the drain region of the first MOSFET chip and the first plurality of through-holes, thereby establishing an electrical connection between the drain of the first MOSFET wafer and the power input Vin. The second copper plate 586 covers the drain region of the second MOSFET chip and the second plurality of through-holes, thereby establishing an electrical connection between the drain of the second MOSFET chip and the source of the first MOSFET chip. Top RDL 580 is formed by applying a seed layer, photolithography, copper plating, stripping and etching standard processes. Block 416 may be followed by block 418.

[0034] In block 418, reference is now made to Fig.5I(Top view), forming the top molding layer 518. Back grinding and marking processes are used. Block 418 may be followed by a singulation process.

[0035] Those skilled in the art will recognize that modifications to the embodiments disclosed herein are possible. For example, the number of chips in the semiconductor package may vary. Other modifications may be made by those skilled in the art, and all such modifications are considered to fall within the scope of the invention as defined by the claims.

Claims

1. A semiconductor package, comprising: Two or more chips include: a first chip; and a second chip; a first molding layer; a second molding layer, a bottom surface of the second molding layer directly contacting a top surface of the first molding layer; a third molding layer, a bottom surface of the third molding layer directly contacting a top surface of the second molding layer; a fourth molding layer, a bottom surface of the fourth molding layer directly contacting a top surface of the third molding layer; a bottom redistribution layer (RDL) including a power input pin, a switch pin, and a ground pin, a bottom surface of the bottom RDL being exposed from the bottom of the first molding layer, and a top surface of the bottom RDL being butted against a bottom surface of the second molding layer; a middle RDL, a bottom surface of the middle RDL directly contacts the second molding layer, and a top surface of the middle RDL is connected to a bottom surface of the third molding layer; and A top RDL, a bottom surface of the top RDL abuts against a top surface of the third molding layer. 2 . The semiconductor package of claim 1 , wherein at least one of the first chip and the second chip comprises a first front surface electrode electrically connected to the ground pin and a rear surface electrode electrically connected to the switch pin.

3. The semiconductor package of claim 1, wherein the top RDL comprises a copper plate substantially covering the entire rear surface of at least one of the first chip and the second chip, the copper plate comprising rear surface electrodes electrically connected to switch pins, wherein the copper plate is connected to a plurality of through holes connected to the switch pins. 4 . The semiconductor package of claim 3 , the two or more chips further comprising a third chip including a plurality of front surface electrodes connected to the intermediate RDL.

5. The semiconductor package of claim 1, wherein the first chip comprises a first front surface electrode electrically connected to the switch pin, and a rear surface electrode electrically connected to the power input pin; and The second chip includes: a first front surface electrode electrically connected to the ground pin, and One is electrically connected to the rear surface electrode of the switch pin.

6. The semiconductor package according to claim 5, The top RDL includes: a first copper plate; as well as a second copper; wherein the first copper plate substantially covers the entire rear surface of the first chip and is connected to a first plurality of through holes connected to the power input pins; and The second copper plate substantially covers the entire rear surface of the third chip and is connected to a second plurality of through holes connected to the switch pins.

7. The semiconductor package according to claim 6, wherein the top surface of the first copper plate is covered by the fourth molding layer; and The top surface of the second copper plate is covered by the fourth molding layer.

8. The semiconductor package according to claim 6, wherein The first plurality of through holes are arranged along a first direction; and The second plurality of through holes are arranged along a second direction perpendicular to the first direction.

9. The semiconductor package of claim 5, wherein the two or more chips further include a third chip; wherein, A sum of a front surface area of ​​the first chip, a front surface area of ​​the second chip, and a front area of ​​the third chip is at least 67% of a top surface area of ​​the semiconductor package.

10. The semiconductor package of claim 5, wherein the semiconductor package is a DC-DC buck converter.

11. The semiconductor package of claim 5, wherein the semiconductor package is a quad flat no-lead (QFN) package.

12. A method for manufacturing a semiconductor package, the method comprising the following steps: Prepare two or more chips, including: a first chip; and a second chip; forming a chip-level molding layer, wherein a plurality of front electrodes of the first chip and the second chip are exposed from a first surface of the chip-level molding layer; forming an intermediate redistribution layer RDL on the first surface of the chip-level molding layer; forming a lower molding layer covering the intermediate RDL, wherein the lower molding layer extends from the first surface of the chip-level molding layer to the first surface of the lower mold layer; forming a plurality of lower layer through holes through the first surface of the lower layer molding layer to the middle RDL; forming a bottom RDL and a plurality of through holes passing through the plurality of lower layer through-holes on a first surface of the lower mold layer; forming a lowermost molding layer, a bottom surface of the bottom RDL being exposed from a bottom surface of the lowermost molding layer; drilling a first plurality of via holes and a second plurality of via holes through the chip-level molding layer to the intermediate RDL; forming a first plurality of through-holes from the first plurality of through-holes, forming a second plurality of through-holes from the second plurality of through-holes, and forming a top RDL on a second surface of the chip level molding layer opposite to the first surface of the chip level molding layer; and A top molding layer is formed surrounding at least a portion of the top RDL.

13. The method of claim 12, wherein the bottom RDL comprises: A power input pin, a switch pin, and A ground pin; and At least one of the first chip and the second chip includes a first front surface electrode electrically connected to a ground pin, and One is electrically connected to the rear surface electrode of the switch pin.

14. The method of claim 13, wherein the top RDL comprises a copper plate that substantially covers the entire rear surface of at least one of the first chip and the second chip, the copper plate comprising the rear surface electrodes electrically connected to the switch pins; and wherein the copper plate is connected to a plurality of through-holes that are connected to the switch pins.

15. The method of claim 13, wherein the two or more chips further include a third chip; and wherein a plurality of front surface electrodes of the third chip are connected to the intermediate RDL.

16. The method of claim 15, The top RDL includes: a first copper plate; as well as a second copper; wherein the first copper plate substantially covers the entire rear surface of the first chip and is connected to a first plurality of through holes, wherein the first plurality of through holes are connected to the power input pins; and The second copper plate substantially covers the entire rear surface of the third chip and is connected to a second plurality of through holes connected to the switch pins.

17. The method of claim 16, wherein a top surface of the first copper plate is covered by the top molding layer; and wherein a top surface of the second copper plate is covered by the top molding layer.

18. The method of claim 15, wherein the semiconductor package is a DC-DC buck converter.

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