A digital channelized fast signal processing method and system based on Nyquist folding

Abstract

The present invention discloses a digital channelized fast signal processing method and system based on Nyquist folding. The method first uses the NYFR structure to undersample the signal received by the antenna using the analog periodic non-uniform sampling pulse train generated by the local oscillator, and folds the frequency band of the signal spectrum to below the Nyquist frequency. Secondly, the modulated signal folded below the Nyquist frequency is discretely digitized using the ADC integrated in the RFSoC. Finally, the discretely digitized data is divided into multiple sub-channels through digital channelization processing based on the IDFT multi-phase filtering structure. The receiver demodulates multiple sub-channels that arrive at the same time in parallel, reconstructs the signal received by the antenna, and completes the NYFR structure to quickly receive and process signals. The present invention significantly improves the instantaneous ultra-wide frequency band real-time monitoring and processing capabilities, can realize the reception and processing of instantaneous ultra-wide bandwidth frequency band signals, and reduces costs and complexity.

Description

Technical Field

[0001] The present invention belongs to the technical field of ultra-wideband receivers, and in particular relates to a digital channelized fast signal processing method and system based on Nyquist folded reception (NYFR) and radio frequency system on chip (RFSoC). Background Art

[0002] With the development of modern electronic technology, the frequency band used by signals has been extended to Ku or higher frequency bands, which brings higher challenges to the real-time monitoring and processing of ultra-wide frequency bands. Traditional conventional receivers use high-speed analog-to-digital converters (ADCs) to sample and process analog signals. However, due to the sampling frequency limitation of ADC devices, it is difficult to use a single low-speed ADC to achieve instantaneous reception and real-time processing of ultra-wide frequency bands, which limits the effective application in scenarios such as spectrum sensing.

[0003] In order to overcome the above problems, NYFR technology came into being. NYFR technology is a new sub-Nyquist sampling technology, which mixes the input signal with the local oscillator modulation signal to fold the high-frequency signal into a lower frequency band, thereby sampling the high-frequency signal at a lower sampling rate. NYFR technology not only reduces the dependence on high-frequency ADC, but also reduces the complexity and cost of the system.

[0004] Although NYFR technology can fold high-frequency signals into lower frequency bands, there will be multiple NYFR output signals in the frequency range output after the multi-component signals are folded, which increases the difficulty of processing NYFR output signals, and the NYFR folding process will also cause the signal-to-noise ratio to deteriorate. Therefore, digital channelization technology is introduced. Digital channelization can divide a frequency band into multiple narrowband channels, and each channel can be processed independently and in parallel. This not only enhances the system's multi-signal receiving and processing capabilities, but also reduces the data rate, while compensating for the deterioration of the signal-to-noise ratio caused by NYFR, and effectively improves the processing performance and real-time performance of the signal receiving system. By combining digital channelization and NYFR, the system can complete the real-time reception and processing of signals in an ultra-wide frequency band under low-speed ADC conditions, solving the problem of signal separation and rapid processing of multi-component NYFR output signals.

[0005] The emergence of RFSoC has brought new breakthroughs in the design of digital channelized receivers. RFSoC integrates ADC (analog-to-digital converter) and DAC (digital-to-analog converter), and combines programmable logic resources (FPGA) to provide a highly integrated, high-performance solution. A digital channelized fast signal reception and processing technology based on NYFR and RFSoC, through the combination of NYFR system architecture and digital channelization, can achieve the reception and processing of instantaneous ultra-wide bandwidth frequency band signals using only one low-speed ADC.

[0006] This digital channelized fast signal reception and processing technology based on NYFR and RFSoC has many advantages over traditional methods. First, it greatly reduces the demand for high-speed ADCs and reduces system costs. The introduction of digital channelization separates multi-component NYFR output signals, allowing multiple NYFR output signals to be quickly processed in parallel, while improving the SNR and ensuring the fast processing performance of NYFR output signals. In addition, the built-in FPGA of RFSoC makes the system more flexible and scalable when processing complex NYFR output signals. These advantages make the digital channelized real-time signal reception and processing technology based on NYFR and RFSoC have broad application prospects and important practical significance in the fields of electronic warfare and spectrum sensing. Summary of the invention

[0007] The present invention proposes a digital channelization fast signal processing method and system based on Nyquist folding, the purpose of which is to overcome the instantaneous receiving bandwidth of conventional receivers being limited by the ADC sampling rate. At the same time, by digitally channelizing the multi-component NYFR output signal, the frequency band folded below the Nyquist frequency by NYFR is divided into multiple narrowband channels, and the multi-component NYFR output signal can be separated. The present invention has the advantages of using a small amount of resources to realize the reception of instantaneous ultra-wideband signals and real-time processing of multiple NYFR output signals. Finally, the technology is applied to the RFSoC platform, and real-time monitoring of signals in ultra-wide bandwidth frequency bands can be realized with only one RFSoC integrated ADC and built-in FPGA. Compared with the traditional digital channelized receiver, which is limited by the upper limit of ADC sampling frequency and has difficulty in obtaining a larger instantaneous monitoring bandwidth, the present invention adopts the digital channelized fast signal receiving and processing technology based on NYFR and RFSoC. Through digital channelization, the frequency band below the Nyquist frequency after folding the NYFR is divided into multiple narrowband channels. Each channel can be processed in parallel, and the multi-component NYFR output signal can be effectively extracted and separated, so as to realize real-time reception and rapid processing of multi-component signals in an ultra-wide frequency band. At the same time, digital channelization reduces the data rate, improves the signal-to-noise ratio (SNR), and effectively improves the NYFR output signal processing performance. This technology can complete the real-time reception and processing of instantaneous ultra-wide frequency band multi-component signals with only a single-chip low-speed ADC.

[0008] A digital channelized fast signal processing method based on Nyquist folding, the technical solution adopted is:

[0009] The analog periodic non-uniform sampling pulse train generated by the local oscillator (LO) is used through the NYFR structure to undersample the high-frequency signal of the ultra-wide frequency band received by the antenna, and the frequency band of the signal spectrum is folded from the high frequency band to below the Nyquist frequency.

[0010] The NYFR structure output is folded to a complex modulated signal below the Nyquist frequency, and is discretely digitized using the ADC with a sampling rate of fs integrated in the RFSoC. The data after discrete digitization is real data.

[0011] The data discretely digitized by ADC is processed by digital channelization based on the inverse discrete Fourier transform IDFT multi-phase filtering structure to reduce the data rate and improve the signal-to-noise ratio. The digital channelization divides the frequency band below the Nyquist frequency after NYFR folding into multiple narrowband sub-channels, separates the multi-component NYFR output signal, and the receiver demodulates multiple sub-channels arriving at the same time in parallel to reconstruct the original signal, thus completing the NYFR structure's rapid reception and processing of ultra-wideband signals.

[0012] Preferably, the input noisy signal of the NYFR structure is s(t), and the zero-crossing rising edge is used to control the sampling clock of the RF front end to generate a local oscillator (LO) non-uniform sampling pulse train p(t).

[0013]

[0014] Where, δ(·) is the impulse function, k is a positive integer, and LO is modulated by sinusoidal frequency modulation. fLO is the LO carrier frequency, fsin is the modulation frequency, This is the initial phase of LO.

[0015] Input noisy signal: s(t) = A cos(2πfct) + w(t)

[0016] A is the signal amplitude, fc is the input signal carrier frequency, w(t) is the noise, s(t) and p(t) are mixed to obtain xs(t)=s(t)p(t), and then xs(t) is passed through a low-pass filter with a passband cutoff frequency of fLO / 2 to obtain the NYFR output signal x(t).

[0017]

[0018] A1 is the amplitude of the NYFR output signal, kNZ=round(fc / fLO), round(·) is rounding, sgn(·) is the sign function, w1(t) is the output noise, and the carrier frequency of the complex modulated signal output by the NYFR structure is |fc-kNZfLO|.

[0019] Preferably, the ADC with a sampling rate of fs built into the RFSoC chip is used to discretely digitize the NYFR output signal. The frequency range of the discrete digitized signal is 0 to fs / 2, and the discrete digitization interval Ts=1 / fs. The data after discrete digitization by the ADC is real data. The expression after discrete digitization by the ADC can be written as:

[0020]

[0021] When the local oscillator carrier frequency is fLO, the signal frequency band received by the antenna is divided into a frequency band every fLO / 2. The signals of each frequency band are folded into the frequency band of 0 to fLO / 2 through undersampling, and have different Nyquist zone NZ label information. The NZ label is sgn(fc-kNZfLO)kNZ, which is convenient for subsequent signal reconstruction.

[0022] Preferably, based on the FIR low-pass filter, the real data x(n) discretely digitized by the ADC is digitally channelized based on multiphase filtering and IDFT efficient structure, and the ADC discretely digitized data is digitally channelized into K channels, where K is an integer multiple of 2, and the channels are divided into even-type channels, with 50% overlap between channels. The frequency range of 0 to fs / 2 is evenly divided into K1=K / 2 channels, and the other half of the channels are mirror images of negative frequencies, which are useless for subsequent processing and are discarded. The bandwidth of each sub-channel is B=fs / (2K1), and the processing bandwidth is 2B.

[0023] Preferably, the parameters of the FIR low-pass filter are designed according to the passband cutoff frequency fpass=(fs / 2) / K, the stopband start frequency fstop=2fpass, and the order is 8K. The prototype FIR low-pass filter is subjected to K-fold decimation and then 2-fold interpolation to determine the multiphase component filters hl, l=0, 1, ..., K-1 of each channel.

[0024] Preferably, the data x(n) after discrete digitization by ADC is extracted M=K / 2 times as the data input of each channel. The l-th channel data xl(m)=x(Mm-l), l=0,1,…,K-1 passes through the multi-phase component filter hl, l=0,1,…,K-1, and the result is εl=xl*hl (* is convolution), l=0,1,…,K-1; then the result εl, l=0,1,…,K-1 of the K-channel multi-phase filtering is subjected to K-point IDFT transformation to move the spectrum to the baseband.

[0025] Preferably, the output of the efficient digital channelization structure based on polyphase filtering and IDFT is:

[0026]

[0027] Perform K-point IDFT transformation on the polyphase filtering results of K channels, and then multiply by the coefficient (-1) lm , and obtain the digital channelized output yl(m), l=0,1,…,K-1.

[0028] Preferably, the data rate of the ADC sampling data is reduced after digital channelization processing, which has strong real-time performance and is convenient for subsequent data processing. The ADC with a sampling rate of fs integrated in RFSoC is used for sampling, and digital channelization of K channels with 50% overlap between channels is performed. The data extraction multiple is M=K / 2 times, and the frequency range of 0~fs / 2 is divided into K1=K / 2 channels. The bandwidth of each channel is fs / (2K1), and the processing bandwidth is fs / K1. The ADC sampling data is converted into a clock using fs / K1, and each clock inputs K1 ADC sampling data into the digital channelization module. The digital channelization processes the ADC sampling data in parallel. After digital channelization, the data output by each subchannel is converted from one input real number data with a data rate of fs to two IQ data with a data rate of fs / K1, and the data rate is reduced by K1 / 2 times. At the same time, compared with the ADC data with a sampling rate of fs, the channelized data can ideally improve the SNR of 10lgK1dB.

[0029] Finally, a low-speed ADC is used to monitor the reception of signals within an ultra-wide frequency band.

[0030] Another aspect of the present invention provides a digital channelized fast signal processing system based on Nyquist folding, comprising a NYFR receiving module, an ADC discretization module and a digital channelization module.

[0031] The NYFR receiving module is used to perform under-sampling of the signal received by the antenna using the analog periodic non-uniform sampling pulse train generated by the local oscillator LO, and fold the frequency band of the signal spectrum below the Nyquist frequency.

[0032] The ADC discretization module performs ADC discrete digitization on the modulated signal folded below the Nyquist frequency.

[0033] The digital channelization module divides the data discretely digitized by the ADC into multiple sub-channels through digital channelization processing based on the IDFT multi-phase filtering structure. The receiver demodulates multiple sub-channels arriving at the same time in parallel to reconstruct the signal received by the antenna.

[0034] The present invention provides a digital channelization fast signal processing method and system based on Nyquist folding. By applying digital channelization to NYFR reception, the frequency band below the Nyquist frequency after NYFR folding is divided into multiple narrowband channels, and multi-component NYFR output signals can be effectively extracted and separated. Multiple NYFR output signals can be received and quickly processed simultaneously and in parallel, which significantly improves the instantaneous ultra-wide frequency band real-time monitoring and processing capabilities of the system. Only one ADC is needed to realize the reception and processing of instantaneous ultra-wide bandwidth frequency band signals, which reduces the system cost and complexity. The built-in FPGA of RFSoC realizes digital channelization processing, has high integration, and improves the signal-to-noise ratio, which provides an efficient and reliable solution for the real-time reception and processing of signals in the ultra-wide frequency band. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a flowchart of the present invention;

[0036] Figure 2 It is the NYFR structure diagram;

[0037] Figure 3 This is the NZ zone numbering diagram of different frequency bands after NYFR folding;

[0038] Figure 4 It is the signal spectrum diagram of the 12.7GHz single-carrier signal sampled and output by the ADC of the NYFR receiving structure;

[0039] Figure 5 It is a digital channelization frequency domain partition diagram of 32 channels with 50% overlap;

[0040] Figure 6 This is the signal spectrum diagram of the 12.7GHz single-carrier signal after digital channelization by the NYFR receiving structure;

[0041] Figure 7 This is a diagram of the digital channelization structure based on IDFT polyphase filtering;

[0042] Figure 8 This is the block diagram of the FPGA implementation of polyphase filtering;

[0043] Fig. 9 This is a diagram of digital channelized FPGA simulation results;

[0044] Fig.10 It is the signal spectrum diagram of the ADC sampling output of two single-carrier signals at 5.25GHz and 16.8GHz;

[0045] Fig.11 This is the output spectrum diagram of the 5th subchannel when two single-carrier signals of 5.25GHz and 16.8GHz are input;

[0046] Fig.12This is the output spectrum diagram of the 8th subchannel when two single-carrier signals of 5.25 GHz and 16.8 GHz are input. DETAILED DESCRIPTION

[0047] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0048] A digital channelization fast signal processing system based on Nyquist folding mainly includes a NYFR receiving module, an ADC sampling and a digital channelization module. The NYFR receiving module receives the signal from the antenna, and uses the periodic non-uniform sampling characteristics of the LO modulated signal to fold the high-frequency signal on the ultra-wide frequency band to the 0-2GHz frequency band where the ADC can sample without distortion (the LO carrier frequency is selected as 4GHz). The 5GHz sampling rate ADC integrated in the RFSoC is used to discretely digitize the NYFR output signal, and the signal folded and output to the 0-2GHz frequency band by the NYFR is sampled, and the sampled data is real data. Digital channelization uses the built-in FPGA of the RFSoC to perform digital channelization processing of 32 channels based on the IDFT multi-phase filtering structure on the data sampled by the ADC, wherein the 0-2.5GHz frequency range where the ADC can sample without distortion is evenly divided into 16 channels, and each sub-channel outputs two IQ data for subsequent signal processing. The channelization adopts a channelization with 50% overlap between channels, which reduces the data rate, improves the signal-to-noise ratio, and has no blind spots within the coverage bandwidth.

[0049] like Figure 1 and Figure 2 As shown, a digital channelization fast signal processing method based on Nyquist folding includes the following steps:

[0050] Step 1: Through the NYFR structure, the analog periodic non-uniform sampling pulse train generated by the local oscillator LO is used to undersample the signal received by the antenna and fold the frequency band of the signal spectrum below the Nyquist frequency.

[0051] Step 2: The modulated signal folded below the Nyquist frequency is discretely digitized using the RFSoC’s integrated ADC with a sampling rate of fs.

[0052] Step 3: The data discretely digitized by the ADC is divided into multiple sub-channels through digital channelization processing based on the IDFT multi-phase filtering structure. The receiver demodulates multiple sub-channels arriving at the same time in parallel and reconstructs the signal received by the antenna, completing the NYFR structure to quickly receive and process the signal.

[0053] In this embodiment, the input noisy signal of the NYFR structure is s(t), and the zero-crossing rising edge is used to control the sampling clock of the RF front end to generate a local oscillator (LO) non-uniform sampling pulse train p(t), and tk is the zero-crossing rising edge time.

[0054]

[0055] Where, δ(·) is the impulse function, k is a positive integer, and LO is modulated by sinusoidal frequency modulation. fLO is the LO carrier frequency, which is 4 GHz. fsin is the modulation frequency, which is 10 MHz. is the initial phase of LO. p(t) can be written as:

[0056] Input signal: s(t) = Acos(2πfct) + w(t), A is the signal amplitude, fc is the input signal carrier frequency, and w(t) is the noise. s(t) is mixed with the modulated non-uniform sampling pulse train generated by LO to obtain xs(t) = s(t)p(t). The mixed signal xs(t) passes through a low-pass filter with a passband cutoff frequency of fLO / 2 to obtain the NYFR output signal x(t). In this embodiment, fLO uses 4GHz, so the passband cutoff frequency of the low-pass filter is 2GHz. The NYFR output signal x(t) can be expressed as:

[0057]

[0058] A1 is the NYFR output signal amplitude, kNZ = round(fc / fLO), round(·) is rounding, sgn(·) is the sign function, and w1(t) is the output noise. The carrier frequency of the complex modulated signal folded to the 0-2GHz frequency band by the NYFR structure is |fc-kNZfLO|.

[0059] In this embodiment, the 5 GHz sampling rate ADC integrated in the RFSoC chip is used to discretely digitize the NYFR output signal x(t). The frequency range of the discrete digitized signal is 0 to 2.5 GHz, the discrete digitization interval Ts=0.2 ns, and the data after discrete digitization by the ADC is real data. The expression after discrete digitization by the ADC can be written as:

[0060]

[0061] When the LO carrier frequency fLO is 4GHz and the modulation frequency fsin is 10MHz, the ultra-wide frequency band is divided into a frequency band every 2GHz. The signals of each frequency band are folded into the frequency band of 0~2G through undersampling and have different NZ label information. The NZ label is sgn(fc-kNZfLO)kNZ, which is convenient for subsequent signal demodulation and reconstruction. Figure 3As shown in the NZ zone numbering, the monitored ultra-wide frequency band is divided into an NZ zone every fLO / 2, and the frequency range of each zone is pfLO / 2 to (p+1)fLO / 2, where p = 0, 1, 2, ..., P. (P+1)fLO / 2 is the upper frequency limit of the monitored ultra-wide frequency band. When p is an even number, the NZ zone is numbered p / 2, and when p is an odd number, the NZ zone is numbered -(p+1) / 2.

[0062] In this embodiment, when NYFR receives a single carrier signal with a frequency of 12.7 GHz, kNZ=round(fc / fLO) is 3. Theoretically, the carrier frequency of the complex modulated signal output by the NYFR structure after the signal carrier frequency fc=12.7 GHz is |fc-kNZfLO|=0.7 GHz. The spectrum diagram after discrete digitization by ADC is as follows: Figure 4 As shown, the carrier frequency of the signal is 0.7 GHz. For conventional sampling structures, if you want to collect signals within 12.7 GHz, the required ADC sampling rate is at least 25.4 GHZ. In this embodiment, the ADC sampling rate required by NYFR only needs to be greater than 2 GHz to effectively collect signals within 12.7 GHz, and even process signals with higher frequencies, which shows the advantage of NYFR in reducing the sampling rate requirements.

[0063] In this embodiment, the data x(n) sampled by the ADC is digitally channelized based on the IDFT multi-phase filtering efficient structure, such as Figure 5 As shown in the channel division diagram, a division method of 32 channels arranged in an even pattern is adopted, with 50% overlap between channels. The frequency range of 0 to 2.5 GHz is evenly divided into 16 sub-channels, and the channel numbers are 0, 1, 2, ..., 15, and the other half of the channels are mirror images of negative frequencies. The bandwidth of each sub-channel is 156.25 MHz, and the processing bandwidth is 312.5 MHz. The center frequency of each sub-channel is the channel number multiplied by 156.25 MHz. Since the frequency band output after NYFR folding in this embodiment has a frequency range of 0 to 2 GHz, only the channels in the range of 0 to 2 GHz are used for subsequent processing and calculation. Figure 6 It is the 4th channel output after the ADC sampling data is digitally channelized. The sub-channel center frequency is 4 times 156.25MHz, and the center frequency is 625MHz. It is the output signal spectrum diagram of the 12.7GHz signal after being sampled by the ADC and then channelized after the NYFR structure.

[0064] In this embodiment, 32 channels of digital channelization are adopted, and the parameters of the FIR low-pass filter are designed according to the passband cutoff frequency fpass=78.125MHz and the stopband starting frequency fstop=156.25MHz. According to the description, the order of the prototype FIR low-pass filter in this embodiment is 256 orders, which is extracted 32 times and then interpolated 2 times to determine the multi-phase component filter hl of each channel, l=0,1,…,31.

[0065] In this embodiment, the Figure 7 The digital channelization based on the IDFT multi-phase filtering efficient structure shown in the figure reduces the amount of calculation and saves FPGA resources. It adopts 32-channel digital channelization, so the signal x(n) after ADC discrete digitization is extracted 16 times. In the FPGA, the ADC discrete digitized data with a sampling rate of 5GHz is converted into 16 ADC discrete digitized data with a clock rate of 312.5MHz, and each clock is input in parallel as the data input of each channel. The implementation of the multi-phase filtering process of each channel in the FPGA is shown in the figure. Figure 8 As shown in the figure, the FPGA filtering implementation of the multi-phase filter order is 8. Each channel multi-phase filtering process can be pipelined with 8 multipliers, and the ADC discrete digital data can be processed in real time and in parallel. The result of the l-th channel data xl(m) = x(Mm-l), l = 0, 1, ..., 31 after passing through the multi-phase component filter hl, l = 0, 1, ..., 31 is εl = xl*hl (* is convolution), l = 0, 1, ..., 31, and then the result of the multi-phase filtering of 32 channels εl, l = 0, 1, ..., 31 is transformed by 32 points of IDFT to move the spectrum to the baseband. IDFT uses a butterfly operation fast algorithm in FPGA to process data in pipeline parallel to realize real-time processing of ADC discrete digital data. During the entire implementation process, the data does not need to be stored and flows directly to the next level, and no data accumulation is generated during the operation.

[0066] In this embodiment, the output of digital channelization based on the IDFT polyphase filtering efficient structure is:

[0067]

[0068] Perform a 32-point IDFT transform on the polyphase filtering results of the 32 channels, and then multiply by the coefficient (-1) lm , and obtain the digital channelized output yl(m), l=0,1,…,31.

[0069] In this embodiment, the built-in FPGA of RFSoC is used to implement digital channelization, which has fast real-time processing speed, low data rate, and saves subsequent calculation amount. An ADC with a sampling rate of 5GHz is used for discrete digitization, and digital channelization of 32 channels with 50% overlap between channels is performed. The frequency range of 0-2.5GHz is divided into 16 channels, and the ADC discrete digitized data is converted into a 312.5MHz clock. Each clock inputs 16 ADC discrete digitized data into the digital channelization module. The digital channelization module processes the data in parallel. After digital channelization, the data of each sub-channel is converted from real number data with an ADC data rate of 5GHz to IQ two-way data with a data rate of 312.5MHz, and the data rate is reduced by 8 times. Ideally, the data after digital channelization can improve the SNR by about 12dB, making the signal more accurate and stable, so that the ability to process the NYFR output signal in the subsequent process is greatly improved. The FPGA simulation of digital channelization is as follows Fig. 9 As shown, the FPGA performs digital channelization processing on the ADC sampling data in parallel. The whole process is carried out in the form of a pipeline. The data flows directly from the previous level to the next level. No data is stored in the whole operation process. It only takes about 122ns from the ADC sampling data input to the digital channelization data output. It has strong real-time performance and realizes the real-time processing capability of the receiver for multi-component NYFR output signals.

[0070] In the present invention, a digital channelized fast signal processing method based on Nyquist folding uses RFSoC integrated ADC and built-in FPGA, which reduces external connections and wiring and improves the reliability and stability of the system. The signal output by the NYFR structure is digitally channelized, and the frequency band below the Nyquist frequency after NYFR folding is divided into multiple narrowband channels, and the multi-component NYFR output signal is effectively extracted and separated, so that the receiver can process multiple NYFR output signals in real time and in parallel quickly, so that the NYFR technology can be applied to real-time signal reception. For the input of two signals, such as the simultaneous input of single-carrier signals of 5.25 GHz and 16.8 GHz, theoretically, the carrier frequency of the 5.25 GHz signal after folding is 1.25 GHz, and the carrier frequency of the 16.8 GHz signal after folding is 0.8 GHz. The actual output signal spectrum after ADC discrete digitization is as shown in the figure. Fig.10 As shown, it is consistent with the theoretical value. Fig.11 In order to actually collect the spectrum of the output signal of the 5th channel after digital channelization, the channel center frequency is 781.25MHz, corresponding to the signal after 16.8GHz single carrier folding. Fig.12To actually collect the spectrum of the 8th channel output signal after digital channelization, the channel center frequency is 1.25GHz, which corresponds to the signal after folding the 5.25GHz single carrier, which is consistent with the theoretical value. In this embodiment, digital channelization is introduced to convert the 5GHz rate real data of the ADC discrete digitized NYFR output signal into IQ two-way data output at a rate of 312.5MHz for each subchannel, thereby reducing the data rate by 8 times. Ideally, the signal-to-noise ratio can be improved by about 12dB, thereby improving the subsequent signal processing efficiency. By combining NYFR and digital channelization and applying them to the RFSoC platform, it is possible to use a single ADC to receive and monitor signals in an instantaneous ultra-wide bandwidth frequency band.

[0071] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A digital channelized fast signal processing method based on Nyquist folding, characterized in that: The following steps are involved: Step 1: Through the NYFR structure, the analog periodic non-uniform sampling pulse train generated by the local oscillator LO is used to undersample the signal received by the antenna, and the frequency band of the signal spectrum is folded below the Nyquist frequency; Step 2: The modulated signal folded below the Nyquist frequency is discretely digitized using the ADC with a sampling rate of fs integrated in the RFSoC. The specific implementation process is as follows: The ADC with a sampling rate of fs built into the RFSoC chip is used to discretely digitize the NYFR output signal. The frequency range of the discrete digitized signal is 0 to fs / 2, and the discrete digitization interval is T s =1 / fs, the data after ADC discrete digitization is real data, and the expression after ADC discrete digitization is written as: Among them, the local oscillator carrier frequency is f LO , then the signal frequency band received by the antenna is every f LO / 2 is divided into a frequency band, and the signals of each frequency band are folded to 0~f through undersampling. LO / 2 frequency band, and has different label information, labelled as sgn(f c -k NZ f LO ) NZ ; Step 3: The data discretely digitized by the ADC is divided into multiple sub-channels through digital channelization processing based on the IDFT multi-phase filtering structure. The receiver demodulates multiple sub-channels arriving at the same time in parallel and reconstructs the signal received by the antenna, completing the NYFR structure to quickly receive and process the signal.

2. The digital channelized fast signal processing method based on Nyquist folding according to claim 1, characterized in that: The input noisy signal of the NYFR structure is s(t), and the sampling clock of the RF front end is controlled by the zero-crossing rising edge to generate the local oscillator LO non-uniform sampling pulse train p(t): Where, δ(·) is the impulse function, k is a positive integer, and LO is modulated by sinusoidal frequency modulation. f LO is the LO carrier frequency, f sin is the modulation frequency, It is the initial phase of LO; Input noisy signal: s(t) = A cos(2πf c t)+w(t); Where A is the signal amplitude, f c is the input signal carrier frequency, w(t) is the noise, s(t) and p(t) are mixed to get x s (t) = S(t)p(t), and then x s (t) passes through a passband with a cutoff frequency of f LO The NYFR output signal x(t) is obtained by a low-pass filter of / 2: A1 is the NYFR output signal amplitude, k NZ =round(f c / f LO ), round(·) is rounding, sgn(·) is the sign function, w1(t) is the output noise, and the carrier frequency of the modulated signal output by the NYFR structure is |f c -k NZ f LO |.

3. The digital channelization fast signal processing method based on Nyquist folding according to claim 2, characterized in that: The specific implementation process of step 3 is as follows: The real number data x(n) discretely digitized by the ADC is subjected to multi-phase filtering based on the FIR low-pass filter and digital channelization processing based on IDFT. The ADC sampling data is digitally channelized into K channels, where K is an integer multiple of 2. The channels are divided into even-arranged channels with a 50% overlap between the channels. The frequency range of 0 to fs / 2 is evenly divided into K1=K / 2 channels, and the other half of the channels are mirror images of negative frequencies and are discarded. The bandwidth of each sub-channel is B=fs / (2K1), and the processing bandwidth is 2B.

4. The digital channelized fast signal processing method based on Nyquist folding according to claim 3, characterized in that: The polyphase filtering based on the FIR low-pass filter is specifically implemented as follows: The parameters of the FIR low-pass filter are based on the passband cutoff frequency f pass =(fs / 2) / K, stopband start frequency f stop =2f pass , the order is designed to be 8K; after K times decimation according to the FIR low-pass filter, 2 times interpolation is performed to determine the multiphase component filter h of each channel l , l=0,1,…,K-1.

5. The digital channelization fast signal processing method based on Nyquist folding according to claim 4, characterized in that: The specific process of the digital channelization processing based on FIR low-pass filter polyphase filtering and IDFT is as follows: The ADC discrete digitized data x(n) is extracted M = K / 2 times as the data input of each channel; the lth channel data x l (m) = x(Mm-l), l = 0, 1, ..., K-1 through the multiphase component filter h l , the result after l=0,1,…,K-1 is ε l =x l *h l ; where * is convolution, l = 0, 1, ..., K-1; then the result of K channel polyphase filtering ε l , l=0,1,…,K-1, perform K-point IDFT transformation to move the spectrum to the baseband.

6. The digital channelized fast signal processing method based on Nyquist folding according to claim 5, characterized in that: The output of the digital channelization processing based on FIR low-pass filter polyphase filtering and IDFT is: Perform K-point IDFT transformation on the polyphase filtering results of K channels, and then multiply by the coefficient (-1) lm , and obtain the digital channelized output y l (m), l=0,1,…,K-1.

7. A digital channelized fast signal processing system based on Nyquist folding, used to implement the digital channelized fast signal processing method according to any one of claims 1 to 6, characterized in that: It includes NYFR receiving module, ADC discretization module and digital channelization module; The NYFR receiving module is used to undersample the signal received by the antenna using the analog periodic non-uniform sampling pulse train generated by the local oscillator LO, and fold the frequency band of the signal spectrum below the Nyquist frequency; The ADC discretization module performs ADC discrete digitization on the modulated signal folded below the Nyquist frequency; The digital channelization module divides the data discretely digitized by the ADC into multiple sub-channels through digital channelization processing based on the IDFT multi-phase filtering structure. The receiver demodulates multiple sub-channels arriving at the same time in parallel to reconstruct the signal received by the antenna.

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