Semiconductor device

Abstract

Disclosed is a semiconductor device including: an active pattern including a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending in a second direction between the first edge portion and the second edge portion; a bit line extending along a third direction on the first edge portion; a storage node contact on the second edge portion; a first active pad between the bit line and the first edge portion; and a second active pad between the storage node contact and the second edge portion. The first active pad extends beyond the first edge portion in the third direction. The second active pad extends beyond the second edge portion in a direction opposite the third direction.

Description

Technical Field

[0001] The inventive concept relates to semiconductors, and more particularly, to semiconductor devices and methods of manufacturing the same. Background Art

[0002] Semiconductor devices play an important role in the electronics industry due to their small size, multiple functions and / or low manufacturing cost. Semiconductor devices can be classified into any of semiconductor memory devices that store logic data, semiconductor logic devices that process logic data operations, and hybrid semiconductor devices that have both memory and logic elements.

[0003] Recently, the high speed and low energy consumption of electronic products may require the semiconductor devices embedded in the electronic products to have high operating speed and / or lower operating voltage. In order to meet the above requirements, semiconductor devices have been highly integrated. Therefore, in order to improve the reliability of semiconductor devices, people have conducted various researches. Summary of the invention

[0004] Some embodiments of the inventive concept provide a semiconductor device that is easy to manufacture and has a higher integration density, and a method of manufacturing the same.

[0005] Some embodiments of the inventive concept provide a semiconductor device having improved electrical performance and higher reliability and a method of manufacturing the same.

[0006] The objects of the present invention are not limited to the above contents, and those skilled in the art will clearly understand other objects not mentioned above through the following description.

[0007] According to some embodiments of the present inventive concept, a semiconductor device may include: a substrate; an active pattern located on the substrate, the active pattern including a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending between the first edge portion and the second edge portion of the active pattern in a second direction, the second direction intersecting the first direction; a bit line extending on the first edge portion of the active pattern in a third direction, the third direction intersecting the first direction and the second direction; a storage node contact located on the second edge portion of the active pattern; a first active pad located between the bit line and the first edge portion of the active pattern; and a second active pad located between the storage node contact and the second edge portion of the active pattern. The first active pad extends beyond the first edge portion of the active pattern in the third direction. The second active pad extends beyond the second edge portion of the active pattern in a direction opposite to the third direction.

[0008] According to some embodiments of the present invention, a semiconductor device may include: a substrate; an active pattern located on the substrate, the active pattern including a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending between the first edge portion and the second edge portion of the active pattern in a second direction, the second direction intersecting the first direction; a bit line extending on the first edge portion of the active pattern in a third direction, the third direction intersecting the first direction and the second direction; a storage node contact located on the second edge portion of the active pattern; a first active pad located between the bit line and the first edge portion of the active pattern; and a second active pad located between the storage node contact and the second edge portion of the active pattern. With respect to the substrate, a top surface of the second active pad is higher than a bottom surface of the bit line.

[0009] According to some embodiments of the present invention, a semiconductor device may include: a substrate; an active pattern located on the substrate, the active pattern including a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending between the first edge portion and the second edge portion of the active pattern along a second direction, the second direction intersecting the first direction; a bit line extending on the first edge portion of the active pattern along a third direction, the third direction intersecting the first direction and the second direction; a lower storage node contact located on the active pattern The invention relates to a method for storing a plurality of active patterns, wherein the first active pad is disposed on the second edge portion of the active pattern; an upper storage node contact, the upper storage node contact being located on the lower storage node contact, the upper storage node contact partially overlapping the lower storage node contact in a direction perpendicular to the second direction; a first active pad, the first active pad being between the bit line and the first edge portion of the active pattern; a second active pad, the second active pad being between the lower storage node contact and the second edge portion of the active pattern; a landing pad, the landing pad being located on the upper storage node contact; and a data storage pattern, the data storage pattern being located on the landing pad. The first active pad extends beyond the first edge portion of the active pattern in the third direction. The second active pad extends beyond the second edge portion of the active pattern in a direction opposite to the third direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0011] Figure 1B Shown is a partial display Figure 1A A magnified view of the configuration shown in .

[0012] Figure 2A , Figure 2B , Figure 2C and Figure 2D The Figure 1A Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0013] Figures 3 to 5 Shown along Figure 1A A cross-sectional view taken along line AA'.

[0014] Fig. 6A , Figure 6B and Figure 6C The Figure 1A Cross-sectional views taken along line BB', line CC' and line DD'.

[0015] Fig. 7A , Figure 7B and Figure 7C The Figure 1A Cross-sectional views taken along line BB', line CC' and line DD'.

[0016] Fig. 8A and Figure 8B The Figure 1A A cross-sectional view taken along line AA' and line DD'.

[0017] Fig. 9 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0018] Fig. 10A , Fig. 10B and Fig. 10C The Fig. 9 Cross-sectional views taken along line AA', line CC' and line DD'.

[0019] Fig.11 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0020] Fig.12 Shown along Fig.11 A cross-sectional view taken along line AA'.

[0021] Fig.13 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0022] Fig.14A and Fig. 14BThe Fig.13 A cross-sectional view taken along line BB' and line DD'.

[0023] Fig.15 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0024] Fig.16A , Fig. 16B , Fig. 16C and Fig.16D The Fig.15 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0025] Fig.17 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0026] Fig.18A , Fig.18B , Fig.18C and Fig.18D The Fig.17 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0027] Fig.19 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0028] Fig. 20A , Fig. 20B , Fig. 20C and Fig.20D The Fig.19 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0029] Fig.21 Shown along Fig.19 A cross-sectional view taken along line AA'.

[0030] Fig. 22 is a plan view showing a semiconductor device according to some embodiments of the inventive concept.

[0031] Fig.23A , Fig. 23B , Fig.23C and Fig.23D The Fig. 22 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0032] Fig.24A and Fig. 24B The Figure 1A A cross-sectional view taken along line BB' and line CC'.

[0033] Fig.25 , Fig.26A , Fig.26B , Fig.26C , Fig.26D , Fig. 27 , Fig.28A , Fig.28B , Fig.28C , Fig.28D , Fig.29 , Fig. 30A , Fig. 30B , Fig. 30C , Fig.30D , Fig.31 , Fig.32A , Fig.32B , Fig.32C , Fig.32D , Fig.33 , Fig.34A , Fig.34B , Fig.34C and Fig.34D are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0034] Fig.35 is a cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0035] Figure 36 to Figure 39 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0036] Figure 40 to Figure 43 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0037] Fig.44 , Fig.45A , Fig.45B , Fig.45C , Fig.46 , Fig.47A , Fig.47B and Fig.47C are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0038] Fig.48 , Fig.49A , Fig.49B and Fig.49C are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0039] Fig.50A and Fig.50B is a cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0040] Fig.51 , Fig.52A , Fig.52B , Fig.52C , Fig.53 , Fig.54A , Fig.54B and Fig.54C are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0041] Fig.55 and Fig.56 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0042] Fig.57 , Fig.58A and Fig.58B are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0043] Fig.59 , Fig.60A , Fig.60B , Fig.60C and Fig.60D are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0044] Fig.61 , Fig.62A , Fig.62B , Fig.62C , Fig.62D , Fig.63 , Fig.64A , Fig.64B , Fig.64C and Fig.64D are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0045] Fig.65 and Fig.66 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0046] Fig.67 , Fig.68A , Fig.68B , Fig.68C and Fig.68D are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0047] Fig.69A and Fig.69B is a cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0048] Some embodiments of the present inventive concept will now be described in detail with reference to the accompanying drawings to help clearly explain the present inventive concept.

[0049] Figure 1A is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Figure 1B Shown is a partial display Figure 1A A magnified view of the configuration shown in . Figure 2A , Figure 2B , Figure 2C and Figure 2D The Figure 1A Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0050] refer to Figure 1A and FIG. 2A to FIG. 2D , a substrate 100 may be provided. The substrate 100 may be a semiconductor substrate, for example, a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0051] A device isolation pattern STI defining an active pattern ACT may be provided in the substrate 100. The active pattern ACT may be provided in plurality. For example, the active pattern ACT may include a portion of the substrate 100 surrounded by the device isolation pattern STI. For ease of description, unless otherwise specifically stated in the present disclosure, the substrate 100 may be defined as indicating another portion other than the portion of the substrate 100.

[0052] Each active pattern ACT may have a shape elongated in a first direction D1 parallel to the bottom surface of the substrate 100. The active patterns ACT may be spaced apart from each other in a second direction D2 and a third direction D3 that intersect each other and are parallel to the bottom surface of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 may intersect each other. The active pattern ACT may have a shape protruding in a fourth direction D4 perpendicular to the bottom surface of the substrate 100. For example, the active pattern ACT may include silicon, such as single crystal silicon.

[0053] The active pattern ACT may include a first edge portion EA1 and a second edge portion EA2 spaced apart from each other in the first direction D1, and may further include a center portion CA between the first edge portion EA1 and the second edge portion EA2. The first edge portion EA1 and the second edge portion EA2 may be opposite ends of the active pattern ACT in the first direction D1. The center portion CA may be provided below a word line WL passing through the active pattern ACT described later. The word line WL described later may vertically overlap the center portion CA of the active pattern ACT. The center portions CA of the active pattern ACT may be spaced apart from each other in the second direction D2 and the third direction D3.

[0054] The first and second edge portions EA1 and EA2 and the central portion CA may each include an impurity region doped with impurities (eg, n-type or p-type impurities) therein. The impurity region may constitute or form a source / drain region and / or a channel region.

[0055] Adjacent active patterns ACT may be arranged side by side along the second direction D2 (or the opposite direction thereof) or the third direction D3 (or the opposite direction thereof). In the present disclosure, the phrase "adjacent active patterns ACT are arranged side by side along a certain direction" may mean that the first edge portions EA1 of adjacent active patterns ACT are arranged along a certain direction.

[0056] refer to Figure 1B , the first active pattern ACT1, the second active pattern ACT2, the third active pattern ACT3 and the fourth active pattern ACT4 may be arranged in a clockwise direction. The first active pattern ACT1 and the second active pattern ACT2 next thereto may be arranged side by side along the second direction D2. The fourth active pattern ACT4 and the third active pattern ACT3 next thereto may be arranged side by side along the second direction D2. The first active pattern ACT1 and the fourth active pattern ACT4 next thereto may be arranged side by side along the third direction D3. The second active pattern ACT2 and the third active pattern ACT3 next thereto may be arranged side by side along the third direction D3.

[0057] The second edge portion EA2 of the fourth active pattern ACT4, the first edge portion EA1 of the first active pattern ACT1, the second edge portion EA2 of the third active pattern ACT3, and the first edge portion EA1 of the second active pattern ACT2 may be sequentially disposed along the second direction D2. The first edge portion EA1 of the first active pattern ACT1 may be interposed between the second edge portion EA2 of the fourth active pattern ACT4 and the second edge portion EA2 of the third active pattern ACT3. The second edge portion EA2 of the third active pattern ACT3 may be interposed between the first edge portion EA1 of the first active pattern ACT1 and the first edge portion EA1 of the second active pattern ACT2.

[0058] According to the inventive concept, since the active patterns ACT are arranged side by side along the second direction D2 (or the opposite direction thereof) or the third direction D3 (or the opposite direction thereof), the arrangement of components in the semiconductor device can be simplified. Therefore, the difficulty of patterning the semiconductor device can be reduced, and as a result, the semiconductor device can be easily manufactured. In addition, since the arrangement of components is relatively simple, the integration of the semiconductor device can be improved.

[0059] refer to Figure 1A and FIG. 2A to FIG. 2D The device isolation pattern STI may include a dielectric material, such as silicon oxide (SiO 2 ) and at least one of silicon nitride (SiN). The device isolation pattern STI may be a single layer formed of a single material or a multilayer including two or more materials. In the present disclosure, each of the terms "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "at least one of A, B or C" may include one or any possible combination of the elements listed in the corresponding one of the above expressions.

[0060] An active pad XO may be provided on a first edge portion EA1 and a second edge portion EA2 of an active pattern ACT. The active pad XO may include a first active pad XO1 on the first edge portion EA1 of the active pattern ACT and a second active pad XO2 on the second edge portion EA2 of the active pattern ACT. The first active pad XO1 may be between the first edge portion EA1 of the active pattern ACT and a bit line BL, which will be discussed below. The second active pad XO2 may be between the second edge portion EA2 of the active pattern ACT and a storage node contact BC, which will be discussed below. The first active pad XO1 and the second active pad XO2 may be between a word line WL described later, which is adjacent to each other in a third direction D3. The first active pad XO1 may have a top surface XO1a, which is located at a lower height than a top surface XO2a of the second active pad XO2.

[0061] The first and second active pads XO1 and XO2 may include the same material as the active pattern ACT. For example, the first and second active pads XO1 and XO2 may include at least one of silicon (eg, single crystal silicon), germanium, and / or silicon germanium.

[0062] The first active pad XO1 may extend beyond the first edge portion EA1 of the active pattern ACT in the third direction D3. For example, the first active pad XO1 may cover or overlap the top surface EA1a of the first edge portion EA1 of the active pattern ACT, and may extend along the third direction D3 onto the uppermost surface STIa of the device isolation pattern STI adjacent to the first edge portion EA1. When viewed in a plane, the area of ​​a vertical overlap region between a bit line BL described later and the top surface XO1a of the first active pad XO1 may be greater than the area of ​​a vertical overlap region between a bit line BL described later and the top surface EA1a of the first edge portion EA1 of the active pattern ACT.

[0063] The second active pad XO2 may extend beyond the second edge portion EA2 of the active pattern ACT in a direction opposite to the third direction D3. For example, the second active pad XO2 may cover or overlap the top surface EA2a of the second edge portion EA2 of the active pattern ACT, and may extend along the direction opposite to the third direction D3 onto the uppermost surface STIa of the device isolation pattern STI adjacent to the second edge portion EA2. When viewed in a plane, the area of ​​a vertical overlap region between a storage node contact BC described later and the top surface XO2a of the second active pad XO2 may be greater than the area of ​​a vertical overlap region between a storage node contact BC described later and the top surface EA2a of the second edge portion EA2 of the active pattern ACT.

[0064] refer to Figure 1B, the first active pad XO1 and the second active pad XO2 may be provided in plural, respectively. The first active pad XO1 may be provided on the first edge portion EA1 of each of the first active pattern ACT1, the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4. The second active pad XO2 may be provided on the second edge portion EA2 of each of the first active pattern ACT1, the second active pattern ACT2, the third active pattern ACT3, and the fourth active pattern ACT4. The second active pad XO2 on the second edge portion EA2 of the fourth active pattern ACT4, the first active pad XO1 on the first edge portion EA1 of the first active pattern ACT1, the second active pad XO2 on the second edge portion EA2 of the third active pattern ACT3, and the first active pad XO1 on the first edge portion EA1 of the second active pattern ACT2 may be sequentially arranged along the second direction D2. The first active pad XO1 and the second active pad XO2 adjacent to each other in the second direction D2 may be spaced apart from each other across the active dielectric pattern X1, which will be discussed below. The first active pads XO1 adjacent to each other in the third direction D3 may be spaced apart from each other across the word line WL, which will be discussed below. The second active pads XO2 adjacent to each other in the third direction D3 may be spaced apart from each other across the word line WL, which will be discussed below.

[0065] Return to reference Figure 1A and FIG. 2A to FIG. 2D , the active dielectric pattern XI may be between the first active pad XO1 and the second active pad XO2. The active dielectric pattern XI may be between the word lines WL adjacent to each other in the third direction D3, as described below. The active dielectric pattern XI may separate the first active pad XO1 and the second active pad XO2 adjacent thereto from each other in the second direction D2. The active dielectric pattern XI may have a top surface Xia, which is located at a height higher than the top surface XO1a of the first active pad XO1. The top surface XIa of the active dielectric pattern XI may be located at substantially the same height as the top surface XO2a of the second active pad XO2. The active dielectric pattern XI may have a bottom surface, which is located at a height lower than the top surface EA1a of the first edge portion EA1 and the top surface EA2a of the second edge portion EA2. The bottom surface of the active dielectric pattern XI may be located at a height lower than the uppermost surface STIa of the device isolation pattern STI. The active dielectric pattern XI may include a dielectric material. For example, the active dielectric pattern X1 may include silicon oxide (SiO 2 ) and at least one of silicon nitride (SiN).

[0066] The active dielectric pattern XI may be provided in plurality. Active dielectric patterns XI adjacent to each other in the second direction D2 may be spaced apart from each other across the first active pad XO1 or the second active pad XO2. As described below, the active dielectric pattern XI may be linearly disposed along the second direction D2 between word lines WL adjacent to each other along the third direction D3. Active dielectric patterns XI adjacent to each other in the third direction D3 may be spaced apart from each other across the word lines WL, which will be discussed below.

[0067] The word line WL may pass through the active pattern ACT and the device isolation pattern STI. The word line WL may be between the first active pads XO1 adjacent to each other in the third direction D3 and between the second active pads XO2 adjacent to each other in the third direction D3. The word line WL may be provided in multiple pieces. The word lines WL may extend along the second direction D2 and may be spaced apart from each other in the third direction D3. The word line WL may be provided on the central portion CA of the active pattern ACT and between the first edge portion EA1 and the second edge portion EA2. The central portion CA of the active pattern ACT may be a portion of the active pattern ACT located below the word line WL. The first edge portion EA1 of the active pattern ACT may be another portion of the active pattern ACT protruding from the word line WL in the third direction D3. The second edge portion EA2 of the active pattern ACT may be another portion of the active pattern ACT protruding from the word line WL in the direction opposite to the third direction D3. For example, one word line WL may extend along the second direction D2 on a central portion CA of the active pattern ACT linearly disposed side by side along the second direction D2.

[0068] Each word line WL may include a gate electrode GE, a gate dielectric pattern GI, and a gate capping pattern GC. The gate electrode GE may penetrate the active pattern ACT and the device isolation pattern STI in the second direction D2. The gate dielectric pattern GI may be between the gate electrode GE and the active pattern ACT and between the gate electrode GE and the device isolation pattern STI. A gate capping pattern GC covering or overlapping the top surface of the gate electrode GE may be provided on the gate electrode GE. The gate electrode GE may include a conductive material. The gate electrode GE may be a single layer formed of one material or a multilayer formed of two or more materials. The gate dielectric pattern GI may include, for example, silicon oxide (SiO 2 ) or at least one of a high-k dielectric material. In the present disclosure, a high-k dielectric material may be defined as a material indicating that its dielectric constant is greater than that of silicon oxide. The gate capping pattern GC may include silicon nitride (SiN).

[0069] The word line WL may have a first top surface W1a and a second top surface W2a. The first top surface W1a of the word line WL may be a portion of the top surface of the word line WL located below the bit line BL, which will be discussed below, and the second top surface W2a of the word line WL may be another portion of the top surface of the word line WL. The second top surface W2a of the word line WL may be located below the fence pattern FN, which will be discussed below. The first top surface W1a and the second top surface W2a of the word line WL may be located at different heights from each other. The first top surface W1a of the word line WL may be located at a lower height than the second top surface W2a of the word line WL. The first top surface W1a of the word line WL may be located at substantially the same height as the top surface XO1a of the first active pad XO1. The second top surface W2a of the word line WL may be located at substantially the same height as the top surface XO2a of the second active pad XO2.

[0070] refer to Figure 1B , a first word line WL1 and a second word line WL2 spaced apart from each other in the third direction D3 may be provided. The first word line WL1 may be provided on a central portion CA of the first active pattern ACT1 and a central portion CA of the second active pattern ACT2, and may extend along the second direction D2. The second word line WL2 may be provided on a central portion CA of the fourth active pattern ACT4 and a central portion CA of the third active pattern ACT3, and may extend along the second direction D2. A second edge portion EA2 of the fourth active pattern ACT4, a first edge portion EA1 of the first active pattern ACT1, a second edge portion EA2 of the third active pattern ACT3, and a first edge portion EA1 of the second active pattern ACT2 may be sequentially disposed between the first word line WL1 and the second word line WL2 along the second direction D2.

[0071] Return to reference Figure 1A and FIG. 2A to FIG. 2D , a lower storage node contact BCx may be provided on the second edge portion EA2 of the active pattern ACT. For example, the lower storage node contact BCx may be between the bit lines BL adjacent to each other in the second direction D2 as described below, and between the fence patterns FN adjacent to each other in the third direction D3 as described below. The lower storage node contact BCx may be in contact with the top surface XO2a of the second active pad XO2. For example, the lower storage node contact BCx may completely cover or completely overlap the top surface XO2a of the second active pad XO2. The lower storage node contact BCx may be electrically connected to the second edge portion EA2 of the active pattern ACT through the second active pad XO2. For example, the lower storage node contact BCx may include at least one of silicon (e.g., impurity-containing polysilicon) and a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and Co).

[0072] According to the present invention, the second active pad XO2 can be further extended on the second edge portion EA2 of the active pattern ACT in a direction opposite to the third direction D3. Therefore, the contact area between the second active pad XO2 and the lower storage node contact BCx can be increased. In addition, even when the lower storage node contact BCx is not aligned, the lower storage node contact BCx can contact the second active pad XO2. Since the second active pad XO2 is provided, electrical connection can be easily achieved between the lower storage node contact BCx and the second edge portion EA2 of the active pattern ACT. Therefore, the semiconductor device can have improved electrical performance and enhanced reliability.

[0073] The lower storage node contact BCx may be provided in plurality. The plurality of lower storage node contacts BCx may be spaced apart from each other in the second direction D2 and the third direction D3. The lower storage node contacts BCx adjacent to each other in the second direction D2 may be spaced apart from each other across the bit line BL, which will be discussed below. The lower storage node contacts BCx adjacent to each other in the third direction D3 may be spaced apart from each other across the fence pattern FN, which will be discussed below.

[0074] refer to Figure 1B , a first lower storage node contact BCx1, a second lower storage node contact BCx2, a third lower storage node contact BCx3, and a fourth lower storage node contact BCx4 spaced apart from each other in the second direction D2 and the third direction D3 may be provided. The first lower storage node contact BCx1, the second lower storage node contact BCx2, the third lower storage node contact BCx3, and the fourth lower storage node contact BCx4 may be arranged in a clockwise direction. The first lower storage node contact BCx1, the second lower storage node contact BCx2, the third lower storage node contact BCx3, and the fourth lower storage node contact BCx4 may be provided on the second edge portion EA2 of the first active pattern ACT1, the second edge portion EA2 of the second active pattern ACT2, the second edge portion EA2 of the third active pattern ACT3, and the second edge portion EA2 of the fourth active pattern ACT4, respectively. When viewed in a plane, the third lower storage node contact BCx3 and the fourth lower storage node contact BCx4 may be between the first word line WL1 and the second word line WL2. When viewed in a plan view, the second and third lower storage node contacts BCx2 and BCx3 may be interposed between the first and second bit lines BL1 and BL2 , which will be discussed below.

[0075] Return to reference Figure 1A and FIG. 2A to FIG. 2D, a fence pattern FN may be provided on the word line WL. For example, as described below, the fence pattern FN may be interposed between the bit lines BL adjacent to each other in the second direction D2 and between the lower storage node contacts BCx adjacent to each other in the third direction D3. The fence pattern FN may have a bottom surface that is located at a height substantially the same as or lower than the second top surface W2a of the word line WL and the top surface XO2a of the second active pad XO2. The bottom surface of the fence pattern FN may be located at a height higher than the bottom surface of the bit line BL, which will be discussed below.

[0076] The fence pattern FN may be provided in plurality. The plurality of fence patterns FN may be spaced apart from each other in the second direction D2 and the third direction D3. The fence patterns FN adjacent to each other in the second direction D2 may be spaced apart from each other across the bit line BL, which will be discussed below. The fence patterns FN adjacent to each other in the third direction D3 may be spaced apart from each other across the lower storage node contact BCx. The fence pattern FN may include, for example, silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon carbonitride (SiCN) and silicon oxycarbonitride (SiOCN).

[0077] The buffer pattern BP may cover or overlap the top surface of the lower storage node contact BCx and the top surface of the fence pattern FN. The buffer pattern BP may be between the bit lines BL adjacent to each other in the second direction D2, as described below. For example, the buffer pattern BP may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The buffer pattern BP may be a single layer formed of one material or a multilayer formed of two or more materials. The buffer pattern BP may be a composite layer including a lower buffer pattern and an upper buffer pattern.

[0078] The bit line trench region BTR may be defined between the lower storage node contacts BCx adjacent to each other along the second direction D2 and between the fence patterns FN adjacent to each other along the second direction D2. The bit line trench region BTR may be provided on the first active pad XO1. The bit line trench region BTR may cause the active dielectric pattern XI and the gate capping pattern GC to each have an upper portion recessed to a certain depth. The bit line trench region BTR may extend along the third direction D3 on the first edge portion EA1 of the active pattern ACT linearly arranged side by side along the third direction D3.

[0079] The bit line trench region BTR may be located at a height higher than the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT. The bit line trench region BTR may be spaced apart from the second edge portion EA2 of the active pattern ACT. The bit line trench region BTR may not vertically overlap the second edge portion EA2.

[0080] The bit line trench region BTR may be provided in plurality. The plurality of bit line trench regions BTR may be spaced apart from each other in the second direction D2. The bit line trench regions BTR adjacent to each other in the second direction D2 may be spaced apart from each other across the lower storage node contact BCx or the fence pattern FN.

[0081] refer to Figure 1B , a first bit line trench region BTR1 and a second bit line trench region BTR2 spaced apart from each other in the second direction D2 may be provided. The first bit line trench region BTR1 may extend along the third direction D3 while being provided on the first edge portion EA1 of the first active pattern ACT1 and the first edge portion EA1 of the fourth active pattern ACT4. The second bit line trench region BTR2 may extend along the third direction D3 while being provided on the first edge portion EA1 of the second active pattern ACT2 and the first edge portion EA1 of the third active pattern ACT3. The second lower storage node contact BCx2 and the fourth lower storage node contact BCx4 may be interposed between the first bit line BL1 and the second bit line BL2, which will be discussed below.

[0082] Return to reference Figure 1A and FIG. 2A to FIG. 2D , in the bit line trench region BTR, the bit line BL may be provided on the first edge portion EA1 of the active pattern ACT. The bit line BL may be in contact with the top surface XO1a of the first active pad XO1. For example, the bit line BL may completely cover or completely overlap the top surface XO1a of the first active pad XO1. The bit line BL may be electrically connected to the first edge portion EA1 of the active pattern ACT through the first active pad XO1.

[0083] According to the concept of the present invention, the first active pad XO1 can be further extended along the third direction D3 on the first edge portion EA1 of the active pattern ACT. Therefore, the contact area between the first active pad XO1 and the bit line BL can be increased. Since the first active pad XO1 is provided, the bit line BL can be easily electrically connected to the first edge portion EA1 of the active pattern ACT. Therefore, the semiconductor device can have enhanced electrical characteristics.

[0084] The bit line BL may have a bottom surface located at a height lower than the top surface XO2 a of the second active pad XO2 and the bottom surface of the lower storage node contact BCx.

[0085] The bit line BL may be provided in plurality. The bit lines BL may be spaced apart from each other in the second direction D2 and may extend along the third direction D3. One bit line BL may extend along the third direction D3 on the first edge portion EA1 of the active pattern ACT linearly disposed side by side along the third direction D3. For example, one bit line BL may contact the first active pad XO1 on the linearly disposed first edge portion EA1 of the active pattern ACT.

[0086] The bit line BL may be a multilayer including two or more materials. For example, the bit line BL may include a lower bit line BLx and an upper bit line BLy. The upper bit line BLy may extend along the third direction D3. The lower bit line BLx may be interposed between the first active pad XO1 and the upper bit line BLy.

[0087] The lower bit line BLx may include at least one of a first barrier pattern (not shown) that prevents diffusion of a material included in the upper bit line BLy and a first silicide pattern (not shown) that increases contact resistance between the upper bit line BLy and the first edge portion EA1. For example, the lower bit line BLx may include at least one of a metal silicide (e.g., one or more silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co) and a metal nitride (e.g., one or more nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co). For example, the upper bit line BLy may include a metal material such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co.

[0088] refer to Figure 1B , there may be a first bit line BL1 and a second bit line BL2 spaced apart from each other in the second direction D2. The first bit line BL1 may be provided in the first bit line trench region BTR1. The second bit line BL2 may be provided in the second bit line trench region BTR2. The first bit line BL1 may extend along the third direction D3 while being provided on the first edge portion EA1 of the first active pattern ACT1 and the first edge portion EA1 of the fourth active pattern ACT4. The second bit line BL2 may extend along the third direction D3 while being provided on the first edge portion EA1 of the second active pattern ACT2 and the first edge portion EA1 of the third active pattern ACT3. When viewed in a plane, the second edge portion EA2 of the second active pattern ACT2 and the second edge portion EA2 of the third active pattern ACT3 may be interposed between the first bit line BL1 and the second bit line BL2.

[0089] Return to reference Figure 1A and FIG. 2A to FIG. 2D, in the bit line trench region BTR, a bit line cover pattern BCP may be provided on the top surface of the bit line BL. The bit line cover pattern BCP may extend along the third direction D3 together with the bit line BL. The bit line cover pattern BCP may be provided in plurality. Multiple bit line cover patterns BCP may be spaced apart from each other in the second direction D2. The bit line cover pattern BCP may overlap vertically with the bit line BL. The bit line cover pattern BCP may be formed by a single layer or multiple layers. The bit line cover pattern BCP may include a first cover pattern, a second cover pattern, and a third cover pattern stacked sequentially. Each of the first to third cover patterns may include silicon nitride (SiN). In some embodiments, the bit line cover pattern BCP may include four or more stacked cover patterns.

[0090] In the bit line trench region BTR, a bit line spacer BSP may be provided on the side surface of the bit line BL and the side surface of the bit line cover pattern BCP. The bit line spacer BSP may cover or overlap the side surface of the bit line BL, the side surface of the bit line cover pattern BCP, and the inner side surface of the bit line trench region BTR. The bit line spacer BSP may cover or overlap the side surface of the lower storage node contact BCx. The bit line spacer BSP may contact the active dielectric pattern XI. The bit line spacer BSP may extend along the third direction D3 on the side surface of the bit line BL. For example, the bit line spacer BSP may have a top surface substantially at the same height as the top surface of the buffer pattern BP. The bit line spacer BSP may be provided in plurality. Multiple bit line spacers BSP may be spaced apart from each other in the second direction D2. In one bit line trench region BTR, two bit line spacers BSP adjacent to each other in the second direction D2 may be spaced apart from each other across one bit line BL. For example, the bit line spacer BSP may include silicon oxide (SiO 2 The bit line spacer BSP may be a single layer formed of one material or a multilayer formed of two or more materials.

[0091] A mold pattern MP may be provided on the buffer pattern BP, the bit line capping pattern BCP, and the bit line spacer BSP. The mold pattern MP may surround the landing pad LP, which will be discussed below. The mold pattern MP may be interposed between adjacent landing pads LP. When viewed in a plan view, the mold pattern MP may have a grid shape including contact holes CH, which will be discussed below. For example, the mold pattern MP may include silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon carbonitride (SiCN) and silicon oxycarbonitride (SiOCN).

[0092] A contact hole CH may be provided on the second edge portion EA2 of the active pattern ACT. The contact hole CH may penetrate the mold pattern MP and the buffer pattern BP. The contact hole CH may cause the lower storage node contact BCx, the bit line cover pattern BCP, and the bit line spacer BSP to each have an upper portion recessed to a certain depth. The contact hole CH may be offset from the lower storage node contact BCx in the second direction D2 (or the opposite direction thereof). A portion of the contact hole CH may overlap vertically with the bit line BL. A portion of the contact hole CH may overlap vertically with the lower storage node contact BCx. The contact hole CH may be provided in plurality. A plurality of contact holes CH may be linearly arranged along the second direction D2, and may be arranged in a zigzag manner along the third direction D3.

[0093] In the contact hole CH, an upper storage node contact BCy may be provided on the second edge portion EA2 of the active pattern ACT. The upper storage node contact BCy may be provided on and in contact with the lower storage node contact BCx. The upper storage node contact BCy may be electrically connected to the second edge portion EA2 of the corresponding active pattern ACT through the corresponding lower storage node contact BCx and the corresponding second active pad XO2. The upper storage node contact BCy may be offset from the lower storage node contact BCx in the second direction D2 (or the opposite direction thereof). A portion of the upper storage node contact BCy may overlap vertically with the bit line BL. The upper storage node contact BCy may be in contact with the bit line cover pattern BCP and the bit line spacer BSP. The upper storage node contact BCy and the lower storage node contact BCx may constitute or form a storage node contact BC.

[0094] The lowermost surface of the upper storage node contact BCy may be located at a lower height than the top surface of the lower storage node contact BCx.

[0095] The upper storage node contact Bcy may be provided in plurality. A plurality of upper storage node contacts BCy may be provided in the contact hole CH accordingly. The upper storage node contacts BCy may be spaced apart from each other in the second direction D2 and the third direction D3. The upper storage node contacts BCy may be linearly arranged along the second direction D2 together with the contact hole CH, and arranged in a zigzag shape along the third direction D3.

[0096] In the contact hole CH, a landing pad LP may be provided on the upper storage node contact BCy. The landing pad LP may overlap vertically with the upper storage node contact BCy. The landing pad LP may be electrically connected to the second edge portion EA2 of the corresponding active pattern ACT through the corresponding upper storage node contact BCy, the corresponding lower storage node contact BCx, and the corresponding second active pad XO2. The landing pad LP may have a bottom surface located at a height higher than the top surface of the bit line cover pattern BCP. The bottom surface of the landing pad LP may be located at a height higher than the bottom surface of the mold pattern MP. The landing pad LP may be provided in plurality. A plurality of landing pads LP may be spaced apart from each other in the second direction D2 and the third direction D3. For example, the landing pad LP may include at least one metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co). A second silicide pattern SC may be further provided between the landing pad LP and the upper storage node contact BCy. The second silicide pattern SC may include a metal silicide (e.g., one or more silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co). In some embodiments, a second barrier pattern (not shown) may be interposed between the landing pad LP and other components and may prevent diffusion of a material contained in the landing pad LP. The second barrier pattern may include a metal nitride (e.g., one or more nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, and / or Co).

[0097] A landing pad spacer LSP may be provided on the side surface of the landing pad LP. The landing pad spacer LSP may surround and cover or overlap the side surface of the landing pad LP. The landing pad spacer LSP may cover or overlap the inner side surface of the contact hole CH. The outer side surface of the landing pad spacer LSP may be aligned with the side surface of the second silicide pattern SC, but the inventive concept is not limited thereto. Although not shown in the figure, the outer side surface of the landing pad spacer LSP may protrude in a direction away from the center of the contact hole CH compared to the second silicide pattern SC. The landing pad spacer LSP may include silicon oxide (SiO 2 ), at least one of silicon nitride (SiN), silicon carbonitride (SiCN) and / or silicon oxycarbonitride (SiOCN).

[0098] A data storage pattern DSP may be provided on the landing pad LP. The data storage pattern DSP may be provided in plurality. The plurality of data storage patterns DSP may be spaced apart from each other in the second direction D2 and / or the third direction D3. Each data storage pattern DSP may be electrically connected to the second edge portion EA2 of the corresponding active pattern ACT through the corresponding landing pad LP and the corresponding storage node contact BC.

[0099] For example, the data storage pattern DSP may be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor device according to the present invention may be a dynamic random access memory (DRAM). For example, the data storage pattern DSP may include a magnetic tunnel junction pattern. In this case, the semiconductor device according to the present invention may be a magnetic random access memory (MRAM). For another example, the data storage pattern DSP may include a phase change material or a variable resistance material. In this case, the semiconductor device according to the present invention may be a phase change random access memory (PRAM) or a resistance random access memory (ReRAM). However, this is merely an example, and the present invention is not limited thereto. The data storage pattern DSP may include various structures and / or materials capable of storing data.

[0100] refer to Figures 3 to 24B , various embodiments of the inventive concept will be described below. For the sake of brevity of description, explanations of components that are repeated with those discussed above will be omitted, and the differences will be discussed in detail.

[0101] Figures 3 to 5 Shown along Figure 1A A cross-sectional view taken along line AA'.

[0102] refer to Figures 3 to 5 The top surfaces EA1a and EA2a of the first and second edge portions EA1 and EA2 of the active pattern ACT may be located at a lower height than the uppermost surface STIa of the device isolation pattern STI. The bottom surfaces of the first and second active pads XO1 and XO2 may be located at a lower height than the uppermost surface STIa of the device isolation pattern STI.

[0103] refer to Figure 3 , bottom surfaces of the first and second active pads XO1 and XO2 may be located at a lower height than the bottom surface of the active dielectric pattern X1. The bottom surfaces of the active dielectric pattern X1 may be located at substantially the same height.

[0104] refer to Figure 4 and Figure 5, the active dielectric pattern XI may include a first active dielectric pattern XI1 and a second active dielectric pattern XI2 whose bottom surfaces are located at different heights. The first active dielectric pattern XI1 may have a bottom surface XIb1, which is located at a height higher than the bottom surface XIb2 of the second active dielectric pattern XI2. The bottom surface XIb1 of the first active dielectric pattern XI1 may be located at substantially the same height as the uppermost surface STIa of the device isolation pattern STI. The bottom surface XIb1 of the first active dielectric pattern XI1 may be located at a height higher than the top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2. The bottom surface XIb2 of the second active dielectric pattern XI2 may be located at a height lower than the top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2.

[0105] refer to Figure 4 The second active dielectric pattern XI2 may be interposed between the first and second active pads XO1 and XO2 sequentially disposed in the second direction D2. The first active dielectric pattern XI1 may be interposed between the first and second active pads XO1 and XO2 sequentially disposed in a direction opposite to the second direction D2.

[0106] refer to Figure 5 The second active dielectric pattern XI2 may be interposed between the first active pads XO1 and the second active pads XO2 sequentially disposed in a direction opposite to the second direction D2. The first active dielectric pattern XI1 may be interposed between the first active pads XO1 and the second active pads XO2 sequentially disposed in the second direction D2.

[0107] Fig. 6A , Figure 6B and Figure 6C The Figure 1A Cross-sectional views taken along line BB', line CC' and line DD'.

[0108] refer to FIG. 6A to FIG. 6C The first top surface W1a of the word line WL may be located at substantially the same height as the second top surface W2a of the word line WL. The first and second top surfaces W1a and W2a of the word line WL may be located at substantially the same height as the top surfaces EA1a and EA2a of the first and second edge portions EA1 and EA2 of the active pattern ACT.

[0109] The fence pattern FN may include an upper fence pattern FNy and a lower fence pattern FNx. The lower fence pattern FNx may be provided on the word line WL. The lower fence pattern FNx may extend along the second direction D2 on the word line WL. The lower fence pattern FNx may be between the first active pads XO1 adjacent to each other in the third direction D3 and between the second active pads XO2 adjacent to each other in the third direction D3. The lower fence pattern FNx may be provided in plurality. The lower fence patterns FNx may be spaced apart from each other in the third direction D3. The lower fence patterns FNx adjacent to each other in the third direction D3 may be spaced apart from each other across the first active pad XO1 or the second active pad XO2.

[0110] The lower fence pattern FNx may have a first top surface Fx1a and a second top surface Fx2a located at different heights. The first top surface Fx1a of the lower fence pattern FNx may be located below the bit line BL. The second top surface Fx2a of the lower fence pattern FNx may be located below the upper fence pattern FNy. The first top surface Fx1a of the lower fence pattern FNx may be located at a lower height than the second top surface Fx2a of the lower fence pattern FNx. The first top surface Fx1a of the lower fence pattern FNx may be located at substantially the same height as the top surface XO1a of the first active pad XO1. The second top surface Fx2a of the lower fence pattern FNx may be located at substantially the same height as the top surface XO2a of the second active pad XO2. The lower fence pattern FNx may have a bottom surface located at substantially the same or lower height than the top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT.

[0111] The upper fence pattern FNy may be provided on the lower fence pattern FNx. The upper fence pattern FNy and the lower fence pattern FNx may be distinguished from each other through an interface thereof and contact each other through the interface.

[0112] Fig. 7A , Figure 7B and Figure 7C The Figure 1A Cross-sectional views taken along line BB', line CC' and line DD'.

[0113] refer to FIG. 7A to FIG. 7C , the first top surface W1a and the second top surface W2a of the word line WL may have a FIG. 6A to FIG. 6C The characteristics in question are the same or similar characteristics.

[0114] The fence pattern FN may extend along the second direction D2 on the word line WL. The first active pads XO1 adjacent to each other in the third direction D3 may be spaced apart from each other across the fence pattern FN. The second active pads XO2 adjacent to each other in the third direction D3 may be spaced apart from each other across the fence pattern FN. The fence pattern FN may extend in the fourth direction D4 from a position between the second active pads XO2 adjacent to each other in the third direction D3 to a position between the lower storage node contacts BCx adjacent to each other in the third direction D3.

[0115] The fence pattern FN may have a first top surface F1a and a second top surface F2a located at different heights. The first top surface F1a and the bottom surface of the fence pattern FN may have the same height as the reference FIG. 6A to FIG. 6C The first top surface Fx1a and the bottom surface of the lower fence pattern FNx discussed above have the same or similar characteristics. The second top surface F2a of the fence pattern FN may be located at substantially the same height as the top surface of the lower storage node contact BCx.

[0116] Fig. 8A and Figure 8B The Figure 1A A cross-sectional view taken along line AA' and line DD'.

[0117] refer to Fig. 8A and Figure 8B , the top surface XO2a of the second active pad XO2 may be located at a height higher than the top surface XIa of the active dielectric pattern XI. The top surface XO2a of the second active pad XO2 may be located at a height higher than the top surface GIa of the gate dielectric pattern GI.

[0118] The lower storage node contact BCx may have a bottom surface BCxb located at a height lower than the top surface XO2a of the second active pad XO2. The lower storage node contact BCx may cover or overlap the upper portion of the second active pad XO2. For example, the lower storage node contact BCx may completely cover or completely overlap the top surface XO2a of the second active pad XO2 and the side surface of the upper portion of the second active pad XO2. The lower storage node contact BCx may extend from a position between the second active pad XO2 and the gate cover pattern GC toward the gate dielectric pattern GI. Therefore, the contact area between the second active pad XO2 and the lower storage node contact BCx may be increased. Therefore, electrical connection may be easily achieved between the lower storage node contact BCx and the second edge portion EA2 of the active pattern ACT, and the electrical characteristics of the semiconductor device may be increased.

[0119] Fig. 9 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Fig. 10A , Fig. 10B and Fig. 10CThe Fig. 9 Cross-sectional views taken along line AA', line CC' and line DD'.

[0120] refer to Figures 9 to 10C The top surface EA1a of the first edge portion EA1 of the active pattern ACT may be located at a lower height than the top surface EA2a of the second edge portion EA2 of the active pattern ACT. The top surfaces EA1a and EA2a of the first and second edge portions EA1 and EA2 of the active pattern ACT may be located at a higher height than the uppermost surface STIa of the device isolation pattern STI.

[0121] In a plan view, the first active pad XO1 may surround and cover or overlap a side surface of the first edge portion EA1. In a plan view, the second active pad XO2 may surround and cover or overlap a side surface of the second edge portion EA2. A top surface XO1a of the first active pad XO1 may be located at substantially the same height as a top surface EA1a of the first edge portion EA1 of the active pattern ACT, and at a height lower than a top surface EA2a of the second edge portion EA2 of the active pattern ACT. A top surface XO2a of the second active pad XO2 may be located at substantially the same height as a top surface EA2a of the second edge portion EA2 of the active pattern ACT.

[0122] The active dielectric pattern XI may be interposed between the first active pad XO1 and the second active pad XO2. The active dielectric pattern XI may cover or overlap the uppermost surface STIa of the device isolation pattern STI. The active dielectric pattern XI may have a top surface located at substantially the same height as the top surface EA2a of the second edge portion EA2 of the active pattern ACT.

[0123] The first top surface W1a of the word line WL may be located at substantially the same height as the top surface EA1a of the first edge portion EA1 of the active pattern ACT. The second top surface W2a of the word line WL may be located at substantially the same height as the top surface EA2a of the second edge portion EA2 of the active pattern ACT.

[0124] The bit line BL may contact the first active pad XO1 and the first edge portion EA1 of the active pattern ACT. The bit line BL may have a bottom surface located at a lower height than a top surface EA2a of the second edge portion EA2 of the active pattern ACT.

[0125] The lower storage node contact BCx may be in contact with the second active pad XO2 and the second edge portion EA2 of the active pattern ACT.

[0126] Fig.11 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Fig.12 Shown along Fig.11 A cross-sectional view taken along line AA'.

[0127] refer to Fig.12 and Fig.13 , a first active additional pad SXO1 may be provided on a side surface of the first active pad XO1. The first active additional pad SXO1 may be provided on a top surface of the active dielectric pattern XI. The first active additional pad SXO1 may be provided in plurality. Among the first active additional pads SXO1 adjacent to each other in the second direction D2, one first active additional pad SXO1 may cover or overlap one side surface of the first active pad XO1, and another first active additional pad SXO1 may cover or overlap another side surface of the first active pad XO1. The first active additional pads SXO1 adjacent to each other in the third direction D3 may be spaced apart from each other across the word line WL.

[0128] A second active additional pad SXO2 may be provided on a side surface of the second active pad XO2. The second active additional pad SXO2 may be provided on the top surface of the active dielectric pattern X1. The second active additional pad SXO2 may be provided in plurality. In pairs of second active additional pads SXO2 adjacent to each other in the second direction D2, one second active additional pad SXO2 may cover or overlap one side surface of the second active pad XO2, and another second active additional pad SXO2 may cover or overlap another side surface of the second active pad XO2. The second active additional pads SXO2 adjacent to each other in the third direction D3 may be spaced apart from each other across the word line WL.

[0129] The first and second active additional pads SXO1 and SXO2 may include the same material as the active pattern ACT. For example, the first and second active additional pads SXO1 and SXO2 may include at least one of silicon (eg, single crystal silicon), germanium, and / or silicon germanium.

[0130] The top surface XIa of the active dielectric pattern XI may be located at a lower height than the top surfaces XO1a and XO2a of the first active pad XO1 and the second active pad XO2. The top surface XIa of the active dielectric pattern XI may be located at a higher height than the top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2, but the inventive concept is not limited thereto. Although not shown, the top surface XIa of the active dielectric pattern XI may be located at a lower height than the top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2.

[0131] An active additional dielectric pattern SXI may be provided on the active dielectric pattern XI. The active additional dielectric pattern SXI may be between the first active additional pad SXO1 and the second active additional pad SXO2. The active additional dielectric pattern SXI may include a dielectric material. For example, the active additional dielectric pattern SXI may include silicon oxide (SiO 2 ) and / or at least one of silicon nitride (SiN).

[0132] The bit line BL may contact the first active additional pad SXO1. The bit line BL may have a bottom surface located at a lower height than a top surface of the second active additional pad SXO2. The bit line BL may be electrically connected to the first edge portion EA1 of the active pattern ACT through the first active pad XO1 and the first active additional pad SXO2.

[0133] The lower storage node contact BCx may contact the second active additional pad SXO2. The active additional dielectric pattern SXI may separate the lower storage node contact BCx from the active dielectric pattern XI. The storage node contact BC may be electrically connected to the second edge portion EA2 of the active pattern ACT through the second active pad XO2 and the second active additional pad SXO2.

[0134] Fig.13 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Fig.14A and Fig. 14B The Fig.13 A cross-sectional view taken along line BB' and line DD'.

[0135] refer to Figures 13 to 14B , the fence pattern FN may not be provided. The word line WL may extend along the third direction D3 between the second active pads XO2 adjacent to each other in the third direction D3, and may extend along the fourth direction D4 between the adjacent lower storage node contacts BCx. The second top surface W2a of the word line WL may be located at substantially the same height as the top surface of the lower storage node contact BCx. The word line WL may contact the buffer pattern BP. The bit line trench regions BTR adjacent to each other in the second direction D2 may be spaced apart from each other across the word line WL. The lower storage node contacts BCx adjacent to each other in the third direction D3 may be spaced apart from each other across the word line WL.

[0136] Fig.15 and Fig.17 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Fig.16A , Fig. 16B , Fig. 16C and Fig.16D The Fig.15Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′. Fig.18A , Fig.18B , Fig.18C and Fig.18D The Fig.17 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0137] refer to Figures 15 to 18D , neither the fence pattern FN nor the lower storage node contact BCx may be provided.

[0138] The second active pad XO2 may contact the upper storage node contact BCy and the buffer pattern BP. The top surface XO2a of the second active pad XO2 may be located at a height higher than the top surface of the bit line BL. The top surface XO2a of the second active pad XO2 may be located at a height higher than the lowermost surface of the upper storage node contact BCy.

[0139] The active dielectric pattern XI may be in contact with the upper storage node contact BCy.

[0140] The word line WL may make contact with the buffer pattern BP. A second top surface W2a of the word line WL may be located at substantially the same height as a top surface XO2a of the second active pad XO2.

[0141] refer to Figures 17 to 18D , when viewed in a plan view, the contact hole CH may be interposed between the bit lines BL adjacent to each other in the second direction D2. The contact hole CH may vertically overlap the second active pad XO2. The contact holes CH may be arranged two-dimensionally along the second direction D2 and the third direction D3. For example, the contact holes CH in a certain queue may be arranged side by side along the second direction D2, and the contact holes CH in another queue may be arranged side by side along the third direction D3. Therefore, as with reference Figures 15 to 16D Compared with the semiconductor device in question, even when the contact holes CH are not aligned, the electrical connection between the second active pad XO2 and the upper storage node contact BCy can be easily achieved.

[0142] When viewed in a plan view, the upper storage node contact BCy, the second silicide pattern SC, a lower landing pad LPx described later, and a landing pad spacer LSP may be interposed between the bit lines BL adjacent to each other in the second direction D2.

[0143] The landing pad LP may include a lower landing pad LPx and an upper landing pad LPy. The lower landing pad LPx may have a Figures 1A to 2DThe same or similar characteristics as the landing pad LP discussed. An upper landing pad LPy may be provided on the lower landing pad LPx and the mold pattern MP. The upper landing pad LPy may be offset from the lower landing pad LPx in the second direction D2 (or the opposite direction thereof). Portions of the upper landing pad LPy may overlap vertically with the bit line BL. The upper landing pad LPy may be provided in plurality. The upper landing pad LPy may be linearly arranged in the second direction D2 and arranged in a zigzag manner in the third direction D3. The lower landing pad LPx and the upper landing pad LPy may include the same or different materials. However, this is not limited thereto, and various changes may be made to the structure and material of the landing pad LP within the scope known to those skilled in the art.

[0144] The filling pattern FIL may surround the upper landing pad LPy. The filling pattern FIL may be between adjacent upper landing pads LPy. When viewed in a plane, the filling pattern FIL may have a grid shape including holes, and the upper landing pad LPy may partially or completely fill the holes. The filling pattern FIL may penetrate the upper landing pad LPy. For example, the filling pattern FIL may include silicon nitride (SiN), silicon oxide (SiO 2 ) and / or at least one of silicon oxynitride (SiON). In some embodiments, the filling pattern FIL may include an empty space (or air gap) including an air layer.

[0145] Fig.19 and Fig. 22 is a plan view showing a semiconductor device according to some embodiments of the inventive concept. Fig. 20A , Fig. 20B , Fig. 20C and Fig.20D The Fig.19 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′. Fig.21 Shown along Fig.19 A cross-sectional view taken along line AA'. Fig.23A , Fig. 23B , Fig.23C and Fig.23D The Fig. 22 Cross-sectional views taken along line AA′, line BB′, line CC′ and line DD′.

[0146] refer to Figures 19 to 23D , the second active pad XO2 and the lower storage node contact BCx may have a reference Fig. 8A and Figure 8B The same or similar characteristics as those discussed.

[0147] The lower landing pad LPx may be provided on the lower storage node contact BCx. For example, the lower landing pad LPx may contact the top surface of the lower storage node contact BCx. The lower landing pad LPx may be interposed between the bit line capping patterns BCP adjacent to each other in the second direction D2. The lower landing pad LPx may be interposed between the fence patterns FN adjacent to each other in the third direction D3.

[0148] The lower landing pad LPx may be provided in plurality. The plurality of lower landing pads LPx may be spaced apart from each other in the second direction D2 and the third direction D3. Lower landing pads LPx adjacent to each other in the second direction D2 may be spaced apart from each other across the bit line capping pattern BCP. Lower landing pads LPx adjacent to each other in the third direction D3 may be spaced apart from each other across the fence pattern FN.

[0149] refer to FIG. 20A to FIG. 20D , the lower landing pad LPx may have a top surface having substantially the same height as a top surface of the bit line capping pattern BCP. Fig.21 and FIG. 23A to FIG. 23D , the lower landing pad LPx may have a top surface located at a lower height than a top surface of the bit line capping pattern BCP.

[0150] In some embodiments, the upper storage node contact BCy, the second silicide pattern SC, and the landing pad spacer LSP may not be provided.

[0151] refer to Figures 19 to 20D , the mold pattern MP may not be provided. The upper landing pad LPy may be provided on the lower landing pad LPx. The upper landing pad LPy may be in contact with the bit line capping pattern BCP, the bit line spacer BSP, and the lower landing pad LPx. The upper landing pad LPy and the filling pattern FIL may have the same Figures 17 to 18D The same or similar characteristics as those discussed.

[0152] refer to Fig.21 , the lower landing pad LPx may be interposed between the buffer pattern BP and the lower storage node contact BCx.

[0153] The upper landing pad LPy may be provided in the contact hole CH. For example, the upper landing pad LPy may partially or completely fill the contact hole CH. The upper landing pad LPy may be in contact with the bit line capping pattern BCP and the bit line spacer BSP. The upper landing pad LPy may be in contact with the lower landing pad LPx at a height lower than the bottom surface of the mold pattern MP. The upper landing pad LPy may have a top surface having substantially the same height as the top surface of the mold pattern MP. The upper landing pad LPy may have a lowermost surface located at a lower height than the top surface of the lower landing pad LPx.

[0154] refer to Figures 22 to 23D , the mold pattern MP may not be provided. An interlayer dielectric layer ILD may be provided on the front surface of the substrate 100. For example, the interlayer dielectric layer ILD may be provided on the bit line capping pattern BCP and the buffer pattern BP. The interlayer dielectric layer ILD may include at least one of silicon nitride, silicon oxide and / or silicon oxynitride. In some embodiments, the interlayer dielectric layer ILD may include a blank area. The contact hole CH may penetrate the interlayer dielectric layer ILD, and when viewed in a plane, the interlayer dielectric layer ILD may have a grid shape including the contact hole CH.

[0155] A bottom electrode BE may be provided on the lower landing pad LPx. The bottom electrode BE may include a lower portion BEx lower than a contact level CLV and an upper portion BEy higher than the contact level CLV. The contact level CLV may be defined as indicating a height at which a top surface of the interlayer dielectric layer ILD is located. For example, the lower portion BEx and the upper portion BEy of the bottom electrode BE may be distinguished from each other without an interface and contact with each other, but the inventive concept is not limited thereto.

[0156] The lower portion BEx of the bottom electrode BE may be provided in the contact hole CH. The lower portion BEx of the bottom electrode BE may partially or completely fill the contact hole CH. The lower portion BEx of the bottom electrode BE may contact the bit line capping pattern BCP, the bit line spacer BSP, and the lower landing pad LPx. The lower portion BEx of the bottom electrode BE may have a lowermost surface located at a height lower than the top surface of the lower landing pad LPx.

[0157] The upper portion BEy of the bottom electrode BE may be provided on the lower portion BEx of the bottom electrode BE. The upper portion BEy of the bottom electrode BE may have a columnar shape. In some embodiments, the upper portion BEy of the bottom electrode BE may have a hollow cylindrical shape, one end of which is closed. According to some embodiments, although not shown, the upper portion BEy of the bottom electrode BE may have a columnar lower portion and a hollow cylindrical upper portion.

[0158] The bottom electrode BE may be provided in plural. The bottom electrodes BE may be spaced apart from each other in the second direction D2 and the third direction D3. When viewed in a plan view, the bottom electrodes BE may be arranged to have a honeycomb shape. For example, six bottom electrodes BE may be provided to constitute or form a hexagon, which surrounds one bottom electrode BE located at the center of the hexagon.

[0159] A top electrode TE may be provided on the bottom electrode BE. For example, the top electrode TE may cover or overlap the top surface of the upper portion BEy of the bottom electrode BE, and may surround and cover or overlap the side surface of the lower portion BEy of the bottom electrode BE. The top electrode TE may partially or completely fill the space between the upper portions BEy of the bottom electrode BE.

[0160] Each of the bottom electrode BE and the top electrode TE may include a conductive material. For example, each of the bottom electrode BE and the top electrode TE may include doped silicon (Si), doped silicon germanium (SiGe), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au and / or Ag), a metal nitride (e.g., one or more nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au and / or Ag), titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (e.g., TiAlN), tantalum aluminum nitride (e.g., TaAlN), a conductive oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 ), CRO(CaRuO 3 ) and / or LSCo) and / or at least one of metal silicide. Each of the bottom electrode BE and the top electrode TE may be a single layer formed of one material or a multilayer formed of two or more materials.

[0161] The dielectric layer DL may be interposed between the top electrode TE and each upper portion BEy of the bottom electrode BE and between the top electrode TE and the interlayer dielectric layer ILD. The dielectric layer DL may conformally cover or overlap the upper portion BEy of the bottom electrode BE. For example, the dielectric layer DL may include: at least one metal oxide, such as HfO 2 、ZrO 2 、Al 2 O 3 ,La 2 O 3 、 2 O 3 and TiO 2 ; and / or perovskite dielectric materials, such as SrTiO 3 (STO), (Ba,Sr)TiO 3 (BST), BaTiO 3 , PZT and / or PLZT.

[0162] Fig.24A and Fig. 24B Cross-sectional views taken along line BB' and line CC' of FIG. 1 are respectively shown.

[0163] refer to Fig.24A and Fig. 24B, the first top surface W1a of the word line WL may be located at a height higher than the top surface XO1a of the first active pad XO1. The first top surface W1a of the word line WL may be located at a height higher than the top surface of the lower bit line BLx. Therefore, the upper bit line BLy and the gate electrode GE may have an increased spacing distance and reduced electrical interference. Therefore, the semiconductor device may have enhanced electrical characteristics.

[0164] refer to Figures 25 to 69B , a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept will be described in detail below. For the sake of brevity of description, explanations of components that are repeated with those discussed above will be omitted, and the differences will be discussed in detail.

[0165] Figures 25 to 34D 1 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept. For example, Fig.25 , Fig. 27 , Fig.29 , Fig.31 and Fig.33 is a plan view showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Fig.26A , Fig.28A , Fig. 30A , Fig.32A and Fig.34A The Fig.25 , Fig. 27 , Fig.29 , Fig.31 and Fig.33 A cross-sectional view taken along line AA'. Fig.26B , Fig.28B , Fig. 30B , Fig.32B and Fig.34B The Fig.25 , Fig. 27 , Fig.29 , Fig.31 and Fig.33 A cross-sectional view taken along line BB'. Fig.26C , Fig.28C , Fig. 30C , Fig.32C and Fig.34C The Fig.25 , Fig. 27 , Fig.29 , Fig.31 and Fig.33 A cross-sectional view taken along line CC'. Fig.26D , Fig.28D , Fig.30D , Fig.32D and Fig.34D The Fig.25 , Fig. 27 , Fig.29 , Fig.31 and Fig.33 A cross-sectional view taken along line D-D'.

[0166] refer to Figures 25 to 26D , a substrate 100 may be prepared. A first active mask pattern AMP may be formed on the substrate 100. The first active mask pattern AMP may include a plurality of patterns elongated in the first direction D1 and a plurality of groove regions between the plurality of patterns. For example, the plurality of patterns may have side surfaces, each of which has a straight profile.

[0167] The first active mask pattern AMP may be formed by performing a patterning process on the active mask layer. For example, the patterning process may include performing an exposure process once. In some embodiments, the patterning process may include performing an exposure process twice or more, for example, performing a multiple patterning technique.

[0168] refer to Figures 27 to 28D , a second active mask pattern (not shown) may be provided on the substrate 100. The second active mask pattern may include a plurality of patterns elongated in the third direction D3 and a plurality of groove regions between the plurality of patterns.

[0169] The substrate 100 may be subjected to a removal process to form an active pattern ACT. The removal process may include using the first active mask pattern AMP and the second active mask pattern as an etching mask to perform an etching process on the substrate 100. In the etching process, a first line groove region LTR1 and a second line groove region LTR2 may be formed between the active patterns ACT. The groove region of the first active mask pattern AMP may form the first line groove region LTR1. The first line groove region LTR1 may extend along a first direction D1 between the active patterns ACT. The groove region of the second active mask pattern may form a second line groove region LTR2. The second line groove region LTR2 may extend along a third direction D3 between the active patterns ACT.

[0170] The device isolation pattern STI may be formed to partially or completely fill the first and second line trench regions LTR1 and LTR2. The formation of the device isolation pattern STI may include performing a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process.

[0171] refer to Figures 29 to 30D, a first active pad XO1 extending along a third direction D3 may be formed on a first edge portion EA1 of the active pattern ACT. A second active pad XO2 extending along the third direction D3 may be formed on a second edge portion EA2 of the active pattern ACT. The formation of the first active pad XO1 and the second active pad XO2 may include performing an embossing process in which an active pad layer (not shown) is used. For example, an active pad layer may be formed on the front surface of the substrate 100, and then the active pad layer may be removed to form the first active pad XO1 and the second active pad XO2. The first active pad XO1 may have a top surface having substantially the same height as a top surface of the second active pad XO2.

[0172] When the etching process is performed, the upper portion of the device isolation pattern STI may be recessed to a certain depth. After the etching process, a trench region may be formed between the first active pad XO1 and the second active pad XO2. A portion of the trench region may extend along the third direction D3 on the central portion CA of the active pattern ACT. Another portion of the trench region may extend along the third direction D3 between the active patterns ACT adjacent to each other along the first direction D1.

[0173] The active dielectric pattern XI may be formed to partially or completely fill the trench region between the first active pad XO1 and the second active pad XO2. The active dielectric pattern XI may have a top surface that is located at substantially the same height as the top surfaces of the first active pad XO1 and the second active pad XO2 and may be coplanar with the top surfaces of the first active pad XO1 and the second active pad XO2.

[0174] refer to Figures 31 to 32D , a word line WL may be formed to pass through the active pattern ACT and the device isolation pattern STI. The word line WL may be formed to penetrate the first active pad XO1 and the second active pad XO2. Therefore, one first active pad XO1 may be divided into a plurality of first active pads XO1 spaced apart from each other in the third direction D3, and one second active pattern XO2 may be divided into a plurality of second active pads XO2 spaced apart from each other in the third direction D3.

[0175] The formation of the word line WL may include forming a mask pattern on the active pattern ACT and the device isolation pattern STI, performing an anisotropic etching process using the mask pattern, forming a trench region through the active pattern ACT and the device isolation pattern STI, and partially or completely filling the trench region with the word line WL. The word line WL may be formed between the central portion CA of the active pattern ACT and the first and second edge portions EA1 and EA2.

[0176] Partially or completely filling the trench area with the word line WL may include, for example, conformally depositing a gate dielectric pattern GI on an inner surface of the trench area; partially or completely filling the trench area with a conductive layer; allowing the conductive layer to undergo an etch-back process and / or a polishing process to form a gate electrode GE; and forming a gate cover pattern GC on the gate electrode GE that partially or completely fills an unoccupied portion of the trench area.

[0177] Lower storage node contacts BCx and fence patterns FN that are alternately arranged along the third direction D3 may be formed on the substrate 100. Lower storage node contacts BCx extending along the second direction D2 may be formed on the second edge portion EA2 of the active pattern ACT. Fence patterns FN extending along the second direction D2 may be formed on the center portion CA of the active pattern ACT. For example, the formation of the lower storage node contacts BCx and the fence pattern FN may include: forming a lower storage node contact layer (not shown) to form the front surface of the substrate 100; and forming the fence pattern FN to divide the lower storage node contact layer into a plurality of lower storage node contacts BCx spaced apart from each other in the third direction D3. Thereafter, a buffer pattern BP may be formed to cover or overlap the front surface of the substrate 100.

[0178] A bit line mask pattern BMP may be formed on the buffer pattern BP. The bit line mask pattern BMP may include a plurality of mask patterns that are spaced apart from each other in the second direction D2 and each of which extends along the third direction D3. The bit line mask pattern BMP may be formed on the second edge portion EA2 of the active pattern ACT. For example, the bit line mask pattern BMP may completely cover or overlap the top surface EA2a of the second edge portion EA2. The bit line mask pattern BMP may be formed so as not to overlap vertically with the first edge portion EA1, and when viewed in a plane, the bit line mask pattern BMP may be formed offset from the first edge portion EA1 in the second direction D2.

[0179] refer to Figures 33 to 34D, the bit line mask pattern BMP may be used as an etching mask to perform a removal process of removing the buffer pattern BP, the lower storage node contact BCx, the fence pattern FN, the upper portion of the word line WL, the upper portion of the active dielectric pattern XI, and the upper portion of the first active pad XO1, so that the bit line trench region BTR may be formed on the first edge portion EA1 of the active pattern ACT. The bit line trench region BTR extending along the third direction D3 may be formed on the first edge portion EA1 of the active pattern ACT. The bit line trench region BTR may separate one lower storage node contact BCx into a plurality of lower storage node contacts BCx spaced apart from each other in the second direction D2. The bit line trench region BTR may separate one fence pattern FN into a plurality of fence patterns FN spaced apart from each other in the second direction D2. The bit line trench region BTR may separate one buffer pattern BP into a plurality of buffer patterns BP spaced apart from each other in the second direction D2. When the bit line trench region BTR is formed, the top surface of the word line WL may be partially recessed. Therefore, the top surface of the word line WL may be divided into a first top surface W1a and a second top surface W2a. The lower storage node contact BCx, the buffer pattern BP, and the fence pattern FN may have side surfaces exposed outwardly on the inner side surface of the bit line trench region BTR. The active dielectric pattern XI and the first active pad XO1 may have upper portions exposed outwardly on the inner bottom surface of the bit line trench region BTR. The first top surface W1a of the word line WL may be exposed outwardly on the inner bottom surface of the bit line trench region BTR.

[0180] A bit line spacer BSP may be formed in the bit line trench region BTR. The bit line spacer BSP may be formed to cover or overlap the inner side surface of the bit line trench region BTR. For example, a pair of bit line spacers BSP may cover or overlap the opposite side surfaces of the bit line trench region BTR. The formation of the bit line spacer BSP may include, for example, forming a bit line spacer layer (not shown) to cover or overlap the inner surface of the bit line trench region BTR and the top surface of the buffer pattern BP; and removing a portion of the bit line spacer layer. The bit line spacer BSP may be formed or formed by the residue of the bit line spacer layer that is not removed on the inner side surface of the bit line trench region BTR.

[0181] The lower bit line BLx may be formed between the paired bit line spacers BSP in the bit line trench region BTR. The lower bit line BLx may be formed on the first active pad XO1. For example, the lower bit line BLx may be formed by selective epitaxial growth. Selective epitaxial growth may be one of deposition methods that grows a specific material only on a specific region.

[0182] An upper bit line BLy and a bit line capping pattern BCP stacked sequentially may be formed on the lower bit line BLx. The formation of the bit line capping pattern BCP may include, for example, forming a bit line capping layer (not shown) to partially or completely fill the bit line trench region BTR and cover or overlap the front surface of the substrate 100, and removing the upper portion of the bit line capping layer to form the bit line capping patterns BCP separated from each other. Removing the upper portion of the bit line capping layer may include performing a chemical mechanical polishing process on the bit line capping layer. After the removal process, the bit line capping pattern BCP may have a top surface that is located at substantially the same height as the top surface of each of the buffer pattern BP and the bit line spacer BSP, and is coplanar with the top surface of each of the buffer pattern BP and the bit line spacer BSP. Thereafter, a mold pattern MP may be formed to cover or overlap the front surface of the substrate 100.

[0183] refer to Figure 1A and FIG. 2A to FIG. 2D , a contact hole CH penetrating the mold pattern MP may be formed. For example, the formation of the contact hole CH may include: forming a mask pattern (not shown) including a hole (not shown) to cover or overlap the top surface of the mold pattern MP; and using the mask pattern as an etching mask to perform a removal process on the mold pattern MP. When the removal process is performed, the buffer pattern BP, the bit line capping pattern BCP, the bit line spacer BSP, and the lower storage node contact BCx may also be partially removed, and the remaining portions of the buffer pattern BP, the bit line capping pattern BCP, the bit line spacer BSP, and the lower storage node contact BCx may be exposed to the outside on the inner surface of the contact hole CH.

[0184] An upper storage node contact BCy may be formed accordingly in the contact hole CH. For example, the formation of the upper storage node contact BCy may include: forming an upper storage node contact layer (not shown) to partially or completely fill the contact hole CH and cover or overlap the top surface of the mold pattern MP; removing the upper storage node contact layer on the top surface of the mold pattern MP to form upper storage node contacts BCy separated from each other; and removing the upper portion of each upper storage node contact BCy. Removing the upper storage node contact layer on the top surface of the mold pattern MP may include performing a chemical mechanical polishing process on the upper storage node contact layer. Removing the upper portion of the upper storage node contact BCy may include performing an etch-back process on the upper storage node contact BCy. Therefore, the upper storage node contact BCy may have a top surface that is located at a height lower than the top surface of the mold pattern MP.

[0185] A second silicide pattern SC may be formed on the upper storage node contact BCy in the contact hole CH. The second silicide pattern SC may be formed by selective epitaxial growth. A second barrier pattern (not shown) may be further formed together with the second silicide pattern SC.

[0186] A landing pad spacer LSP (such as Figure 2A and / or Figure 4 The landing pad spacer LSP may be formed by forming a landing pad spacer layer (not shown) to conformally cover or overlap the inner surface of the contact hole CH on the second silicide pattern SC. For example, the formation of the landing pad spacer LSP may include: forming a landing pad spacer layer (not shown) to conformally cover or overlap the inner surface of the contact hole CH and the top surface of the mold pattern MP; and etching the landing pad spacer layer to form the landing pad spacer LSP.

[0187] Afterwards, a landing pad LP (such as Figure 2A and / or Figure 4 As shown), to partially or completely fill the unoccupied portion of the contact hole CH. For example, the formation of the landing pad LP may include: forming a landing pad layer (not shown) to partially or completely fill the unoccupied portion of the contact hole CH and cover or overlap the top surface of the mold pattern MP; and removing the upper portion of the landing pad layer to form landing pads LP separated from each other. Removing the upper portion of the landing pad layer may include performing a chemical mechanical polishing process on the landing pad layer. Therefore, the landing pad LP may have a top surface that is located at substantially the same height as the top surface of the mold pattern MP and is coplanar with the top surface of the mold pattern MP.

[0188] Thereafter, a data storage pattern DSP may be correspondingly formed on the landing pad LP.

[0189] Fig.35 is a cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0190] refer to Fig.35 , in forming a reference Figures 27 to 28D After the active pattern ACT and the device isolation pattern STI are discussed, a first active pad XO1 may be formed on a first edge portion EA1 of the active pattern ACT. A second active pad XO2 may be formed on a second edge portion EA2 of the active pattern ACT. The formation of the first active pad XO1 and the second active pad XO2 may include performing an engraving process in which an active dielectric layer (not shown) is used. For example, after forming an active dielectric layer on the front surface of the substrate 100, the active dielectric layer may be removed to form an active dielectric pattern XI, and the first active pad XO1 and the second active pad XO2 may be formed between the active dielectric patterns XI.

[0191] When the removal process is performed, the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT may be partially removed. Therefore, the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT may have top surfaces EA1a and EA2a, which are located at a lower height than the uppermost surface STIa of the device isolation pattern STI. Each of the first active pad XO1 and the second active pad XO2 may have a bottom surface, which is located at a lower height than the bottom surface of the active dielectric pattern X1.

[0192] Thereafter, the reference Figure 3 Semiconductor devices discussed.

[0193] Figure 36 to Figure 39 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0194] refer to Fig.36 and Fig.37 , in forming a reference Figures 27 to 28D After the active pattern ACT and the device isolation pattern STI discussed, a first active dielectric pattern XI1 extending along the third direction D3 may be formed on the central portion CA of the active pattern ACT. The formation of the first active dielectric pattern XI1 may include: forming an active dielectric layer (not shown) to cover or overlap the front surface of the substrate 100; and removing the active dielectric layer to form the first active dielectric pattern XI1. When the removal process is performed, the device isolation pattern STI and the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT may also be partially removed, and the process may expose the top surface of the device isolation pattern STI and the top surface EA1a of the first edge portion EA1 and the top surface EA2a of the second edge portion EA2 of the active pattern ACT to the outside. Therefore, the exposed top surface of the device isolation pattern STI and the exposed top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT may be located at a height lower than the uppermost surface STIa of the device isolation pattern STI. Top surfaces EA1a and EA2a of the first and second edge portions EA1 and EA2 of the active pattern ACT may be located at a lower height than the center portion CA of the active pattern ACT.

[0195] The active pad layer XOL is formed to cover or overlap top surfaces EA1a and EA2a of the first and second edge portions EA1 and EA2 of the active pattern ACT, the exposed device isolation pattern STI, and the first active dielectric pattern XI1.

[0196] refer to Fig.38 and Fig.39, a removal process may be performed on the active pad layer XOL. The removal process may include an anisotropic etching process, and thus a portion of the active pad layer XOL may remain on the side surface of the first active dielectric pattern XI1 without being removed. A portion of the active pad layer XOL may remain on the first edge portion EA1 and the second edge portion EA2, and may constitute or form the first active pad XO1 and the second active pad XO2. When the removal process is performed, a portion of the device isolation pattern STI may also be removed, and a top surface STIa of the device isolation pattern STI may be exposed outwardly. The exposed top surface STIa of the device isolation pattern STI may be located at a height lower than the top surfaces EA1a and EA2a of the first edge portion EA1 and the second edge portion EA2 of the active pattern ACT.

[0197] The second active dielectric pattern XI2 extending along the third direction D3 may be formed between the active patterns ACT adjacent to each other along the first direction D1. The second active dielectric pattern XI2 may be formed to cover or overlap the exposed top surface STIa of the device isolation pattern STI.

[0198] Thereafter, the semiconductor fabrication methods discussed above can be used to fabricate the reference Figure 4 Semiconductor devices discussed.

[0199] Figure 40 to Figure 43 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0200] refer to Figure 40 to Figure 43 , in forming a reference Figures 27 to 28D After the active patterns ACT and the device isolation patterns STI discussed above, a first active dielectric pattern XI1 extending along the third direction D3 may be formed between the active patterns ACT adjacent to each other along the first direction D1. The formation of the first active dielectric pattern XI1 may be similar to that of the reference Fig.36 and 37 The situation under discussion.

[0201] The first active pad XO1 may be formed on the first edge portion EA1 of the active pattern ACT. The second active pad XO2 may be formed on the second edge portion EA2 of the active pattern ACT. The formation of the first active pad XO1 and the second active pad XO2 may be similar to that of the reference numeral 2. Fig.38 and Fig.39 The second active dielectric pattern XI2 extending along the third direction D3 may be formed on the central portion CA of the active pattern ACT.

[0202] The device isolation pattern STI and the first and second edge portions EA1 and EA2 of the active pattern ACT may have similar Figure 36 to Figure 39 The feature in question.

[0203] Thereafter, the semiconductor fabrication methods discussed above can be used to fabricate the reference Figure 5 Semiconductor devices discussed.

[0204] Figures 44 to 47C are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0205] refer to Figures 44 to 45C , in forming a reference Figures 27 to 28D After the active pattern ACT and the device isolation pattern STI discussed above, a word line WL may be formed to pass through the active pattern ACT and the device isolation pattern STI. The formation of the word line WL may be similar to that of the reference Figures 31 to 32D Afterwards, the first active pad XO1 and the second active pad XO2 may be formed. The formation of the first active pad XO1 and the second active pad XO2 may be similar to that of the reference Figures 29 to 30D Since the word line WL is formed after the first and second active pads XO1 and XO2 are formed, the first and second active pads XO1 and XO2 may have top surfaces located at a higher height than the top surface of the word line WL.

[0206] On the word line WL, a lower fence pattern FNx may be formed to penetrate the first and second active pads XO1 and XO2. The lower fence pattern FNx may be formed to extend along the second direction D2 on the word line WL.

[0207] refer to Figures 46 to 47C , lower storage node contacts BCx and upper fence patterns FNy alternately arranged along the third direction D3 may be formed on the substrate 100. Lower storage node contacts BCx extending along the second direction D2 may be formed on the second edge portion EA2 of the active pattern ACT. Upper fence patterns FNy extending along the second direction D2 may be formed on the lower fence patterns FNx. For example, the formation of the lower storage node contacts BCx and the upper fence patterns FNy may be similar to that of the reference FIG. 32A to FIG. 32D The formation of the lower storage node contact BCx and the fence pattern FN is discussed.

[0208] Thereafter, the reference FIG. 6A to FIG. 6C Semiconductor devices discussed.

[0209] Figures 48 to 49C are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0210] refer to Figure 48 to Figure 4 9D, in reference Figures 44 to 45C After the first active pad XO1 and the second active pad XO2 are formed, lower storage node contacts BCx and fence patterns FN alternately arranged along the third direction D3 may be formed on the substrate 100. For example, the formation of the lower storage node contacts BCx and the fence patterns FN may be similar to that of the reference Figures 32A to 32D The situation under discussion.

[0211] The fence pattern FN may be formed through the first active pad XO1 and the second active pad XO2. Therefore, the fence pattern FN may separate the first active pads XO1 from each other in the third direction D3, and may also separate the second active pads XO2 from each other in the third direction D3.

[0212] Thereafter, the reference 7A to 7C Semiconductor devices discussed.

[0213] Fig.50A and Fig.50B is a cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0214] refer to Fig.50A and Fig.50B , in reference Figures 31 to 32D After the word line WL discussed is formed, a removal process may be performed on the upper portion of each of the active dielectric pattern XI and the gate dielectric pattern GI. Each of the active dielectric pattern XI and the gate dielectric pattern GI may have an etching selectivity relative to surrounding components (e.g., the gate capping pattern GC and the first active pad XO1 and the second active pad XO2). Therefore, although the active dielectric pattern XI and the gate dielectric pattern GI are both removed when the removal process is performed, the surrounding components may not be removed or may be removed less. Each of the first active pad XO1 and the second active pad XO2 may be exposed outwardly at its top surface and the side surface of its upper portion.

[0215] The active dielectric pattern XI and the gate dielectric pattern GI may have top surfaces XIa and GIa located at a lower height than top surfaces XO1a and XO2a of the first and second active pads XO1 and XO2.

[0216] Afterwards, the semiconductor fabrication methods discussed above can be used to fabricate the reference Fig. 8A and Figure 8B Semiconductor devices discussed.

[0217] Figures 51 to 54C are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0218] refer to Figures 51 to 52C , in reference Figures 27 to 28D After the active pattern ACT and the device isolation pattern STI discussed are formed, a removal process may be performed on the upper portion of the device isolation pattern STI. Therefore, the device isolation pattern STI may have an uppermost surface STIa located at a lower height than the top surface of the active pattern ACT, and the upper portion of the active pattern ACT may have a side surface exposed outward.

[0219] The active pad XO may be formed to surround the exposed side surface of the upper portion of the active pattern ACT. For example, the formation of the active pad XO may include: forming an active pad layer (not shown) to conformally cover or overlap the top surface and side surface of the active pattern ACT and the uppermost surface STIa of the device isolation pattern STI, and removing the active pad on the top surface of the active pattern ACT and the top surface of the device isolation pattern STI. The active pad layer may not be removed on the side surface of the active pattern ACT, and the remaining portion of the active pad may constitute or form the active pad XO.

[0220] Afterwards, an active dielectric pattern XI may be formed on the device isolation pattern STI between the active patterns ACT. Top surfaces EA1a and EA2a of the first and second edge portions EA1 and EA2 of the active pattern ACT, the top surface of the active pad XO, and the top surface of the active dielectric pattern XI may be located at substantially the same height and coplanar with each other.

[0221] refer to Figure 53 to Figure 5 4D, a word line WL may be formed to pass through the active pattern ACT, the device isolation pattern STI, and the active pad XO. The formation of the word line WL may be similar to that of the reference Figures 31 to 32D When the word line WL is formed, the active pad XO may be divided into a first active pad XO1 and a second active pad XO2.

[0222] Thereafter, the reference Figures 9 to 10C Semiconductor devices discussed.

[0223] Fig.55 and Fig.56 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0224] refer to Fig.55 and Fig.56 , in reference Figures 29 to 30D After the active dielectric pattern XI is formed as discussed, a removal process may be performed on an upper portion of the active dielectric pattern XI. Thus, each of the first active pad XO1 and the second active pad XO2 may have a side surface exposed outward.

[0225] The first active additional pad SXO1 may be formed to cover or overlap the exposed side surface of the first active pad XO1. The first active additional pad SXO1 may extend along the third direction D3 on the side surface of the first active pad XO1. The second active additional pad SXO2 may be formed to cover or overlap the exposed side surface of the second active pad XO2. The second active additional pad SXO2 may extend along the third direction D3 on the side surface of the second active pad XO2. For example, the formation of the first active additional pad SXO1 and the second active additional pad SXO2 may include: forming an active additional pad layer (not shown) to cover or overlap the top surface and the exposed side surface of the first active pad XO1 and the second active pad XO2 and the top surface of the active dielectric pattern XI; and removing the active additional pad layer to form the first active additional pad SXO1 and the second active additional pad SXO2. The active additional dielectric pattern SXI may be formed on the active dielectric pattern XI between the first active additional pad SXO1 and the second active additional pad SXO2.

[0226] Thereafter, the reference Figure 11 to Figure 12 Semiconductor devices discussed.

[0227] Figures 57 to 58B are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0228] refer to Figures 57 to 58B , in reference Figures 29 to 30D After the active dielectric pattern XI is formed as discussed, a lower storage node contact layer may be formed on the front surface of the substrate 100 before forming the word lines WL.

[0229] Afterwards, a word line WL may be formed to pass through the active pattern ACT and the device isolation pattern STI. The word line WL may be formed to penetrate the first active pad XO1, the second active pad XO2, and the lower storage node contact layer. Therefore, the first active pad XO1 may be formed to be spaced apart from each other in the third direction D3, and the second active pad XO2 may be formed to be spaced apart from each other in the third direction D3. In addition, a plurality of lower storage node contacts BCx may be formed, which are spaced apart from each other in the third direction D3, and each of the lower storage node contacts BCx extends in the second direction D2. The formation of the word line WL may be similar to that of the reference numeral 1. Figures 31 to 32D The situation under discussion.

[0230] Thereafter, the reference Figures 13 to 14B Semiconductor devices discussed.

[0231] Figures 59 to 60Dare plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0232] refer to Figures 59 to 60D , in reference Figures 31 to 32D After the formation of the word line WL discussed above, reference may be omitted. Figures 31 to 32D The formation of the lower storage node contact BCx discussed, and the buffer pattern BP may be formed to cover or overlap the front surface of the substrate 100. The first and second active pads XO1 and XO2 and the active dielectric pattern XI may each be formed to have a location at a position greater than the reference Figures 29 to 30D The height in question is the top surface.

[0233] After forming the buffer pattern BP, without a separate process for forming the lower storage node contact BCx, the bit line BL, the bit line capping pattern BCP, the mold pattern MP, the upper storage node contact BCy, and the data storage pattern DSP may be sequentially formed using the above-mentioned semiconductor manufacturing method to form a reference Figures 15 to 16D The semiconductor device in question.

[0234] In some embodiments, after the step of forming the buffer pattern BP, referring to Figures 17 to 18D The semiconductor manufacturing method discussed for forming a semiconductor device may be partially different from the semiconductor manufacturing method described above.

[0235] refer to Figures 17 to 18D , a bit line trench region BTR, a bit line spacer BSP, a bit line BL, a bit line capping pattern BCP, and a mold pattern MP may be sequentially formed, and each of them may be similar to the reference Figures 33 to 34D The method discussed is formed.

[0236] Afterwards, a contact hole CH may be formed between the bit lines BL adjacent to each other in the second direction D2. When the contact hole CH is formed, the upper portion of each of the second active pad XO2 and the active dielectric pattern X1 may be recessed to a certain depth and exposed to the outside. For example, the contact holes CH in a certain queue may be arranged side by side along the second direction D2, and the contact holes CH in another queue may be arranged side by side along the third direction D3.

[0237] An upper storage node contact BCy, a second silicide pattern SC, and a landing pad spacer LSP may be formed in the contact hole CH, and each of them may be similar to the reference Figure 1A and FIG. 2A to FIG. 2D Formed as discussed.

[0238] Thereafter, a lower landing pad LPx may be formed to partially or completely fill the unoccupied portion of the contact hole CH. The formation of the lower landing pad LPx may be similar to that described in reference to FIG. Figure 1Aand FIG. 2A to FIG. 2D The formation of the landing pad LP is discussed.

[0239] Afterwards, an upper landing pad LPy may be formed on the lower landing pad LPx. The formation of the upper landing pad LPy may include: sequentially forming an upper landing pad layer (not shown) and a mask pattern (not shown) to cover or overlap the top surface of the lower landing pad LPx; and performing an anisotropic etching process using the mask pattern as an etching mask, in which the landing pad layer is removed to form a plurality of upper landing pads LPy.

[0240] Thereafter, a filling pattern FIL may be formed on the region where the landing pad layer is removed. The filling pattern FIL may be formed to surround each upper landing pad LPy. A data storage pattern DSP may be formed on each upper landing pad LPy.

[0241] Figures 61 to 64D are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0242] refer to Figures 61 to 62D , after removing the reference Fig.50A and Fig.50B After each active dielectric pattern XI and gate dielectric pattern GI are discussed, a lower storage node contact BCx and a lower landing pad LPx may be sequentially stacked and formed on the substrate 100 .

[0243] A fence pattern FN extending along the second direction D2 may be formed on the word line WL. The fence pattern FN may be formed to penetrate the lower storage node contact BCx and the lower landing pad LPx. Therefore, the lower storage node contacts BCx may be spaced apart from each other in the third direction D3, and the lower landing pads LPx may be spaced apart from each other in the third direction D3.

[0244] refer to Figures 63 to 64D , you can omit the reference Figures 31 to 32D The formation of the buffer pattern BP discussed above. The bit line trench region BTR, the bit line spacer BSP, the bit line BL, and the bit line capping pattern BCP may be sequentially formed, and each of them may be similar to the reference Figures 33 to 34D Formed as discussed.

[0245] Afterwards, the reference can be omitted Figures 33 to 34D The formation of the mold pattern MP discussed. In addition, reference Figure 1A and FIG. 2A to FIG. 2D The formation of the upper storage node contact BCy, the second silicide pattern SC, and the landing pad spacer LSP are discussed.

[0246] The upper landing pad layer LPL may be formed to cover or overlap the front surface of the substrate 100. The landing pad mask pattern LMP may be formed on the upper landing pad layer LPL. The landing pad mask pattern LMP may have the same shape as the reference numeral 140 when viewed in a plane. Figure 1A and FIG. 2A to FIG. 2D The contact holes CH discussed are located similarly. The landing pad mask patterns LMP may be disposed linearly along the second direction D2, and may be arranged in a zigzag shape along the third direction D3.

[0247] refer to Figures 19 to 20D The landing pad mask pattern LMP may be used as an etching mask to perform an etching process in which the upper landing pad layer LPL is etched to form a plurality of upper landing pads LPy. The etching process may include an anisotropic etching process.

[0248] Thereafter, a filling pattern FIL may be formed on the region where the upper landing pad LPy is removed. The filling pattern FIL may be formed to surround each of the upper landing pads LPy. A data storage pattern DSP may be formed on each of the upper landing pads LPy.

[0249] Fig.65 and Fig.66 are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0250] refer to Fig.65 and Fig.66 , in reference Figures 63 to 64D After the bit line capping pattern BCP discussed above is formed, a mold pattern MP may be formed. For example, the mold pattern MP may be formed similarly to the method described in reference to Figures 33 to 34D The situation under discussion.

[0251] refer to Fig.19 and Fig.21 , a contact hole CH may be formed to penetrate the mold pattern MP. The formation of the contact hole CH may be similar to that of the reference Figure 1A and FIG. 2A to FIG. 2D The situation under discussion.

[0252] Afterwards, the reference can be omitted Figure 1A and FIG. 2A to FIG. 2D The formation of the upper storage node contact BCy, the second silicide pattern SC, and the landing pad spacer LSP are discussed.

[0253] The upper landing pad LPy may be formed to partially or completely fill the unoccupied portion of the contact hole CH. For example, the formation of the upper landing pad LPy may include: forming an upper landing pad layer (not shown) to partially or completely fill the unoccupied portion of the contact hole CH and cover or overlap the top surface of the mold pattern MP; and removing the upper portion of the upper landing pad layer to form upper landing pads LPy separated from each other. Removing the upper portion of the upper landing pad layer may include performing a chemical mechanical polishing process on the upper landing pad layer. A data storage pattern DSP may be formed on each of the upper landing pads LPy.

[0254] Figures 67 to 68D are plan views and cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0255] refer to Figures 67 to 68D , in reference Figures 61 to 62D After the lower landing pad LPx in question is formed, a buffer pattern BP may be formed on the lower landing pad LPx.

[0256] The bit line trench region BTR, the bit line spacer BSP, the bit line BL, and the bit line capping pattern BCP may be sequentially formed, and each of them may be similar to the reference numerals. Figures 33 to 34D Reference may be omitted. Figures 33 to 34D Formation of the mold pattern MP discussed An interlayer dielectric layer ILD may be formed on the front surface of the substrate 100 .

[0257] refer to Figures 22 to 23D , a contact hole CH may be formed to penetrate the interlayer dielectric layer ILD. The formation of the contact hole CH may be similar to that of the reference Figure 1A and FIG. 2A to FIG. 2D The situation under discussion.

[0258] References can be omitted Figure 1A and FIG. 2A to FIG. 2D The formation of the upper storage node contact BCy, the second silicide pattern SC, and the landing pad spacer LSP are discussed.

[0259] A bottom electrode BE may be formed on the contact hole CH. The formation of the bottom electrode BE may include: forming a bottom electrode layer (not shown) to partially or completely fill the contact hole CH and cover or overlap the top surface of the interlayer dielectric layer ILD; and removing the bottom electrode layer to form the bottom electrode BE. The bottom electrode BE may include a lower portion BEx and an upper portion BEy.

[0260] The dielectric layer DL may be formed to conformally cover or overlap the top surface of the interlayer dielectric layer ILD and the upper portions BEy of the bottom electrodes BE. The top electrode TE may be formed between and over the upper portions BEy of the bottom electrodes BE.

[0261] Fig.69A and Fig.69B is a cross-sectional view showing a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0262] refer to Fig.69A and Fig.69B , as reference Figures 31 to 32D When the bit line trench region BTR is formed as discussed, a gate capping pattern GC may be formed whose top surface GCa is located at a height higher than the top surface of the first active pad XO1 and the top surface GIa of the gate dielectric pattern GI. This may be adjusted by using the etching selectivity between the gate capping pattern GC and its surrounding components (e.g., the first active pad XO1 and the gate dielectric pattern GI). When the bit line trench region BTR is formed, the gate capping pattern GC may be removed less than the surrounding components.

[0263] According to the inventive concept, a first active pad may be provided between a bit line and a first edge portion of an active pattern, and a second active pad may be provided between a storage node contact and a second edge portion of the active pattern. Therefore, an easy electrical connection may be provided between the bit line and the first edge portion and between the storage node contact and the second edge portion. Therefore, the semiconductor device may have improved electrical performance and enhanced reliability.

[0264] The above description provides some embodiments for explaining the inventive concept. Therefore, the inventive concept is not limited to the above embodiments, and those skilled in the art will appreciate that changes in form and detail may be made without departing from the spirit of the inventive concept and the described features.

Claims

1. A semiconductor device, comprising: substrate; an active pattern, the active pattern being located on the substrate, wherein the active pattern includes a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending along a second direction between the first edge portion and the second edge portion of the active pattern, wherein the second direction intersects the first direction; a bit line extending along a third direction on the first edge portion of the active pattern, wherein the third direction intersects the first direction and the second direction; a storage node contact located on the second edge portion of the active pattern; a first active pad located between the bit line and the first edge portion of the active pattern; and a second active pad located between the storage node contact and the second edge portion of the active pattern, wherein the first active pad extends in the third direction beyond the first edge portion of the active pattern, and The second active pad extends beyond the second edge portion of the active pattern in a direction opposite to the third direction.

2. The semiconductor device according to claim 1, wherein With respect to the substrate, a top surface of the second active pad is higher than a bottom surface of the bit line.

3. The semiconductor device according to claim 1, wherein With respect to the substrate, a bottom surface of the storage node contact is higher than a bottom surface of the bit line.

4. The semiconductor device according to claim 1, further comprising: A bit line cover pattern, the bit line cover pattern is located on the bit line; as well as a bottom electrode, the bottom electrode being located on the storage node contact, Wherein, the bottom electrode contacts the bit line covering pattern.

5. The semiconductor device according to claim 1, wherein With respect to the substrate, a top surface of the bit line is lower than a bottom surface of the storage node contact.

6. The semiconductor device according to claim 1, wherein The storage node contact partially overlaps the bit line in a direction perpendicular to the second direction.

7. The semiconductor device according to claim 1, further comprising: a first active additional pad, the first active additional pad being located on a side surface of the first active pad; as well as A second active additional pad is located on a side surface of the second active pad.

8. The semiconductor device according to claim 1, wherein The first active pad and the second active pad include a same material as that of the active pattern.

9. The semiconductor device according to claim 1, in, The active pattern is a first active pattern, Wherein, the semiconductor device further comprises: a second active pattern, the second active pattern being adjacent to the first active pattern in the second direction; a third active pattern, the third active pattern being adjacent to the second active pattern in the third direction; and a fourth active pattern, the fourth active pattern being adjacent to the first active pattern in the third direction, and Wherein, the second edge portion of the fourth active pattern, the first edge portion of the first active pattern, the second edge portion of the third active pattern, and the first edge portion of the second active pattern are sequentially disposed along the second direction.

10. The semiconductor device according to claim 9, in, The word line is a first word line, The semiconductor device further includes a second word line, wherein the second word line is adjacent to the first word line in the third direction. wherein the first word line intersects the first active pattern and the second active pattern, and The second word line intersects the third active pattern and the fourth active pattern.

11. A semiconductor device, comprising: substrate; an active pattern, the active pattern being located on the substrate, wherein the active pattern includes a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending along a second direction between the first edge portion and the second edge portion of the active pattern, wherein the second direction intersects the first direction; a bit line extending along a third direction on the first edge portion of the active pattern, wherein the third direction intersects the first direction and the second direction; a storage node contact located on the second edge portion of the active pattern; a first active pad located between the bit line and the first edge portion of the active pattern; and a second active pad located between the storage node contact and the second edge portion of the active pattern, Wherein, relative to the substrate, a top surface of the second active pad is higher than a bottom surface of the bit line.

12. The semiconductor device according to claim 11, wherein With respect to the substrate, a bottom surface of the storage node contact is higher than a bottom surface of the bit line.

13. The semiconductor device according to claim 11, wherein The first active pad and the second active pad include a same material as that of the active pattern.

14. The semiconductor device according to claim 11, wherein When viewed in a plan view of the semiconductor device, an area of ​​an overlap region between the bit line and a top surface of the first active pad is larger than an area of ​​an overlap region between the bit line and a top surface of the first edge portion of the active pattern.

15. The semiconductor device according to claim 11, wherein When viewed in a plan view of the semiconductor device, an overlapping region between the storage node contact and a top surface of the first active pad has a larger area than an overlapping region between the storage node contact and a top surface of the first edge portion of the active pattern.

16. The semiconductor device according to claim 11, in, The active pattern is a first active pattern, Wherein, the semiconductor device further comprises: a second active pattern, the second active pattern being adjacent to the first active pattern in the second direction; a third active pattern, the third active pattern being adjacent to the second active pattern in the third direction; and a fourth active pattern, the fourth active pattern being adjacent to the first active pattern in the third direction, and Wherein, the second edge portion of the fourth active pattern, the first edge portion of the first active pattern, the second edge portion of the third active pattern, and the first edge portion of the second active pattern are sequentially disposed along the second direction.

17. A semiconductor device, comprising: substrate; an active pattern, the active pattern being located on the substrate, wherein the active pattern includes a first edge portion and a second edge portion spaced apart from each other in a first direction; a word line extending along a second direction between the first edge portion and the second edge portion of the active pattern, wherein the second direction intersects the first direction; a bit line extending along a third direction on the first edge portion of the active pattern, wherein the third direction intersects the first direction and the second direction; a lower storage node contact, the lower storage node contact being located on the second edge portion of the active pattern; an upper storage node contact, the upper storage node contact being located on the lower storage node contact, wherein the upper storage node contact partially overlaps the lower storage node contact in a direction perpendicular to the second direction; a first active pad between the bit line and the first edge portion of the active pattern; a second active pad between the lower storage node contact and the second edge portion of the active pattern; a landing pad located on the upper storage node contact; and a data storage pattern, the data storage pattern being located on the landing pad, wherein the first active pad extends in the third direction beyond the first edge portion of the active pattern, and The second active pad extends beyond the second edge portion of the active pattern in a direction opposite to the third direction.

18. The semiconductor device according to claim 17, wherein: The upper storage node contact is offset from the lower storage node contact in the second direction or in a direction opposite to the second direction.

19. The semiconductor device according to claim 17, further comprising: A bit line cover pattern, the bit line cover pattern is located on the bit line, Wherein, the upper storage node contact is in contact with the bit line covering pattern.

20. The semiconductor device according to claim 19, wherein With respect to the substrate, a bottom surface of the landing pad is higher than a top surface of the bit line capping pattern.

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