Semiconductor device

Abstract

A semiconductor device includes: a bit line on a cell region of a substrate; a contact plug located between the bit lines; a landing pad on the contact plug; the peripheral grid electrode is located on the peripheral circuit area of the substrate; a lower interlayer insulating layer covering a side surface of the peripheral gate; a peripheral contact plug penetrating the lower interlayer insulating layer; a peripheral interconnection layer on the lower interlayer insulating layer and the peripheral contact plug; and a peripheral insulating structure passing between the peripheral interconnect layers, where the peripheral insulating structure includes a first peripheral insulating structure partially penetrating the lower interlayer insulating layer, and where the peripheral insulating structure includes a second peripheral insulating structure partially penetrating the lower interlayer insulating layer. The first peripheral insulating structure includes a first peripheral insulating layer, a second peripheral insulating layer on the first peripheral insulating layer and passing between the peripheral interconnect layers, and a mixture layer between the lower interlayer insulating layer and the first peripheral insulating layer.

Description

Technical Field

[0001] Example embodiments relate to a semiconductor device including a peripheral insulation structure. Background Art

[0002] The demand for high performance, high speed and / or multi-function of semiconductor devices is increasing, thereby increasing the integration density of semiconductor devices. When manufacturing semiconductor devices with fine patterns corresponding to the trend of high integration density of semiconductor devices, it may be desirable to realize patterns with fine width or fine spacing. Summary of the invention

[0003] According to example embodiments, a semiconductor device may include: a substrate including a cell region and a peripheral circuit region; a bit line structure disposed on the cell region; a contact plug disposed between the bit line structures; a landing pad structure disposed on the contact plug; a peripheral gate structure disposed on the peripheral circuit region; a lower interlayer insulating layer covering a side surface of the peripheral gate structure; a peripheral contact plug penetrating the lower interlayer insulating layer; a plurality of peripheral interconnect layers disposed on the lower interlayer insulating layer and the peripheral contact plug; and a plurality of peripheral insulating structures passing between the plurality of peripheral interconnect layers, wherein the plurality of peripheral insulating structures include a first peripheral insulating structure partially penetrating the lower interlayer insulating layer, and wherein the first peripheral insulating structure includes a first peripheral insulating layer, a second peripheral insulating layer disposed on the first peripheral insulating layer and passing between the plurality of peripheral interconnect layers, and a mixture layer disposed between the lower interlayer insulating layer and the first peripheral insulating layer.

[0004] According to example embodiments, a semiconductor device may include: a substrate including a cell region and a peripheral circuit region; a bit line structure disposed on the cell region; a first contact plug and a second contact plug, the first contact plug and the second contact plug being disposed between the bit line structures and spaced apart from each other; a spacer structure disposed on a side surface of one of the bit line structures and in contact with the second contact plug; a first landing pad structure disposed on the first contact plug and including a first lower landing pad and a first upper landing pad located on the first lower landing pad; a second landing pad structure disposed on the second contact plug and including a second lower landing pad and a second upper landing pad located on the second lower landing pad; a cell insulation pattern, the cell insulation pattern being located between the first landing pad structure and the second landing pad structure; a peripheral gate structure, which is arranged on the peripheral circuit area; a lower interlayer insulating layer, which covers the side surface of the peripheral gate structure; a peripheral contact plug, which penetrates the lower interlayer insulating layer; a plurality of peripheral interconnection layers, which are located on the lower interlayer insulating layer and the peripheral contact plug; and a plurality of peripheral insulation structures, which pass through and partially penetrate the lower interlayer insulating layer between the plurality of peripheral interconnection layers, wherein the lower surface of the unit insulation pattern includes a first portion in contact with the upper surface of the spacer structure and a second portion in contact with the second lower landing pad, and wherein the lower end of the second portion of the unit insulation pattern is set at a height lower than the lower end of the first portion of the unit insulation pattern.

[0005] According to example embodiments, a semiconductor device may include: a substrate including a cell region and a peripheral circuit region; a first active region, the first active region being disposed on the substrate in the cell region; a cell gate structure, the cell gate structure being disposed in the substrate in the cell region, intersecting the first active region and extending in a first horizontal direction; a bit line structure, the bit line structure intersecting the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction; a contact plug, the contact plug being disposed between the bit line structures; a landing pad structure, the landing pad structure being disposed on the contact plug and including a lower landing pad and an upper landing pad located on the lower landing pad; a peripheral gate structure, the peripheral gate structure being disposed on the peripheral circuit region; a lower interlayer insulating layer, the lower interlayer insulating layer covering the lower landing pad; Covering the side surface of the peripheral gate structure; a peripheral contact plug, the peripheral contact plug penetrating the lower interlayer insulating layer; a plurality of peripheral interconnection layers, the plurality of peripheral interconnection layers being located on the lower interlayer insulating layer and the peripheral contact plug; and a plurality of peripheral insulation structures, the plurality of peripheral insulation structures passing between the plurality of peripheral interconnection layers, wherein the plurality of peripheral insulation structures include a first peripheral insulation structure partially penetrating the lower interlayer insulating layer, wherein the first peripheral insulation structure includes a first peripheral insulation layer, a second peripheral insulation layer disposed on the first peripheral insulation layer and passing between the plurality of peripheral interconnection layers, and a mixture layer located between the lower interlayer insulating layer and the first peripheral insulation layer, wherein the lower interlayer insulating layer and the first peripheral insulation layer include silicon oxide, and wherein the mixture layer and the second peripheral insulation layer include silicon nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Features will become apparent to those skilled in the art by describing exemplary embodiments in detail with reference to the accompanying drawings, in which:

[0007] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments;

[0008] Figure 2 yes Figure 1 An enlarged top view of area "A" in FIG.

[0009] Figure 3A It is along Figure 2 A cross-sectional view along lines II-I' and II-II';

[0010] Figure 3B It is along Figure 1 A cross-sectional view along line III-III';

[0011] Figure 4 yes Figure 3AAn enlarged view of area "B" in FIG.

[0012] Figure 5A Pictured Figure 3B Magnified images of areas "C" and "D" in FIG.

[0013] Figure 5B is a graph indicating the proportion of silicon nitride in the mixture layer;

[0014] Figures 6 to 8 is a cross-sectional view of a semiconductor device according to an example embodiment;

[0015] Fig.9A and Fig. 9B is a cross-sectional view illustrating a semiconductor device according to example embodiments;

[0016] FIG. 10A to FIG. 20B are cross-sectional views of stages in a method of manufacturing a semiconductor device according to an example embodiment; and

[0017] Fig.21 is a cross-sectional view illustrating a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings as follows.

[0019] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments.

[0020] refer to Figure 1 , the semiconductor device 100 according to the example embodiment may include a cell area CA, an interface area IA, and a peripheral circuit area PA. The peripheral circuit area PA may be disposed to surround the cell area CA, and the interface area IA may be disposed between the cell area CA and the peripheral circuit area PA. The cell area CA may refer to an area in which a memory cell of a dynamic random access memory (DRAM) device is disposed, and in the peripheral circuit area PA, a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit may be disposed. The interface area IA may electrically connect the cell area CA to the peripheral circuit area PA.

[0021] Figure 2 It's a picture. Figure 1 An enlarged view of region 'A' of the semiconductor device is illustrated. Figure 3A It is along Figure 2 Cross-sectional view along lines II' and II-II'. Figure 3B It is along Figure 1 Cross-sectional view along line III-III'.

[0022] Figure 4 It's a picture. Figure 3A Magnified view of area "B" in FIG. Figure 5A It's a picture. Figure 3B Magnified images of areas "C" and "D".

[0023] refer to Figures 2 to 5A , the semiconductor device 100 according to the example embodiment may include a cell gate structure GS disposed in the substrate 3, a buffer layer 21 disposed on the substrate 3, a bit line structure BLS, a spacer structure SP, a contact plug 60, a landing pad structure LP, a cell insulation pattern 72, and a capacitor structure 80 in the cell area CA. For example, the semiconductor device 100 may be applicable to a cell array of a dynamic random access memory (DRAM). The semiconductor device 100 may also include a peripheral gate structure GS_P disposed on the substrate 3, a lower interlayer insulation layer 130, a peripheral contact plug 170, a peripheral interconnection layer 171, and a peripheral insulation structure IS in the peripheral circuit area PA.

[0024] In detail, the substrate 3 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon germanium. The substrate 3 may be configured as a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer.

[0025] In the cell region CA, the substrate 3 may include a first active region 6a, a first device isolation layer 6s, a first impurity region 9a, and a second impurity region 9b. The first device isolation layer 6s may be an insulating layer extending downward from the upper surface of the substrate 3, and may define the first active region 6a. For example, the first active region 6a may correspond to a portion of the upper surface of the substrate 3 surrounded by the first device isolation layer 6s. In a top view, the first active region 6a may be in the shape of a strip having a short axis and a long axis, and may extend in a direction inclined relative to the X direction and the Y direction. The first device isolation layer 6s may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may include a single layer or multiple layers.

[0026] The first active region 6a may include a first impurity region 9a and a second impurity region 9b extending from the upper surface of the substrate 3 to a predetermined depth. The first impurity region 9a and the second impurity region 9b may be spaced apart from each other. The first impurity region 9a and the second impurity region 9b may be set as the source / drain region of the transistor. For example, for one first active region 6a, two unit gate structures GS may intersect with the one first active region 6a, a drain region may be formed between the two unit gate structures GS, and a source region may be formed in a region opposite to the drain region for the two unit gate structures GS. For example, the first impurity region 9a may correspond to the drain region, and the second impurity region 9b may correspond to the source region. The source region and the drain region may be formed by the first impurity region 9a and the second impurity region 9b, and the first impurity region 9a and the second impurity region 9b are formed by doping or ion implanting substantially the same impurities, and may be referred to interchangeably depending on the circuit configuration of the transistor finally formed. The first impurity region 9a and the second impurity region 9b may include impurities having a conductivity opposite to that of the substrate 3. For example, the first active region 6 a may include P-type impurities, and the first impurity region 9 a and the second impurity region 9 b may include N-type impurities.

[0027] In the cell region CA, the cell gate structures GS may extend in the X direction and may be spaced apart from each other in the Y direction. Likewise, the cell gate structure GS may intersect the first active region 6a. For example, two cell gate structures GS may intersect the first active region 6a. Transistors each including a cell gate structure GS and first and second impurity regions 9a and 9b may form a buried channel array transistor (BCAT).

[0028] In the cross-sectional view, the cell gate structure GS may be buried in the substrate 3, for example, the cell gate structure GS may be disposed in a gate trench 12 formed in the substrate 3. The cell gate structure GS may include a cell gate dielectric layer 14 disposed in the gate trench 12, a gate electrode 16, and a gate capping layer 18. The cell gate dielectric layer 14 may be conformally formed on the inner wall of the gate trench 12. The gate electrode 16 may be disposed at a lower portion of the gate trench 12, and the gate capping layer 18 may be disposed at an upper portion of the cell gate structure GS and may fill the gate trench 12.

[0029] The cell gate dielectric layer 14 may include, for example, silicon oxide or a material having a high-κ material. In an example embodiment, the cell gate dielectric layer 14 may be formed by oxidizing the first active region 6a, or may be formed by deposition. The gate electrode 16 may include a conductive material, for example, at least one of polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). The gate cap layer 18 may include, for example, silicon nitride.

[0030] In the cell region CA, a buffer layer 21 may be disposed on the first active region 6a, the first device isolation layer 6s and the cell gate structure GS. The buffer layer 21 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. The buffer layer 21 may be configured as a single layer or multiple layers.

[0031] In the cell area CA, the bit line structure BLS may extend in the Y direction and may be spaced apart from each other in the X direction. The bit line structure BLS may be in the shape of a strip extending in the Y direction. The bit line structure BLS may include a bit line BL and a bit line capping layer 28 located on the bit line BL. The bit line BL may include a first conductive layer 25a, a second conductive layer 25b, and a third conductive layer 25c stacked in sequence on the buffer layer 21. The first conductive layer 25a and may include polysilicon. The second conductive layer 25b may include a metal-semiconductor compound. The metal-semiconductor compound may be, for example, a layer obtained by silicideing a portion of the first conductive layer 25a. For example, the metal-semiconductor compound may include cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides, or may include nitrides, such as TiSiN. The third conductive layer 25c may include a metal material, such as titanium (Ti), tantalum (Ta), tungsten (W), and aluminum (Al). The bit line BL may further include a plug portion 25p disposed below the first conductive layer 25a and extending downward and in contact with the first impurity region 9a. The plug portion 25p may be disposed in a contact hole H formed on the upper surface of the substrate 3. In a plan view, the plug portion 25p may be in contact with a central portion of the first active region 6a. The plug portion 25p may electrically connect the first active region 6a to the bit line structure BLS. The plug portion 25p may include the same material as that of the first conductive layer 25a.

[0032] The bit line cover layer 28 may include a first cover layer 28a, a second cover layer 28b, and a third cover layer 28c stacked in sequence on the bit line BL. A side surface of the first cover layer 28a may be coplanar with the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c. The first cover layer 28a, the second cover layer 28b, and the third cover layer 28c may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0033] The spacer structure SP may be respectively disposed on both side surfaces of the bit line structure BLS and may extend in the Y direction beside the surface of the bit line structure BLS. The spacer structure SP may include a first spacer SP1, a second spacer SP2, a third spacer SP3, and a fourth spacer SP4 disposed on the side surface of the bit line structure BLS. The first spacer SP1 may be conformally disposed along the side surface of the bit line structure BLS and the side surface of the contact hole H. The second spacer SP2 may be disposed on the first spacer SP1 and may fill the contact hole H. The third spacer SP3 may cover the side surface of the first spacer SP1, and the fourth spacer SP4 may cover the side surface of the third spacer SP3. The third spacer SP3 and the fourth spacer SP4 may cover the upper surface of the second spacer SP2. The first spacer SP1, the second spacer SP2, the third spacer SP3, and the fourth spacer SP4 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the first spacer SP1 and the fourth spacer SP4 may include at least one of SiN, SiCN, SiON, and SiOCN. The third spacer SP3 may include silicon oxide.

[0034] like Figure 4 As illustrated, the spacer structure SP may further include a mixture layer SP5 disposed on the third spacer SP3 and in contact with the cell insulating pattern 72. In example embodiments, the mixture layer SP5 may include silicon oxide and silicon nitride and may be formed by nitriding a portion of the third spacer SP3. In the mixture layer SP5, silicon oxide and silicon nitride may not be spatially isolated from each other but may be mixed with each other. The mixture layer SP5 may include SiO 2 , at least one of SiN and SiON.

[0035] Figure 5B is a graph indicating the ratio of silicon nitride of the mixture layer SP5.

[0036] refer to Figure 5B In example embodiments, the ratio of silicon nitride to silicon oxide in the mixture layer SP5 may vary depending on the depth. For example, the ratio may have a maximum value at a specific depth. In example embodiments, the “depth” may refer to a distance in a direction away from the upper surface.

[0037] Return to reference Figure 3A , the contact plug 60 may be disposed between the bit line structures BLS and may be in contact with the spacer structure SP. When viewed in a plan view, the contact plug 60 may be disposed between the bit line structures BLS and between the cell gate structures GS.

[0038] The lower end of the contact plug 60 may be disposed at a height lower than the upper surface of the substrate 3, and the upper surface of the contact plug 60 may be disposed at a height lower than the upper end of the bit line structure BLS (e.g., relative to the bottom of the substrate 3). The contact plug 60 may extend into the substrate 3, may contact the second impurity region 9b of the first active region 6a, and may be electrically connected to the second impurity region 9b. The contact plug 60 may be formed of a conductive material such as polysilicon (Si), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), and aluminum (Al). In example embodiments, the contact plug 60 may include doped polysilicon and may include N-type impurities such as phosphorus (P), arsenic (Ar), and antimony (Sb).

[0039] like Figure 2 As shown, the semiconductor device 100 may further include a fence structure 63 disposed between the bit line structures BLS. In a plan view, the fence structure 63 may overlap vertically with the cell gate structure GS, and may be arranged alternately with the contact plugs 60 in the Y direction. The fence structure 63 may spatially isolate the contact plugs 60 from each other, and may electrically insulate the contact plugs 60 from each other. The fence structure 63 may be in the shape of a bar or a column extending in the vertical direction. Although not shown, the lower surface of the fence structure 63 may be in contact with the gate cap layer 18 of the cell gate structure GS. The fence structure 63 may include an insulating material, such as silicon nitride.

[0040] The semiconductor device 100 may further include a metal-semiconductor compound layer 66 disposed on the upper surface of the contact plug 60. The metal-semiconductor compound layer 66 may be in contact with the side surface of the spacer structure SP. The metal-semiconductor compound layer 66 may be formed by silicideing a portion of the contact plug 60 including polysilicon. The metal-semiconductor compound layer 66 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides.

[0041] The landing pad structure LP may be disposed on the metal-semiconductor compound layer 66. The landing pad structure LP may include a lower landing pad 70 and an upper landing pad 71. The upper landing pad 71 may be electrically connected to the lower landing pad 70, and the landing pad structure LP may be electrically connected to the second impurity region 9b of the first active region 6a through the contact plug 60. The lower landing pad 70 may include a metal nitride, such as titanium nitride (TiN).

[0042] The upper landing pad 71 may be disposed on the lower landing pad 70. In an example embodiment, the upper landing pad 71 may be in a tapered cylindrical shape. For example, the lower surface of the upper landing pad 71 may be wider than the upper surface of the upper landing pad 71, and the horizontal width of the upper landing pad 71 may decrease upward. The upper landing pad 71 may include a metal layer 71a and a metal nitride layer 71b. The metal nitride layer 71b may cover the metal layer 71a. For example, the metal nitride layer 71b may extend along the side surface and the upper surface of the metal layer 71a, and may cover the side surface and the upper surface of the metal layer 71a. The lower surface of the metal nitride layer 71b may be coplanar with the lower surface of the metal layer 71a. The metal layer 71a may include, for example, at least one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), ruthenium (Ru), and aluminum (Al). For example, the metal layer 71a may include tungsten (W). The metal nitride layer 71 b may include, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), ruthenium nitride (RuN), and aluminum nitride (AlN).

[0043] In the cell area CA, the cell insulation pattern 72 may be disposed between the landing pad structures LP. The cell insulation pattern 72 may spatially isolate the landing pad structures LP from each other, and may electrically insulate the landing pad structures LP from each other. The cell insulation pattern 72 may contact the bit line structure BLS, the spacer structure SP, the lower landing pad 70, and the upper landing pad 71. In an example embodiment, the cell insulation pattern 72 may have a step difference. For example, a portion of the lower surface of the cell insulation pattern 72 may protrude toward the lower landing pad 70 in an area where the spacer structure SP and the lower landing pad 70 contact each other. A portion of the cell insulation pattern 72 may contact the side surface of the spacer structure SP. For example, the lower surface of the cell insulation pattern 72 may include a first portion 72a in contact with the upper surface of the spacer structure SP and a second portion 72b in contact with the lower landing pad 70. The lower end of the second portion 72b may be disposed at a height lower than the lower end of the first portion 72a (e.g., relative to the bottom of the substrate 3). A side surface of the fourth spacer SP4 may be in contact with (eg, in direct contact with) both the lower landing pad 70 and the cell insulation pattern 72 .

[0044] Likewise, a portion of the side surface of the cell insulating pattern 72 may protrude toward the lower landing pad 70 in a region where the lower landing pad 70 and the upper landing pad 71 contact each other. A portion of the cell insulating pattern 72 may contact the lower surface of the upper landing pad 71. For example, the cell insulating pattern 72 may contact only the metal nitride layer 71b of the upper landing pad 71. In another example, a portion of the cell insulating pattern 72 may contact the lower surface of the metal layer 71a.

[0045] The cell insulating pattern 72 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. For example, the cell insulating pattern 72 may include silicon nitride.

[0046] In the cell area CA, the semiconductor device 100 may further include an etch stop layer 75 covering the upper surface of the cell insulation pattern 72. A capacitor structure 80 may be disposed on the landing pad structure LP and the cell insulation pattern 72. The capacitor structure 80 may include a lower electrode 82, a capacitor dielectric layer 84, and an upper electrode 86. The lower electrode 82 may penetrate the etch stop layer 75 and may contact the upper surface of the landing pad structure LP. The capacitor dielectric layer 84 may cover the lower electrode 82 and the etch stop layer 75, and the upper electrode 86 may cover the capacitor dielectric layer 84. The capacitor structure 80 may be electrically connected to the landing pad structure LP and the contact plug 60.

[0047] The lower electrode 82 and the upper electrode 86 may include, for example, at least one of a doped semiconductor, a metal nitride, a metal, and a metal oxide. The lower electrode 82 and the upper electrode 86 may include, for example, at least one of polysilicon, titanium nitride (TiN), tungsten (W), titanium (Ti), ruthenium (Ru), and tungsten nitride (WN). For example, the capacitor dielectric layer 84 may include at least one high-κ material, such as zirconium oxide (ZrO 2 ), aluminum oxide (Al 2 O 3 ) and hafnium oxide (Hf 2 O 3 ).

[0048] In the peripheral circuit area PA, the substrate 3 may further include a second device isolation layer 7, a second active region 8, a first peripheral impurity region 10, and a second peripheral impurity region 11. The second device isolation layer 7 may be an insulating layer extending downward from the upper surface of the substrate 3, and may define the second active region 8. For example, the second active region 8 may correspond to a portion of the upper surface of the substrate 3 surrounded by the second device isolation layer 7. The second active region 8 may include a first peripheral impurity region 10 and a second peripheral impurity region 11 extending from the upper surface of the substrate 3 to a predetermined depth. The first peripheral impurity regions 10 may be spaced apart from each other, and the peripheral gate structure GS_P is interposed between the first peripheral impurity regions 10. The second peripheral impurity region 11 may be disposed in the first peripheral impurity region 10.

[0049] The second device isolation layer 7 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and may include a single layer or a plurality of layers. The first peripheral impurity region 10 may include, for example, N-type impurities or P-type impurities. The second peripheral impurity region 11 may include impurities having the same conductivity as that of the first peripheral impurity region 10, and the impurity concentration of the second peripheral impurity region 11 may be greater than the impurity concentration of the first peripheral impurity region 10.

[0050] In the peripheral circuit region PA, a peripheral gate structure GS_P may be disposed on the second active region 8. The peripheral gate structure GS_P may have a structure similar to that of the bit line BL and may be formed of a material similar to that of the bit line BL, but the horizontal width of the peripheral gate structure GS_P in the X direction may be wider than the horizontal width of the bit line BL in the X direction.

[0051] The peripheral gate structure GS_P may include a peripheral gate dielectric layer 120, a first conductive layer 125a, a second conductive layer 125b, a third conductive layer 125c, and a peripheral gate capping layer 128a stacked on the substrate 3 in the stated order. The peripheral gate dielectric layer 120 may include, for example, silicon oxide, silicon nitride, or a high-κ material. The high-κ material may refer to a dielectric material having a dielectric constant higher than that of silicon oxide. The first conductive layer 125a, the second conductive layer 125b, and the third conductive layer 125c of the peripheral gate structure GS_P may include the same material as the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c of the bit line BL, respectively. The peripheral gate capping layer 128a may include the same material as the first capping layer 28a of the bit line capping layer 28.

[0052] The semiconductor device 100 may further include a peripheral gate spacer 129, a first peripheral cover layer 128b, a second peripheral cover layer 128c, and a lower interlayer insulating layer 130 in the peripheral circuit area PA. The peripheral gate spacer 129 may cover the side surface of the peripheral gate structure GS_P. For example, the peripheral gate spacers 129 may be spaced apart from each other, the peripheral gate structure GS_P is interposed between the peripheral gate spacers 129, and may cover the side surface of the first conductive layer 125a, the side surface of the second conductive layer 125b, the side surface of the third conductive layer 125c, and the side surface of the peripheral gate cover layer 128a.

[0053] The peripheral gate spacer 129 may include a first peripheral spacer 129a, a second peripheral spacer 129b, a third peripheral spacer 129c, and a mixture layer 129d. The first peripheral spacer 129a may cover the side surface of the peripheral gate structure GS_P. The second peripheral spacer 129b may cover the side surface of the first peripheral spacer 129a, and the third peripheral spacer 129c may cover the side surface of the second peripheral spacer 129b. The mixture layer 129d may be disposed on the second peripheral spacer 129b. For example, Figure 5A As shown, a portion of the first peripheral spacer 129a may extend in a horizontal direction along the upper surface of the substrate 3. In another example, the lower surfaces of the first peripheral spacer 129a, the second peripheral spacer 129b, and the third peripheral spacer 129c may be coplanar with each other. The first peripheral spacer 129a and the third peripheral spacer 129c may include, for example, silicon nitride, and the second peripheral spacer 129b may include, for example, silicon oxide.

[0054] In example embodiments, the mixture layer 129d may include silicon oxide and silicon nitride, and may be formed by nitriding a portion of the second peripheral spacer 129b. In the mixture layer 129d, silicon oxide and silicon nitride may not be spatially isolated but may be mixed with each other. The mixture layer 129d may include SiO 2 , SiN and SiON. In an exemplary embodiment, Figure 5B As illustrated, the ratio of silicon nitride to silicon oxide in the mixture layer 129d may vary depending on the depth from the upper surface of the mixture layer 129d.

[0055] The first peripheral cover layer 128b may cover the substrate 3, the peripheral gate spacer 129, and the peripheral gate structure GS_P, and may be conformally formed. The lower interlayer insulating layer 130 may partially cover the first peripheral cover layer 128b. The upper surface of the lower interlayer insulating layer 130 may be coplanar with the upper surface of the first peripheral cover layer 128b. The second peripheral cover layer 128c may cover the lower interlayer insulating layer 130 and the first peripheral cover layer 128b.

[0056] The first and second peripheral capping layers 128b and 128c may include the same materials as the second and third capping layers 28b and 28c of the bit line capping layer 28, respectively, and may include, for example, silicon nitride. The lower interlayer insulating layer 130 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0057] In the peripheral circuit region PA, a peripheral contact plug 170 may be disposed adjacent to the peripheral gate structure GS_P and may be electrically connected to the second active region 8. For example, the peripheral contact plug 170 may penetrate the second peripheral cover layer 128c, the lower interlayer insulating layer 130, and the first peripheral cover layer 128b, and may contact the second peripheral impurity region 11. The peripheral contact plug 170 may include the same material as that of the lower landing pad 70. For example, the peripheral contact plug 170 may include titanium nitride (TiN). In example embodiments, the peripheral contact plug 170 may include a void V therein.

[0058] The semiconductor device 100 may further include a metal-semiconductor compound layer 166 disposed between the peripheral contact plug 170 and the second peripheral impurity region 11. The metal-semiconductor compound layer 166 may be formed by silicideing a portion of the second active region 8. The metal-semiconductor compound layer 166 may include, for example, cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), or other metal silicides.

[0059] The peripheral interconnect layer 171 may be disposed on the peripheral contact plug 170 and may extend in a horizontal direction. The peripheral interconnect layer 171 may include a metal layer 171a and a metal nitride layer 171b located on the metal layer 171a. The metal nitride layer 171b may cover the metal layer 171a. For example, the metal nitride layer 171b may extend along the side surface and the upper surface of the metal layer 171a (e.g., longitudinally) and may cover the side surface and the upper surface of the metal layer 171a. The lower surface of the metal nitride layer 171b may be coplanar with the lower surface of the metal layer 171a. The metal layer 171a may include, for example, at least one of titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), ruthenium (Ru), and aluminum (Al). For example, the metal layer 171a may include tungsten (W). The metal nitride layer 171 b may include, for example, at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), molybdenum nitride (MoN), ruthenium nitride (RuN), and aluminum nitride (AlN).

[0060] The peripheral insulation structure IS may penetrate the peripheral interconnection layer 171 and may extend in a vertical direction (e.g., longitudinally). The peripheral insulation structure IS may spatially isolate the peripheral interconnection layers 171 from each other and electrically insulate the peripheral interconnection layers 171. In example embodiments, the peripheral insulation structure IS may include a first peripheral insulation structure IS1, a second peripheral insulation structure IS2, and a third peripheral insulation structure IS3. The first peripheral insulation structure IS1 may be disposed adjacent to the peripheral contact plug 170 and may include a mixture layer ISa, a first peripheral insulation layer ISb, and a second peripheral insulation layer ISc. The lower end (e.g., the lowermost end) of the first peripheral insulation structure IS1 may be disposed at a height lower than the upper surface (e.g., the uppermost surface) of the peripheral gate structure GS_P (e.g., relative to the bottom of the substrate 3). In example embodiments, the lower end of the first peripheral insulation structure IS1 may be disposed at a height lower than the upper end of the gap V of the peripheral contact plug 170. The mixture layer ISa may be formed by nitriding a portion of the lower interlayer insulation layer 130. The mixture layer ISa may extend along the lower surface and side surface of the first peripheral insulation layer ISb. The first peripheral insulating layer ISb may be disposed on the mixture layer ISa, and the upper surface of the first peripheral insulating layer ISb may include a concave curved surface. The second peripheral insulating layer ISc may be disposed on the first peripheral insulating layer ISb and may penetrate the peripheral interconnect layer 171 and the second peripheral cover layer 128c. The upper surface of the second peripheral insulating layer ISc may be coplanar with the upper surface of the peripheral interconnect layer 171.

[0061] In example embodiments, the mixture layer ISa may include silicon oxide and silicon nitride, and in the mixture layer ISa, the silicon oxide and the silicon nitride may not be spatially isolated from each other but may be mixed with each other. 2 , SiN and SiON. In an exemplary embodiment, Figure 5B As shown, the ratio of silicon nitride to silicon oxide in the mixture layer ISa may vary depending on the depth from the upper surface of the mixture layer ISa. The first peripheral insulating layer ISb may include, for example, SiO 2 , SiN, SiON, SiBN, SiCN, ZnO, HfO 2 In example embodiments, the first peripheral insulating layer ISb may include SiO 2 And may include hydrogen ions (H+).

[0062] In example embodiments, the second peripheral insulating structure IS2 may extend in a vertical direction and may penetrate the peripheral gate spacer 129. The second peripheral insulating structure IS2 may include a mixture layer ISa, a first peripheral insulating layer ISb, and a second peripheral insulating layer ISc stacked in sequence. The mixture layer ISa may be disposed between the first peripheral insulating layer ISb and the lower interlayer insulating layer 130. The first peripheral insulating layer ISb may penetrate the peripheral gate spacer 129 and may contact the mixture layer 129d of the peripheral gate spacer 129.

[0063] In example embodiments, the third peripheral insulating structure IS3 may extend in a vertical direction and may partially penetrate the peripheral gate capping layer 128a. The third peripheral insulating structure IS3 may not include the mixture layer ISa but may include the first peripheral insulating layer ISb and the second peripheral insulating layer ISc.

[0064] Among the peripheral insulation structures IS in example embodiments, the first peripheral insulation structure IS1 may have the largest horizontal width (eg, in the X direction) and the largest depth (eg, in the Z direction). The third peripheral insulation structure IS3 may have the smallest horizontal width and the smallest depth.

[0065] The upper end of each first peripheral insulating layer ISb included in the first peripheral insulating structure IS1, the second peripheral insulating structure IS2, and the third peripheral insulating structure IS3 may be disposed at a height lower than the second peripheral cover layer 128c (e.g., relative to the bottom of the substrate 3). However, in example embodiments, the upper end of the first peripheral insulating layer ISb may be lower than the lower surface of the peripheral interconnection layer 171, and the first peripheral insulating layer ISb may be spaced apart from the peripheral interconnection layer 171 (e.g., vertically spaced apart) and may not contact the peripheral interconnection layer 171.

[0066] The semiconductor device 100 may further include a peripheral etch stop layer 175, an upper interlayer insulating layer 180, and a peripheral contact structure MC disposed on the peripheral interconnect layer 171 in the peripheral circuit region PA. The peripheral etch stop layer 175 may cover the peripheral insulation structure IS and the peripheral interconnect layer 171. The upper interlayer insulating layer 180 may cover the peripheral etch stop layer 175. The peripheral contact structure MC may penetrate the upper interlayer insulating layer 180 and the peripheral etch stop layer 175, and may be electrically connected to at least one peripheral interconnect layer 171.

[0067] like Figure 3B and Figure 5AAs illustrated, the peripheral insulation structure IS according to example embodiments may include a mixture layer ISa and a first peripheral insulation layer ISb, so that the peripheral insulation structure IS may protect the lower interlayer insulation layer 130 in a process of etching the upper landing pad 71. Therefore, the lower interlayer insulation layer 130 may be prevented from being excessively etched, and defects of the semiconductor device 100 may be prevented or significantly reduced.

[0068] Figures 6 to 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments. Figures 6 to 8 Corresponding to along Figure 1 Section along line III-III'.

[0069] refer to Figure 6 , the semiconductor device 200 may include a first peripheral insulation structure IS1, a second peripheral insulation structure IS2, and a third peripheral insulation structure IS3 penetrating the peripheral interconnection layer 171. In example embodiments, an upper end of a first peripheral insulation layer ISb included in each of the first peripheral insulation structure IS1, the second peripheral insulation structure IS2, and the third peripheral insulation structure IS3 may be disposed at a height higher than an upper surface of the lower interlayer insulation layer 130, and may be disposed at a height lower than a lower surface of the peripheral interconnection layer 171. The first peripheral insulation layer ISb may partially contact the second peripheral cover layer 128c.

[0070] refer to Figure 7 , the semiconductor device 300 may include a first peripheral insulation structure IS1, a second peripheral insulation structure IS2, and a third peripheral insulation structure IS3 that penetrate the peripheral interconnect layer 171. In example embodiments, the upper end of the first peripheral insulation layer ISb included in each of the first peripheral insulation structure IS1 and the second peripheral insulation structure IS2 may be set at a height lower than the upper surface of the lower interlayer insulation layer 130. The second peripheral insulation layer ISc included in each of the first peripheral insulation structure IS1 and the second peripheral insulation structure IS2 may be partially in contact with the mixture layer ISa. In example embodiments, the third peripheral insulation structure IS3 may include a single-layer second peripheral insulation layer ISc (e.g., without the first peripheral insulation layer ISb). The second peripheral insulation layer ISc in the third peripheral insulation structure IS3 may extend in a vertical direction from the upper surface of the peripheral interconnect layer 171 and may be in contact with the peripheral gate structure GS_P. The second peripheral insulation layer ISc may include the same material as that of the second peripheral insulation structure IS2.

[0071] refer to Figure 8, the semiconductor device 400 may include a first peripheral insulation structure IS1, a second peripheral insulation structure IS2, and a third peripheral insulation structure IS3 that penetrate the peripheral interconnect layer 171. In example embodiments, an upper end of the first peripheral insulation layer ISb included in the first peripheral insulation structure IS1 may be disposed at a lower height (e.g., relative to the bottom of the substrate 3) than upper ends of the first peripheral insulation layer ISb included in the second peripheral insulation structure IS2 and the third peripheral insulation structure IS3. An upper end of the first peripheral insulation layer ISb included in the third peripheral insulation structure IS3 may be disposed at a higher height than upper ends of the first peripheral insulation layer ISb included in the first peripheral insulation structure IS1 and the second peripheral insulation structure IS2. In the following reference Fig.18A and Fig.18B In the etching process described above, since the etchant can further flow into the first opening OP1 having a relatively large horizontal width, the first peripheral insulating layer ISb can be further etched. Figure 8 As illustrated, an upper end of a first peripheral insulating layer ISb included in the first peripheral insulating structure IS1 may be disposed at a height lower than an upper end of another first peripheral insulating layer ISb.

[0072] Fig.9A and Fig. 9B is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0073] refer to Fig.9A and Fig. 9B , the semiconductor device 500 may include a landing pad structure LP disposed on the contact plug 60 in the cell area CA. The landing pad structure LP may include a lower landing pad 70 and an upper landing pad 71. In example embodiments, the lower landing pad 70 and the upper landing pad 71 may include the same material and may be integrally formed, for example, integrated with each other as a single unit. The portion of the landing pad structure LP disposed below the bit line structure BLS may be referred to as the lower landing pad 70, and the portion of the landing pad structure LP disposed above the bit line structure BLS may be referred to as the upper landing pad 71. Since the lower landing pad 70 and the upper landing pad 71 include the same material, they may be referred to below. Fig.19A In the etching process described above, the lower landing pad 70 and the upper landing pad 71 are etched at the same time. Therefore, the side surface of the lower landing pad 70 and the side surface of the upper landing pad 71 can be coplanar with each other, and no step difference occurs between the side surfaces of the cell insulation pattern 72. Fig.19A The upper landing pad 71 is also etched in the etching process in FIG. 1 , so a portion of an upper surface and a portion of a side surface of the upper landing pad 71 may include a curved surface. In example embodiments, the lower landing pad 70 and the upper landing pad 71 may include titanium nitride (TiN).

[0074] In the peripheral circuit region PA, the semiconductor device 100 may include a peripheral contact plug 170 penetrating the lower interlayer insulating layer 130 and a peripheral interconnection layer 171 located on the peripheral contact plug 170. In example embodiments, the peripheral contact plug 170 may include the same material as that of the peripheral interconnection layer 171 and may be integrally formed. In example embodiments, the peripheral contact plug 170 and the peripheral interconnection layer 171 may include titanium nitride (TiN).

[0075] FIG. 10A to FIG. 20B is a cross-sectional view illustrating various stages in a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A and Fig. 20A The unit area CA is shown in FIG. Figure 3A The corresponding vertical cross-section. Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B and Fig. 20B The peripheral circuit area PA is shown in FIG. Figure 3B The corresponding vertical cross-section.

[0076] refer to Fig. 10A and Fig. 10B , a first device isolation layer 6s and a cell gate structure GS may be formed in the substrate 3 in the cell area CA. The first device isolation layer 6s may be formed by performing the following planarization process: forming a groove on the upper surface of the substrate 3, filling the groove with an insulating material, and etching the substrate 3 and the insulating material. The first device isolation layer 6s may define a first active region 6a. For example, the first active region 6a may correspond to a portion of the upper surface of the substrate 3 surrounded by the first device isolation layer 6s. In a plan view, the first active region 6a may be in the shape of a strip having a short axis and a long axis, and may be spaced apart from each other. The first device isolation layer 6s may be configured as a single layer or multiple layers.

[0077] In example embodiments, the first and second impurity regions 9a and 9b may be formed by implanting impurities into the substrate 3 before forming the first device isolation layer 6s. However, in example embodiments, the first and second impurity regions 9a and 9b may be formed after forming the first device isolation layer 6s or in another process.

[0078] Thereafter, the gate trench 12 may be formed by anisotropically etching the substrate 3. The gate trench 12 may extend in the X direction and may intersect the first active region 6a and the first device isolation layer 6s. The cell gate structure GS may be formed by forming a cell gate dielectric layer 14, a gate electrode 16, and a gate capping layer 18 in the gate trench 12. The cell gate dielectric layer 14 may be conformally formed on the inner wall of the gate trench 12. The gate electrode 16 may be formed by forming a conductive material on the cell gate dielectric layer 14 and recessing the conductive material. The gate capping layer 18 may be formed by forming an insulating material on the gate electrode 16 to fill the gate trench 12 and performing a planarization process. In example embodiments, as shown in FIG. Fig. 10A As illustrated, the gate trench 12 may be formed to have a greater depth in the first device isolation layer 6 s than in the first active region 6 a .

[0079] In the peripheral circuit area PA, a second device isolation layer 7 may be formed in the substrate 3. In example embodiments, the second device isolation layer 7 may be formed simultaneously with the first device isolation layer 6s. The second device isolation layer 7 may define a second active region 8. For example, the second active region 8 may correspond to a portion of the upper surface of the substrate 3 surrounded by the second device isolation layer 7.

[0080] refer to Fig.11A and Fig. 11B , a buffer layer 21, a bit line structure BLS, and a spacer structure SP may be formed on the substrate 3 in the cell region CA. The buffer layer 21 may be formed on the upper surface of the substrate 3, the upper surface of the first active region 6a, the upper surface of the first device isolation layer 6s, and the upper surface of the cell gate structure GS. The buffer layer 21 may be configured as a single layer or a plurality of layers.

[0081] The bit line structure BLS may be formed on the buffer layer 21. The bit line structure BLS may be formed by etching the buffer layer 21 to expose the first active region 6a to form a contact hole H, stacking a conductive material layer on the contact hole H, forming an insulating material layer on the conductive material layer, and patterning the conductive material layer and the insulating material layer. For example, the conductive material layer and the insulating material layer may be patterned to form grooves extending in the Y direction and spaced apart from each other in the X direction. The upper surface of the first active region 6a may be partially exposed due to the patterning process. The bit line structure BLS may extend in the Y direction and may be spaced apart from each other in the X direction.

[0082] The bit line structure BLS may include a bit line BL having a conductive material and a bit line capping layer 28 having an insulating material. The bit line BL may include a first conductive layer 25a, a second conductive layer 25b, and a third conductive layer 25c stacked in sequence, and the bit line BL may include a plug portion 25p disposed in the contact hole H. The bit line capping layer 28 may include a first capping layer 28a, a second capping layer 28b, and a third capping layer 28c stacked in sequence.

[0083] The spacer structure SP may be formed on both side surfaces of the bit line structure BLS. The spacer structure SP may include a first spacer SP1, a second spacer SP2, a third spacer SP3, and a fourth spacer SP4. The first spacer SP1 may be formed by conformally depositing an insulating material along the side surface of the bit line structure BLS and the inner wall of the contact hole H. The second spacer SP2 may be formed by depositing an insulating material on the first spacer SP1 to fill the contact hole H. The third spacer SP3 may be formed by forming an insulating material to cover the side surface of the second spacer SP2 and etching the insulating material, and the fourth spacer SP4 may be formed by forming an insulating material to cover the side surface of the third spacer SP3 and etching the insulating material. The spacer structure SP may extend in the Y direction along the side surface of the bit line structure BLS.

[0084] After the spacer structure SP is formed, a process of etching the buffer layer 21 may be performed to expose the upper surface of the first active region 6a. The space between the bit line structures BLS may be referred to as a trench T. For example, the trench T may be defined by side surfaces of adjacent spacer structures SP facing each other and may extend in the Y direction.

[0085] A peripheral gate structure GS_P, a first peripheral cover layer 128 b , a second peripheral cover layer 128 c , a peripheral gate spacer 129 , and a lower interlayer insulating layer 130 may be formed on the substrate 3 in the peripheral circuit region PA.

[0086] The peripheral gate structure GS_P may include a peripheral gate dielectric layer 120, a first conductive layer 125a, a second conductive layer 125b, a third conductive layer 125c, and a peripheral gate capping layer 128a stacked in order. The peripheral gate structure GS_P may be formed by forming a dielectric material on a substrate 3, stacking a conductive material and an insulating material on the dielectric material, and patterning the dielectric material, the conductive material, and the insulating material. In an example embodiment, the first conductive layer 125a, the second conductive layer 125b, and the third conductive layer 125c of the peripheral gate structure GS_P may be formed in the same process as the process of forming the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c of the bit line BL. The first conductive layer 125a, the second conductive layer 125b, and the third conductive layer 125c of the peripheral gate structure GS_P may include the same materials as the first conductive layer 25a, the second conductive layer 25b, and the third conductive layer 25c of the bit line BL, respectively. In example embodiments, the peripheral gate capping layer 128 a of the peripheral gate structure GS_P may be formed in the same process as that of forming the first capping layer 28 a of the bit line capping layer 28 .

[0087] After the peripheral gate structure GS_P is formed, a peripheral gate spacer 129 covering the side surface of the peripheral gate structure GS_P may be formed. The peripheral gate spacer 129 may be formed by forming an insulating material to cover the peripheral gate structure GS_P and anisotropically etching the insulating material. The peripheral gate spacer 129 may be composed of a single layer or a plurality of layers. In an example embodiment, the peripheral gate spacer 129 may include a first peripheral spacer 129a, a second peripheral spacer 129b, and a third peripheral spacer 129c. The first peripheral spacer 129a, the second peripheral spacer 129b, and the third peripheral spacer 129c may be formed by conformally stacking insulating materials in sequence along the substrate 3 and the peripheral gate structure GS_P and etching the insulating materials.

[0088] After the peripheral gate structure GS_P is formed, a first peripheral impurity region 10 may be formed in the substrate 3 using the peripheral gate structure GS_P as an ion implantation mask.

[0089] The first peripheral cover layer 128b may be conformally formed along the surface of the substrate 3, the surface of the second device isolation layer 7, the surface of the peripheral gate structure GS_P, and the surface of the peripheral gate spacer 129. The lower interlayer insulating layer 130 may be formed by forming an insulating material to cover the first peripheral cover layer 128b and performing a planarization process to expose the upper surface of the first peripheral cover layer 128b. The second peripheral cover layer 128c may be formed to cover the upper surface of the first peripheral cover layer 128b and the upper surface of the lower interlayer insulating layer 130. In example embodiments, the first peripheral cover layer 128b and the second peripheral cover layer 128c may be formed simultaneously with the second cover layer 28b and the third cover layer 28c of the bit line cover layer 28, respectively.

[0090] refer to Fig. 12A and Fig. 12B , the contact plug 60 may be formed in the trench T in the cell area CA. The contact plug 60 may be formed by filling the trench T with a conductive material to cover the spacer structure SP and etching back the conductive material. The upper surface of the contact plug 60 may be set at a height lower than the upper end of the bit line structure BLS. The contact plug 60 may contact the upper surface of the first active region 6a and may partially fill the space between the spacer structures SP. Thereafter, a portion of the spacer structure SP may be etched by an etching process. For example, the upper portions of the first spacer SP1, the third spacer SP3, and the fourth spacer SP4 may be partially removed. The contact plug 60 may be electrically connected to the first active region 6a, for example, the second impurity region 9b.

[0091] In example embodiments, after the contact plug 60 is formed, a Figure 2 The illustrated fence structure 63. The fence structure 63 may be formed by removing a portion of the contact plug 60 and filling the space from which the portion of the contact plug 60 is removed with an insulating material. The fence structure 63 may be formed to overlap with the cell gate structure GS in a vertical direction between the bit line structures BLS. The fence structures 63 may be spaced apart from each other in the X direction and the Y direction. For example, the contact plugs 60 may be alternately arranged with the fence structures 63 in the Y direction between the bit line structures BLS. In some example embodiments, the process of forming the fence structure 63 may be performed before the process of forming the contact plug 60.

[0092] A peripheral contact hole PH may be formed in the peripheral circuit region PA by anisotropically etching the second peripheral cover layer 128c, the lower interlayer insulating layer 130, and the first peripheral cover layer 128b. The peripheral contact hole PH may be formed adjacent to the peripheral gate structure GS_P, and may expose the upper surface of the first peripheral impurity region 10. Since the lower interlayer insulating layer 130 may include a material different from that of the first peripheral cover layer 128b and the second peripheral cover layer 128c, the lower interlayer insulating layer 130 may have an etching selectivity with the first peripheral cover layer 128b and the second peripheral cover layer 128c. In example embodiments, the lower interlayer insulating layer 130 may be further etched by an etching process compared to the first peripheral cover layer 128b and the second peripheral cover layer 128c, and the peripheral contact hole PH may have a relatively large horizontal width in the lower interlayer insulating layer 130.

[0093] refer to Fig.13A and Fig. 13B , a lower landing pad 70 may be formed in the cell area CA. The lower landing pad 70 may be formed by forming a metal material to cover the bit line structure BLS and the spacer structure SP and planarizing the metal material. In example embodiments, the metal material may be formed by a deposition process such as a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, and an atomic layer deposition (ALD) method.

[0094] In example embodiments, a metal-semiconductor compound layer 66 may be formed between the contact plug 60 and the lower landing pad 70. The metal-semiconductor compound layer 66 may be formed by silicideing a portion of the contact plug 60.

[0095] In the peripheral circuit region PA, a second peripheral impurity region 11, a metal-semiconductor compound layer 166, and a peripheral contact plug 170 may be formed. The second peripheral impurity region 11 may be formed on the upper surface of the second active region 8 exposed by the peripheral contact hole PH using an ion implantation process. The metal-semiconductor compound layer 166 may be formed by silicideing a portion of the second active region 8. The peripheral contact plug 170 may be formed by forming a metal material to fill the peripheral contact hole PH on the metal-semiconductor compound layer 166 and planarizing the metal material. For example, a void V may be formed in the peripheral contact plug 170. In another example, the peripheral contact plug 170 may not include the void V. The peripheral contact plug 170 may be electrically connected to the impurity region. In example embodiments, the peripheral contact plug 170 may be formed simultaneously with the lower landing pad 70. For example, the peripheral contact plug 170 may include the same material as the material of the lower landing pad 70.

[0096] refer to Fig.14A and Fig. 14B , a preliminary upper landing pad 71p may be formed on the lower landing pad 70 in the cell area CA. The preliminary upper landing pad 71p may cover an upper surface of the bit line structure BLS, an upper surface of the spacer structure SP, and an upper surface of the lower landing pad 70. In example embodiments, the preliminary upper landing pad 71p may include a material different from that of the lower landing pad 70. For example, the lower landing pad 70 may include titanium nitride, and the preliminary upper landing pad 71p may include tungsten.

[0097] A preliminary peripheral interconnection layer 171p may be formed on the peripheral contact plug 170 in the peripheral circuit area PA. The preliminary peripheral interconnection layer 171p may cover the upper surface of the second peripheral cover layer 128c and the upper surface of the peripheral contact plug 170. In example embodiments, the preliminary peripheral interconnection layer 171p may be formed simultaneously with the preliminary upper landing pad 71p. For example, the preliminary peripheral interconnection layer 171p may include the same material as that of the preliminary upper landing pad 71p.

[0098] refer to Fig.15A and Fig. 15B , the lower landing pad 70 and the preliminary upper landing pad 71p in the cell area CA may be patterned by an etching process. A portion of the bit line structure BLS and a portion of the spacer structure SP may be etched by an etching process. The etched preliminary upper landing pads 71p may be spaced apart from each other.

[0099] In the peripheral circuit area PA, the preliminary peripheral interconnect layer 171p may be patterned by an etching process. In example embodiments, a first opening OP1, a second opening OP2, and a third opening OP3 may be formed by an etching process. The first opening OP1 may penetrate the preliminary peripheral interconnect layer 171p and the second peripheral cover layer 128c, and may expose the lower interlayer insulating layer 130. The second opening OP2 may penetrate the preliminary peripheral interconnect layer 171p and the second peripheral cover layer 128c, and may expose the first peripheral cover layer 128b and the peripheral gate spacer 129. The third opening OP3 may penetrate the preliminary peripheral interconnect layer 171p and the second peripheral cover layer 128c, and may expose the first peripheral cover layer 128b and the peripheral gate cover layer 128a.

[0100] In example embodiments, the horizontal widths and depths of the first opening OP1, the second opening OP2, and the third opening OP3 may be different from each other. For example, the first opening OP1 having the largest width may be formed to be the deepest, and the third opening OP3 having the smallest width may be formed to be the shallowest. In a plan view, the first opening OP1, the second opening OP2, and the third opening OP3 may be in a line-and-space shape.

[0101] refer to Fig.16A and Fig. 16B , a nitridation process may be performed. The nitridation process may include supplying NH 3 Gas. In example embodiments, in the cell area CA, the upper landing pad 71 may be formed by partially nitriding the surface of the preliminary upper landing pad 71p. The upper landing pad 71 may include a metal layer 71a and a metal nitride layer 71b. The metal layer 71a may include tungsten (W), and the metal nitride layer 71b may include tungsten nitride (WN). Although not shown, as shown in FIG. Figure 4 As described, a portion of the second spacer SP2 of the spacer structure SP may be nitrided.

[0102] In the peripheral circuit area PA, a portion of the lower interlayer insulating layer 130 may be nitrided. For example, the mixture layer ISa may be formed by nitriding a portion of the lower interlayer insulating layer 130 exposed by the first opening OP1 and the second opening OP2. Likewise, the mixture layer 129d may be formed by nitriding a portion of the peripheral gate spacer 129 exposed by the second opening OP2. In the mixture layer ISa formed on the lower interlayer insulating layer 130 and the mixture layer 129d formed on the peripheral gate spacer 129, silicon oxide and silicon nitride may be mixed.

[0103] In the peripheral circuit area PA, the peripheral interconnection layer 171 may be formed by partially nitriding the preliminary peripheral interconnection layer 171p. For example, a portion of the preliminary peripheral interconnection layer 171p exposed by the first opening OP1, the second opening OP2, and the third opening OP3 and a surface of the preliminary peripheral interconnection layer 171p may be partially nitrided. The peripheral interconnection layer 171 may include a metal layer 171a and a metal nitride layer 171b. The metal layer 171a may include tungsten (W), and the metal nitride layer 171b may include tungsten nitride (WN).

[0104] refer to Fig.17A and Fig. 17B , an insulating layer 172 may be formed in the cell area CA and the peripheral circuit area PA. In the cell area CA, the insulating layer 172 may fill the space between the lower landing pad 70 and the upper landing pad 71. In the peripheral circuit area PA, the insulating layer 172 may fill the first opening OP1, the second opening OP2, and the third opening OP3. After the insulating layer 172 is formed, the upper surface of the upper landing pad 71 and the upper surface of the peripheral interconnect layer 171 may be exposed by a planarization process or an etching process.

[0105] refer to Fig.18A and Fig.18B, in the cell area CA, the insulating layer 172 may be completely removed by an etching process, and the bit line structure BLS, the spacer structure SP, and the lower landing pad 70 may be exposed.

[0106] In the peripheral circuit area PA, the insulating layer 172 may be etched by an etching process, but may not be completely removed but may be retained, thereby forming a first peripheral insulating layer ISb. The first peripheral insulating layer ISb may partially fill the first opening OP1, the second opening OP2, and the third opening OP3. For example, in the example in the figure, the upper ends of the first peripheral insulating layer ISb formed on the first opening OP1, the second opening OP2, and the third opening OP3 may be set at the same height. In another example, the etchant may further flow into the first opening OP1 having a relatively wide horizontal width, and the height of the first peripheral insulating layer ISb formed in the first opening OP1 may be relatively low.

[0107] refer to Fig.19A and Fig.19B , the lower landing pad 70 may be etched in the cell region CA. In example embodiments, the etching of the lower landing pad 70 may include a cleaning process. The cleaning process may include providing NF 3 Gas. The lower landing pad 70 can be selectively etched by the cleaning process. Fig.15A In the described etching process, even if the lower landing pad 70 is not sufficiently etched, the lower landing pad 70 can be etched by the cleaning process so that the lower landing pads 70 can be connected to each other, thereby preventing electrical short circuits. Therefore, process dispersion in the process of manufacturing the semiconductor device 100 can be reduced, and defects of the semiconductor device 100 can be prevented and reduced.

[0108] In the peripheral circuit region PA, even if the cleaning process is performed, the lower interlayer insulating layer 130 is not etched because the first peripheral insulating layer ISb formed along the first, second, and third openings OP1, OP2, and OP3 can protect the lower interlayer insulating layer 130.

[0109] refer to Fig. 20A and Fig. 20B , a cell insulating pattern 72 may be formed between the lower landing pad 70 and the upper landing pad 71 in the cell area CA. The cell insulating pattern 72 may be formed by forming an insulating material to cover the lower landing pad 70 and etching the insulating material to expose the upper landing pad 71. The cell insulating pattern 72 may electrically insulate the adjacent lower and upper landing pads 70 and 71 from each other.

[0110] In the peripheral circuit area PA, a second peripheral insulating layer ISc may be formed on the first peripheral insulating layer ISb. The second peripheral insulating layer ISc may be formed simultaneously with the cell insulation pattern 72. For example, the second peripheral insulating layer ISc may be formed by forming an insulating material to cover the first peripheral insulating layer ISb and the peripheral interconnect layer 171 and etching the insulating material to expose the peripheral interconnect layer 171. The first peripheral insulating layer ISb, the second peripheral insulating layer ISc, and the mixture layer ISa covering the lower surface of the first peripheral insulating layer ISb formed in the first opening OP1 may form a first peripheral insulation structure IS1. The mixture layer ISa, the first peripheral insulating layer ISb, and the second peripheral insulating layer ISc disposed at a position corresponding to the second opening OP2 may form a second peripheral insulation structure IS2. The first peripheral insulating layer ISb and the second peripheral insulating layer ISc disposed at a position corresponding to the third opening OP3 may form a third peripheral insulation structure IS3.

[0111] Reference again Figure 3A and Figure 3B , an etch stop layer 75 and a capacitor structure 80 may be formed on the cell insulation pattern 72 and the upper landing pad 71 in the cell region CA. The etch stop layer 75 may be formed to cover the cell insulation pattern 72 and the upper landing pad 71, and the lower electrode 82 may penetrate the etch stop layer 75 and may contact the upper landing pad 71. A capacitor dielectric layer 84 may be formed on the etch stop layer 75 and the lower electrode 82, and an upper electrode 86 may be formed on the capacitor dielectric layer 84. The lower electrode 82, the capacitor dielectric layer 84, and the upper electrode 86 may form a capacitor structure 80.

[0112] In the peripheral circuit area PA, a peripheral etch stop layer 175, an upper interlayer insulating layer 180, and a peripheral contact structure MC may be formed to complete the manufacture of the semiconductor device 100. The peripheral etch stop layer 175 may be formed to cover the peripheral interconnect layer 171 and the peripheral insulating structure IS. The upper interlayer insulating layer 180 may be formed on the peripheral etch stop layer 175. The peripheral contact structure MC may be formed to penetrate the peripheral etch stop layer 175 and the upper interlayer insulating layer 180 and to contact the peripheral interconnect layer 171.

[0113] Fig.21 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0114] refer to Fig.21 , the semiconductor device 600 may include a peripheral contact plug 170 disposed adjacent to the peripheral gate structure GS_P and electrically connected to the first peripheral impurity region 10 and the second peripheral impurity region 11. In example embodiments, Figure 3BUnlike the illustrated semiconductor device 100 , the peripheral contact plug 170 may not include the void V. The peripheral contact plug 170 may be completely filled with a conductive material, such as titanium nitride (TiN).

[0115] By way of summary and review, the exemplary embodiments provide a semiconductor device including a peripheral insulation structure penetrating a peripheral interconnect layer. That is, according to the aforementioned exemplary embodiments, the peripheral insulation structure may be formed on a lower interlayer insulation layer, and may include a mixture layer, a first peripheral insulation layer, and a second peripheral insulation layer. Therefore, the lower interlayer insulation layer may be prevented from being over-etched, and defects of the semiconductor device may be prevented or significantly reduced.

[0116] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only, and not for purposes of limitation. In some cases, as will be clear to one of ordinary skill in the art from the time of filing this application, unless otherwise specifically indicated, features, characteristics, and / or elements described with respect to a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described with respect to other embodiments. Therefore, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: A substrate, the substrate comprising a cell region and a peripheral circuit region; A bit line structure, the bit line structure is located on the cell region; a contact plug, the contact plug being located between the bit line structures; a landing pad structure, the landing pad structure being located on the contact plug; A peripheral gate structure, the peripheral gate structure is located on the peripheral circuit area; a lower interlayer insulating layer, the lower interlayer insulating layer covering a side surface of the peripheral gate structure; a peripheral contact plug penetrating the lower interlayer insulating layer; a plurality of peripheral interconnect layers, the plurality of peripheral interconnect layers being located on the lower interlayer insulating layer and the peripheral contact plugs; as well as a plurality of peripheral insulating structures passing between the plurality of peripheral interconnect layers, wherein the plurality of peripheral insulating structures include a first peripheral insulating structure partially penetrating the lower interlayer insulating layer, and The first peripheral insulating structure includes a first peripheral insulating layer, a second peripheral insulating layer located on the first peripheral insulating layer and passing between the plurality of peripheral interconnection layers, and a mixture layer located between the lower interlayer insulating layer and the first peripheral insulating layer.

2. The semiconductor device according to claim 1, wherein The lower interlayer insulating layer and the first peripheral insulating layer include silicon oxide, and the second peripheral insulating layer includes silicon nitride.

3. The semiconductor device according to claim 1, wherein: The mixture layer of the first peripheral insulating structure includes silicon oxide and silicon nitride, and A ratio of silicon nitride to silicon oxide in the mixture layer of the first peripheral insulating structure varies depending on a depth from an upper surface of the mixture layer.

4. The semiconductor device according to claim 1, wherein: A lower end of the first peripheral insulating structure is located at a height lower than an upper surface of the peripheral gate structure.

5. The semiconductor device according to claim 1, wherein: Each of the plurality of peripheral interconnect layers includes a metal layer and a metal nitride layer, and The metal nitride layer covers the metal layer and extends along an upper surface and a side surface of the metal layer. 6 . The semiconductor device according to claim 1 , further comprising a peripheral gate spacer covering a side surface of the peripheral gate structure, the plurality of peripheral insulating structures comprising a second peripheral insulating structure partially penetrating the peripheral gate spacer.

7. The semiconductor device according to claim 6, wherein: The second peripheral insulating structure includes a first peripheral insulating layer, a second peripheral insulating layer located on the first peripheral insulating layer and passing between the plurality of peripheral interconnection layers, and a mixture layer located between the lower interlayer insulating layer and the first peripheral insulating layer.

8. The semiconductor device according to claim 6, wherein: The depth of the first peripheral insulating structure is greater than the depth of the second peripheral insulating structure, and An upper end of the first peripheral insulation layer of the first peripheral insulation structure is located at a height lower than an upper end of the first peripheral insulation layer of the second peripheral insulation structure.

9. The semiconductor device according to claim 6, wherein: The peripheral gate spacer includes a mixture layer contacting the second peripheral insulating structure.

10. The semiconductor device according to claim 9, wherein: The mixture layer of the peripheral gate spacer includes silicon oxide and silicon nitride, and A ratio of silicon nitride to silicon oxide in the mixture layer of the peripheral gate spacer varies depending on a depth from an upper surface of the mixture layer.

11. The semiconductor device according to claim 1, wherein: The plurality of peripheral insulating structures include a third peripheral insulating structure partially penetrating the peripheral gate structure, and The third peripheral insulating structure includes a first peripheral insulating layer contacting the peripheral gate structure and a second peripheral insulating layer on the first peripheral insulating layer and including a material different from that of the first peripheral insulating layer.

12. The semiconductor device according to claim 1, wherein: The peripheral contact plug includes a void, and A lower end of the first peripheral insulating structure is located at a height lower than an upper end of the gap.

13. The semiconductor device according to claim 1, further comprising a peripheral cover layer between the lower interlayer insulating layer and at least one of the plurality of peripheral interconnect layers, the peripheral cover layer comprising a material different from that of the lower interlayer insulating layer.

14. The semiconductor device according to claim 1, wherein The peripheral contact plug includes a same material as that of at least one peripheral interconnection layer among the plurality of peripheral interconnection layers and is integrated with the at least one peripheral interconnection layer among the plurality of peripheral interconnection layers.

15. A semiconductor device, comprising: A substrate, the substrate comprising a cell region and a peripheral circuit region; A bit line structure, the bit line structure is located on the cell region; a first contact plug and a second contact plug, the first contact plug and the second contact plug being located between the bit line structures and spaced apart from each other; a spacer structure located on a side surface of one of the bit line structures and in contact with the second contact plug; a first landing pad structure located on the first contact plug and comprising a first lower landing pad and a first upper landing pad located on the first lower landing pad; a second landing pad structure located on the second contact plug and comprising a second lower landing pad and a second upper landing pad located on the second lower landing pad; a unit insulation pattern, wherein the unit insulation pattern is located between the first landing pad structure and the second landing pad structure; A peripheral gate structure, the peripheral gate structure is located on the peripheral circuit area; a lower interlayer insulating layer, the lower interlayer insulating layer covering a side surface of the peripheral gate structure; a peripheral contact plug penetrating the lower interlayer insulating layer; a plurality of peripheral interconnect layers, the plurality of peripheral interconnect layers being located on the lower interlayer insulating layer and the peripheral contact plugs; a plurality of peripheral insulating structures passing between the plurality of peripheral interconnect layers and partially penetrating the lower interlayer insulating layer, wherein a lower surface of the unit insulation pattern includes a first portion contacting an upper surface of the spacer structure and a second portion contacting the second lower landing pad, and Wherein, a lower end of the second portion of the unit insulating pattern is disposed at a height lower than a lower end of the first portion of the unit insulating pattern.

16. The semiconductor device according to claim 15, wherein: A side surface of the cell insulation pattern protrudes toward the second lower landing pad in a region where the second lower landing pad and the second upper landing pad contact each other, and The cell insulation pattern contacts a lower surface of the second upper landing pad.

17. The semiconductor device according to claim 16, wherein: The cell insulation pattern is in contact with a side surface of the first upper landing pad and is not in contact with a lower surface of the first upper landing pad.

18. The semiconductor device according to claim 15, wherein: A side surface of the spacer structure contacts the second lower landing pad and the cell insulation pattern.

19. The semiconductor device according to claim 15, wherein: The first upper landing pad includes a metal layer and a metal nitride layer, and The metal nitride layer covers the metal layer and extends along an upper surface and a side surface of the metal layer.

20. A semiconductor device, comprising: A substrate, the substrate comprising a cell region and a peripheral circuit region; a first active region, the first active region being located on the substrate in the cell region; a cell gate structure, the cell gate structure being located in the substrate in the cell region, intersecting the first active region and extending in a first horizontal direction; a bit line structure intersecting the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction; a contact plug, the contact plug being located between the bit line structures; a landing pad structure located on the contact plug and comprising a lower landing pad and an upper landing pad located on the lower landing pad; A peripheral gate structure, the peripheral gate structure is located on the peripheral circuit area; a lower interlayer insulating layer, the lower interlayer insulating layer covering a side surface of the peripheral gate structure; a peripheral contact plug penetrating the lower interlayer insulating layer; a plurality of peripheral interconnect layers, the plurality of peripheral interconnect layers being located on the lower interlayer insulating layer and the peripheral contact plugs; a plurality of peripheral insulating structures passing between the plurality of peripheral interconnect layers, wherein the plurality of peripheral insulating structures include a first peripheral insulating structure partially penetrating the lower interlayer insulating layer, wherein the first peripheral insulating structure comprises a first peripheral insulating layer, a second peripheral insulating layer located on the first peripheral insulating layer and passing between the plurality of peripheral interconnection layers, and a mixture layer located between the lower interlayer insulating layer and the first peripheral insulating layer, wherein the lower interlayer insulating layer and the first peripheral insulating layer include silicon oxide, and Wherein, the mixture layer and the second peripheral insulating layer include silicon nitride.

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