Display device

Abstract

A display device includes a substrate, a plurality of pixel electrodes disposed on the substrate and spaced apart from each other by a first pitch, and a plurality of light emitting elements disposed on the plurality of pixel electrodes, respectively. Each of the plurality of pixel electrodes has a rectangular shape having a long side and a short side, and a width of each of the plurality of light emitting elements is larger than a width of the short side and smaller than the first pitch between the plurality of pixel electrodes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0079379 filed in the Korean Intellectual Property Office on June 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] As multimedia technology develops, the importance of display devices has steadily increased. Examples of display devices include organic light emitting display devices and liquid crystal display (LCD) devices.

[0005] The display device is a device for displaying an image, and includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element such as a light-emitting diode (LED). Examples of light-emitting diodes include an organic light-emitting diode (OLED) using an organic material as a light-emitting material and an inorganic light-emitting diode using an inorganic material as a light-emitting material. The display panel includes a plurality of pixels, each of which may include a pixel electrode and a light-emitting element.

[0006] However, some of the light emitting elements may collapse due to the arrangement or shape of the pixel electrode. Therefore, the light output efficiency of the light emitting elements may be low, and image quality may be reduced. Summary of the invention

[0007] Aspects of the present disclosure provide a display device and a method of manufacturing the display device capable of preventing defects caused by collapse of a light emitting element when the light emitting element is arranged on a pixel electrode.

[0008] According to an embodiment, a display device includes a substrate, a plurality of pixel electrodes and a plurality of light emitting elements. The plurality of pixel electrodes are arranged on the substrate and are spaced apart from each other by a first spacing. The plurality of light emitting elements are respectively arranged on the plurality of pixel electrodes. Each of the plurality of pixel electrodes has a rectangular shape, and the rectangular shape has a long side and a short side. The width of each of the plurality of light emitting elements is greater than the width of the short side and less than the first spacing between the plurality of pixel electrodes.

[0009] In an embodiment, each of the multiple light emitting elements includes: a second semiconductor layer; an active layer disposed on the second semiconductor layer; and a first semiconductor layer disposed on the active layer, and a width of the first semiconductor layer is greater than the width of the short side and less than the first spacing between the multiple pixel electrodes.

[0010] In an embodiment, each of the multiple light-emitting elements also includes a connecting electrode, which is arranged on the first semiconductor layer and connected to a corresponding one of the multiple pixel electrodes, and a width of the connecting electrode is greater than the width of the short side of the one pixel electrode and less than the first spacing between the multiple pixel electrodes.

[0011] In an embodiment, the width of each of the plurality of light emitting elements is in a range from about 8 μm to about 16 μm.

[0012] In an embodiment, the width of the short side of one pixel electrode among the plurality of pixel electrodes is in the range of about 6 μm to about 8 μm, the length of the long side of the one pixel electrode is in the range of about 45 μm to about 55 μm, and the first spacing is in the range of about 16 μm to about 19 μm.

[0013] The display device may further include a first planarization layer disposed between the pixel electrodes.

[0014] The one pixel electrode may include a pixel reflective layer disposed in contact with the light emitting element.

[0015] The pixel reflective layer may have a reflectivity of about 80% or more.

[0016] In an embodiment, the number of the light emitting elements disposed on the one pixel electrode is three, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second pitch, and the second pitch is in a range of about 10 μm to about 20 μm.

[0017] In an embodiment, the number of the light emitting elements disposed on the one pixel electrode is two, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second pitch, and the second pitch is in a range of about 15 μm to about 20 μm.

[0018] In an embodiment, the number of the light emitting elements disposed on the one pixel electrode is four, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second pitch, and the second pitch is in a range of about 10 μm to about 15 μm.

[0019] In an embodiment, the display device further includes: a second planarization layer, which is arranged on the first planarization layer and between the multiple light-emitting elements; and a common electrode, which is arranged on the second planarization layer and the multiple light-emitting elements; and a wavelength converter, which is arranged on the common electrode, wherein the wavelength converter includes: partition walls, which separate multiple emission areas; a wavelength conversion layer, which is arranged between the multiple partition walls and overlaps with the multiple emission areas; a light blocking member, which is arranged on the partition walls; and a color filter, which is arranged on the wavelength conversion layer, wherein the light blocking member does not overlap with a corresponding one of the multiple pixel electrodes.

[0020] According to an embodiment, a display device includes a substrate, a plurality of pixel electrodes and a plurality of light emitting elements. The plurality of pixel electrodes are arranged on the substrate and are spaced apart from each other at a first spacing. The plurality of light emitting elements are respectively arranged on the plurality of pixel electrodes. Each of the plurality of pixel electrodes has a rectangular shape having a long side and a short side. The width of each of the plurality of light emitting elements is greater than the width of the short side. The ratio of the width of the short side to the first spacing is 1:1.7 to 1:1.8.

[0021] In an embodiment, each of the multiple light emitting elements includes: a second semiconductor layer; an active layer disposed on the second semiconductor layer; and a first semiconductor layer disposed on the active layer, and a width of the first semiconductor layer is greater than the width of the short side and less than the first spacing between the multiple pixel electrodes.

[0022] In an embodiment, each of the multiple light-emitting elements also includes a connecting electrode, which is arranged on the first semiconductor layer and connected to a corresponding one of the multiple pixel electrodes, and a width of the connecting electrode is greater than the width of the short side of the one pixel electrode and less than the first spacing between the multiple pixel electrodes.

[0023] In an embodiment, the width of each of the plurality of light emitting elements is in the range of about 8 μm to about 16 μm, the width of the short side of the one pixel electrode is in the range of about 6 μm to about 8 μm, the length of the long side of the one pixel electrode is in the range of about 45 μm to about 55 μm, and the first spacing is in the range of about 16 μm to about 19 μm.

[0024] The display device may further include a first planarization layer disposed on the substrate between the plurality of pixel electrodes.

[0025] In an embodiment, the number of the light emitting elements disposed on the one pixel electrode is three, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second pitch, and the second pitch is in a range of about 10 μm to about 20 μm.

[0026] In an embodiment, the number of the light emitting elements disposed on the one pixel electrode is two, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second pitch, and the second pitch is in a range of about 15 μm to about 20 μm.

[0027] In an embodiment, the number of the light emitting elements disposed on the one pixel electrode is four, the light emitting elements disposed on the one pixel electrode are spaced apart from each other at a second pitch, and the second pitch is in a range of about 10 μm to about 15 μm.

[0028] According to the display device according to the embodiment, the width of the light emitting element is smaller than the cross-sectional width of the pixel electrode, so that the light emitting element can be prevented from being deflected toward the edge of the pixel electrode and collapsing in the pixel electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0030] Figure 1 is a plan view of a display device according to an embodiment;

[0031] Figure 2 is a schematic layout diagram showing a circuit of a display substrate of a display device according to an embodiment;

[0032] Figure 3 is an equivalent circuit diagram of one pixel of a display device according to an embodiment;

[0033] Figure 4 is an equivalent circuit diagram of one pixel of a display device according to an embodiment;

[0034] Figure 5 is an equivalent circuit diagram of one pixel of a display device according to an embodiment;

[0035] Figure 6 It is schematically shown Figure 1 A cross-sectional view of a portion of a display area of ​​a display device;

[0036] Figure 7 is a schematic diagram showing a Figure 6 A cross-sectional view of a pixel electrode and a light-emitting element;

[0037] Figure 8is a schematic diagram showing a Figure 6 A cross-sectional view of a pixel electrode and a light-emitting element;

[0038] Fig. 9 is a plan view of a pixel electrode and a light emitting element according to an embodiment;

[0039] Fig.10 is a plan view of a pixel electrode and a light emitting element according to an embodiment;

[0040] Fig.11 is a plan view of a pixel electrode and a light emitting element according to an embodiment;

[0041] Fig.12 is a flowchart showing a method of manufacturing a display device according to an embodiment;

[0042] Figures 13 to 25 is a diagram illustrating a method of manufacturing a display device according to an embodiment;

[0043] Fig.26 is an exemplary diagram schematically showing a virtual reality device including a display device according to an embodiment;

[0044] Fig. 27 is an exemplary diagram schematically showing a smart device including a display device according to an embodiment;

[0045] Fig.28 is a diagram schematically showing an example of a vehicle including a display device according to an embodiment; and

[0046] Fig.29 is a diagram schematically showing an example of a transparent display device including a display device according to an embodiment. DETAILED DESCRIPTION

[0047] Embodiments will now be described more fully below with reference to the accompanying drawings. However, embodiments may be provided in different forms and should not be construed as limiting. Throughout the disclosure, the same reference numerals represent the same components.

[0048] It should also be understood that when a layer or substrate is referred to as being "on" another layer or substrate, the layer or substrate can be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

[0049] Furthermore, the phrase “in a plan view” means when the target portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross section obtained by vertically cutting the target portion is viewed from the side.

[0050] When an element is referred to as being “connected” or “coupled” to another element, the element may be “directly connected” or “directly coupled” to the other element or “electrically connected” or “electrically coupled” to the other element with one or more intervening elements interposed therebetween.

[0051] As used herein, the terms "about" or "approximately" include the stated value and refer to within an acceptable range of deviation of the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0052] In the specification and claims, for the purpose of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunction or disjunction sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a plan view of a display device according to an embodiment.

[0055] Reference Figure 1 The display device 10 according to the embodiment can be applied to a smart phone, a mobile phone, a tablet personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a television, a game console, a watch-type electronic device, a head-mounted display, a monitor of a personal computer, a laptop computer, a car navigation system, a car dashboard, a digital camera, a video camera, an external billboard, an electronic billboard, a medical device, an inspection device, various household appliances (such as a refrigerator and a washing machine) or an Internet of Things device. In this article, a television (TV) is described as an example of a display device, and the TV can have a high resolution or an ultra-high resolution, such as high definition (HD), ultra-high definition (UHD), 4K, and 8K.

[0056] In addition, the display device 10 according to the embodiment may be classified into various types according to the display method. Examples of the display device 10 may include an organic light emitting display device, an inorganic light emitting display (inorganic EL) device, a quantum dot light emitting display (QED) device, a micro LED display device, a nano LED display device, a plasma display device (PDP), a field emission display (FED) device, a cathode ray tube (CRT) display device, a liquid crystal display (LCD) device, and an electrophoretic display (EPD) device, etc. Hereinafter, an organic light emitting display device will be described as an example of the display device 10. However, the embodiments of the present disclosure are not limited to the organic light emitting display device, and other display devices described above or known in the art may be applied within the same scope of the present disclosure.

[0057] Furthermore, in the drawings, the first direction DR1 refers to the horizontal direction of the display device 10, the second direction DR2 refers to the vertical direction of the display device 10, and the third direction DR3 refers to the thickness direction of the display device 10. In this case, "left", "right", "upper", and "lower" refer to directions when the display device 10 is viewed from above. For example, "right side" refers to one side of the first direction DR1, "left side" refers to the other side of the first direction DR1, "upper side" refers to one side of the second direction DR2, and "lower side" refers to the other side of the second direction DR2. In addition, "top" refers to one side of the third direction DR3, and "bottom" refers to the other side of the third direction DR3.

[0058] In a plan view, the display device 10 according to the embodiment may have a square shape, for example, a square shape. In addition, when the display device 10 is a television, it may have a rectangular shape with a long side located in the horizontal direction. However, the present disclosure is not limited thereto, and the long side of the display device 10 may extend in the vertical direction. For example, the display device 10 may be mounted to be rotatable so that its long side is variably positioned to extend in the horizontal direction or the vertical direction. In addition, the display device 10 may have a circular shape or an elliptical shape.

[0059] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA may be an active area that displays an image. The display area DPA may have a square shape similar to the overall shape of the display device 10 in a plan view, but the present disclosure is not limited thereto.

[0060] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix. In a plan view, the shape of each pixel PX may be a rectangle or a square. However, each pixel PX may alternatively have a rhombus shape with each side thereof tilted relative to a direction of one side of the display device 10. The pixel PX may include a plurality of color pixels PX. For example, although not limited thereto, the pixel PX may include a first color pixel PX of red, a second color pixel PX of green, and a third color pixel PX of blue. For example, the color pixels PX may be arranged in a stripe type or Type layout.

[0061] The non-display area NDA may be disposed around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA may have a square shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 10.

[0062] In the non-display area NDA, a driving circuit or a driving element for driving the display area DPA may be provided. Figure 1 In the non-display area NDA provided adjacent to the lower side of the display device 10, a pad portion may be provided on the display substrate of the display device 10, and an external device EXD may be mounted on a pad electrode of the pad portion. The external device EXD may include, for example, a connection film, a printed circuit board, a driver integrated circuit DIC, a connector, and a wiring connection film. A scan driver SDR (for example, a driver circuit) formed on the display substrate of the display device 10 may be provided adjacent to the second side ( Figure 1 The scanning driver SDR may directly contact the upper surface of the display substrate.

[0063] Figure 2 is a schematic layout diagram showing a circuit of a display substrate of a display device according to an embodiment.

[0064] Reference Figure 2 , a plurality of wirings are disposed on the first substrate of the display substrate. In an embodiment, the plurality of wirings may include a scan line SCL, a sensing signal line SSL, a data line DTL, a reference voltage line RVL, and a first power line ELVDL.

[0065] The scan lines SCL and the sensing signal lines SSL may extend in a first direction DR1. The scan lines SCL and the sensing signal lines SSL may be connected to a scan driver SDR. The scan driver SDR may include a driving circuit. The scan driver SDR may be disposed on one side of the non-display area NDA on the display substrate, but the present disclosure is not limited thereto. For example, the scan driver SDR may be disposed on both sides of the non-display area NDA. The scan driver SDR is connected to a signal connection line CWL, and at least one end of the signal connection line CWL may be formed in a first portion of the non-display area NDA and / or a second portion of the non-display area NDA to be connected to an external device ( Figure 1 The pad WPD_CW of the external device EXD).

[0066] The data line DTL and the reference voltage line RVL may extend in a second direction DR2 crossing the first direction DR1. The first power line ELVDL may include a portion extending in the second direction DR2. The first power line ELVDL may also include a portion extending in the first direction DR1. The first power line ELVDL may have a mesh structure, but the present disclosure is not limited thereto.

[0067] At least one end of the data line DTL, the reference voltage line RVL, and the first power line ELVDL may be provided with a wiring pad WPD. Each wiring pad WPD may be provided in a pad portion PDA of the non-display area NDA. In an embodiment, a wiring pad WPD_DT of the data line DTL (hereinafter referred to as "data pad WPD_DT"), a wiring pad WPD_RV of the reference voltage line RVL (hereinafter referred to as "reference voltage pad WPD_RV"), and a wiring pad WPD_ELVD of the first power line ELVDL (hereinafter referred to as "first power pad WPD_ELVD") are provided in the pad portion PDA of the non-display area NDA. In another example, the data pad WPD_DT, the reference voltage pad WPD_RV, and the first power pad WPD_ELVD may be provided in another part of the non-display area NDA. As described above, an external device ( Figure 1 The external device EXD in the wiring pad WPD can be mounted on the wiring pad WPD. The external device EXD can be mounted on the wiring pad WPD by applying an anisotropic conductive film or ultrasonic welding, etc.

[0068] In an embodiment, each pixel PX on the display substrate includes a pixel driving circuit. The above wiring may pass through each pixel PX or its vicinity to apply a driving signal to each pixel driving circuit. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors of each pixel driving circuit may be modified differently. Hereinafter, as an example, a 3T1C structure including three transistors and one capacitor will be described in conjunction with the pixel driving circuit. However, the present disclosure is not limited thereto, and other modified pixel PX structures such as a 2T1C structure, a 7T1C structure, and a 6T1C structure may be adopted.

[0069] Figure 3 According to the embodiment Figure 1 Equivalent circuit diagram of a pixel in the display area.

[0070] Reference Figure 3 In addition to the light emitting element LE, the display device 10 according to the embodiment (see Figure 1 ) each pixel PX also includes three transistors DTR, STR1 and STR2 and a storage capacitor CST.

[0071] The light emitting element LE emits light according to the current supplied through the driving transistor DTR. The light emitting element LE may be implemented as an inorganic light emitting diode, an organic light emitting diode, a micro light emitting diode, or a nano light emitting diode.

[0072] The first electrode (i.e., the anode electrode) of the light emitting element LE is connected to the source electrode of the driving transistor DTR, and the second electrode (i.e., the cathode electrode) of the light emitting element LE is connected to the second power line ELVSL, and a low potential voltage (second source voltage) lower than the high potential voltage (first source voltage) of the first power line ELVDL is supplied to the second power line ELVSL.

[0073] The driving transistor DTR adjusts the current flowing from the first power line ELVDL to which the first source voltage is applied to the light emitting element LE according to the voltage difference between its gate electrode and its source electrode. The gate electrode of the driving transistor DTR can be connected to the first electrode of the first transistor STR1, the source electrode of the driving transistor DTR can be connected to the first electrode of the light emitting element LE, and the drain electrode of the driving transistor DTR can be connected to the first power line ELVDL to which the first power voltage is applied.

[0074] The first transistor STR1 is turned on by a scan signal of the scan line SCL to connect the data line DTL to the gate electrode of the driving transistor DTR. The gate electrode of the first transistor STR1 may be connected to the scan line SCL, the first electrode of the first transistor STR1 may be connected to the gate electrode of the driving transistor DTR, and the second electrode of the first transistor STR1 may be connected to the data line DTL.

[0075] The second transistor STR2 is turned on by the sensing signal of the sensing signal line SSL to connect the initialization voltage line VIL to the source electrode of the driving transistor DTR. The gate electrode of the second transistor STR2 can be connected to the sensing signal line SSL, the first electrode of the second transistor STR2 can be connected to the initialization voltage line VIL, and the second electrode of the second transistor STR2 can be connected to the source electrode of the driving transistor DTR.

[0076] In an embodiment, a first electrode of each of the first transistor STR1 and the second transistor STR2 is a source electrode, and a second electrode of each of the first transistor STR1 and the second transistor STR2 is a drain electrode, but the present disclosure is not limited thereto and may be vice versa.

[0077] The storage capacitor CST is formed between the gate electrode and the source electrode of the driving transistor DTR. The storage capacitor CST stores a voltage difference between the gate voltage of the driving transistor DTR and the power voltage.

[0078] The driving transistor DTR, the first transistor STR1 and the second transistor STR2 may be thin film transistors. Figure 3 In the description, it is assumed that the driving transistor DTR, the first transistor STR1, and the second transistor STR2 are N-type metal oxide semiconductor field effect transistors (MOSFETs), but the present disclosure is not limited thereto. That is, the driving transistor DTR, the first transistor STR1, and the second transistor STR2 may be P-type MOSFETs, or some of the driving transistor DTR, the first transistor STR1, and the second transistor STR2 may be N-type MOSFETs, and the others may be P-type MOSFETs.

[0079] Figure 4 According to the embodiment Figure 1 Equivalent circuit diagram of a pixel of the display area DPA.

[0080] Reference Figure 4The first electrode of the light emitting element LE may be connected to the first electrode of the fourth transistor STR4 and the second electrode of the sixth transistor STR6, and the second electrode of the light emitting element LE may be connected to the second power line ELVSL. The parasitic capacitor Cel may be formed between the first electrode and the second electrode of the light emitting element LE.

[0081] Each pixel PX includes a driving transistor DTR, a switching element, and a storage capacitor CST. The switching element includes a first transistor STR1, a second transistor STR2, a third transistor STR3, a fourth transistor STR4, a fifth transistor STR5, and a sixth transistor STR6.

[0082] The driving transistor DTR includes a gate electrode, a first electrode, and a second electrode. The driving transistor DTR controls a drain-source current (Ids) (hereinafter referred to as "driving current") flowing between the first electrode of the driving transistor DTR and the second electrode of the driving transistor DTR according to a data voltage applied to the gate electrode of the driving transistor DTR.

[0083] The storage capacitor CST is formed between the gate electrode of the driving transistor DTR and the first power line ELVDL. One electrode of the storage capacitor CST may be connected to the gate electrode of the driving transistor DTR, and the other electrode of the storage capacitor CST may be connected to the first power line ELVDL.

[0084] When the first electrode of the driving transistor DTR and each of the first transistor STR1 to the sixth transistor STR6 is a source electrode, the second electrode of the driving transistor DTR and each of the first transistor STR1 to the sixth transistor STR6 may be a drain electrode. For example, when the first electrode of the driving transistor DTR and each of the first transistor STR1 to the sixth transistor STR6 is a drain electrode, the second electrode of the driving transistor DTR and each of the first transistor STR1 to the sixth transistor STR6 may be a source electrode. In an embodiment, the transistor STR1 may include a pair of transistors STR1-1 and STR1-2; and the transistor STR3 may include a pair of transistors STR3-1 and STR3-2. The emission line EL connects the gate of the transistor STR5 and the gate of the transistor STR6.

[0085] The active layer of the driving transistor DTR and each of the first to sixth transistors STR1 to STR6 may be formed of any one of polysilicon, amorphous silicon, and an oxide semiconductor. When the semiconductor layer of the driving transistor DTR and each of the first to sixth transistors STR1 to STR6 is formed of polysilicon, the process for forming the semiconductor layer may be a low temperature polysilicon (LTPS) process.

[0086] In addition, Figure 4 In the embodiment, although the driving transistor DTR and the first to sixth transistors STR1 to STR6 may be formed of P-type metal oxide semiconductor field effect transistors (MOSFETs), they are not limited thereto as they may be formed of N-type MOSFETs.

[0087] Furthermore, a first power voltage of the first power line ELVDL, a second power voltage of the second power line ELVSL, and a third power voltage of the third power line VIL may be set in consideration of characteristics of the driving transistor DTR or characteristics of the light emitting element LE.

[0088] Figure 5 According to the embodiment Figure 1 Equivalent circuit diagram of a pixel of the display area DPA.

[0089] Figure 5 Examples and Figure 4 The embodiment of the present invention is different in that the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 are formed as P-type MOSFETs, and the first transistor STR1 and the third transistor STR3 are formed as N-type MOSFETs.

[0090] Reference Figure 5 The active layer of each of the driving transistor DTR, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5 and the sixth transistor STR6 configured as a P-type MOSFET can be formed of polysilicon, and the active layer of each of the first transistor STR1 and the third transistor STR3 configured as an N-type MOSFET can be formed of an oxide semiconductor.

[0091] Figure 5 Examples and Figure 4 The embodiment of the present invention is different in that the gate electrode of the second transistor STR2 and the gate electrode of the fourth transistor STR4 are connected to the write scan line GWL, and the gate electrode of the first transistor STR1 is connected to the control scan line GCL. Figure 5 In the embodiment, since the first transistor STR1 and the third transistor STR3 are formed by N-type MOSFETs, a scan signal of a gate high voltage can be applied to the control scan line GCL and the initialization scan line GIL. On the contrary, the second transistor STR2, the fourth transistor STR4, the fifth transistor STR5, and the sixth transistor STR6 are formed as P-type MOSFETs, so that a scan signal of a gate low voltage can be applied to the write scan line GWL and the emission line ELk.

[0092] Meanwhile, it should be noted that the equivalent circuit diagram of the pixel according to the above-mentioned embodiment of the present specification is not limited to Figures 3 to 5 Except for those shown in Figures 3 to 5 In addition to the embodiments shown in , the equivalent circuit diagram of the pixel according to the embodiments of the present specification can be formed with other known circuit structures that can be adopted by those skilled in the art.

[0093] Figure 6 It is schematically shown Figure 1 4 is a cross-sectional view of a portion of a display area DPA of a display device. Figure 7 is a schematic diagram showing a Figure 6 A cross-sectional view of a pixel electrode and a light-emitting element. Figure 8 is a cross-sectional view schematically showing a pixel electrode and a light emitting element according to an embodiment.

[0094] Reference Figure 6 , the display device 10 may include a display substrate 100 and a wavelength converter 200 disposed on the display substrate 100 .

[0095] The display substrate 100 may include a first substrate 110 and a light emitting element unit LEP disposed on the first substrate 110. The first substrate 110 may be an insulating substrate. The first substrate 110 may include a transparent material. For example, the first substrate 110 may include a transparent insulating material such as glass or quartz. The first substrate 110 may be a rigid substrate. However, the first substrate 110 is not limited thereto. The first substrate 110 may include a plastic such as polyimide, and may have a flexible property so that the first substrate 110 may be twisted, bent, folded or curled. A plurality of emission areas EA1, EA2 and EA3 and a non-emission area NEA may be defined in the first substrate 110. A plurality of non-emission areas NEA may be provided.

[0096] The switching elements T1, T2, and T3 may be located on the first substrate 110. In an embodiment, the first switching element T1 is located in the first emission area EA1 of the first substrate 110, the second switching element T2 is located in the second emission area EA2 of the first substrate 110, and the third switching element T3 is located in the third emission area EA3 of the first substrate 110. However, the present disclosure is not limited thereto. For example, in another embodiment, at least one of the first switching element T1, the second switching element T2, and the third switching element T3 may be located in the non-emission area NEA.

[0097] In one embodiment, each of the first switching element T1, the second switching element T2, and the third switching element T3 may be a thin film transistor including amorphous silicon, polycrystalline silicon, or an oxide semiconductor. In addition, a plurality of signal lines (e.g., gate lines, data lines, and power lines, etc.) transmitting signals to the switching elements may be further located on the first substrate 110.

[0098] Each of the switching elements T1, T2, and T3 may include a semiconductor layer 65, a gate electrode 75, a source electrode 85a, and a drain electrode 85b. Specifically, a buffer layer 60 may be disposed on the first substrate 110. The buffer layer 60 may be disposed to cover the entire surface of the first substrate 110. The buffer layer 60 may include silicon nitride, silicon oxide, or silicon oxynitride, and may be formed as a single layer or a double layer of the material.

[0099] The semiconductor layer 65 may be disposed on the buffer layer 60. The semiconductor layer 65 may form a channel of each of the switching elements T1, T2, and T3. The semiconductor layer 65 may include amorphous silicon, polycrystalline silicon, or an oxide semiconductor. For example, the oxide semiconductor may include a binary compound (AB) such as indium, zinc, gallium, tin, titanium, aluminum, hafnium (Hf), zirconium (Zr), and magnesium (Mg). x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z In an embodiment, the semiconductor layer 65 includes indium gallium zinc oxide (IGZO).

[0100] The gate insulating layer 70 may be disposed on the semiconductor layer 65. The gate insulating layer 70 may include a silicon compound or a metal oxide, etc. For example, the gate insulating layer 70 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. In an embodiment, the gate insulating layer 70 includes silicon oxide.

[0101] The gate electrode 75 may be disposed on the gate insulating layer 70. The gate electrode 75 may be disposed to overlap the semiconductor layer 65. The gate electrode 75 may include a conductive material. The gate electrode 75 may include a conductive material such as ITO, IZO, ITZO, and In 2 O 3 The gate electrode 75 may be formed of a metal oxide or a metal such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni). For example, the gate electrode 75 may be formed as a Cu / Ti double layer in which an upper layer made of copper is stacked on a lower layer made of titanium, but the present disclosure is not limited thereto.

[0102] The first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be disposed on the gate electrode 75. The first interlayer insulating layer 80 may be disposed on the gate electrode 75, and the second interlayer insulating layer 82 may be disposed on the first interlayer insulating layer 80. In an embodiment, the first interlayer insulating layer 80 directly contacts the gate electrode 75, and the second interlayer insulating layer 82 directly contacts the first interlayer insulating layer 80. Each of the first interlayer insulating layer 80 and the second interlayer insulating layer 82 may include an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, or zinc oxide (ZnO x , which can be ZnO or ZnO 2 ) etc. However, the present disclosure is not limited thereto, and the second interlayer insulating layer 82 may include an organic insulating material capable of flattening the stepped portion disposed thereunder. Although two interlayer insulating layers, the first interlayer insulating layer 80 and the second interlayer insulating layer 82, have been shown and described in the present embodiment, the present disclosure is not limited thereto. For example, the first interlayer insulating layer 80 and the second interlayer insulating layer 82 may be replaced with a single interlayer insulating layer.

[0103] The source electrode 85a and the drain electrode 85b may be disposed on the second interlayer insulating layer 82. The source electrode 85a and the drain electrode 85b may contact the semiconductor layer 65 through a contact hole penetrating the first interlayer insulating layer 80, the second interlayer insulating layer 82, and the gate insulating layer 70. The source electrode 85a and the drain electrode 85b may include an indium ion battery such as ITO, IZO, ITZO, and Indium ion battery. 2 O 3 The source electrode 85a and the drain electrode 85b may be formed as a Cu / Ti double layer in which an upper layer made of copper is stacked on a lower layer made of titanium, or a metal oxide such as copper (Cu), titanium (Ti), aluminum (Al), molybdenum (Mo), tantalum (Ta), calcium (Ca), chromium (Cr), magnesium (Mg), and nickel (Ni). For example, the source electrode 85a and the drain electrode 85b may be formed as a Cu / Ti double layer in which an upper layer made of copper is stacked on a lower layer made of titanium, but the present disclosure is not limited thereto.

[0104] The first planarization layer 120 may be disposed on the first switching element T1, the second switching element T2, and the third switching element T3. The first planarization layer 120 may include an organic material. For example, the first planarization layer 120 may include an acrylic resin, an epoxy resin, an imide resin, an ester resin, etc. In an embodiment, the first planarization layer 120 may include a positive photosensitive material or a negative photosensitive material.

[0105] The pixel connection electrode 125 may be disposed on the first planarization layer 120. The pixel connection electrode 125 may be disposed to correspond to each of the first switching element T1, the second switching element T2, and the third switching element T3, and may be electrically connected to each of the first switching element T1, the second switching element T2, and the third switching element T3. For example, a separate pixel electrode 125 may exist for each of the first switching element T1, the second switching element T2, and the third switching element T3. The pixel connection electrode 125 may connect the pixel electrodes PE1, PE2, and PE3 to be described below to the above-mentioned switching elements T1, T2, and T3. The pixel connection electrode 125 may contact the switching elements T1, T2, and T3 through a contact hole penetrating the first planarization layer 120.

[0106] The second planarization layer 130 may be disposed on the first planarization layer 120 and the pixel connection electrode 125. The second planarization layer 130 may planarize a stepped portion disposed thereunder. The second planarization layer 130 and the first planarization layer 120 may include the same material.

[0107] The light emitting element unit LEP may be disposed on the second planarization layer 130. The light emitting element unit LEP may include a plurality of pixel electrodes PE1, PE2, and PE3, a plurality of light emitting elements LE, and a common electrode CE.

[0108] The plurality of pixel electrodes PE1, PE2, and PE3 may include a first pixel electrode PE1, a second pixel electrode PE2, and a third pixel electrode PE3. The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be used as a first electrode of the light emitting element LE, and may be an anode electrode or a cathode electrode. The first pixel electrode PE1 may be positioned in the first emission area EA1, the second pixel electrode PE2 may be positioned in the second emission area EA2, and the third pixel electrode PE3 may be positioned in the third emission area EA3.

[0109] The first pixel electrode PE1 may penetrate the second planarization layer 130 to be connected to the first switching element T1 , the second pixel electrode PE2 may penetrate the second planarization layer 130 to be connected to the second switching element T2 , and the third pixel electrode PE3 may penetrate the second planarization layer 130 to be connected to the third switching element T3 .

[0110] The pixel electrodes PE1, PE2 and PE3 may be directly connected to the pixel connection electrode 125 through the contact hole penetrating the second planarization layer 130, and may be electrically connected to the switching elements T1, T2 and T3 respectively through the pixel connection electrode 125. The first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a metal. The metal may include, for example, copper (Cu), titanium (Ti), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. In addition, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a multilayer structure in which two or more metal layers are stacked. For example, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may have a two-layer structure in which a copper layer is stacked on a titanium layer, but the present disclosure is not limited thereto. In addition, the first pixel electrode PE1, the second pixel electrode PE2 and the third pixel electrode PE3 may include a reflective layer coated with a reflective material.

[0111] In an embodiment, each of the pixel electrodes PE1, PE2 and PE3 includes a pixel electrode layer P1 and a pixel reflective layer P3. Figure 7 and Figure 8 The light emitting element LE disposed on the first pixel electrode PE1 is described as an example, but the present disclosure is not limited thereto, and the light emitting elements LE disposed on the second pixel electrode PE2 and the third pixel electrode PE3 may have the same structure.

[0112] Reference Figure 7 and Figure 8 , the pixel electrode layer P1 can be electrically connected to the switching element. The pixel electrode layer P1 can also be used to provide adhesion to the contact material between the second planarization layer 130 and the light emitting element LE. In an embodiment, the pixel electrode layer P1 is a single layer, but in other embodiments, the pixel electrode layer P1 can have multiple metal layers. For example, the pixel electrode layer P1 may include a lower electrode layer containing titanium and an upper electrode layer containing copper.

[0113] The pixel reflective layer P3 may be disposed on the pixel electrode layer P1 and may be in direct contact with the light emitting element LE. The pixel reflective layer P3 may be disposed between the pixel electrode layer P1 and the light emitting element LE. The pixel reflective layer P3 may be formed by coating the pixel electrode layer P1 with a reflective material having a reflectivity of at least 80%. For example, the reflective material may be Ag, Ni, Cr, or the like.

[0114] In an embodiment, the pixel electrode layer P1 is formed to have the same width as the pixel reflective layer P3. Therefore, the pixel electrode layer P1 may completely overlap the pixel reflective layer P3 in the thickness direction (third direction DR3).

[0115] Reference Figure 6 and Figure 8 , a plurality of light emitting elements LE may be disposed on the first pixel electrode PE1 , the second pixel electrode PE2 , and the third pixel electrode PE3 .

[0116] That is, the light emitting element LE may be disposed in each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. The light emitting element LE may be a vertical light emitting diode element elongated in the third direction DR3. That is, the length of the light emitting element LE in the third direction DR3 may be longer than the length of the light emitting element LE in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 or the length in the second direction DR2. For example, the length of the light emitting element LE in the third direction DR3 may be approximately 1 μm to 5 μm. However, the present disclosure is not limited thereto, and the length of the light emitting element LE in the third direction DR3 may also be equal to or less than the length in the horizontal direction.

[0117] Reference Figure 7 and Figure 8 , the light emitting element LE may have a cylindrical shape, a disk shape, or a rod shape with a height longer than a width. However, the present disclosure is not limited thereto, and the light emitting element LE may have various shapes, such as a rod shape, a wire shape, a tube shape, a polygonal prism shape (such as a regular cube, a cuboid, and a hexagonal prism), or a shape extending in one direction and having a partially inclined outer surface.

[0118] The light emitting element LE may be a micro light emitting diode element. In the thickness direction of the display substrate 100 (i.e., in the third direction DR3), the light emitting element LE may include a connection electrode 150, a first semiconductor layer SEM1, an active layer MQW, and a second semiconductor layer SEM2. The connection electrode 150, the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 may be sequentially stacked in the third direction DR3.

[0119] The connection electrode 150 may be disposed on the plurality of pixel electrodes PE1, PE2, and PE3. The connection electrode 150 may be in direct contact with the plurality of pixel electrodes PE1, PE2, and PE3. Figure 8 As shown in , the width of the connection electrode 150 is the same as the width of the light emitting element LE. Hereinafter, the width of the light emitting element LE and the width of the connection electrode 150 may be used interchangeably. Figure 7As shown in FIG. 1 , when the width of the light emitting element LE increases from one end of the light emitting element LE to the other end of the light emitting element LE, the width of the light emitting element LE is the width of the first semiconductor layer SEM1. In an embodiment, the width of the light emitting element LE is greater than the width of the corresponding pixel electrode (eg, pixel electrode PE1). Fig. 9 Describe the width of the light emitting element LE and the corresponding width of the pixel electrode.

[0120] The connection electrode 150 may include a reflective layer 151 and a connection layer 153. The reflective layer 151 may be used to reflect light emitted from the active layer MQW of the light emitting element LE. The reflective layer 151 may be disposed adjacent to the active layer MQW of the light emitting element LE. The reflective layer 151 may include a metal material having electrical conductivity and high light reflectivity. The reflective layer 151 may include, for example, aluminum (Al) or silver (Ag) or an alloy thereof.

[0121] The connection layer 153 may be used to transmit the emission signal from the first pixel electrode PE1 to the light emitting element LE. The connection layer 153 may be an ohmic connection electrode. However, the present disclosure is not limited thereto, and the connection layer 153 may be a Schottky connection electrode. The connection layer 153 may be disposed at the lowermost end of the light emitting element LE and may be further away from the active layer MQW than the reflective layer 151. The connection layer 153 may include at least one of gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and titanium (Ti). For example, the connection layer 153 may include a 9:1 alloy, an 8:2 alloy, or a 7:3 alloy of gold and tin, or may include an alloy (SAC305) of copper, silver, and tin.

[0122] although Figure 7 and Figure 8 A double-layered light emitting element LE is shown in which the connection electrode 150 has one reflective layer 151 and one connection layer 153, but the present disclosure is not limited thereto. In some cases, the light emitting element LE may include a connection electrode 150 in which a large number of layers are stacked or some layers may be omitted.

[0123] The first semiconductor layer SEM1 may be disposed on the connection electrode 150. The first semiconductor layer SEM1 may be a p-type (also referred to as a P-type) semiconductor and may include Al x Ga y In 1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the semiconductor material may be any one or more of p-type doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer SEM1 may be doped with a p-type dopant, and the p-type dopant may be Mg, Zn, Ca, or Ba, etc. For example, the first semiconductor layer SEM1 may be p-GaN doped with p-type Mg. The thickness of the first semiconductor layer SEM1 may be in the range of 30nm to 200nm, but is not limited thereto.

[0124] The active layer MQW may be disposed on the first semiconductor layer SEM1. The active layer MQW may emit light by recombination of electron-hole pairs according to an electrical signal applied via the first semiconductor layer SEM1 and the second semiconductor layer SEM2. The active layer MQW may emit first light having a central wavelength band of 450 nm to 495 nm, that is, light of a blue wavelength band.

[0125] The active layer MQW may include a material having a single quantum well or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW may have a structure in which a plurality of well layers and a plurality of barrier layers are alternately stacked. The well layer may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but the present disclosure is not limited thereto. The thickness of the well layer may be approximately 1 nm to 4 nm, and the thickness of the barrier layer may be 3 nm to 10 nm.

[0126] For example, the active layer MQW may have a structure in which a semiconductor material having a large energy band gap and a semiconductor material having a small energy band gap are alternately stacked, and may include other III- to V-group semiconductor materials according to the wavelength band of the emitted light. The light emitted by the active layer MQW is not limited to the first light, and in some cases, a second light (light in a green wavelength band) or a third light (light in a red wavelength band) may be emitted. In an embodiment, when the semiconductor material included in the active layer MQW includes indium, the color of the emitted light may vary depending on the content of indium. For example, as the content of indium decreases, the wavelength band of light emitted from the active layer MQW may shift to a red wavelength band, and as the content of indium increases, the wavelength band of light emitted from the active layer MQW may shift to a blue wavelength band.

[0127] The second semiconductor layer SEM2 may be disposed on the active layer MQW. The second semiconductor layer SEM2 may be an n-type (also referred to as an N-type) semiconductor. The second semiconductor layer SEM2 may include Al x Ga y In 1-x-yN(0≤x≤1, 0≤y≤1, 0≤x+y≤1). For example, the semiconductor material may be any one or more of n-type doped AlGaInN, GaN, AlGaN, InGaN, AlN and InN. The second semiconductor layer SEM2 may be doped with an n-type dopant, and the n-type dopant may be Se, Si, Ge or Sn, etc. For example, the second semiconductor layer SEM2 may be n-GaN doped with n-type Si. The thickness of the second semiconductor layer SEM2 may be in the range of 2μm to 4μm, but the present disclosure is not limited thereto.

[0128] In an embodiment, an electron blocking layer is disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer may be disposed on the first semiconductor layer SEM1. The electron blocking layer may be a layer for suppressing or preventing excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer may be p-AlGaN doped with p-type Mg. The thickness of the electron blocking layer may be in the range of 10 nm to 50 nm, but the present disclosure is not limited thereto. In addition, the electron blocking layer may be omitted.

[0129] The superlattice layer may be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer may be a layer for relieving stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer may be formed of InGaN or GaN. The thickness of the superlattice layer may be about 50 nm to about 200 nm. The superlattice layer may be omitted.

[0130] In addition, the light emitting element LE may include a first side insulating layer INS1 , a side reflective layer RFL1 , and a second side insulating layer INS2 sequentially surrounding the first semiconductor layer SEM1 , the active layer MQW, and the second semiconductor layer SEM2 .

[0131] The first side insulating layer INS1 may surround a side surface of the light emitting element LE, for example, an outer peripheral surface of the light emitting element LE. The first side insulating layer INS1 may insulate the light emitting element LE from other layers. The first side insulating layer INS1 may be directly disposed on the outer peripheral surfaces of the first semiconductor layer SEM1, the second semiconductor layer SEM2, and the active layer MQW to surround the first semiconductor layer SEM1, the second semiconductor layer SEM2, and the active layer MQW. In an embodiment, the first side insulating layer INS1 surrounds the entire outer peripheral surface of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2.

[0132] The first side insulating layer INS1 may be disposed to surround the light emitting element LE. The first side insulating layer INS1 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiOx N y ), aluminum oxide (Al x O y ) and aluminum nitride (AlN). The thickness of the first side insulating layer INS1 may be about 0.1 μm, but is not limited thereto.

[0133] The side reflective layer RFL1 may be disposed on the first side insulating layer INS1. The side reflective layer RFL1 may be disposed to surround the side surface of the light emitting element LE. For example, the side reflective layer RFL1 may surround the outer peripheral surface of the light emitting element LE, and may surround the side surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 of the light emitting element LE.

[0134] The side reflection layer RFL1 may reflect light emitted from the light emitting element LE. For example, the side reflection layer RFL1 may reflect light emitted from the active layer MQW of the light emitting element LE and emitted to the side surface upward (for example, in the third direction DR3). That is, the side reflection layer RFL1 may increase the light output efficiency of the light emitting element LE. To this end, the side reflection layer RFL1 may be provided to surround at least the side surface of the active layer MQW of the light emitting element LE.

[0135] The side reflection layer RFL1 may include a metal material having high reflectivity, for example, aluminum or silver, or an alloy of aluminum or silver.

[0136] The second side insulating layer INS2 may be disposed on the side reflective layer RFL1 to surround the outside of the light emitting element LE. For example, the second side insulating layer INS2 is formed to surround the side surface and the top surface of the side reflective layer RFL1, but both ends of the light emitting element LE in the longitudinal direction may be at least partially exposed. In an embodiment, the second side insulating layer INS2 does not cover the first semiconductor layer SEM1 and the second semiconductor layer SEM2 of the light emitting element LE. One end of the second side insulating layer INS2 contacting the common electrode CE may overlap with one end of the first side insulating layer INS1 and the side reflective layer RFL1.

[0137] The second side insulating layer INS2 and the first side insulating layer INS1 may include the same material. The second side insulating layer INS2 may include an inorganic insulating material such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ) and aluminum nitride (AlN). The thickness of the second side insulating layer INS2 may be about 0.1 μm, but is not limited thereto.

[0138] The third planarization layer 135 may be disposed on the second planarization layer 130 where the pixel electrodes PE1, PE2, and PE3 are not disposed. The third planarization layer 135 may include an organic material to planarize the stepped portions of the pixel electrodes PE1, PE2, and PE3. For example, the third planarization layer 135 may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated ester resin, polyphenylene resin, polyphenylene sulfide resin, or benzocyclobutene (BCB), etc.

[0139] Reference Figure 6 The planarization layer PLL may be disposed on the third planarization layer 135 where the plurality of light emitting elements LE1, LE2, and LE3 are not disposed. The planarization layer PLL may planarize the lower step so that the common electrode CE may be formed. The planarization layer PLL and the third planarization layer 135 may include the same material, but are not limited thereto.

[0140] The common electrode CE may be disposed on the planarization layer PLL and the plurality of light emitting elements LE. Specifically, the common electrode CE may be disposed on the surface of the first substrate 110 on which the light emitting elements LE are formed, and may be disposed entirely in the display area DPA and the non-display area NDA. The common electrode CE is disposed to overlap each of the emission areas EA1, EA2, and EA3 in the display area DPA, and may have a thin thickness to allow light to be emitted. For example, the thickness of the common electrode CE may be approximately to But it is not limited to this.

[0141] The common electrode CE may be directly disposed on the top surface and the side surface of the plurality of light emitting elements LE. The common electrode CE may be in direct contact with the second semiconductor layer SEM2 of the side surface of the light emitting element LE. Figure 6 As shown in , the common electrode CE may be a common layer covering a plurality of light emitting elements LE and is provided by commonly connecting the plurality of light emitting elements LE. Since the conductive second semiconductor layer SEM2 has a patterned structure in each of the light emitting elements LE, a common voltage may be applied to each light emitting element LE via the common electrode CE.

[0142] Since the common electrode CE is completely disposed on the first substrate 110 and applies a common voltage, the common electrode CE may include a material having low resistance, such as aluminum (Al), silver (Ag), or copper (Cu).

[0143] The light emitting element LE may receive a pixel voltage or an anode voltage from each of the pixel electrodes PE1, PE2 and PE3, and may receive a common voltage through the common electrode CE. The light emitting element LE may emit light with a predetermined brightness according to a voltage difference between the pixel voltage and the common voltage.

[0144] Meanwhile, the wavelength converter 200 may be disposed on the light emitting element unit LEP. The wavelength converter 200 may include a partition wall PW, a wavelength conversion layer QDL, color filters CF1, CF2, and CF3, a light blocking member BK, and a passivation layer PTL.

[0145] The partition wall PW may be disposed on the common electrode CE of the display area DPA and may separate the plurality of emission areas EA1, EA2, and EA3. The partition wall PW may be disposed to extend in the first direction DR1 and the second direction DR2 and may be formed in a lattice pattern throughout the display area DPA. In addition, the partition wall PW may not overlap with the plurality of emission areas EA1, EA2, and EA3 and may overlap with the non-emission area NEA.

[0146] The partition wall PW may include a plurality of openings OP1, OP2, and OP3 exposing the common electrode CE. The plurality of openings OP1, OP2, and OP3 may include a first opening OP1 overlapping the first emission area EA1, a second opening OP2 overlapping the second emission area EA2, and a third opening OP3 overlapping the third emission area EA3. Here, the plurality of openings OP1, OP2, and OP3 may correspond to the plurality of emission areas EA1, EA2, and EA3, respectively. That is, the first opening OP1 may correspond to the first emission area EA1, the second opening OP2 may correspond to the second emission area EA2, and the third opening OP3 may correspond to the third emission area EA3.

[0147] The partition wall PW may be used as a space for forming a wavelength conversion layer QDL. To this end, the partition wall PW may have a predetermined thickness. For example, the thickness of the partition wall PW may be in the range of about 1 μm to about 10 μm. The partition wall PW may include an organic insulating material to have a predetermined thickness. The organic insulating material may include, for example, epoxy resin, acrylic resin, cardo resin, or imide resin.

[0148] The wavelength conversion layer QDL may be disposed on each of the plurality of openings OP1, OP2, and OP3. The wavelength conversion layer QDL may emit light by converting or shifting the peak wavelength of the incident light to another specific peak wavelength. The wavelength conversion layer QDL may convert a portion of the first blue light emitted from the light emitting element LE into a fourth yellow light. In the wavelength conversion layer QDL, the first light and the fourth light may be mixed to emit a fifth white light. The fifth light may be converted into the first light by the first color filter CF1, into the second light by the second color filter CF2, and into the third light by the third color filter CF3.

[0149] The wavelength conversion layer QDL may be disposed in each of the plurality of openings OP1, OP2, and OP3, and may be disposed to be spaced apart from each other. For example, the wavelength conversion layer QDL may include portions spaced apart from each other. That is, the wavelength conversion layer QDL may be formed in an island pattern of dot shapes spaced apart from each other. For example, the wavelength conversion layer QDL may be disposed in each of the first opening OP1, the second opening OP2, and the third opening OP3 in a one-to-one correspondence. In addition, the wavelength conversion layer QDL may be disposed to overlap with each of the first emission area EA1, the second emission area EA2, and the third emission area EA3. In an embodiment, each of the wavelength conversion layers QDL completely overlaps with the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0150] The wavelength conversion layer QDL may include a first matrix resin BRS1 and first wavelength conversion particles WCP1. The first matrix resin BRS1 may include a light-transmitting organic material. For example, the first matrix resin BRS1 may include epoxy resin, acrylic resin, cardo resin, or imide resin.

[0151] The first wavelength conversion particle WCP1 can convert the first light incident from the light emitting element LE into a fourth light. For example, the first wavelength conversion particle WCP1 can convert the light of the blue wavelength band into the light of the yellow wavelength band. The first wavelength conversion particle WCP1 can be a quantum dot (QD), a quantum rod, a fluorescent material, or a phosphorescent material. For example, a quantum dot can be a particle material that emits a specific color light when an electron transitions from a conduction band to a valence band.

[0152] Quantum dots can be semiconductor nanocrystal materials. Quantum dots can have a specific band gap depending on their composition and size. Therefore, quantum dots can absorb light and then emit light with an inherent wavelength. Examples of semiconductor nanocrystals of quantum dots can include IV group nanocrystals, II-VI group compound nanocrystals, III-V group compound nanocrystals, IV-VI group compound nanocrystals, or combinations thereof.

[0153] The II-VI compounds may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds. The binary compounds may be selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof. The ternary compounds may be selected from the group consisting of InZnP, AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof. The quaternary compound may be selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and mixtures thereof.

[0154] The III-V compound may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds. The binary compound may be selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb and mixtures thereof. The ternary compound may be selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InAlP, InNAs, InNSb, InPAs, InPSb and mixtures thereof. The quaternary compound may be selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb and mixtures thereof.

[0155] IV-VI compounds may be selected from the group consisting of binary compounds, ternary compounds and quaternary compounds. Binary compounds are selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof, and ternary compounds are selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof. Quaternary compounds are selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof. Group IV elements may be selected from the group consisting of Si, Ge and mixtures thereof. Group IV compounds may be binary compounds selected from the group consisting of SiC, SiGe and mixtures thereof.

[0156] The binary compound, ternary compound or quaternary compound may be present in the particle at a uniform concentration, or may be present in the same particle in a state where the concentration distribution is partially different. In addition, the particle may have a core / shell structure in which one quantum dot surrounds another quantum dot. The interface between the core and the shell may have a concentration gradient in which the concentration of the element present in the shell decreases toward the center.

[0157] In an embodiment, the quantum dot has a core-shell structure including a core containing the above-mentioned nanocrystals and a shell surrounding the core. The shell of the quantum dot can be used as a protective layer for maintaining semiconductor properties by preventing chemical denaturation of the core and / or as a charging layer for imparting electrophoretic properties to the quantum dot. The shell can be a single layer or a multilayer. Examples of the shell of the quantum dot can include metal or non-metal oxides, semiconductor compounds, and combinations thereof.

[0158] For example, metal or non-metal oxides can be binary compounds such as SiO 2 、Al 2 O 3 、TiO 2 、ZnO、MnO、Mn 2 O 3 , Mn 3 O 4 , CuO, FeO, Fe 2 O 3 , Fe 3 O 4 , CoO, Co 3 O 4 and NiO; or ternary compounds such as MgAl 2 O 4 、CoFe 2 O 4 、NiFe 2 O 4 and CoMn 2 O 4, but the present disclosure is not limited thereto.

[0159] In addition, the semiconductor compound can be, for example, CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP or AlSb, etc., but is not limited thereto.

[0160] The wavelength conversion layer QDL may further include a scatterer for scattering the light of the light emitting element LE in random directions. The scatterer may have a refractive index different from that of the first matrix resin BRS1 and form an optical interface with the first matrix resin BRS1. For example, the scatterer may be a light scattering particle. The scatterer may be a material capable of scattering at least a portion of the transmitted light, but may be, for example, metal oxide particles or organic particles. Examples of metal oxides may include titanium oxide (TiO 2 )、ZrO 2 ), aluminum oxide (Al 2 O 3 ), indium oxide (In 2 O 3 ), zinc oxide (ZnO) and tin oxide (SnO 2 ). Examples of the material of the organic particles may include acrylic resin and polyurethane resin, etc. Regardless of the incident direction of the incident light, the scatterer may scatter the light in random directions without substantially converting the wavelength of the light.

[0161] In the embodiment, as the thickness of the wavelength conversion layer QDL increases in the third direction DR3, the content of the first wavelength conversion particles WCP1 included in the wavelength conversion layer QDL increases, so that the light conversion efficiency of the wavelength conversion layer QDL increases. Accordingly, the thickness of the wavelength conversion layer QDL can be set in consideration of the light conversion efficiency of the wavelength conversion layer QDL.

[0162] In the above-mentioned wavelength converter 200, a portion of the first light emitted from the light emitting element LE can be converted into a fourth light in the wavelength conversion layer QDL. The wavelength conversion layer QDL can emit a fifth white light, which is a color mixture of the first light and the fourth light. For the fifth light emitted from the wavelength conversion layer QDL, the first color filter CF1 to be described below can transmit only the first light, the second color filter CF2 can transmit only the second light, and the third color filter CF3 can transmit only the third light. Accordingly, the light emitted from the wavelength converter 200 can be blue light, red light, and green light of the first light, the second light, and the third light, respectively, thereby achieving full color.

[0163] A plurality of color filters CF1, CF2, and CF3 may be disposed on the partition wall PW and the wavelength conversion layer QDL. The plurality of color filters CF1, CF2, and CF3 may be disposed to overlap with the plurality of openings OP1, OP2, OP3, and the wavelength conversion layer QDL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3.

[0164] The first color filter CF1 may be disposed to overlap with the first emission area EA1, and a portion of the first color filter CF1 may overlap with the non-emission area NEA. In addition, the first color filter CF1 may be disposed on the first opening OP1 of the partition wall PW to overlap with the first opening OP1, and may partially overlap with the light blocking member BK. The first color filter CF1 may transmit the first light emitted from the light emitting element LE, and absorb or block the second light and the third light. For example, the first color filter CF1 may transmit light of a blue wavelength band, and absorb or block light of other wavelength bands such as green and red.

[0165] The second color filter CF2 may be arranged to overlap with the second emission area EA2, and a portion of the second color filter CF2 may overlap with the non-emission area NEA. In addition, the second color filter CF2 may be arranged on the second opening OP2 of the partition wall PW to overlap with the second opening OP2, and may partially overlap with the light blocking member BK. The second color filter CF2 may transmit the second light, and absorb or block the first light and the third light. For example, the second color filter CF2 may transmit light of a green wavelength band, and absorb or block light of other wavelength bands such as blue and red.

[0166] The third color filter CF3 may be arranged to overlap with the third emission area EA3, and a portion of the third color filter CF3 may overlap with the non-emission area NEA. In addition, the third color filter CF3 may be arranged on the third opening OP3 of the partition wall PW to overlap with the third opening OP3, and may partially overlap with the light blocking member BK. The third color filter CF3 may transmit the third light, and absorb or block the first light and the second light. For example, the third color filter CF3 may transmit light of a red wavelength band, and absorb or block light of other wavelength bands such as blue and green.

[0167] The light blocking member BK may be disposed on the partition wall PW. The light blocking member BK may overlap with the non-emission area NEA to block the transmission of light. Similar to the partition wall PW, the light blocking member BK may be disposed approximately in a lattice shape in a plan view. In an embodiment, the light blocking member BK is disposed to overlap with the partition wall PW and does not overlap with the emission areas EA1, EA2, and EA3. In an embodiment, the light blocking member BK does not overlap with the pixel electrodes (e.g., pixel electrodes PE1, PE2, PE3, etc.).

[0168] In an embodiment, the light blocking member BK includes an organic light blocking material and may be formed by a process of coating and exposing the organic light blocking material. The light blocking member BK may include a dye or pigment having a light blocking property and may be a black matrix. At least a portion of the light blocking member BK may overlap with adjacent color filters CF1, CF2, and CF3, and the color filters CF1, CF2, and CF3 may be disposed on at least a portion of the light blocking member BK.

[0169] External light incident from the outside of the display device 10 may cause distortion in the color reproducibility of the wavelength converter 200. When the light blocking member BK according to the present embodiment is provided on the wavelength converter 200, at least a portion of the external light is absorbed by the light blocking member BK. Accordingly, color distortion caused by reflection of external light can be reduced. In addition, the light blocking member BK can prevent light interference (which causes color mixing) between adjacent emission areas, thereby further increasing color reproducibility.

[0170] The passivation layer PTL may be disposed on the plurality of color filters CF1, CF2, and CF3 and the light blocking member BK. The passivation layer PTL may be disposed on the uppermost portion of the display device 10 to protect the plurality of color filters CF1, CF2, and CF3 and the light blocking member BK at the lower portion. A surface (e.g., a bottom surface of the passivation layer PTL) may be in contact with the top surface of each of the plurality of color filters CF1, CF2, and CF3 and the light blocking member BK.

[0171] The passivation layer PTL may include an inorganic insulating material to protect the plurality of color filters CF1, CF2, and CF3 and the light blocking member BK. For example, the passivation layer PTL may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al x O y ) or aluminum nitride (AlN), but is not limited thereto. The passivation layer PTL may have a predetermined thickness, for example, in the range of about 0.01 μm to about 1 μm. However, the present disclosure is not limited thereto.

[0172] Reference Figure 7 and Figure 8 , the light emitting element LE can have different shapes. For example, Figure 7 In the embodiment, the side surface of the light emitting element LE is inclined at a certain angle and becomes narrower toward the bottom surface of the light emitting element LE; and Figure 8 In the embodiment, the side surfaces of the light emitting element LE are not inclined but straight.

[0173] Fig. 9 is a plan view of a pixel electrode and a light emitting element according to an embodiment. Fig.10 is a plan view of a pixel electrode and a light emitting element according to an embodiment. Fig.11 is a plan view of a pixel electrode and a light emitting element according to an embodiment.

[0174] refer to Fig. 9 , the display area DPA of the display device 10 (see Figure 1 ) may include a plurality of pixels PX. A pixel PX may be defined as a minimum light emitting unit capable of displaying white light.

[0175] Each of the pixels PX may include first to third sub-pixels SPX1, SPX2, and SPX3 that emit light. Each of the sub-pixels SPX1, SPX2, and SPX3 may include a plurality of light-emitting elements LE. In an embodiment of the present disclosure, each of the sub-pixels SPX includes three light-emitting elements LE, but the present disclosure is not limited thereto. Fig.10 and Fig.11 As shown in , each of the sub-pixels SPX may include two light emitting elements LE or four light emitting elements LE. In addition, each of the light emitting elements LE is shown to have a circular shape in a plan view, but the embodiments of the present disclosure are not limited thereto. Each of the light emitting elements LE may have a polygonal shape (such as a triangular shape, a quadrilateral shape, a pentagonal shape, a hexagonal shape, and an octagonal shape), an elliptical shape, or an atypical shape.

[0176] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a rectangular shape with a long side PE-1 positioned in the vertical direction. However, they are not limited thereto and may have a rectangular shape with a short side PE-2 positioned in the vertical direction. The length D of the long side PE-1 of the pixel electrode PE is PE-1 It may be in the range of about 45 μm to about 55 μm. The length D of the short side PE-2 PE-2 It may be in the range of about 6 μm to about 8 μm. For example, the length of the long side PE- 1 of the pixel electrode PE may be about 50 μm, and the length of the short side PE- 2 thereof may be about 7 μm.

[0177] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may have a rectangular shape with a long side PE-1 positioned in the vertical direction. However, they are not limited thereto and may have a rectangular shape with a short side PE-2 positioned in the vertical direction.

[0178] The first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be arranged to be aligned on any line extending in one direction. For example, the pixel electrodes may be arranged in a matrix and may be arranged to be spaced apart from each other by the same first spacing D1. The first spacing D1 is referred to as a separation distance. The separation distance may range from about 18 μm to about 19 μm. For example, the first spacing D1 may be about 19 μm.

[0179] In an embodiment, a ratio of a length of a short side PE- 2 of the pixel electrodes PE1 , PE2 , and PE3 to a separation distance D1 between the pixel electrodes PE1 , PE2 , and PE3 is about 1:1.7 to about 1:1.8.

[0180] A plurality of light emitting elements LE may be disposed on one pixel electrode PE1, PE2, PE3. For example, three light emitting elements LE may be disposed on the first pixel electrode PE1. A plurality of light emitting elements LE may be arranged at the same second spacing D2. For example, the second spacing D2 may be in the range of about 10 μm to about 20 μm. For example, the second spacing D2 may be about 15 μm. For example, the light emitting elements LE may be spaced apart from each other at the same second spacing D2 in the vertical direction.

[0181] Width or diameter D of the light emitting element LE LE It may be in the range of about 8 μm to about 16 μm. In an embodiment, the width or diameter D of the light emitting element LE LE The width or diameter D of the light emitting element LE is longer than the length of the short side PE-2 of the pixel electrodes PE1, PE2 and PE3. For example, the length of the short side PE-2 may be about 7 μm, and the separation distance D1 between the pixel electrodes PE1, PE2 and PE3 may be about 19 μm. LE It can be longer than the length of the short side PE-2 of the pixel electrodes PE1, PE2 and PE3, and can be smaller than the separation distance D1 between the pixel electrodes PE1, PE2 and PE3. In this way, the light emitting element LE does not interfere with the adjacent pixel electrodes. Therefore, the light emission of each sub-pixel SPX can be controlled.

[0182] In the embodiment, the length of the short side PE-2 of the pixel electrodes PE1, PE2 and PE3 is equal to the width or diameter D of the light emitting element LE. LE The ratio is about 1:1.5 to 1:2.3. By setting the length of its short side PE-2 to be smaller than the width or diameter D of the light emitting element LE, LE The pixel electrodes PE1, PE2 and PE3 can prevent the light emitting element LE from being deflected toward the edge of the pixel electrode PE1 and collapsing in the pixel electrode PE1. LEWhen the width or diameter D of the light emitting element LE is sufficiently larger than the length of the short side PE-2 of the pixel electrodes PE1, PE2 and PE3, the light emitting element LE will not collapse even if the light emitting element LE is arranged to be biased toward the edge of the pixel electrode PE1 in the pixel electrode PE1. LE When the width or diameter D of the light emitting element LE is greater than about 2.3 times the length of the short side PE-2 of the pixel electrode PE1, the supporting pixel electrode PE1 becomes very narrow, and thus the alignment of the light emitting element LE may become more difficult. LE When the length of the short side PE-2 of the pixel electrodes PE1, PE2 and PE3 is about 1.5 to 2.3 times, the light emitting element LE can be prevented from collapsing when the light emitting element LE is disposed toward the edge of the pixel electrode PE1 in the pixel electrode PE1.

[0183] In the embodiment, the length of the short side PE-2 of the pixel electrodes PE1, PE2 and PE3 is 1 / 2 of the width or diameter D of the light emitting element LE. LE Small enough so that the light absorption of the pixel electrodes PE1, PE2 and PE3 can be reduced. Therefore, the light output efficiency can be improved. In addition, since the size of the pixel electrodes PE1, PE2 and PE3 is reduced, the moisture penetration reliability or heat resistance reliability due to external characteristics may be reduced.

[0184] Reference Figures 9 to 11 , two to four light emitting elements LE may be disposed on one pixel electrode PE1, PE2, PE3. When less than two light emitting elements LE are disposed, that is, when one light emitting element LE is disposed on one pixel electrode PE1, PE2, PE3, the light emission efficiency may be reduced. In addition, when more than four light emitting elements LE are disposed on one pixel electrode PE1, PE2, PE3, the light emission efficiency may be reduced due to interference between the light emitting elements LE disposed in one pixel electrode.

[0185] Reference Fig.10 , and Fig. 9 The difference is that two light emitting elements LE are provided on each of the pixel electrodes PE. Fig.11 , and Fig. 9 The difference is that four light emitting elements LE are provided on each of the pixel electrodes PE.

[0186] Reference Fig.10 and Fig.11 The lengths of the long side and the short side of the pixel electrode PE can be Fig. 9 For example, the length of the long side PE-1 may be in the range of about 45 μm to about 55 μm. The length of the short side PE-2 may be in the range of about 6 μm to about 8 μm.

[0187] In addition, the first pixel electrode PE1, the second pixel electrode PE2, and the third pixel electrode PE3 may be arranged to be aligned on any line extending in one direction. For example, they may be arranged in a matrix and may be arranged to be spaced apart from each other by the same first spacing D1. The first spacing D1 is referred to as a separation distance. A separation distance may be in the range of about 18 μm to about 19 μm. For example, the first spacing D1 may be about 19 μm.

[0188] In an embodiment, a ratio of a length of a short side PE- 2 of the pixel electrodes PE1 , PE2 , and PE3 to a separation distance between the pixel electrodes PE1 , PE2 , and PE3 is in a range of about 1:1.7 to about 1:1.8.

[0189] Width or diameter D of the light emitting element LE LE It may be in the range of about 8 μm to about 16 μm. As the number of pixel electrodes PE in one pixel decreases, the size of the light emitting element LE may increase, but the present disclosure is not limited thereto.

[0190] Reference Fig. 9 , the light emitting element LE1 can be realized by the light emitting elements LE1-1, LE1-2 and LE1-3.

[0191] Reference Fig.10 When two light emitting elements are disposed on a pixel electrode PE1, PE2, PE3, the width or diameter D of the light emitting element LE is LE The second pitch D2 may be about 15 μm. The plurality of light emitting elements LE may be arranged at the same second pitch D2. For example, the second pitch D2 may be in the range of about 15 μm to about 20 μm. For example, the second pitch D2 may be about 20 μm. Fig.10 The light emitting element LE1 may be implemented by light emitting elements LE1 - 1 and LE1 - 2 .

[0192] Reference Fig.11 When four light emitting elements are disposed on one pixel electrode PE1, PE2, PE3, the width or diameter D of the light emitting element LE is LE The second pitch D2 may be about 15 μm. The plurality of light emitting elements LE may be arranged at the same second pitch D2. For example, the second pitch D2 may be in the range of about 10 μm to about 15 μm. For example, the second pitch D2 may be about 10 μm. Fig.11 The light emitting element LE1 may be implemented by light emitting elements LE1-1, LE1-2, LE1-3, and LE1-4.

[0193] Hereinafter, a manufacturing process of the display device 10 according to the embodiment will be described with reference to other drawings.

[0194] Fig.12is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Figures 13 to 25 is a diagram illustrating a method of manufacturing a display device according to an embodiment.

[0195] Figures 13 to 25 is a diagram showing a display device 10 (see Figure 1 ) is a cross-sectional view of a structure showing the formation order of each layer. Figures 13 to 25 The light emitting element unit LEP (see FIG. Figure 6 ) manufacturing process, and these can be approximately corresponded to Figure 6 In addition, hereinafter, the first emission area EA1 (see Figure 6 ) and the second emission area EA2 (see Figure 6 ).

[0196] Reference Fig.12 According to the embodiment, the method for manufacturing the display device 10 includes a step S100 of forming a plurality of light emitting elements on a base substrate, a step S110 of forming a substrate including a pixel electrode, a step S120 of bonding the plurality of light emitting elements to the pixel electrode, and a step S130 of connecting an organic layer and a common electrode to the light emitting elements.

[0197] First, refer to Fig.13 and Fig.14 , a plurality of light emitting elements LE are formed on the base substrate BSUB.

[0198] Specifically, a base substrate BSUB is prepared. The base substrate BSUB may be sapphire (Al 2 O 3 ) substrate or a silicon wafer containing silicon. Although a case where the base substrate BSUB is a sapphire substrate will be described as an example, embodiments of the present disclosure are not limited thereto.

[0199] A plurality of semiconductor material layers USEL, SEM2L, MQWL and SEM1L are formed on a base substrate BSUB. A plurality of semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, the semiconductor material layer can be formed using one of electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering and metal organic chemical vapor deposition (MOCVD), preferably using metal organic chemical vapor deposition (MOCVD). However, the present disclosure is not limited thereto.

[0200] Generally, the precursor material for forming the plurality of semiconductor material layers can be selected to form the target material within a generally selectable range without any limitation. For example, the precursor material can be a metal precursor including an alkyl group such as a methyl group or an ethyl group. Examples of the precursor material can include, but are not limited to, trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ) and triethyl phosphate ((C 2 H 5 ) 3 PO 4 ).

[0201] Specifically, the third semiconductor material layer USEL is formed on the base substrate BSUB. Although the drawings show that the third semiconductor material layer USEL is stacked in one layer, the present disclosure is not limited thereto, and a plurality of layers may also be formed. The third semiconductor material layer USEL may be configured to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the base substrate BSUB. For example, the third semiconductor material layer USEL may include an undoped semiconductor, and may be a material that is not n-type or p-type doped. In an embodiment, the third semiconductor material layer USEL may be, but is not limited to, at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.

[0202] The second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer USEL by using the above-described method.

[0203] In an embodiment, next, the plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L are etched to form a plurality of light emitting elements LE.

[0204] Specifically, a plurality of first mask patterns MP1 are formed on the first semiconductor material layer SEM1L. The first mask pattern MP1 may be a hard mask including an inorganic material, or a photoresist mask including an organic material. The first mask pattern MP1 prevents the plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L disposed thereunder from being etched. Then, a plurality of light emitting elements LE are formed by partially etching (first etching) the plurality of semiconductor material layers using the plurality of first mask patterns MP1 as masks.

[0205] like Fig.14As shown in FIG. 1 , the plurality of semiconductor material layers USEL, SEM2L, MQWL, and SEM1L not overlapping the first mask pattern MP1 are etched and removed on the base substrate BSUB, and the portions not etched by overlapping the first mask pattern MP1 may be formed into a plurality of light emitting elements LE.

[0206] For example, the process of etching the semiconductor material layer may be performed by a dry etching method, a wet etching method, a reactive ion etching (RIE) method, a deep reactive ion etching (DRIE) method, or an inductively coupled plasma reactive ion etching (ICP-RIE) method, etc. The dry etching method may be suitable for vertical etching because anisotropic etching may be performed. In the case of using the above etching techniques, chlorine gas (Cl 2 ) or oxygen (O 2 ) as an etchant. However, the present disclosure is not limited thereto.

[0207] The plurality of semiconductor material layers USEL, SEM2L, MQWL and SEM1L overlapping the first mask pattern MP1 are not etched and are formed into a plurality of light emitting elements LE. Accordingly, the plurality of light emitting elements LE are formed by including the third semiconductor layer USE, the second semiconductor layer SEM2, the active layer MQW and the first semiconductor layer SEM1.

[0208] In the embodiments, next, refer to Figures 15 to 17 , a first insulating layer and a reflective layer are formed on the side surfaces of the light emitting element LE.

[0209] Specifically, the insulating material layer INSL is formed on the outer surfaces of the plurality of light emitting elements LE. The insulating material layer INSL may be formed on the entire surface of the base substrate BSUB, and not only on the light emitting elements LE but also on the top surface of the base substrate BSUB exposed by the light emitting elements LE.

[0210] Then, a reflective material layer RFLL is formed on the insulating material layer INSL. The reflective material layer RFLL is formed on the entire surface of the base substrate BSUB so that it can be formed not only on the light emitting element LE but also on the top surface of the base substrate BSUB exposed by the light emitting element LE on the insulating material layer INSL.

[0211] In an embodiment, next, a second etch (2nd etch) may be performed to partially remove the insulating material layer INSL and the reflective material layer RFLL to form a first insulating layer INS1 and a side reflective layer RFL1 exposing a top surface of the light emitting element LE.

[0212] Specifically, the second etching (second etching) may be performed to partially remove the insulating material layer INSL and the reflective material layer RFLL so that the insulating material layer INSL and the reflective material layer RFLL surround the side surface of the light emitting element LE while exposing the top surface of the light emitting element LE. Specifically, in this process, the insulating material layer INSL and the reflective material layer RFLL may be partially removed to expose the top surface of the first semiconductor layer SEM1 of the light emitting element LE. The process of partially removing the insulating material layer INSL and the reflective material layer RFLL may be performed by a process such as etchback after dry etching, which is anisotropic etching, but the present disclosure is not limited thereto. Accordingly, a first insulating layer INS1 and a side reflective layer RFL1 surrounding the light emitting element LE may be formed.

[0213] In the embodiments, next, refer to Fig.18 , a second insulating layer INS2 and a connecting electrode 150 of the light emitting element LE are formed.

[0214] Specifically, the second insulating layer INS2 may be formed in the same manner as the manufacturing process of the first insulating layer INS1 described above. For example, an insulating material layer INSL is formed on a base substrate BSUB on which the light emitting element LE is formed, and the second insulating layer INS2 is formed on the outer surface of the light emitting element LE by performing a second etching (second etching) that partially removes the insulating material layer INSL. However, the second insulating layer INS2 may be formed not only on the side surface of the light emitting element LE but also on a portion of its top surface. An opening is defined on the top surface of the light emitting element LE by the second insulating layer INS2.

[0215] The connection electrode 150 is formed on the top surface of the light emitting element LE defined by the second insulating layer INS2. The connection electrode 150 may be formed in the opening by stacking an electrode material layer on the base substrate BSUB and then etching it through an etching process. The connection electrode 150 is formed on the first semiconductor layer SEM1 through the opening.

[0216] Reference Fig.19 , the first support film SPF1 is attached to Fig.18 On a plurality of light emitting elements LE on a base substrate BSUB manufactured in the process.

[0217] Specifically, the first support film SPF1 is attached to the plurality of light emitting elements LE formed on the base substrate BSUB. The first support film SPF1 may be aligned on the plurality of light emitting elements LE and may be attached to each connection electrode 150 of the plurality of light emitting elements LE. The plurality of light emitting elements LE may be provided in a large number and thus may be attached to the first support film SPF1 without separation.

[0218] The first support film SPF1 may be composed of a support layer and an adhesive layer disposed on the support layer. The support layer may be made of a transparent material having mechanical stability to allow light to pass therethrough. For example, the support layer may include a transparent polymer such as polyester, polyacrylic acid, polyepoxy, polyethylene, polystyrene, or polyethylene terephthalate. The adhesive layer may include an adhesive material for bonding the light emitting element LE. For example, the adhesive material may include polyurethane acrylate, epoxy acrylate, or polyester acrylate. The adhesive material may be a material whose bonding strength changes as ultraviolet light (UV) or heat is applied, and thus the adhesive layer may be easily separated from the light emitting element LE.

[0219] Then, refer to Fig. 20 By irradiating the base substrate BSUB with laser light (first laser light), the light emitting element LE is separated from the base substrate BSUB. The base substrate BSUB is separated from each of the third semiconductor layers USE of the plurality of light emitting elements LE.

[0220] The process of separating the base substrate BSUB may be a laser lift-off (LLO) process. In the laser lift-off process using laser, a KrF excimer laser (248 nm wavelength) may be used as a light source. The energy density of the excimer laser may be about 550 mJ / cm 2 About 950mJ / cm 2 The incident area can be about 50×50μm 2 About 1×1cm 2 By irradiating the laser to the base substrate BSUB, the base substrate BSUB may be separated from the light emitting element LE.

[0221] In the embodiments, next, refer to Fig.21 , the first transfer film LFL1 is attached to the plurality of light emitting elements LE separated from the base substrate BSUB.

[0222] Specifically, the first transfer film LFL1 is attached on each of the third semiconductor layers USE of the plurality of light emitting elements LE. The first transfer film LFL1 may be aligned on the plurality of light emitting elements LE and may be attached to each of the third semiconductor layers USE of the plurality of light emitting elements LE.

[0223] The first transfer film LFL1 may include a stretchable material. The stretchable material may include, for example, polyolefin, polyvinyl chloride (PVC), elastomeric silicone, elastomeric polyurethane, or elastomeric polyisoprene. Like the first support film SPF1 described above, the first transfer film LFL1 may also include a support layer and an adhesive layer to adhere and support the plurality of light emitting elements LE. The plurality of light emitting elements LE are arranged to be spaced apart at a predetermined first interval D1.

[0224] Then, refer to Fig. 22 , the first support film SPF1 is separated from the plurality of light emitting elements LE. After UV or heat is applied to the first support film SPF1 to reduce the adhesive strength of the adhesive layer of the first support film SPF1, the first support film SPF1 may be physically or naturally separated. In an embodiment, next, the first transfer film LFL1 (1st ORI) is stretched. The first transfer film LFL1 may be stretched two-dimensionally in the first direction DR1 and the second direction DR2.

[0225] Since the first transfer film LFL1 is stretched, the separation distance between the plurality of light emitting elements LE attached to the first transfer film LFL1 may be greater than Fig.21 The first interval D1 is larger than the second interval D2. Accordingly, the plurality of light emitting elements LE may be arranged in a dot shape on the first transfer film LFL1 at the second interval D2.

[0226] The tensile strength (or tensile strength) of the first transfer film LFL1 may be adjusted according to a desired separation distance between the light emitting elements LE, and may be, for example, about 120 gf / inch. However, the present disclosure is not limited thereto.

[0227] The present embodiment has described an example in which one stretching process is performed, but is not limited thereto. The stretching process may be performed a plurality of times.

[0228] In the embodiments, next, refer to Fig.23 , the first transfer film LFL1 is bonded to the first substrate 110 , and the plurality of light emitting elements LE are adhered to the first pixel electrode PE1 and the second pixel electrode PE2 .

[0229] Specifically, the first transfer film LFL1 is aligned on the first substrate 110. In this case, the connection electrode 150 of the light emitting element LE formed on the first transfer film LFL1 is aligned to face the first substrate 110. Figure 6 As shown in FIG. 1 , the first substrate 110 may have a plurality of pixel electrodes PE1 and PE2 formed thereon.

[0230] In the embodiment, next, the first substrate 110 and the first transfer film LFL1 are bonded together. Specifically, the connection electrode 150 of the light emitting element LE formed on the first transfer film LFL1 is in contact with the pixel electrodes PE1 and PE2 of the first substrate 110. In this case, the connection electrode 150 of the light emitting element LE is in contact with the pixel electrodes PE1 and PE2. Subsequently, the first substrate 110 and the first transfer film LFL1 are bonded by melt-bonding the connection electrode 150 of the light emitting element LE and the pixel electrodes PE1 and PE2. A plurality of light emitting elements LE are bonded to the top surfaces of the pixel electrodes PE1 and PE2.

[0231] In the fusion bonding, the laser may be irradiated to the pixel electrodes PE1 and PE2 from a position above the first substrate 110. The high heat of the laser may be transferred to the pixel electrodes PE1 and PE2 irradiated with the laser, so that the interface between the connection electrode 150 of the light emitting element LE and the pixel electrodes PE1 and PE2 may be bonded. Specifically, the pixel electrodes PE1 and PE2 may include copper (Cu) having excellent thermal conductivity, and may have excellent bonding properties relative to the connection electrode 150 of the light emitting element LE. Yttrium aluminum garnet (YAG) may be used as a laser source for fusion bonding.

[0232] In this case, because the width of the light emitting element LE is greater than that of the pixel electrode PE1, even if the center of the array of light emitting elements LE is shifted from the center of the pixel electrode PE1 and does not coincide therewith, the phenomenon that the light emitting element LE collapses from the pixel electrode PE1 can be minimized.

[0233] Then, the third semiconductor layer USE may be removed by ashing, and a portion of the third semiconductor layer USE may be left.

[0234] In the embodiments, next, refer to Fig.24 , a planarization layer PLL and a common electrode CE are formed on the first substrate 110 , and a light emitting element LE is formed on the first substrate 110 .

[0235] Specifically, a planarization layer PLL may be formed on a plurality of pixel electrodes PE1 and PE2. The planarization layer PLL may be disposed on each emission region and may be disposed to be spaced apart from each other on adjacent emission regions. The planarization layer PLL may be applied using a solution process such as spin coating or inkjet printing and patterned by an exposure process. The planarization layer PLL may be formed to the height of the light emitting element LE, but is not limited thereto.

[0236] Then, refer to Fig.25 , a common electrode CE is formed on the light emitting element LE and the planarization layer PLL. The common electrode CE is continuously formed in the entire display area. The common electrode CE covers the planarization layer PLL and the light emitting element LE and is in direct contact with them. The common electrode CE is formed by directly contacting the top surface of the second semiconductor layer SEM2 of the light emitting element LE.

[0237] Then, if Figure 6 As shown in , the display device 10 according to the embodiment is manufactured by forming a wavelength control layer, a color filter layer, and the like.

[0238] Fig.26 is an exemplary diagram showing a virtual reality device including a display device according to an embodiment. Fig.26A virtual reality device 1 in which the display device 10 according to the embodiment is used is shown.

[0239] Reference Fig.26 The virtual reality device 1 according to the embodiment may be a device in the form of glasses. The virtual reality device 1 according to the embodiment may include a display device 10, a left eye lens 10a, a right eye lens 10b, a support frame 20, left and right temples 30a and 30b, a reflective member 40, and a display device housing 50.

[0240] Fig.26 The virtual reality device 1 including two temples 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to the embodiment may be used in a head mounted display including a head mounted band, and the head mounted band may be mounted on the head instead of the temples 30a and 30b. For example, the virtual reality device 1 according to the embodiment is not limited to Fig.26 The examples shown in and can be applied to various electronic devices in various forms.

[0241] The display device housing 50 can receive the display device 10 and the reflective member 40. The image displayed in the display device 10 can be reflected from the reflective member 40 and provided to the right eye of the user through the right eye lens 10b. Therefore, the user can observe the virtual reality image displayed in the display device 10 through the right eye.

[0242] Fig.26 It is shown that the display device housing 50 is disposed at the right end of the supporting frame 20. However, embodiments of the present disclosure are not limited thereto. For example, the display device housing 50 may be disposed at the left end of the supporting frame 20. In this case, the image displayed in the display device 10 may be reflected from the reflective member 40 and provided to the left eye of the user via the left eye lens 10a. Therefore, the user may observe the virtual reality image displayed in the display device 10 via the left eye. For another example, the display device housing 50 may be disposed at each of the left and right ends of the supporting frame 20. In this case, the user may observe the virtual reality image displayed in the display device 10 via both the left eye and the right eye.

[0243] Fig. 27 is an exemplary diagram illustrating a smart device including a display device according to an embodiment.

[0244] Reference Fig. 27 The display device 10 according to the embodiment may be applied to a smart watch 2 which is one of several smart devices.

[0245] Fig.28 is an exemplary diagram showing a vehicle including a display device according to an embodiment. Fig.28Vehicles in which the display devices 10_a, 10_b, 10_c, 10_d, and 10_e according to the embodiments are used are shown.

[0246] Reference Fig.28 The display devices 10_a, 10_b and 10_c according to the embodiment can be applied to the dashboard of the vehicle, to the central dashboard of the vehicle, or to the CID (Central Information Display) set on the dashboard of the vehicle. In addition, each of the display devices 10_d and 10_e according to the embodiment can be applied to each vehicle interior mirror display replacing each of the side mirrors of the vehicle.

[0247] Fig.29 is an exemplary diagram showing a transparent display device including a display device according to an embodiment.

[0248] Reference Fig.29 , the display device 10 according to the embodiment can be applied to a transparent display device. The transparent display device can transmit light therethrough while displaying an image IM therein. Therefore, a user positioned in front of the transparent display device can observe not only the image IM displayed in the display device 10 but also an object RS or a background positioned behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 6 The first substrate 110 of the display device 10 shown in FIG. Figure 6 ) may include a light-transmitting portion through which light can be transmitted, or may be made of a material through which light can be transmitted.

[0249] Summarizing the above detailed description, those skilled in the art will appreciate that many changes and modifications may be made to the embodiments without departing substantially from the principles of the present disclosure. Therefore, the disclosed embodiments of the present disclosure are used only in a general and descriptive sense, and not for the purpose of limitation.

Claims

1. A display device, wherein: The display device comprises: substrate; a plurality of pixel electrodes disposed on the substrate and spaced apart from each other at a first interval; and A plurality of light emitting elements are respectively arranged on the plurality of pixel electrodes, wherein each of the plurality of pixel electrodes has a rectangular shape having a long side and a short side, and A width of each of the plurality of light emitting elements is greater than a width of the short side and smaller than the first interval between the plurality of pixel electrodes.

2. The display device according to claim 1, wherein: Each of the plurality of light emitting elements includes: a second semiconductor layer; an active layer disposed on the second semiconductor layer; and a first semiconductor layer disposed on the active layer, and The width of the first semiconductor layer is greater than the width of the short side and smaller than the first interval between the plurality of pixel electrodes.

3. The display device according to claim 2, wherein: Each of the plurality of light emitting elements further includes a connection electrode, the connection electrode being disposed on the first semiconductor layer and connected to a corresponding one of the plurality of pixel electrodes, and The width of the connection electrode is greater than the width of the short side of the one pixel electrode and less than the first interval between the plurality of pixel electrodes.

4. The display device according to claim 1, wherein: The width of each of the plurality of light emitting elements is in a range of 8 μm to 16 μm.

5. The display device according to claim 4, wherein: The width of the short side of one of the plurality of pixel electrodes is in a range of 6 μm to 8 μm, The length of the long side of the one pixel electrode is in the range of 45 μm to 55 μm, and The first pitch is in the range of 16 μm to 19 μm.

6. The display device according to claim 3, wherein: The number of the light emitting elements disposed on the one pixel electrode is three, The light emitting elements disposed on the one pixel electrode are spaced apart from each other by a second interval, and The second pitch is in the range of 10 μm to 20 μm.

7. The display device according to claim 3, wherein: The number of the light emitting elements disposed on the one pixel electrode is two, The light emitting elements disposed on the one pixel electrode are spaced apart from each other by a second interval, and The second pitch is in the range of 15 μm to 20 μm.

8. The display device according to claim 3, wherein: The number of the light emitting elements arranged on the one pixel electrode is four, The light emitting elements disposed on the one pixel electrode are spaced apart from each other by a second interval, and The second pitch is in the range of 10 μm to 15 μm.

9. The display device according to claim 5, wherein: The display device further includes: A first planarization layer is arranged on the substrate between the plurality of pixel electrodes; a second planarization layer disposed on the first planarization layer and between the plurality of light emitting elements; and a common electrode, disposed on the second planarization layer and the plurality of light emitting elements; and A wavelength converter is arranged on the common electrode, Wherein, the wavelength converter comprises: A partition wall separating the multiple launch areas; a wavelength conversion layer, disposed between the plurality of partition walls and overlapping the plurality of emission regions; a light blocking member disposed on the partition wall; and a color filter disposed on the wavelength conversion layer, The light blocking member does not overlap with a corresponding one of the plurality of pixel electrodes.

10. The display device according to claim 1, wherein: A ratio of the width of the short side to the first interval is 1:1.7 to 1:1.8.

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