Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a display area and a peripheral area, the peripheral area at least partially surrounds the display area, the peripheral area comprises a first sub-peripheral area, and the display panel is characterized in that the display panel comprises a first substrate, and the first substrate comprises a first substrate; the black matrix and the color resistance parts are arranged on the first substrate, and the color resistance parts are arranged in the display area in an array mode in the first direction and the second direction; the plurality of spacers are arranged on the first substrate; the plurality of spacers comprise a first spacer located in the first sub-peripheral area and a second spacer located in the display area; the second base plate is arranged opposite to the first base plate, and the second base plate comprises a second substrate; the plurality of pixel driving circuits are arranged on the second substrate; the driving chip is arranged on the second substrate and is positioned in the first sub peripheral area; the frame sealing glue is located between the first substrate and the second substrate, and the frame sealing glue surrounds the display area.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display panel and a display device including the display panel. Background Art

[0002] In the manufacturing process of liquid crystal display panels, it is necessary to bind IC (Integrated Circuit Chip) chips on the display panel, and the COG (Chip On Glass) method is generally used to achieve electrical connection between IC and the leads on the glass substrate. IC is mainly combined with the glass substrate through anisotropic conductive film (ACF). Due to the difference in thermal expansion coefficients of the three materials, the glass substrate is prone to deformation and warping after manufacturing, which produces stress on the glass substrate, resulting in light leakage in the product (COG Mura phenomenon).

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore, the above information may contain information that does not constitute the prior art. Summary of the invention

[0004] In one aspect, a display panel is provided, the display panel comprising a display area and a peripheral area, the peripheral area at least partially surrounding the display area, the peripheral area comprising a first sub-peripheral area, the display panel comprising: a first substrate, the first substrate comprising: a first substrate; and a black matrix and a plurality of color resist portions arranged on the first substrate, the plurality of color resist portions being arranged in an array in the display area along a first direction and a second direction; and a plurality of spacers arranged on the first substrate, the plurality of spacers comprising a first spacer located in the first sub-peripheral area and a second spacer located in the display area; a second substrate, the second substrate being arranged opposite to the first substrate, the second substrate comprising: a second substrate; a plurality of pixels arranged on the second substrate A driving circuit, wherein the plurality of pixel driving circuits are arranged in an array in the display area along a first direction and a second direction; and a driving chip disposed on the second substrate, wherein the driving chip is located in the first sub-peripheral area; and a frame sealant, wherein the frame sealant is located between the first substrate and the second substrate, and the frame sealant surrounds the display area, wherein the first spacer is located on a side of the frame sealant away from the display area, and the first spacer is located between the frame sealant and the driving chip in a first direction, wherein the first direction is a direction from the center of the display area to the driving chip; and the display panel also includes a cushioning structure disposed on the first substrate, and the first spacer is located on a side of the cushioning structure facing the second substrate.

[0005] According to some exemplary embodiments, an orthographic projection of the first spacer on the first substrate falls within an orthographic projection of the pad structure on the first substrate.

[0006] According to some exemplary embodiments, an orthographic projection of the first spacer along the first direction and an orthographic projection of the driving chip along the first direction at least partially overlap.

[0007] According to some exemplary embodiments, the first spacer and the frame-sealing glue are spaced apart in a first direction, and a minimum spacing distance between the first spacer and the frame-sealing glue in the first direction is a first spacing distance; the first spacer and the driving chip are spaced apart in the first direction, and a minimum spacing distance between the first spacer and the driving chip in the first direction is a second spacing distance; the first spacing distance is smaller than the second spacing distance.

[0008] According to some exemplary embodiments, the display panel includes a plurality of the first spacers, which are all located between the frame sealing glue and the driving chip in a first direction; and the plurality of the first spacers are spaced apart and distributed in a second direction, and the second direction is perpendicular to the first direction.

[0009] According to some exemplary embodiments, a size of an area where the plurality of first spacers are distributed in the second direction is larger than a size of the driving chip in the second direction.

[0010] According to some exemplary embodiments, the area where the multiple first spacers are distributed includes a first sub-area, a second sub-area and a third sub-area, the second sub-area and the third sub-area are respectively located on both sides of the first sub-area in the second direction, the first sub-area is directly opposite to the driving chip in the first direction; and the ratio of the size of the second sub-area in the second direction to the size of the first sub-area in the second direction is between 0.1 and 0.4; and / or the ratio of the size of the third sub-area in the second direction to the size of the first sub-area in the second direction is between 0.1 and 0.4.

[0011] According to some exemplary embodiments, the area where the multiple first spacers are distributed includes a first sub-area, a second sub-area and a third sub-area, the second sub-area and the third sub-area are respectively located on both sides of the first sub-area in the second direction, and the first sub-area is directly opposite to the driving chip in the first direction; and the multiple first spacers have a first distribution density in the first sub-area, the multiple first spacers have a second distribution density in the second sub-area, and the multiple first spacers have a third distribution density in the third sub-area, the first distribution density is greater than the second distribution density, and the first distribution density is greater than the third distribution density.

[0012] According to some exemplary embodiments, the area where the multiple first spacers are distributed also includes a fourth sub-area and a fifth sub-area, the fourth sub-area is located on the side of the second sub-area away from the first sub-area in the second direction, and the fifth sub-area is located on the side of the third sub-area away from the first sub-area in the second direction; and the multiple first spacers have a fourth distribution density in the fourth sub-area, and the multiple first spacers have a fifth distribution density in the fifth sub-area, the second distribution density is greater than the fourth distribution density, and the third distribution density is greater than the fifth distribution density.

[0013] According to some exemplary embodiments, the second distribution density is equal to the third distribution density; and / or the fourth distribution density is equal to the fifth distribution density.

[0014] According to some exemplary embodiments, a ratio of a size of the second sub-region in the second direction to a size of the first sub-region in the second direction is between 0.1 and 0.4; and / or a ratio of a size of the third sub-region in the second direction to a size of the first sub-region in the second direction is between 0.1 and 0.4.

[0015] According to some exemplary embodiments, a plurality of the first spacers are arranged in a row of spacers in the first direction, and the plurality of the first spacers in the row are arranged at equal intervals in the second direction.

[0016] According to some exemplary embodiments, the plurality of first spacers are arranged in a plurality of rows in the first direction, and the plurality of first spacers in the same row are arranged at equal intervals in the second direction.

[0017] According to some exemplary embodiments, the plurality of first spacers located in two adjacent rows are aligned in the second direction; and / or the plurality of first spacers located in two adjacent rows are staggered in the second direction.

[0018] According to some exemplary embodiments, an orthographic projection of the first spacer on the first substrate has a first size in a first direction and a second size in a second direction, and a ratio of the second size to the first size is greater than 20.

[0019] According to some exemplary embodiments, an orthographic projection of the first spacer on the first substrate has a first size in a first direction and a second size in a second direction, and a ratio of the second size to the first size is less than 5.

[0020] According to some exemplary embodiments, an orthographic projection of the second spacer on the first substrate has a third size in the first direction, and the first size is equal to the third size.

[0021] According to some exemplary embodiments, the first spacer has a first thickness in a third direction, the third direction being perpendicular to the first direction and the second direction; the second spacer has a second thickness in the third direction; and the first thickness is equal to the second thickness.

[0022] According to some exemplary embodiments, an orthographic projection of the second spacer on the first substrate has a fourth size in the first direction, and the second size is equal to the fourth size.

[0023] According to some exemplary embodiments, the pad layer structure includes a first pad layer, and the first pad layer is located in the same layer as the black matrix or the color resist portion located in the display area.

[0024] According to some exemplary embodiments, the pad structure includes a first pad and a second pad, the second pad is located on the side of the first pad facing the second substrate, the first pad and the black matrix in the display area are located on the same layer, and the second pad and the color resistance part in the display area are located on the same layer.

[0025] According to some exemplary embodiments, the first substrate also includes a covering layer located on the side of the color resist portion facing the second substrate; and the pad structure includes a first pad, a second pad and a third pad, the second pad is located on the side of the first pad facing the second substrate, the third pad is located on the side of the second pad facing the second substrate, the first pad and the black matrix located in the display area are located on the same layer, the second pad and the color resist portion located in the display area are located on the same layer, and the third pad and the covering layer located in the display area are located on the same layer.

[0026] According to some exemplary embodiments, an orthographic projection of the first cushion layer on the first substrate and an orthographic projection of the frame sealing adhesive on the first substrate are spaced apart from each other.

[0027] According to some exemplary embodiments, an orthographic projection of the first cushion layer on the first substrate at least partially overlaps with an orthographic projection of the frame sealing adhesive on the first substrate.

[0028] According to some exemplary embodiments, the display panel further includes a groove, the groove is located between the first cushion layer and the black matrix located in the display area, and the orthographic projection of the groove on the first substrate falls within the orthographic projection of the frame sealant on the first substrate.

[0029] In another aspect, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0031] Figure 1 It is a schematic diagram of the principle of warping of a liquid crystal display panel;

[0032] Figure 2 is a schematic plan view of a display substrate according to some exemplary embodiments of the present disclosure;

[0033] Figure 3 is a schematic cross-sectional view of a display panel according to some exemplary embodiments of the present disclosure;

[0034] Figure 4 is a partial cross-sectional schematic diagram of a display panel according to some exemplary embodiments of the present disclosure;

[0035] Figure 5 is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure, wherein the positional relationship between a spacer and a chip in the plan view is schematically shown;

[0036] Figure 6 is a schematic diagram schematically illustrating the relationship between a first spacer and a first spacer wall of a display panel according to some exemplary embodiments of the present disclosure;

[0037] Figure 7 is a schematic diagram schematically illustrating a distribution density of spacers of a display panel according to some exemplary embodiments of the present disclosure;

[0038] Figure 8 is a schematic diagram schematically illustrating another distribution density of spacers of a display panel according to some exemplary embodiments of the present disclosure;

[0039] Fig. 9 is a partial cross-sectional schematic diagram of a display panel according to some other exemplary embodiments of the present disclosure;

[0040] Fig.10 is a schematic plan view of a display panel according to some other exemplary embodiments of the present disclosure;

[0041] Fig.11 is a schematic diagram schematically showing the arrangement of spacers of a display panel according to other exemplary embodiments of the present disclosure;

[0042] Fig.12 is a schematic diagram schematically showing the arrangement of spacer walls of a display panel according to other exemplary embodiments of the present disclosure;

[0043] Fig.13 is a schematic diagram schematically illustrating another distribution density of spacers of a display panel according to other exemplary embodiments of the present disclosure;

[0044] Fig.14 is a schematic diagram schematically illustrating another distribution density of spacers of a display panel according to other exemplary embodiments of the present disclosure;

[0045] Fig.15 is a partial cross-sectional schematic diagram of a display panel according to some further exemplary embodiments of the present disclosure;

[0046] Fig.16 is a schematic plan view of a display panel according to some further exemplary embodiments of the present disclosure;

[0047] Fig.17 is a schematic diagram schematically showing the arrangement of spacers of a display panel according to some further exemplary embodiments of the present disclosure;

[0048] Fig.18 is a schematic diagram schematically showing the arrangement of spacer walls of a display panel according to some further exemplary embodiments of the present disclosure;

[0049] Fig.19 is a schematic diagram schematically showing another distribution density of spacers of a display panel according to some further exemplary embodiments of the present disclosure;

[0050] Fig. 20 is a schematic diagram schematically illustrating another distribution density of spacers of a display panel according to some further exemplary embodiments of the present disclosure;

[0051] Fig.21 is a statistical diagram of effects between display panels according to some exemplary embodiments of the present disclosure and display panels of comparative examples; and

[0052] Fig. 22 is a statistical diagram of effects between display panels according to some other exemplary embodiments of the present disclosure and display panels of comparative examples. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0054] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0055] When an element is described as being "on" another element, "connected to" another element or "coupled to" another element, the element may be directly on the other element, directly connected to the other element or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent" or "on..." versus "directly on...", etc. In addition, the term "connection" may refer to a physical connection, an electrical connection, a communication connection and / or a fluid connection. In addition, the X-axis, the Y-axis and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, YZ, and XZ. As used herein, the term "and / or" includes any and all combinations of one or more of the listed associated items.

[0056] It should be noted that, although the terms "first", "second", etc. may be used herein to describe various parts, components, elements, regions, layers and / or parts, these parts, components, elements, regions, layers and / or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and / or part from another. Thus, for example, the first part, first member, first element, first region, first layer and / or first part discussed below may be referred to as the second part, second member, second element, second region, second layer and / or second part without departing from the teachings of the present disclosure.

[0057] For ease of description, spatial relational terms, such as "upper", "lower", "left", "right", etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, elements described as "below" or "beneath" other elements or features will be oriented "above" or "above" the other elements or features.

[0058] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0059] It should be noted that, in this article, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. Usually, multiple elements, components, structures and / or parts located in the "same layer" have approximately the same thickness.

[0060] In the present disclosure, the functions of the "source electrode" and the "drain electrode" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0061] In the present disclosure, "electrical connection" includes the case where the components are directly connected, and also includes the case where they are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can control the electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having one or more functions.

[0062] In the present disclosure, "parallel" refers to a state where the angle formed by two straight lines is greater than 10° and less than 10°, and therefore, a state where the angle is greater than 5° and less than 5° may be included. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, a state where the angle is greater than 85° and less than 95° may be included.

[0063] The COG process refers to adding IC and leads to the LCD display screen, and using ACF to directly bond the IC to the LCD screen through hot pressing.

[0064] COG Mura refers to the deformation and warping of the glass substrate after the COG process due to the difference in thermal expansion coefficients of different materials. Therefore, when the LCD panel is working, the surface of the pixel matrix is ​​displayed imperfectly, that is, the visual effect is uneven due to the difference in pixels in the local area near the driver chip in the LCD panel.

[0065] The gap problem refers to the fact that the liquid crystal display panel has a color film substrate and an array substrate, and there is a certain gap between the two substrates. The liquid crystal is filled in this gap, and the height of the gap is called the liquid crystal box thickness. When power is applied to the electrodes of the two substrates, the voltage will be applied to the liquid crystal through the electrodes on the two substrates, changing the arrangement of the liquid crystal molecules, thereby realizing image display. However, due to the deformation and warping of the array substrate (glass substrate), the liquid crystal box thickness is uneven, resulting in the problem of uneven brightness of the liquid crystal display panel.

[0066] Figure 1 This is a schematic diagram of the principle of warping of the LCD panel; refer to Figure 1In ultra-thin and ultra-narrow bezel products, the COG Mura problem greatly restricts the product display effect. Since the distance between the driver chip (IC) and the display area AA is small, COG Mura will occur after the COG process. As the resolution of display products continues to increase, the distance between the driver chip and the display area is reduced, and the influence of deformation on the display area increases. The driver chip is bound to the glass substrate through ACF. During hot pressing, the driver chip is squeezed toward the side close to the glass substrate by the hot pressing tool. At this time, the driver chip, ACF and glass substrate are deformed by pressure; when the hot pressing is just over, the driver chip, ACF and glass substrate expand due to heat, so the thickness of the driver chip, ACF and glass substrate increases; when the temperature of the driver chip, ACF and glass substrate returns to normal temperature, due to the difference in thermal expansion coefficients of different materials, the shrinkage of the driver chip is greater than that of the glass substrate, resulting in the glass substrate deforming and warping first, thereby causing the display panel to warp. The warping phenomenon causes a slight change in the orientation of the liquid crystal near the driver chip, which affects the polarization direction of the emitted light and is not completely perpendicular to the polarization direction of the upper load point power supply, resulting in light leakage in the display panel (i.e., COGMura).

[0067] Figure 2 is a schematic diagram showing a substrate; Figure 2 The display substrate in this embodiment includes a display area AA and a peripheral area NA at least partially surrounding the display area AA. The display substrate may include a first side S1, a second side S2, a third side S3 and a fourth side S4. The first side S1 and the second side S2 may be arranged opposite to each other, and the third side S3 and the fourth side S4 may be arranged opposite to each other. For example, Figure 1 In the illustrated embodiment, the first side S1 and the second side S2 may be the right side and the left side of the display substrate, respectively, and the third side S3 and the fourth side S4 may be the lower side and the upper side of the display substrate, respectively.

[0068] It should be noted that the left side, right side, top side and bottom side here may be: the left side, right side, top side and bottom side of the display substrate (screen) viewed by human eyes during display.

[0069] Continue to refer to Figure 1 The display substrate may include a gate driving circuit 5 and a driving chip 4 located in the peripheral area NA. For example, the gate driving circuit 5 may be located on at least one side of the display substrate. Figure 1 In the embodiment shown, the gate driving circuit 5 is located at the first side S1 and the second side S2 of the display substrate. For example, the driving chip 4 may be located at least on one side of the display area AA. Figure 1 In the illustrated embodiment, the driving chip 4 is located on the third side S3 of the display substrate.

[0070] The gate driving circuit 5 may be implemented by a shift register, and the gate driving circuit 5 may provide a scanning signal to each gate line GL on the display substrate. The driving chip 4 may include a data driving circuit, and the data driving circuit may provide a data signal to each data line DL on the display substrate.

[0071] It should be noted that although Figure 1 It is shown that the gate driving circuit 5 is located at the left and right sides of the display area, and the driving chip 4 is located at the lower side of the display area AA. However, the embodiments of the present disclosure are not limited to this. The gate driving circuit 5 and the driving chip 4 can be located at any suitable position in the peripheral area NA.

[0072] For example, the gate driver circuit 5 can adopt the GOA technology, i.e., Gate Driver on Array. In the GOA technology, the gate driver circuit 5 is directly arranged on the array substrate to replace the external chip. Each GOA unit serves as a first-level shift register, and each level of shift register is connected to a gate line. The scanning signal is output in turn through the shift registers at all levels to realize the line-by-line scanning of the pixel unit. In some embodiments, each level of shift register can also be connected to a plurality of gate lines. In this way, it can adapt to the development trend of high resolution and narrow frame of the display substrate.

[0073] The display substrate may further include a second substrate 110 and a plurality of pixel units P disposed on the second substrate 110 and located in the display area AA. The plurality of pixel units P are arranged in an array along a second direction X and a first direction Y, and the second direction X intersects the first direction Y. For example, the second direction X is Figure 1 The horizontal direction in the first direction Y is Figure 1 The vertical direction in the second direction X and the first direction Y, that is, the second direction X and the first direction Y are perpendicular to each other.

[0074] At least one pixel unit P includes a plurality of sub-pixels SP, and the plurality of sub-pixels SP can display different colors through corresponding color filters. For example, the plurality of sub-pixels SP in one pixel unit P may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel can match a red color filter to display red light, the second sub-pixel can match a green color filter to display green light, and the third sub-pixel can match a blue color filter to display blue light.

[0075] It should be noted that Figure 2 The shape of the positive projection of the sub-pixel on the substrate is shown as a rectangle, but the embodiments of the present disclosure are not limited to this. Moreover, the arrangement of the three sub-pixels in a pixel unit P is not limited to Figure 2 The method shown in .

[0076] The display substrate may further include a plurality of data lines DL and a plurality of gate lines GL disposed on the second substrate 10. Figure 1 As shown, at least one of the plurality of data lines DL may extend from the fourth side S4 to the third side S3, thereby being electrically connected to the driving chip 4 located on the third side S3. At least one of the plurality of data lines DL may extend from the first side S1 to the second side S2, thereby being electrically connected to the gate driving circuit 5 located on the first side S1 or the second side S2.

[0077] In the embodiment of the present disclosure, a plurality of data lines DL are arranged at intervals along the second direction X, for example, the plurality of data lines DL are electrically connected to a plurality of columns of sub-pixels SP, respectively. A plurality of gate lines GL are arranged at intervals along the first direction Y, for example, the plurality of gate lines GL are electrically connected to a plurality of rows of sub-pixels SP, respectively.

[0078] Figure 3 is a schematic cross-sectional view of the display panel 100. Figure 3 , the display panel 100 may include a display substrate and a sealant 2. For example, the display panel 100 may include a first substrate, a second substrate and a liquid crystal layer 13. The first substrate may include a first substrate 110 and a color film element disposed on the first substrate 110. That is, the first substrate may be a color film substrate. The second substrate may have the structure of the above-mentioned display substrate. On this basis, the second substrate may include a second substrate 120, the first substrate 110 and the first substrate 110 are arranged opposite to each other, and the second substrate 120 is located below the first substrate 110, and the liquid crystal layer 13 is sandwiched between the first substrate 110 and the second substrate 120. The driving chip 4 is arranged on the second substrate 120 through the anisotropic conductive adhesive film 3. The sealant 2 is surrounded by the peripheral side of the liquid crystal layer 13, and the sealant 2 is located between the first substrate 110 and the second substrate 120.

[0079] Figure 4 is a schematic cross-sectional view of a display panel 100 according to some exemplary embodiments of the present disclosure. Figure 3 and Figure 4, an embodiment of the present disclosure provides a display panel 100, the display panel 100 includes: a display area AA and a peripheral area NA, the peripheral area NA at least partially surrounds the display area AA, the peripheral area NA includes a third side, the display panel 100 includes: a first substrate 11, the first substrate 11 includes: a first substrate 110; and a black matrix 10 and a plurality of color resist portions 20 disposed on the first substrate 110, the plurality of color resist portions 20 are arranged in an array in the display area AA along a first direction and a second direction; and a plurality of spacers disposed on the first substrate 110, the plurality of spacers include a first spacer 31 located in the first sub-peripheral area (for example, a partial peripheral area located on the third side) and a second spacer 32 located in the display area AA; a second substrate 12, the second substrate 12 is disposed opposite to the first substrate 11, the second substrate 12 includes: a second substrate 120; a A plurality of pixel driving circuits 6 on the second substrate 120, the plurality of pixel driving circuits 6 are arranged in an array in the display area AA along a first direction and a second direction; and a driving chip 4 arranged on the second substrate 120, the driving chip 4 being located in the first sub-peripheral area; and a frame sealant 2, the frame sealant 2 being located between the first substrate 11 and the second substrate 12, the frame sealant 2 surrounding the display area AA, wherein the first spacer 31 is located on a side of the frame sealant 2 away from the display area AA, and the first spacer 31 is located between the frame sealant 2 and the driving chip 4 in a first direction, wherein the first direction is a direction from the center of the display area AA to the driving chip 4; and the display panel 100 also includes a cushioning structure 40 arranged on the first substrate 110, the first spacer 31 being located on a side of the cushioning structure 40 facing the second substrate 12. In the embodiment of the present disclosure, the cushion structure 40 and the first spacer 31 provided in the first sub-peripheral region cooperate to form an effective support between the first substrate 11 and the second substrate 12, which has a certain buffering function, so that the second substrate 12 is not easily deformed and warped after the COG process. At the same time, the cushion structure 40 can reduce the step difference between the two ends of the first spacer 31 and the first substrate 11 and the second substrate 12, respectively, so that the buffering effect of the first spacer 31 between the first substrate 11 and the second substrate 12 is better.

[0080] Figure 5 is a schematic plan view of a display panel 100 according to some exemplary embodiments of the present disclosure. Figure 4 and Figure 5The display panel 100 includes: a display area AA and a peripheral area NA, wherein the peripheral area NA at least partially surrounds the display area AA, and the peripheral area NA includes a first side S1, a second side S2, a third side S3, and a fourth side S4. The first side S1 and the second side S2 may be arranged opposite to each other, and the third side S3 and the fourth side S4 may be arranged opposite to each other. For example, Figure 4 In the illustrated embodiment, the first side S1 and the second side S2 may be the right side and the left side of the display panel 100 , respectively, and the third side S3 and the fourth side S4 may be the lower side and the upper side of the display panel 100 , respectively.

[0081] The display panel 100 may include a pad structure 40 disposed on the first substrate 110 , and the first spacer 31 is located on a side of the pad structure 40 facing the second substrate 12 .

[0082] Specifically, the plurality of color resist portions 20 include: red sub-pixels, green sub-pixels and blue sub-pixels. A plurality of black matrices 10 are provided, wherein a portion of the black matrices 10 are arranged in an array along the first direction and the second direction in the display area AA, and the black matrix 10 is arranged between two adjacent sub-pixels; another portion of the black matrix 10 is arranged in the peripheral area NA and arranged along the peripheral side of the display area AA, and the frame sealant 2 is arranged on a side of the black matrix 10 close to the second substrate 120.

[0083] For example, the plurality of color resist portions 20 may include color resist portions of a red sub-pixel, a green sub-pixel, a blue sub-pixel and / or a white sub-pixel, and the black matrix 10 is disposed between two adjacent sub-pixels.

[0084] In the embodiment of the present disclosure, the first substrate 11 further includes a covering layer 120 located on the side of the color resist portion 20 facing the second substrate 12 . The covering layer 120 is coated on the color resist portion 20 with a negative photoresist material. A passivation layer 130 is provided on the side of the covering layer 120 close to the second substrate 120 .

[0085] For example, the passivation layer 130 can be made of non-polar materials SiO2 or Si3N4, or can be made of organic materials PI (polyimide) or BCB (benzocyclobutene). For example, in the embodiment of the present disclosure, the passivation layer 130 can be made of PI.

[0086] It should be noted that the material of the passivation layer 130 is not specifically limited in the embodiment of the present disclosure, and the above materials can be selected to prepare the passivation layer 130 according to actual production conditions.

[0087] In some exemplary embodiments, the pad structure 40 may include a first pad 41 , and the first pad 41 is located in the same layer as the black matrix 10 or the color resist portion 20 located in the display area AA.

[0088] In other exemplary embodiments, the pad structure 40 may include a first pad 41 and a second pad 42, the second pad 42 is located on the side of the first pad 41 facing the second substrate 12, the first pad 41 and the black matrix 10 located in the display area AA are located on the same layer, and the second pad 42 and the color resist portion 20 located in the display area AA are located on the same layer.

[0089] In some further exemplary embodiments, the pad structure 40 may further include a first pad 41, a second pad 42 and a third pad 43, wherein the second pad 42 is located on the side of the first pad 41 facing the second substrate 12, the third pad 43 is located on the side of the second pad 42 facing the second substrate 12, the first pad 41 and the black matrix 10 located in the display area AA are located on the same layer, the second pad 42 and the color resist portion 20 located in the display area AA are located on the same layer, and the third pad 43 and the covering layer 120 located in the display area AA are located on the same layer.

[0090] Specifically, the first pad layer 41 is a black matrix 10, the second pad layer 42 is a color resist layer, and the third pad layer 43 is a flat layer. The black matrix 10 connected to the spacer is located in the same layer as the black matrix 10 in the display area AA, the color resist layer and the color resist portion 20 are located in the same layer, and the flat layer and the cover layer 120 are located in the same layer. The color resist layer can be a color resist portion of any one of a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel. The third pad layer 43 is coated on the surface of the second pad layer 42 with a negative photoresist material. The widths of the first pad layer 41, the second pad layer 42, and the third pad layer 43 in the first direction are equal.

[0091] It should be noted that in the embodiment of the present disclosure, the pad structure 40 may be either the black matrix 10 or the color resist layer, or may be a combination of the black matrix 10 and the color resist layer. However, the embodiment of the present disclosure does not specifically limit the combination relationship of the black matrix 10, the color resist layer, and the planar layer.

[0092] It can be understood that through the assembly relationship of the first pad layer 41, the second pad layer 42 and the third pad layer 43 in the pad structure 40, the gap between the first spacer 31 and the second substrate 120 can be reduced, thereby forming better support between the first substrate 11 and the second substrate 12, suppressing the warping of the second substrate 12, and also improving the Gap problem of the display panel 100.

[0093] In some embodiments of the present disclosure, the orthographic projection of the first cushion layer 41 on the first substrate 110 is spaced apart from the orthographic projection of the frame sealing glue 2 on the first substrate 110 .

[0094] Specifically, in the peripheral area NA, the black matrix 10 connected to the first spacer 31 and the black matrix 10 connected to the frame sealant 2 are arranged at intervals, and the two black matrices 10 are arranged discontinuously. The discontinuously arranged black matrix 10 can ensure that ESD (i.e., electrostatic discharge) does not enter the display area AA. The cover layer 120 and the passivation layer 130 are both arranged protruding from the display area AA, and the side of the black matrix 10 connected to the frame sealant 2 close to the display area AA is located in the cover layer 120.

[0095] In some other exemplary embodiments of the present disclosure, the orthographic projection of the first cushion layer 41 on the first substrate 110 at least partially overlaps with the orthographic projection of the frame sealing glue 2 on the first substrate 110 .

[0096] In the embodiment of the present disclosure, the orthographic projection of the first spacer 31 on the first substrate 110 falls within the orthographic projection of the cushion structure 40 on the first substrate 110 .

[0097] Specifically, a side surface of the first spacer 31 that is close to the driver chip 4 and perpendicular to the first direction does not protrude from the first pad layer 41, and the width of the first spacer 31 in the first direction is smaller than the width of the pad structure 40 in the first direction. For example, in the embodiment of the present disclosure, the vertical section of the first spacer 31 is an inverted trapezoid, and the cross-sectional area of ​​the end of the first spacer 31 close to the second substrate 120 is smaller than the cross-sectional area of ​​the end of the first spacer 31 close to the first substrate 110.

[0098] It should be noted that the shape of the vertical section of the first spacer 31 in the embodiment of the present disclosure may also be a rectangle; however, the embodiment of the present disclosure does not specifically limit the shape of the first spacer 31 .

[0099] Figure 6 Schematic diagram of the relationship between the spacers and the spacer walls of the display panel according to some exemplary embodiments of the present disclosure. Figure 4-Figure 6 In the embodiment of the present disclosure, the display panel 100 includes a plurality of first spacers 31, and the plurality of first spacers 31 are all located between the sealant 2 and the driver chip 4 in the first direction; and the plurality of first spacers 31 are spaced apart in the second direction, and the second direction is perpendicular to the first direction. For example, the first direction may be the Y direction, and the second direction may be the X direction

[0100] The plurality of first spacers 31 are arranged in a row of spacers in the first direction, and the plurality of first spacers 31 in a row are arranged at equal intervals in the second direction.

[0101] Due to the influence of the temperature field around the driving chip 4 , the size L1 of the area where the first spacers 31 are distributed in the second direction is larger than the size L2 of the driving chip 4 in the second direction.

[0102] Specifically, the length L1 of the area of ​​the first spacer 31 distributed in the second direction is greater than the length L2 of the driving chip 4 in the second direction, and the length of the display area AA in the second direction is greater than the length of the first spacer 31 in the second direction.

[0103] For example, the center of the area where the plurality of first spacers 31 are distributed and the center of the driver chip 4 are located on an axis arranged along the first direction. The two ends of the area where the plurality of first spacers 31 are distributed are respectively and equidistantly protruded from the two ends of the driver chip 4. The size L2 of the driver chip 4 in the second direction is 30-35μm, and the size L1 of the area where the plurality of first spacers 31 are distributed in the second direction is 42-49μm. When the size L1 of the driver chip 4 in the second direction is 30μm, the size L1 of the area where the plurality of first spacers 31 are distributed in the second direction is 42μm; when the size L2 of the driver chip 4 in the second direction is 35μm, the size L1 of the area where the plurality of first spacers 31 are distributed in the second direction is 49μm. The distance between the end of the area where the plurality of first spacers 31 are distributed and the end of the driver chip 4 located on the same side is the influence distance L3, and the length of the influence distance L3 is 20% of the size of the driver chip 4 in the second direction.

[0104] It should be noted that the temperature field around the driver chip 4 has an influence range of 20% of the length of the driver chip 4 (ie, the second dimension). For example, the length of the driver chip 4 is in the range of 30 to 35 mm. Figure 5 The heat affected zone of the driver chip is defined as the interval corresponding to L1, and the L1 value is 20% of the length of the driver chip to the left and right respectively. This area is the impact area of ​​the driver chip on the glass substrate after binding, that is, the warping range. In the embodiment of the present disclosure, the effective support position of the first spacer is located in the heat affected zone of the driver chip with a length in the X direction, so as to effectively improve the warping effect. In some embodiments of the present disclosure, the first spacer 31 and the frame sealant 2 are spaced apart in the first direction, and the minimum spacing distance between the first spacer 31 and the frame sealant 2 in the first direction is the first spacing distance D1; the first spacer 31 and the driver chip 4 are spaced apart in the first direction, and the minimum spacing distance between the first spacer 31 and the driver chip 4 in the first direction is the second spacing distance D2; the first spacing distance D1 is less than the second spacing distance D2.

[0105] In some other embodiments of the present disclosure, the orthographic projection of the first spacer 31 on the first substrate 110 has a first size C1 in the first direction and a second size in the second direction, and the ratio of the second size to the first size C1 is less than 5.

[0106] For example, the first size C1 of the first spacer 31 may be 9.5 μm. The embodiment of the present disclosure does not specifically limit the sizes of the first size C1 and the second size, as long as the ratio of the second size to the first size C1 is less than 5.

[0107] In some other disclosed embodiments, the display panel 100 includes a plurality of first spacer walls 33. The plurality of first spacer walls 33 are connected along the second direction to form a spacer wall. The plurality of first spacer walls 33 are arranged in a row in the first direction, and the plurality of first spacer walls 33 in a row are arranged at equal intervals in the second direction. The plurality of first spacer walls 33 are all located between the frame sealant 2 and the driving chip 4 in the first direction; and the plurality of first spacer walls 33 are spaced apart in the second direction, and the second direction is perpendicular to the first direction.

[0108] Due to the influence of the temperature field around the driver chip 4 , the size L2 of the area where the plurality of first spacer walls 33 are distributed in the second direction is larger than the size L1 of the driver chip 4 in the second direction.

[0109] Specifically, the length L1 of the area of ​​the first spacer wall 33 distributed in the second direction is greater than the length L2 of the driving chip 4 in the second direction, and the length of the display area AA in the second direction is greater than the length of the first spacer 31 in the second direction.

[0110] For example, the center of the area where the multiple first spacer walls 33 are distributed and the center of the driver chip 4 are located on an axis arranged along the first direction. The two ends of the area where the multiple first spacer walls 33 are distributed are respectively equidistantly protruding from the two ends of the driver chip 4. The size L2 of the driver chip 4 in the second direction is 30-35μm, and the size of the area where the multiple first spacer walls 33 are distributed in the second direction is 42-49μm. When the size of the driver chip 4 in the second direction is 30μm, the size of the area of ​​the multiple first spacer walls 33 in the second direction is 42μm; when the size of the driver chip 4 in the second direction is 35μm, the size of the multiple first spacer walls 33 in the second direction is 49μm. The distance between the end of the area of ​​the multiple first spacer walls 33 and the end of the driver chip 4 located on the same side is the influence distance L3, and the length of the influence distance L3 is 20% of the size of the driver chip 4 in the second direction.

[0111] In some embodiments of the present disclosure, the first spacer wall 33 and the frame sealing glue 2 are spaced apart in the first direction, and the minimum spacing distance between the first spacer wall 33 and the frame sealing glue 2 in the first direction is a first spacing distance D1; the first spacer wall 33 and the driving chip 4 are spaced apart in the first direction, and the minimum spacing distance between the first spacer wall 33 and the driving chip 4 in the first direction is a second spacing distance D2; the first spacing distance D1 is smaller than the second spacing distance D2.

[0112] In some embodiments of the present disclosure, the orthographic projection of the first spacer wall 33 on the first substrate 110 has a first size C5 in the first direction and a second size C6 in the second direction, and the ratio of the second size to the first size C1 is greater than 20.

[0113] For example, the first dimension C5 of the first spacer wall 33 may be 9.5 μm, and the second dimension C6 may be 300 μm. The disclosed embodiment does not specifically limit the sizes of the first dimension C5 and the second dimension C6, as long as the ratio of the second dimension C6 to the first dimension C5 is greater than 20.

[0114] Figure 7 FIG. 1 is another schematic diagram of the distribution density of the spacers of the display panel according to some exemplary embodiments of the present disclosure. Figure 7 , the area where the multiple first spacers 31 are distributed includes a first sub-area A1, a second sub-area A2 and a third sub-area A3, the second sub-area A2 and the third sub-area A3 are respectively located on both sides of the first sub-area A1 in the second direction, and the first sub-area A1 is directly opposite to the driving chip 4 in the first direction; and the multiple first spacers 31 have a first distribution density in the first sub-area A1, the multiple first spacers 31 have a second distribution density in the second sub-area A2, and the multiple first spacers 31 have a third distribution density in the third sub-area A3, the first distribution density is greater than the second distribution density, and the first distribution density is greater than the third distribution density.

[0115] In some exemplary embodiments of the present disclosure, a ratio of a size of the second sub-region A2 in the second direction to a size of the first sub-region A1 in the second direction is between 0.1 and 0.4.

[0116] In some exemplary embodiments of the present disclosure, a ratio of a size of the third sub-region A3 in the second direction to a size of the first sub-region A1 in the second direction is between 0.1 and 0.4.

[0117] For example, when the size of the driving chip 4 in the second direction is 30μm, the size of the first sub-region A1 in the second direction may be 30μm, the size of the second sub-region A2 in the second direction may be 3μm, and the size of the third sub-region A3 in the second direction may be 3μm; when the size of the driving chip 4 in the second direction is 30μm, the size of the first sub-region A1 in the second direction may be 30μm, the size of the second sub-region A2 in the second direction may be 0.12μm, and the size of the third sub-region A3 in the second direction may be 0.12μm.

[0118] Specifically, the second distribution density is equal to the third distribution density.

[0119] It should be noted that the size of the third sub-area A3 in the second direction may be equal to or unequal to the size of the second sub-area A2 in the second direction. The embodiment of the present disclosure does not specifically limit whether the size of the third sub-area A3 in the second direction is equal to the size of the second sub-area A2 in the second direction.

[0120] Figure 8 FIG. 2 is a schematic diagram of another distribution density of spacers of a display panel according to some exemplary embodiments of the present disclosure. Figure 8 In some other embodiments of the present disclosure, the area where the multiple first spacers 31 are distributed also includes a fourth sub-area A4 and a fifth sub-area A5, the fourth sub-area A4 is located on the side of the second sub-area A2 away from the first sub-area A1 in the second direction, and the fifth sub-area A5 is located on the side of the third sub-area A3 away from the first sub-area A1 in the second direction; and the multiple first spacers 31 have a fourth distribution density in the fourth sub-area A4, and the multiple first spacers 31 have a fifth distribution density in the fifth sub-area A5, the second distribution density is greater than the fourth distribution density, and the third distribution density is greater than the fifth distribution density.

[0121] Specifically, the size of the fourth sub-region A4 in the second direction is equal to the size of the fifth sub-region A5 in the second direction; the fourth distribution density is equal to the fifth distribution density.

[0122] The arrangement pitch between two adjacent first spacers 31 in the influence distance L3 and the first sub-area A1 is 10-50 μm, and the arrangement pitch between two adjacent first spacers 31 outside the two influence distances L3 is greater than 50 μm.

[0123] In some embodiments of the present disclosure, the orthographic projection of the second spacer 32 on the first substrate 110 has a third size C3 in the first direction, and the first size C1 is equal to the third size C3.

[0124] In some embodiments of the present disclosure, the orthographic projection of the second spacer 32 on the first substrate 110 has a fourth dimension in the second direction, and the second dimension C2 is equal to the fourth dimension C4.

[0125] In some embodiments of the present disclosure, the first spacer 31 has a first thickness H1 in a third direction, which is perpendicular to the first direction and the second direction; the second spacer 32 has a second thickness H2 in the third direction; and the first thickness H1 is equal to the second thickness H2.

[0126] For example, the first spacer 31 in the peripheral area NA and the second spacer 32 in the display area AA are equal in size and are arranged in parallel along the first direction.

[0127] Continue to refer to Figure 4 A support structure 50 is provided on a side of the second substrate 120 close to the first substrate 110 , and the support structure 50 is located in the peripheral area NA.

[0128] In some embodiments of the present disclosure, the orthographic projection of the first spacer 31 on the first substrate 110 falls within the orthographic projection of the support structure 50 on the first substrate 110. The support structure 50 is located on a side of the first spacer 31 close to the second substrate 120.

[0129] The support structure 50 can further reduce the gap between the first spacer 31 and the second substrate 120 , thereby providing better support between the first substrate 11 and the second substrate 12 , suppressing the warping of the second substrate 12 , and improving the gap problem of the display panel 100 .

[0130] The support structure 50 may include a first support layer 51, a second support layer 52, and a third support layer 53. For example, the first support layer 51 may be a non-metallic protective layer, the second support layer 52 may be a non-metallic protective layer, and the third support layer 53 may also be a non-metallic protective layer. The second support layer 52 is located on a side of the first support layer 51 close to the first substrate 110, and the third support layer 53 is located on a side of the second support layer 52 close to the first substrate 110.

[0131] A pixel driving circuit 6 is provided on a side of the second substrate 120 close to the first substrate 110. The pixel driving circuit 6 is located in the display area AA. The pixel driving circuit 6 includes a gate 61 provided on the second substrate 120; a gate insulating layer 62 provided on a side of the gate 61 away from the second substrate 120; an active layer 63 provided on a side of the gate insulating layer 62 away from the second substrate 120; a source electrode 64 and a drain electrode 65 provided on a side of the active layer 63 away from the second substrate 120; wherein the source electrode 64 and the drain electrode 65 are respectively arranged on both sides of the active layer 63, the side of the source electrode 64 away from the active layer 63 is connected to the gate insulating layer 62, and the side of the drain electrode 65 away from the second substrate 120 is connected to the gate insulating layer 62. One side of the active layer 63 is connected to the gate insulating layer 62, the source 64 is arranged on the side close to the driver chip 4, and the drain 65 is arranged on the side away from the driver chip 4; a second non-metallic protective layer 52 is arranged on the side of the source 64 and the drain 65 away from the second substrate 120; a passivation layer 130 is arranged on the side of the second non-metallic protective layer 52 away from the second substrate 120; a first conductive electrode 66 is arranged on the side of the drain 65 away from the source 64, the first conductive electrode 66 is located between the second non-metallic protective layer 52 and the gate insulating layer 62, and a second conductive electrode 67 is arranged on the side of the second non-metallic protective layer 52 away from the second substrate 120.

[0132] Fig. 9 is a schematic cross-sectional view of a display panel according to some other exemplary embodiments of the present disclosure; Fig.10 is a front view of a display panel according to some other exemplary embodiments of the present disclosure; Fig.11 Schematic diagram of the layout of spacers of display panels according to other exemplary embodiments of the present disclosure. Figure 9-11 The embodiment shown is different from the above-mentioned embodiment in that Figure 9-11 The same aspects of the illustrated embodiment as those of the above-mentioned embodiment will not be described again, and reference may be made to the detailed description of the above-mentioned embodiment.

[0133] Reference Fig. 9 , Fig.10 and Fig.11 In an embodiment of the present disclosure, the display panel 100 includes a plurality of first spacers 31 , which are arranged into a plurality of rows in a first direction, and a plurality of first spacers 31 in the same row are arranged at equal intervals in a second direction.

[0134] In the embodiment of the present disclosure, a plurality of first spacers 31 located in two adjacent rows are aligned in the second direction.

[0135] For example, two rows of spacers are used as an example for description. The areas where the two rows of first spacers 31 are distributed have the same size in the second direction, and the multiple first spacers 31 in each row correspond to each other one by one.

[0136] like Fig. 9 As shown, the display panel 100 further includes a groove 7 , which is located between the first cushion layer 41 and the black matrix 10 located in the display area AA, and the orthographic projection of the groove 7 on the first substrate 110 falls within the orthographic projection of the frame sealant 2 on the first substrate 110 .

[0137] Specifically, the black matrix 10 connected to the first spacer 31 and the black matrix 10 connected to the frame sealant 2 in the peripheral area NA are continuously arranged, and the groove 7 is opened on the continuous black matrix 10 to ensure that ESD does not enter the display area AA.

[0138] Fig.12 Schematic diagram of the layout of the spacer wall of the display panel according to other exemplary embodiments of the present disclosure. Fig.12 The display panel 100 may further include a plurality of rows of first spacer walls 33, the plurality of rows of first spacer walls 33 are arranged in the first direction to form a plurality of rows of spacers, and the plurality of first spacer walls 33 in the same row are arranged at equal intervals in the second direction. Each first spacer wall 33 includes a plurality of first spacers 31, and the plurality of first spacers 31 are connected along the second direction to form the first spacer wall 33.

[0139] In the embodiment of the present disclosure, the plurality of first spacer walls 33 located in two adjacent rows are aligned in the second direction. Two rows of spacers are used as an example for explanation. The areas where the two rows of first spacer walls 33 are distributed are equal in size in the second direction, and the plurality of first spacer walls 33 in each row correspond to each other.

[0140] Fig.13 is a schematic diagram of another distribution density of spacers of a display panel according to some other exemplary embodiments of the present disclosure; Fig.14 FIG. 2 is a schematic diagram of another distribution density of spacers of a display panel according to other exemplary embodiments of the present disclosure. Fig.13 and Fig.14 , the figure schematically shows two rows of spacers, and the distribution density of each row of spacers is the same as the distribution of the single row of spacers mentioned above.

[0141] Fig.15 is a schematic cross-sectional view of a display panel according to some further exemplary embodiments of the present disclosure; Fig.16 is a front view of a display panel according to some further exemplary embodiments of the present disclosure; Fig.17 Schematic diagram of the layout of spacers of display panels according to some other exemplary embodiments of the present disclosure. Figure 15-17 The embodiment shown is different from the above-mentioned embodiment in that Figure 15-17The same aspects of the illustrated embodiment as those of the above-mentioned embodiment will not be described again, and reference may be made to the detailed description of the above-mentioned embodiment.

[0142] In the embodiments of the present disclosure, referring to Fig.15 , Fig.16 and Fig.17 The display panel 100 includes a plurality of first spacers 31 , which are arranged into a plurality of rows in the first direction, and the plurality of first spacers 31 in the same row are arranged at equal intervals in the second direction.

[0143] In the embodiment of the present disclosure, the plurality of first spacers 31 located in two adjacent rows are arranged alternately in the second direction.

[0144] For example, two rows of spacers are used as an example for description. The areas where the two rows of first spacers 31 are distributed have equal sizes in the second direction, and the distances between the first spacers 31 in one row of spacers and the adjacent two first spacers 31 in the other row of spacers are equal.

[0145] Fig.18 Schematic diagram of the layout of the spacer wall 33 of the display panel 100 according to some other exemplary embodiments of the present disclosure. Fig.18 The display panel 100 may further include multiple rows of first spacer walls 33, which are arranged in the first direction to form multiple rows of spacers, and multiple first spacer walls 33 in the same row are arranged at equal intervals in the second direction. Each first spacer wall 33 includes multiple first spacers 31, and multiple first spacers 31 are connected along the second direction to form the first spacer wall 33; multiple second spacers 32 are connected along the second direction to form the second spacer wall.

[0146] In the embodiment of the present disclosure, a plurality of first spacer walls 33 located in two adjacent rows are arranged alternately in the second direction. Two rows of spacers are used as an example for description. The areas where the two rows of first spacer walls 33 are distributed are equal in size in the second direction, and the distance between the first spacer 31 in one row of first spacer walls 33 and the adjacent two first spacer 31 in another row of first spacer walls 33 is equal.

[0147] Fig.19 is a schematic diagram of another distribution density of spacers of a display panel according to some further exemplary embodiments of the present disclosure; Fig. 20 FIG. 1 is a schematic diagram of another distribution density of spacers of a display panel according to some further exemplary embodiments of the present disclosure. Fig.19 and Fig. 20, the figure schematically shows two rows of first spacer walls 33, and the distribution density of each row of first spacer walls 33 is the same as the distribution mode of the single row of spacers mentioned above. It can be understood that the spacers are not only helpful in preventing the display panel 100 from warping, but also helpful in preventing the frame sealant 2 from overflowing. At the same time, first spacers 31 with different density gradients are set in the second direction. Since the periphery close to the driver chip 4 is greatly affected by the temperature field, the distribution density of the first spacers 31 close to the driver chip 4 is large, so that the warping of the display panel 100 can be further and better suppressed.

[0148] Fig.21 is a statistical diagram of effects between display panels according to some exemplary embodiments of the present disclosure and display panels of comparative examples; Fig. 22 is a statistical diagram of effects between display panels according to some other exemplary embodiments of the present disclosure and display panels of comparative examples.

[0149] Reference Fig.21 , the above Figure 4 The display panel is used as the display panel in the first embodiment. Figure 4 The display panel without spacers is used as the display panel in the comparative example. The same number of display panels in Example 1 and the comparative example are tested, and the following results are obtained: Fig.21 The results are shown. The horizontal axis represents the level of COG Mura, and the higher the level value, the more serious the COG Mura. For example, L1 shows that the COG Mura level of the display panel is more serious than that of L0.5. The vertical axis represents the percentage of the number of display panels with COG Mura levels between two adjacent levels to the total number.

[0150] Depend on Fig.21 The analysis shows that the COG Mura levels of the display panels in Example 1 are all reduced to below L1, and the levels of L1 and below are reduced by 24%; the number of display panels in Example 1 with zero reference (0%) is increased from 19% to 30%. It can be seen that setting a single row of spacers is beneficial to prevent the display panel from warping.

[0151] Reference Fig. 22 , the above Fig.15 The display panel is used as the display panel in the second embodiment. Fig.15 The display panel without spacers is used as the display panel in the comparative example. The same number of display panels in Example 2 and the comparative example are tested, and the following results are obtained: Fig. 22 Results shown.

[0152] Depend on Fig. 22The analysis shows that the COG Mura levels of the display panels of the second embodiment are all reduced to below L1.5, and the level of L1.5 and below is reduced by 10%; the number of display panels of the second embodiment with zero reference (0%) is increased from 36.70% to 75%; the number of display panels of the second embodiment exceeding the L1 level is only 3%. It can be seen that the provision of double-row staggered first spacers 31 is conducive to preventing the display panel from warping.

[0153] Some exemplary embodiments of the present disclosure further provide a display device, wherein the display device includes the display panel as described above.

[0154] It should be understood that the display device according to some exemplary embodiments of the present disclosure has all the features and advantages of the above-mentioned display panel, and these features and advantages can be referred to the above description of the display panel, which will not be repeated here.

[0155] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, the scope of which is defined by the claims and their equivalents.

Claims

1. A display panel, comprising a display area and a peripheral area, wherein the peripheral area at least partially surrounds the display area, and the peripheral area comprises a first sub-peripheral area, wherein: The display panel comprises: A first substrate, the first substrate comprising: a first substrate; and A black matrix and a plurality of color resist portions are disposed on the first substrate, wherein the plurality of color resist portions are arranged in an array in the display area along a first direction and a second direction; and A plurality of spacers disposed on the first substrate, the plurality of spacers comprising a first spacer located in the first sub-peripheral area and a second spacer located in the display area; A second substrate, the second substrate is arranged opposite to the first substrate, and the second substrate comprises: a second substrate; A plurality of pixel driving circuits are disposed on the second substrate, and the plurality of pixel driving circuits are arranged in an array in the display area along a first direction and a second direction; and A driving chip disposed on the second substrate, wherein the driving chip is located in the first sub-peripheral area; as well as A frame sealant, the frame sealant is located between the first substrate and the second substrate, and the frame sealant surrounds the display area. The first spacer is located on a side of the frame sealant away from the display area, and the first spacer is located between the frame sealant and the driver chip in a first direction, wherein the first direction is a direction from the center of the display area to the driver chip; and The display panel further includes a pad structure disposed on the first substrate, and the first spacer is located on a side of the pad structure facing the second substrate.

2. The display panel according to claim 1, wherein: The orthographic projection of the first spacer on the first substrate falls within the orthographic projection of the cushion layer structure on the first substrate.

3. The display panel according to claim 1 or 2, wherein: An orthographic projection of the first spacer along the first direction and an orthographic projection of the driving chip along the first direction at least partially overlap.

4. The display panel according to claim 3, wherein: The first spacer and the frame sealant are spaced apart in a first direction, and a minimum spacing distance between the first spacer and the frame sealant in the first direction is a first spacing distance; The first spacer and the driver chip are spaced apart in the first direction, and the minimum spacing distance between the first spacer and the driver chip in the first direction is a second spacing distance; and The first spacing distance is smaller than the second spacing distance.

5. The display panel according to claim 4, wherein: The display panel includes a plurality of the first spacers, and the plurality of the first spacers are all located between the frame sealant and the driving chip in a first direction; as well as The plurality of first spacers are spaced apart and distributed in a second direction, and the second direction is perpendicular to the first direction.

6. The display panel according to any one of claims 1-2 and 4-5, wherein: The size of the area where the first spacers are distributed in the second direction is larger than the size of the driving chip in the second direction.

7. The display panel according to any one of claims 1.2 and 4-5, wherein: The area where the first spacers are distributed includes a first sub-area, a second sub-area and a third sub-area, the second sub-area and the third sub-area are respectively located on both sides of the first sub-area in the second direction, and the first sub-area is directly opposite to the driving chip in the first direction; as well as The ratio of the size of the second sub-region in the second direction to the size of the first sub-region in the second direction is between 0.1 and 0.4; and / or the ratio of the size of the third sub-region in the second direction to the size of the first sub-region in the second direction is between 0.1 and 0.

4.

8. The display panel according to any one of claims 1-2 and 4-5, wherein: The area where the first spacers are distributed includes a first sub-area, a second sub-area and a third sub-area, the second sub-area and the third sub-area are respectively located on both sides of the first sub-area in the second direction, and the first sub-area is directly opposite to the driving chip in the first direction; as well as Multiple first spacers have a first distribution density in the first sub-region, multiple first spacers have a second distribution density in the second sub-region, and multiple first spacers have a third distribution density in the third sub-region, the first distribution density is greater than the second distribution density, and the first distribution density is greater than the third distribution density.

9. The display panel according to claim 8, wherein: The region where the first spacers are distributed further includes a fourth sub-region and a fifth sub-region, wherein the fourth sub-region is located on a side of the second sub-region away from the first sub-region in the second direction, and the fifth sub-region is located on a side of the third sub-region away from the first sub-region in the second direction; as well as The plurality of first spacers have a fourth distribution density in the fourth sub-region, the plurality of first spacers have a fifth distribution density in the fifth sub-region, the second distribution density is greater than the fourth distribution density, and the third distribution density is greater than the fifth distribution density.

10. The display panel according to claim 9, wherein: The second distribution density is equal to the third distribution density; and / or, The fourth distribution density is equal to the fifth distribution density.

11. The display panel according to claim 10, wherein: The ratio of the size of the second sub-region in the second direction to the size of the first sub-region in the second direction is between 0.1 and 0.4; and / or, A ratio of a size of the third sub-region in the second direction to a size of the first sub-region in the second direction is between 0.1 and 0.

4.

12. The display panel according to any one of claims 1-2 and 4-5, wherein: The plurality of first spacers are arranged in a row of spacers in the first direction, and the plurality of first spacers in the row are arranged at equal intervals in the second direction.

13. The display panel according to any one of claims 1-2 and 4-5, wherein: The plurality of first spacers are arranged in a plurality of rows in the first direction, and the plurality of first spacers in the same row are arranged at equal intervals in the second direction.

14. The display panel according to claim 13, wherein: A plurality of first spacers located in two adjacent rows are aligned in the second direction; and / or, A plurality of first spacers located in two adjacent rows are arranged alternately in the second direction.

15. The display panel according to any one of claims 1-2 and 4-5, wherein: The orthographic projection of the first spacer on the first substrate has a first size in the first direction and a second size in the second direction, and a ratio of the second size to the first size is greater than 20.

16. The display panel according to any one of claims 1-2 and 4-5, wherein: The orthographic projection of the first spacer on the first substrate has a first size in the first direction and a second size in the second direction, and a ratio of the second size to the first size is less than 5.

17. The display panel according to claim 15 or 16, wherein: An orthographic projection of the second spacer on the first substrate has a third size in the first direction, and the first size is equal to the third size.

18. The display panel according to any one of claims 1-2 and 4-5, wherein: The first spacer has a first thickness in a third direction, and the third direction is perpendicular to the first direction and the second direction; The second spacer has a second thickness in the third direction; and The first thickness is equal to the second thickness.

19. The display panel according to claim 16, wherein: An orthographic projection of the second spacer on the first substrate has a fourth size in the second direction, and the second size is equal to the fourth size.

20. The display panel according to any one of claims 1-2 and 4-5, wherein: The pad layer structure includes a first pad layer, and the first pad layer is located in the same layer as the black matrix or the color resistance part located in the display area.

21. The display panel according to claim 20, wherein: The pad structure includes a first pad and a second pad. The second pad is located on the side of the first pad facing the second substrate. The first pad and the black matrix in the display area are located on the same layer. The second pad and the color resistance part in the display area are located on the same layer.

22. The display panel according to claim 20, wherein: The first substrate further comprises a covering layer located on a side of the color resist portion facing the second substrate; as well as The pad structure includes a first pad, a second pad and a third pad, the second pad is located on the side of the first pad facing the second substrate, the third pad is located on the side of the second pad facing the second substrate, the first pad and the black matrix located in the display area are located on the same layer, the second pad and the color resistance part located in the display area are located on the same layer, and the third pad and the covering layer located in the display area are located on the same layer.

23. The display panel according to claim 21 or 22, wherein: The orthographic projection of the first cushion layer on the first substrate is spaced apart from the orthographic projection of the frame sealing adhesive on the first substrate.

24. The display panel according to claim 21 or 22, wherein: The orthographic projection of the first cushion layer on the first substrate at least partially overlaps with the orthographic projection of the frame sealing adhesive on the first substrate.

25. The display panel according to claim 24, wherein: The display panel further includes a groove, wherein the groove is located between the first cushion layer and a black matrix located in the display area, and an orthographic projection of the groove on the first substrate falls within an orthographic projection of the frame sealant on the first substrate.

26. A display device comprising the display panel according to any one of claims 1-25.

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