Command batching for the memory subsystem

Abstract

The present application relates to command batching for a memory subsystem. A memory subsystem may receive multiple commands for multiple transfer units of the memory subsystem and generate a list of the multiple transfer units, the list including pointers between the multiple transfer units. The memory subsystem may store at least one pointer of the list in a shared memory shared by multiple cores, the at least one pointer indicating the next transfer unit in the list. The memory subsystem may send an indicator of a first transfer unit of the list based on storing the at least one pointer in the shared memory, and retrieve the multiple transfer units from the shared memory based on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is a Chinese invention patent application with the title “Command batch processing for memory subsystem”, filed on February 26, 2021, and application number 202110220629.7.

[0003] Cross-references

[0004] This patent application claims priority to U.S. patent application No. 16 / 809,360, filed by Traver et al. on March 4, 2020, entitled “COMMAND BATCHING FOR A MEMORY SUB-SYSTEM,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0005] The technical field relates to command batching for memory subsystems. Background Art

[0006] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0007] A method is described. The method may include receiving a plurality of commands for a plurality of transfer units of a memory subsystem; generating a list of the plurality of transfer units, the list including pointers between the plurality of transfer units; storing at least one pointer of the list in a shared memory shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list; sending an indicator of a first transfer unit of the list from an input / output core to a processing core based at least in part on storing the at least one pointer in the shared memory; and retrieving the plurality of transfer units from the shared memory based at least in part on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

[0008] A system is described. The system may include a plurality of memory devices and a processing device operatively coupled to the plurality of memory devices to perform the following operations: receive a plurality of commands for a plurality of transfer units of a memory subsystem; generate a list of the plurality of transfer units, the list including pointers between the plurality of transfer units; store at least one pointer of the list in a shared memory shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list; send an indicator of a first transfer unit of the list from an input / output core to a processing core based at least in part on storing the at least one pointer in the shared memory; and retrieve the plurality of transfer units from the shared memory based at least in part on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory.

[0009] A non-transitory computer-readable storage medium is described. The non-transitory computer-readable storage medium may include instructions that, when executed by a processing device, cause the processing device to: receive a plurality of commands for a plurality of transfer units of a memory subsystem; generate a list of the plurality of transfer units, the list including pointers between the plurality of transfer units; store at least one pointer of the list in a shared memory shared by a plurality of cores, the at least one pointer indicating a next transfer unit of the list; send an indicator of a first transfer unit of the list from an input / output core to a processing core based at least in part on storing the at least one pointer in the shared memory; and retrieve the plurality of transfer units from the shared memory based at least in part on sending the indicator of the first transfer unit and storing the at least one pointer in the shared memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to the specific embodiments, but are only for explanation and understanding.

[0011] Figure 1 An example of a computing system including a memory subsystem according to some examples of the present disclosure is shown.

[0012] Figure 2 is a diagram of an example method for supporting command batching for a memory subsystem according to some examples of the present disclosure.

[0013] Figure 3 is a block diagram of an example method for supporting command batching for a memory subsystem according to some examples of the present disclosure.

[0014] Figure 4is a block diagram of an example computer system that supports command batching for a memory subsystem according to some examples of the present disclosure. DETAILED DESCRIPTION

[0015] Aspects of the present disclosure relate to command batching for a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of a storage device and a memory module. Figure 1 Examples of storage devices and memory modules are described. Generally speaking, a host system can utilize a memory subsystem that includes one or more components, such as memory devices, that store data. The host system can provide data for storage at the memory subsystem and can request retrieval of data from the memory subsystem.

[0016] The memory device may be a nonvolatile memory device. A nonvolatile memory device is a package of one or more dies. Each die may be composed of one or more planes. For some types of nonvolatile memory devices (e.g., NAND devices), each plane is composed of a set of physical transfer units, such as blocks. Each block is composed of a set of pages. Each page is composed of a set of memory cells that store data bits.

[0017] In some memory subsystems, each write command can be submitted to the memory subsystem's cursor one by one in order for the write operation to proceed. The cursor can be included in the media translation layer and can be used to abstract the data layout and write order of the media. For example, the cursor can be used to ensure that data is written to the memory cell range indicated in the command. In this case, the cursor can receive and process each write command serially. For example, a single data block, also called a transfer unit, can be inserted into a write operation request. The memory subsystem's processing core can then process a single transfer unit at a time.

[0018] If the write commands are directed to the same page or across multiple page boundaries, serially receiving and processing each individual write command may be inefficient, which may increase latency in performing future write operations on the data block. Such techniques (e.g., submitting and processing write commands serially) may cause the memory device to experience a performance loss and an increased number of individual write commands submitted and processed, which may increase signaling overhead and / or processing overhead for performing write operations. A memory subsystem that batches write commands may improve overall memory subsystem performance as the number of submitted write commands is reduced, which may result in increased processing time associated with performing write operations.

[0019] Aspects of the present disclosure address these and other issues by using command batching for memory devices. For example, a list of transfer units can be generated such that the list contains pointers between each transfer unit. In this case, the list can be an instance of a linked list. The pointers to the linked list and the transfer units can be stored in a shared memory. Instead of sending each individual transfer unit as described with reference to some memory subsystems, the memory subsystem can send an indicator of the first transfer unit of the linked list to the processing core. The indicator can be an instance of an internal data description and control block that can be used to pass user data information and data between hardware and firmware components. The transfer unit can then be retrieved from the shared memory based on the indicator associated with the first transfer unit of the linked list. In this case, subsequent transfer units can be retrieved from the shared memory based on the indicator indicating the next transfer unit of the linked list and the stored pointer.

[0020] By generating a linked list and sending an indicator referencing the linked list between processing cores, the overall performance of the memory subsystem can be improved. For example, by sending fewer messages (e.g., only the first node of the linked list) and / or sending shorter messages (e.g., only an indicator) between processing cores, command batching can improve the overall efficiency of the memory subsystem. Once the indicator is received, the memory subsystem (e.g., a cursor of a conversion layer) can retrieve information and / or pointers from the shared memory. The conversion layer can be between the front-end layer and the back-end layer that process user data in the transmission unit. The conversion layer can be an example of a media conversion layer, such as a flash conversion layer (FTL). The cursor can be included in the conversion layer and can be used to abstract the data layout and write order of the media. Such technology can enable the memory subsystem to experience improved read, write and erase speeds and / or reduced power consumption, improved processing time, etc.

[0021] First, in reference Figure 1 The features of the present disclosure are described in the context of the computing environment described. Figure 2 and 3 Features of the present disclosure are described in the context of the methods and block diagrams described herein. Figure 4 These and other features of the present disclosure are further illustrated and described in connection with a computer system for command batching of a memory subsystem.

[0022] Figure 1 An example computing system 100 is shown that includes a memory subsystem 110 according to some embodiments of the present disclosure. The computing environment may include a host system 105 and a memory subsystem 110. The memory subsystem 110 may include media such as one or more non-volatile memory devices (e.g., memory device 130), one or more volatile memory devices (e.g., memory device 140), or a combination thereof.

[0023] The memory subsystem 110 can be a storage device, a memory module, or a combination of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile DIMMs (NVDIMMs).

[0024] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0025] Computing system 100 can include a host system 105 coupled with one or more memory subsystems 110. In some examples, host system 105 is coupled with memory subsystems 110 of different types. Figure 1 An example of a host system 105 is shown coupled to a memory subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0026] The host system 105 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 105 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0027] The host system 105 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), or any other interface. The physical host interface can be used to transfer data between the host system 105 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 105 via a PCIe interface, the host system 105 can further utilize a Non-Volatile Memory Express (NVMe) interface to access components (e.g., the memory device 130). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 105 . Figure 1 Memory subsystem 110 is shown as an example. In general, processor 120 (eg, a host system) can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0028] Memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic RAM (DRAM) and synchronous DRAM (SDRAM).

[0029] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND-type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory can be combined with a stackable cross-grid data access array to store bits based on changes in bulk resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memory can perform write-in-place operations, in which non-volatile memory cells can be programmed without first erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0030] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell, for example, a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and penta-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, or any combination of such memory cell arrays. In some embodiments, a particular memory device may include an SLC portion of memory cells, and an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0031] Although nonvolatile memory components such as a 3D cross-point array of nonvolatile memory cells and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase-change memory (PCM), selectable memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0032] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data at the memory device 130, as well as other such operations. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or other suitable processor.

[0033] The memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in a local memory 125. In the example shown, the local memory 125 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 105.

[0034] In some examples, local memory 125 may include memory registers that store memory pointers, fetched data, etc. Local memory 125 may also include ROM for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been shown as including a memory subsystem controller 115, but in another example of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0035] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 105 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 and / or the memory device 140. The memory subsystem controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include host interface circuitry to communicate with the host system 105 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 130 and / or the memory device 140, and convert responses associated with the memory device 130 and / or the memory device 140 into information for the host system 105.

[0036] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0037] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) to perform media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0038] A memory device may include one or more memory cells, such as NAND memory cells (e.g., NAND flash memory cells). Such memory cells can remain in a charged or uncharged state for a long time. Whether a memory cell is in a charged or uncharged state represents a logical value (e.g., a logical "0" or a logical "1") stored in the cell. Multiple NAND cells can be strung together, and a string can be replicated multiple times in a single block. Each column of cells may be referred to as a "string," and each row may be referred to as a "page." Multiple strings and multiple pages of NAND cells may be collectively referred to as a "block."

[0039] Although NAND cells are capable of remaining in a charged or uncharged state for extended periods, each cell has a finite lifespan. Every time a NAND cell is written to, it is first erased. Erasing a NAND cell can degrade its physical components over time, causing the cell to be associated with a finite number of write and erase operations.

[0040] A data block (e.g., a transfer unit) may contain pages with valid data and pages that do not contain data (e.g., pages that have been previously erased but not yet written). The valid data may then be written (e.g., overwritten) to the memory device (e.g., to a different page of the memory device). To write valid data to a certain location (e.g., a different page of the memory device), the memory controller issues write commands, each of which indicates a memory address (e.g., a destination memory address) to which the valid data is to be written.

[0041] The memory subsystem 110 includes a link manager 150 that can receive commands for transfer units of the memory subsystem 110 and generate a linked list of transfer units. The memory device can use the transfer units to access the memory units. In some cases, the transfer units can be of a different size than the memory block requested by the host system 105. The linked list can include one or more transfer units (e.g., nodes of the linked list) and pointers between the transfer units. In this case, the link manager 150 can link the transfer units to each other via the pointers. The link manager 150 can store the pointers of the linked list in a shared memory accessible by the processor 120. For example, the pointers can be stored separately from the transfer units in the shared memory.

[0042] In some cases, link manager 150 may send an indicator of a transmission unit of the linked list to a processing core of processor 120. In this case, the transmission unit may be retrieved from the shared memory based on the indicator, and the pointer stored in the shared memory may be retrieved. In this case, the indicator sent to the processing core indicates the corresponding transmission unit of the linked list and the pointer associated with the transmission unit.

[0043] In some examples, the memory subsystem controller 115 includes at least a portion of the link manager 150. For example, the memory subsystem controller 115 may include a processor 120 (e.g., a processing device) configured to execute instructions stored in the local memory 125 for performing the operations described herein. In some examples, the link manager 150 is part of the host system 105, an application, or an operating system.

[0044] Link manager 150 may receive multiple transfer units simultaneously or over a period of time. In this case, link manager 150 may link the multiple transfer units to each other via one or more pointers indicating the next transfer unit in the linked list. Link manager 150 may also receive multiple write commands simultaneously or over a period of time. Link manager 150 may process multiple write commands in parallel across page or multi-page boundaries. This parallel processing can reduce the number of times link manager 150 can access each area of ​​the memory subsystem (e.g., NAND), thereby improving performance and reliability. More details regarding the operation of link manager 150 are described below.

[0045] Figure 2 is a diagram of an example method 200 for supporting command batching for a memory subsystem according to some examples of the present disclosure. The method 200 may be performed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the method 200 may be performed by Figure 1 The processes are executed by the link manager 150. Although shown in a particular order or sequence, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated examples should be understood as examples only, and the illustrated processes may be performed in a different order, and some processes may be performed in parallel. In addition, one or more processes may be omitted in various examples. Therefore, not all processes are required in every example. Other process flows are also possible.

[0046] At operation 205, the processing device of the front-end manager may receive a command for a transfer unit. For example, the processing device may receive multiple commands for multiple transfer units of the memory subsystem. The command may be an example of a write command. The command may be received from a host device. In some examples, as shown in FIG. Figure 1 As described, aspects of the operation of 205 may be performed by the link manager 150 .

[0047] In operation 210, the processing device may link the transmission units into a linked list. For example, the processing device of the front-end manager may generate a linked list of multiple transmission units, the linked list including pointers between the multiple transmission units. The pointers between the transmission units may indicate the next transmission unit in the linked list of transmission units. The processing device may set the order of the transmission units in the linked list based on determining the next transmission unit in the linked list. The next transmission unit may be determined based on the order in which the write command is received. In some cases, the next transmission unit may be determined based on determining that the write address of the next transmission unit is adjacent to the write address of the first transmission unit. In addition, the pointer associated with the first TU may point to a second TU that is the next TU in the linked list.

[0048] In some instances, an indicator may be added to at least one internal command, also referred to as a backend command or B-command. For example, method 200 may include assigning a plurality of transfer units in a linked list to at least one B-command based on retrieving a plurality of transfer units to write data to a memory device of a memory subsystem. In some instances, a processing core of a conversion manager may determine that a certain field of a B-command is full. In this case, method 200 may include determining that a plurality of fields of at least one internal command are occupied (e.g., full) based on assigning a plurality of transfer units to at least one internal command. If the B-command is full, the conversion manager may send the B-command to a backend manager. For example, method 200 may include sending at least one internal command to a memory device (e.g., a backend manager) based on determining that a plurality of fields of at least one internal command are occupied. In some instances, the links between the plurality of transfer units in the linked list may be independent of the host command. In some instances, as described in reference to Figure 1 As described, aspects of the operation of 210 may be performed by the link manager 150 .

[0049] At operation 215, the processing device may store the transfer units and pointers associated with each transfer unit in a shared memory. The shared memory may be accessed by multiple processing cores, such as an input / output (I / O) core, an FTL core, and a processing core of a backend manager. For example, the processing device of the transformation manager (e.g., FTL) may store at least one pointer of a linked list in a shared memory shared by multiple cores, the at least one pointer indicating the next transfer unit of the linked list. In some instances, the method 200 may include storing multiple transfer units in a shared memory of the memory subsystem based on receiving multiple commands. In some instances, as shown in reference Figure 1 As described, aspects of the operation of 215 may be performed by the link manager 150 .

[0050] At operation 220, the processing device may send an indicator of the first transmission unit of the linked list to the processing core. For example, the processing core of the front-end manager may send an indicator of the first transmission unit of the linked list from the input / output core to the processing core based on storing at least one pointer in the shared memory. The indicator may be associated with the first transmission unit and sent to the processing core instead of sending the first transmission unit. In some examples, as shown in FIG. Figure 1 As described, aspects of the operation of 220 may be performed by the link manager 150 .

[0051] At operation 225, the processing device may retrieve the transmission units from the shared memory. For example, the processing device may retrieve the plurality of transmission units from the shared memory based on sending an indicator of the first transmission unit and storing at least one pointer in the shared memory. The processing core may receive the indicator and retrieve the transmission unit associated with the indicator. In some cases, the transmission unit may include a pointer indicating the next transmission unit in a linked list of transmission units. The processing core may retrieve a subsequent transmission unit (e.g., the next transmission unit) based on the pointer associated with the first transmission unit. For example, retrieving the plurality of transmission units may include retrieving the first transmission unit from the shared memory based on sending the indicator. In some instances, retrieving the plurality of transmission units may include retrieving at least one pointer from the shared memory based on retrieving the first transmission unit from the shared memory. In some instances, retrieving the plurality of transmission units may include retrieving the next transmission unit from the shared memory based on retrieving the at least one pointer.

[0052] In some cases, the processing core may retrieve a second pointer associated with the second next transmission unit. The second pointer may indicate the second next transmission unit in the transmission unit linked list. Method 200 may include retrieving the second pointer from the shared memory based on retrieving the next transmission unit from the shared memory, and identifying the second next transmission unit based on the second pointer. In some cases, the second next transmission unit may be located after the first transmission unit in the linked list. The second next transmission unit may be linked to the second pointer based on the order in which the write command was received, the write address of the second next transmission unit, or both. In some instances, method 200 may include identifying that a second pointer associated with a second transmission unit in the plurality of transmission units is stored in the shared memory based on retrieving the transmission unit from the shared memory. In some instances, method 200 may include retrieving the second transmission unit from the shared memory based on identifying that the second pointer is stored in the shared memory. In some instances, the processing core of the conversion manager may receive a single call for several transmission units to be included in the linked list.

[0053] In such cases, retrieving the plurality of transmission units can be based on sending a single indicator of a first transmission unit of the plurality of transmission units. In some instances, the indicator comprises a single indicator. In some instances, the processing device can perform a write process based on retrieving the plurality of transmission units from the shared memory to write the plurality of transmission units to a memory device of the memory subsystem. In some instances, as described with reference to Figure 1 As described, aspects of the operation of 225 may be performed by the link manager 150 .

[0054] Figure 3 FIG3 is a block diagram 300 of an example system that supports command batching for a memory subsystem according to some examples of the present disclosure. Block diagram 300 may include a memory subsystem 305. Memory subsystem 305 may include a front-end manager 310, a switch manager 315, a back-end manager 325, and a shared memory 330. Switch manager 315 may include a cursor 320. Block diagram 300 may also include a host system 335.

[0055] The memory subsystem 305 can receive commands for transfer units of the memory subsystem 305 from the host system 335. A cursor 320 can be used to abstract the data layout and write order of the media. For example, the cursor 320 can be located between the front-end manager 310 and the back-end manager 325, which handle the user data in the transfer units. The cursor 320 can ensure that the data is written within the range of NAND flash memory cells indicated in the command received from the host system 335. For example, a write process can be executed to write the transfer units to the memory devices of the memory subsystem 305. The cursor 320 can also aggregate the transfer units into groups for back-end operations at the back-end manager 325. Back-end operations can include issuing B commands to write data to the memory devices of the memory subsystem 305 based on retrieving and aggregating the transfer units into groups.

[0056] In some cases, the front-end manager 310 may generate a list of transfer units. The list may include pointers between each transfer unit. In such cases, the list may be an example of a linked list. For example, a pointer may be associated with a transfer unit and indicate the next transfer unit in the linked list of transfer units. Each transfer unit may include a corresponding pointer. The linked list of transfer units may enable the memory subsystem 305 to improve the overall efficiency of the memory subsystem 305 by operating the transfer units at increased write speeds.

[0057] In some instances, the front-end manager 310 may submit a linked list to a write cursor (e.g., cursor 320). In such instances, the write cursor may package information so that it can iterate over the linked list multiple times. For example, cursor 320 may retrieve a transmission unit in a linked list and then retrieve the next transmission unit in the linked list based on multiple iterations over the same linked list. The transmission units may be linked to each other regardless of the host command received from the host system 335. In such instances, the links between transmission units in the linked list are independent of the host command.

[0058] The operation of cursor 320 can change based on the indication of receiving the linked list. For example, cursor 320 can receive a single call (e.g., a single indicator) associated with the generation of the linked list. In such a case, cursor 320 can receive a single call for several transmission units to be included in the linked list. Based on sending a single call for the first transmission unit included in the linked list, the transmission unit can be retrieved from the linked list. In a conventional memory subsystem, cursor 320 may receive multiple calls for several transmission units, thereby increasing the processing time associated with performing a write operation and reducing overall performance. By receiving a single call for several transmission units, the memory subsystem can reduce the processing time associated with performing a write operation.

[0059] In some cases, shared memory 330 may share more than one layer of firmware (e.g., front-end manager 310, conversion manager 315, and back-end manager 325). Each layer of firmware may be implemented by one or more processing cores. In some embodiments, some processing cores may be dedicated to performing the functions of a particular layer. For example, a first group of cores (e.g., I / O cores) may be dedicated to performing the functions of front-end manager 310, a second group of cores (e.g., FTL cores) may be dedicated to performing the functions of conversion manager 315, and / or a third group of cores may be dedicated to performing the functions of back-end manager 325. In some embodiments, one or more cores may perform functions associated with more than one layer of firmware. A pointer to a linked list may be stored in shared memory 330, where the pointer may indicate the next transfer unit in the linked list. In some cases, the transfer unit and linked list may be stored in shared memory 330. In such cases, the various processing cores associated with each layer may access the pointers, linked lists, and transfer units stored in shared memory 330.

[0060] Front-end manager 310 may send an indicator (e.g., a systag) of the first transmission unit of the linked list from the I / O core to the processing core. The indicator may be an instance of an internal data description and control block, which may be used to transfer user data information and data between hardware and firmware components. The processing core configured to receive the indicator may be included in conversion manager 315 or back-end manager 325. The indicator may include a link to the first transmission unit stored in shared memory. For example, front-end manager 310 may send a single indicator including a link to the first transmission unit among the transmission units stored in shared memory 330 from one processing core to a different processing core. When back-end manager 325 receives the indicator, back-end manager 325 may retrieve the transmission unit linked to the indicator. In some cases, the processing core receiving the indicator may request whether shared memory 330 contains the transmission unit linked to the indicator. If shared memory 330 contains the transmission unit linked to the indicator, the transmission unit may be retrieved from shared memory 330.

[0061] Based on sending an indicator of the first transmission unit and storing the pointer in shared memory 330, the transmission unit can be retrieved from shared memory 330. In such cases, the indicator can be passed down to cursor 320, eliminating the need for the firmware to access and review all indicators. Cursor 320 can iterate over the indicators for multiple host commands received from host system 335, regardless of the host command. Upon receiving an indicator pointing to the first portion of the linked list (e.g., the first transmission unit), if the indicator is linked to a transmission unit, cursor 320 can retrieve the transmission unit from shared memory 330. The next transmission unit can be retrieved based on the pointer of the first transmission unit indicating the next transmission unit. Thus, indicators can be sent to the processing core to retrieve one or more transmission units from shared memory 330 until all transmission units have been retrieved.

[0062] In such cases, by sending an indicator of the first transfer unit relative to the first transfer unit itself, the amount of signaling between the host system 335 and the memory subsystem 305 can be reduced, thereby reducing the latency of future write operations. In such cases, the message size of the indicator can be smaller than the message size of the first transfer unit, thereby reducing the size of messages transmitted between the front-end manager 310 and the back-end manager 325. In some examples, the number of messages transmitted between the processing cores can be reduced based on generating the linked list and sending the indicator of the transfer unit. Reducing the number of messages transmitted between the processing cores can minimize the overhead of wasted cycles moving transfer units from the front-end manager 310 to the back-end manager 325.

[0063] In some cases, a pointer may be retrieved from shared memory 330 based on retrieving the first transmission unit. The pointer may identify the next transmission unit in the linked list stored in shared memory 330. In such cases, the next transmission unit may be retrieved based on retrieving the pointer. In some instances, a next pointer may be retrieved from shared memory 330. The next pointer may be associated with the next transmission unit and may identify the second next transmission unit in the chain of transmission units in the linked list. Thus, based on retrieving the next pointer from shared memory 330, the second next transmission unit may be retrieved from shared memory 330.

[0064] In some instances, an indicator may be added to an internal command (e.g., a B command) in cursor 320. An internal command may include an instruction to write data to a memory device of memory subsystem 305. Transfer units in a linked list may be assigned to the internal command. In some instances, cursor 320 assigns several indicators to pointers to retrieve the transfer units associated with the pointers from shared memory 330, allowing cursor 320 to iterate over the internal commands without interacting with host system 335 for each command. In conventional memory subsystems, indicators may be retrieved from an external source (e.g., a mailbox) and then transferred to cursor 320, thereby increasing the processing time associated with performing write operations. In some cases, cursor 320 may determine that a field of an internal command is full (e.g., occupied). For example, cursor 320 may determine that a field of an internal command is full based on assigning a transfer unit to the internal command. If the field of the internal command is full, cursor 320 may send the internal command to backend manager 325 (e.g., a memory device).

[0065] Figure 4 is a block diagram of an example computer system that supports command batching for a memory subsystem according to some examples of the present disclosure. The computer system 400 may include an instruction set for causing a machine to perform any one or more of the techniques described herein. In some examples, the computer system 400 may correspond to a host system (e.g., a reference Figure 1 105) that includes, is coupled to, or utilizes a memory subsystem (e.g., reference Figure 1 10) or can be used to perform operations of the controller (e.g., to execute an operating system to execute operations corresponding to the reference Figure 1 In some examples, the machine may be connected (e.g., using a network) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0066] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Further, while a single machine is shown, the term "machine" should also be taken to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0067] The example computer system 400 includes a processing device 405, a main memory 410 (e.g., ROM, flash memory, DRAM such as SDRAM or Rambus DRAM (RDRAM)), a static memory 415 (e.g., flash memory, static RAM (SRAM)), etc.), and a data storage system 425, which communicate with each other via a bus 445.

[0068] Processing device 405 represents one or more general-purpose processing devices, such as microprocessors, central processing units, and the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing another instruction set, or a processor implementing a combination of instruction sets. Processing device 405 may also be one or more special-purpose processing devices, such as an ASIC, an FPGA, a DSP, a network processor, and the like. Processing device 405 is configured to execute instructions 435 for performing the operations and steps discussed herein. Computer system 400 may further include a network interface device 420 for communicating via a network 440.

[0069] The data storage system 425 may include a machine-readable storage medium 430 (also referred to as a computer-readable medium) having stored thereon one or more sets of instructions 435 or software embodying any one or more of the methodologies or functions described herein. The instructions 435 may also reside, completely or at least partially, within the main memory 410 and / or within the processing device 405 during execution by the computer system 400, with the main memory 410 and the processing device 405 also constituting machine-readable storage media. The machine-readable storage medium 430, the data storage system 425, and / or the main memory 410 may correspond to a memory subsystem.

[0070] In one example, instructions 435 include implementing instructions corresponding to link manager 450 (e.g., referring to Figure 1 The machine-readable storage medium 430 is a device that stores instructions for the functions of the link manager 150 described herein. Although the machine-readable storage medium 430 is shown as a single medium, the term "machine-readable storage medium" may include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" may also include any medium that can store or encode a set of instructions for execution by a machine and cause the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" may include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0071] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations that leads to a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0072] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0073] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored on a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any other type of medium suitable for storing electronic instructions and each coupled to a computer system bus.

[0074] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with programs according to the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that the teachings of the present disclosure as described herein can be implemented using various programming languages.

[0075] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some instances, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as ROM, RAM, magnetic disk storage media, optical storage media, flash memory components, and the like.

[0076] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the examples of the present disclosure as set forth in the appended claims. The specification and drawings are, therefore, to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A method comprising: receiving a plurality of commands for a plurality of transfer units of a memory subsystem, each of the plurality of transfer units comprising a block of data to be written to a non-volatile memory device; generating a list of the plurality of transmission units based at least in part on receiving the plurality of commands; storing, by the input / output core, at least one pointer to the list in a shared memory based at least in part on generating the list; as well as Based at least in part on storing the at least one pointer in the shared memory, the plurality of transfer units, each comprising the block of data to be written to the non-volatile memory device, are retrieved from the shared memory.

2. The method according to claim 1, further comprising: Based at least in part on storing the at least one pointer in the shared memory, an indicator of a first transfer unit of the list is sent from the input / output core to a processing core. 3 . The method of claim 2 , wherein retrieving the plurality of transmission units is based at least in part on sending the indicator of the first transmission unit, wherein the plurality of transmission units are retrieved by the processing core. The method of claim 2 , wherein the indicator comprises a link to the first transmission unit stored in the shared memory.

5. The method according to claim 1, further comprising: Based at least in part on retrieving the plurality of transmission units, a pointer indicating a next transmission unit of the list of the plurality of transmission units is retrieved from the shared memory.

6. The method according to claim 5, further comprising: A second next transmission unit in the list of the plurality of transmission units is identified based at least in part on retrieving the pointer.

7. The method according to claim 1, further comprising: The list of the plurality of transmission units is sent to a write cursor based at least in part on generating the list, wherein retrieving the plurality of transmission units is based at least in part on sending the list to the write cursor. The method of claim 1 , wherein the list of the plurality of transmission units comprises pointers between the plurality of transmission units.

9. The method of claim 8, wherein the at least one pointer indicates a next transmission unit in the list of the plurality of transmission units.

10. A system comprising: a plurality of memory devices; as well as a processing device operatively coupled to the plurality of memory devices, configured to: receiving a plurality of commands for a plurality of transfer units of a memory subsystem, each of the plurality of transfer units comprising a block of data to be written to a non-volatile memory device; generating a list of the plurality of transmission units based at least in part on receiving the plurality of commands; storing, by the input / output core, at least one pointer to the list in a shared memory based at least in part on generating the list; as well as Based at least in part on storing the at least one pointer in the shared memory, the plurality of transfer units, each comprising the block of data to be written to the non-volatile memory device, are retrieved from the shared memory.

11. The system of claim 10, further comprising: The processing device is configured to perform the following operations: An indicator of a first transmission unit of the list is sent from the input / output core based at least in part on storing the at least one pointer in the shared memory.

12. The system of claim 11, wherein retrieving the plurality of transmission units is based at least in part on sending the indicator of the first transmission unit, wherein the indicator of the first transmission unit is sent to a processing core.

13. The system of claim 11, wherein the indicator comprises a system tag for communicating user data information between hardware and firmware components of the non-volatile memory device.

14. The system of claim 11, further comprising: The processing device is configured to perform the following operations: determining, based at least in part on the request, whether the shared memory includes a transfer unit linked to the indicator; and The transmission unit linked to the indicator is retrieved based at least in part on determining that the shared memory includes the transmission unit.

15. The system of claim 10, wherein the at least one pointer between the plurality of transmission units indicates a next transmission unit of the list of the plurality of transmission units.

16. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to: receiving a plurality of commands for a plurality of transfer units of a memory subsystem, each of the plurality of transfer units comprising a block of data to be written to a non-volatile memory device; generating a list of the plurality of transmission units based at least in part on receiving the plurality of commands; storing, by the input / output core, at least one pointer to the list in a shared memory based at least in part on generating the list; as well as Based at least in part on storing the at least one pointer in the shared memory, the plurality of transfer units, each comprising the block of data to be written to the non-volatile memory device, are retrieved from the shared memory.

17. The non-transitory computer-readable storage medium of claim 16, wherein the processing device further performs the following operations: Based at least in part on storing the at least one pointer in the shared memory, an indicator of a first transmission unit of the list is sent to a processing core.

18. The non-transitory computer-readable storage medium of claim 17, wherein the indicator comprises a message size that is smaller than a message size of the first transmission unit.

19. The non-transitory computer-readable storage medium of claim 17, wherein the processing device further performs the following operations: The indicator is added to an internal command to write data to the non-volatile memory device of the memory subsystem based at least in part on retrieving the plurality of transfer units.

20. The non-transitory computer-readable storage medium of claim 16, wherein the list of the plurality of transmission units comprises pointers between the plurality of transmission units, wherein the at least one pointer indicates a next transmission unit in the list of the plurality of transmission units.

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