Branch prediction processing method and related equipment
By deciding whether to release the first-level cache resources occupied by the target instruction on the wrong branch path based on the branch instruction type and cache resource situation when branch prediction errors are made, the problem of repeated data acquisition caused by branch prediction errors is solved, and processor performance is improved.
Patent Information
- Application Number
- CN202411365941.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2024-12-27
AI Technical Summary
Branch prediction errors cause instructions on the wrong branch path to occupy the memory access resource, affecting the execution of instructions on the correct branch path, and causing the processor to repeatedly obtain data, degrading processor performance.
When a branch predicts errors, based on the type of branch instructions and cache resources, it is decided whether to perform some resource release operations, release the first-level cache resources occupied by the target instructions on the wrong branch path, retain other cache resources, and avoid repeated data acquisition.
By freeing the first-level cache resources occupied by the target instruction on the wrong branch path, it reduces the impact on the correct branch path, and by retaining the data on the wrong branch path in other caches, it avoids the processor from retrieving data repeatedly, thereby improving processor performance .
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Figure CN119201467A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of computer technology, and in particular to a branch prediction processing method and related equipment. Background Art
[0002] Current high-performance processors are basically out-of-order execution processors, which mainly use methods such as branch prediction to solve problems such as data dependencies between out-of-order execution instructions. However, branch prediction is not always accurate, and branch prediction errors may occur.
[0003] Because the execution of instructions on the wrong branch path, such as memory access instructions, will occupy memory access resources and affect the execution of instructions on the correct branch path, the memory access resources occupied by the instructions on the wrong branch path are usually released. However, this will cause the data accessed by the instructions on the wrong branch path to be deleted, and these data may be data that subsequent instructions need to access, resulting in the need to re-acquire these data from the memory when executing subsequent instructions, which is not conducive to improving processor performance. Summary of the invention
[0004] The present application discloses a branch prediction processing method and related devices to avoid a processor from repeatedly acquiring data, thereby improving the performance of the processor.
[0005] In a first aspect, the present application discloses a branch prediction processing method, including: obtaining a branch prediction result of a branch instruction; in a case where the branch prediction result is a branch prediction error, determining whether to perform a partial resource release operation based on the type of the branch instruction; the partial resource release operation is at least used to release the resources of the first-level cache occupied by the target instruction on the erroneous branch path, and retain the resources of other caches occupied by all instructions on the erroneous branch path; the target instruction at least includes a memory access instruction in which the data accessed in the instruction younger than the branch instruction is not in the first-level cache.
[0006] In some embodiments of the present application, the partial resource release operation is used to release the resources of the first-level cache occupied by the target instruction on the erroneous branch path, retain the resources of the second-level cache occupied by all instructions on the erroneous branch path, and control the second-level cache not to backfill the data accessed by the target instruction to the first-level cache; the target instruction includes a memory access instruction in which the data accessed in the instruction younger than the branch instruction is not in the first-level cache.
[0007] In some embodiments of the present application, determining whether to execute a partial resource release operation based on the type of the branch instruction includes: determining whether the branch instruction is an unconditional branch instruction; if the branch instruction is an unconditional branch instruction, executing the partial resource release operation.
[0008] In some embodiments of the present application, it also includes: if the branch instruction is not an unconditional branch instruction, determining whether to execute the partial resource release operation based on the remaining amount of resources in the first-level cache and / or the availability of data accessed by the instructions on the erroneous branch path.
[0009] In some embodiments of the present application, determining whether to execute the partial resource release operation based on the remaining amount of resources in the first-level cache includes: if the remaining amount of resources in the first-level cache is less than a preset value, executing the partial resource release operation; if the remaining amount of resources in the first-level cache is greater than or equal to the preset value, not executing the partial resource release operation, and retaining the resources of the first-level cache occupied by all instructions on the error branch path.
[0010] In some embodiments of the present application, determining whether to execute the partial resource release operation based on the availability of the data accessed by the instructions on the erroneous branch path includes: after refreshing the pipeline where the branch instruction is located, recording the number of times that the data accessed by the instructions on the erroneous branch path and backfilled into the first-level cache has not been accessed; if the number of times the data has not been accessed is greater than a preset number, then executing the partial resource release operation when the next branch prediction result is a branch prediction error.
[0011] In some embodiments of the present application, before determining whether to execute a partial resource release operation based on the type of the branch instruction, it also includes: obtaining the memory access status and new and old identifiers of the instructions on the erroneous branch path, the new and old identifiers being used to indicate whether the instruction is younger than the branch instruction, and the memory access status being used to indicate whether the instruction is an instruction that accesses data that is not in the first-level cache.
[0012] In a second aspect, the present application discloses a processor configured to execute the branch prediction processing method as described in any one of the above items.
[0013] In a third aspect, the present application discloses an electronic device, comprising a processor and a memory; wherein the memory is connected to the processor, and the memory is used to store a computer program; the processor is used to implement a branch prediction processing method as described in any one of the above items by running the computer program stored in the memory.
[0014] In a fourth aspect, the present application discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the branch prediction processing method as described in any one of the above items is executed.
[0015] The branch prediction processing method and related equipment disclosed in the present application determine whether to execute a partial resource release operation according to the type of the branch instruction when the branch prediction result of the branch instruction is a branch prediction error, because the partial resource release operation is at least used to release the resources of the first-level cache occupied by the target instruction on the erroneous branch path, and retain the resources of other caches occupied by all instructions on the erroneous branch path, and the target instruction includes instructions whose data accessed by instructions younger than the branch instruction are not in the first-level cache. Therefore, not only can the target instruction on the erroneous branch path be prevented from occupying the resources of the first-level cache and affecting the execution of the instructions on the correct branch path by releasing the resources of the first-level cache occupied by the target instruction, but also the data accessed by all instructions on the erroneous branch path can be retained by retaining the resources of other caches occupied by all instructions on the erroneous branch path, thereby avoiding the processor or processor core from repeatedly obtaining these data from the memory, thereby improving the performance of the processor. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.
[0017] Figure 1 A schematic diagram of the structure of a processor disclosed in an embodiment of the present application.
[0018] Figure 2 This is a flowchart of a branch prediction processing method disclosed in an embodiment of the present application.
[0019] Figure 3 This is a flowchart of another branch prediction processing method disclosed in an embodiment of the present application.
[0020] Figure 4 This is a flowchart of another branch prediction processing method disclosed in an embodiment of the present application. DETAILED DESCRIPTION
[0021] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0022] like Figure 1 As shown, Figure 1 The structure diagram of a superscalar processor disclosed in an embodiment of the present application is shown in FIG. 1 , wherein the superscalar processor includes one or more processor cores 10, a cache control module 11 and two or more levels of cache, wherein: Figure 1In the description, only a superscalar processor including a first-level Cache L1, a second-level Cache L2 and a third-level Cache L3 is taken as an example to illustrate that the first-level Cache L1 is used to cache instructions or data frequently hit by the processor core 10, the second-level Cache L2 is used to cache data exclusive to the processor core 10, and the data stored in the third-level Cache L3 is shared by each processor core 10.
[0023] Among them, the cache control module 11 is used to perform operations such as writing data at the corresponding address of the memory 12 into the cache or reading data at the corresponding address of the memory 12 temporarily stored in the cache according to the request of the processor core 10. For example, when executing an instruction such as a memory access instruction, the processor core 10 will send a first-level cache access request to the cache control module 11, and the cache control module 11 will check whether the first-level cache L1 has the data to be accessed. If not, the processor core 10 will send a second-level cache access request to the cache control module 11, and the cache control module 11 will check whether the second-level cache L2 has the data to be accessed. If it is in the second-level cache L2, the data in the second-level cache L2 will be fed back to the processor core 10 and backfilled into the first-level cache L1, so that the processor core 10 can directly read the data in the first-level cache L1 next time. If not, the processor core 10 will send a second-level cache access request to the cache control module 11. The cache control module 11 will check whether the second-level cache L2 has the data to be accessed. If it is in the second-level cache L2, the data in the second-level cache L2 will be fed back to the processor core 10 and backfilled into the first-level cache L1. The control module 11 sends a third-level cache access request, and the cache control module 11 will check whether the third-level cache L3 has the data to be accessed. If the third-level cache L3 has the data to be accessed, the data in the third-level cache L3 will be fed back to the processor core 10, and the data will be backfilled into the second-level cache L2, and the second-level cache L2 will backfill the data into the first-level cache L1. If the third-level cache L3 does not have the data, the processor core 10 will send a memory access request to the memory control module, and the memory 12 will write the data to be accessed into the third-level cache L3, and the third-level cache L3 will feed back the data to the processor core 10, and backfill it into the second-level cache L2, and the second-level cache L2 will backfill the data into the first-level cache L1.
[0024] The processor core 10 of the current superscalar processor uses pipeline technology to execute instructions. The pipeline usually includes multiple stages such as instruction fetching, decoding and execution. By controlling different instructions to enter different stages, multiple instructions can be executed in parallel. However, if an instruction in the pipeline is a branch instruction, the instruction may jump due to the different true / false judgment conditions of the branch instruction. Therefore, in the absence of branch prediction, the processor core 10 will wait until the branch instruction passes the execution stage before controlling the next instruction to enter the instruction fetch stage.
[0025] In the case of branch prediction, this waiting can be avoided by predicting whether the branch instruction may jump. Assuming that the branch instruction is predicted to jump, and the instruction on the first branch path is executed after the jump, the processor core 10 will control the next instruction on the first branch path to enter the instruction fetch stage after the branch instruction enters the decoding stage. If the branch prediction is correct, the waiting time of the processor core 10 can be reduced. If the branch prediction is wrong, the pipeline is refreshed and the next instruction of the branch instruction on the second branch path is controlled to enter the instruction fetch stage.
[0026] After refreshing the pipeline, the processor core 10 usually releases the memory resources occupied by the instructions on the wrong branch path, such as the first branch path, such as releasing the storage space occupied by the instructions in the first-level cache L1, the second-level cache L2, and the third-level cache L3. If the memory resources occupied by the instructions on the wrong branch path are not released, the execution of the correct branch path, such as the instructions on the second branch path, will be affected. However, if the memory resources occupied by the instructions on the wrong branch path are released, this will cause the data accessed by the instructions on the wrong branch path to be deleted by the first-level cache L1, the second-level cache L2, and the third-level cache L3, and these data may be data that subsequent instructions need to access, resulting in the need to re-acquire these data from the memory 12 when executing subsequent instructions, which is not conducive to improving the performance of the processor.
[0027] For example, although the judgment condition is false when the branch instruction is executed this time, the branch instruction does not jump, and the second branch path is the correct branch path. However, when the branch instruction is executed next time, if the judgment condition is true, the branch instruction jumps, and the first branch path is the correct branch path. However, because the data pre-fetched by the instructions on the first branch path has been deleted, it is necessary to re-obtain the data to be accessed from memory 12.
[0028] Based on this, the present application discloses a branch prediction processing method. In the case of a branch prediction error, it determines whether to execute a partial resource release operation according to the type of branch instruction. This can not only avoid the target instructions on the wrong branch path occupying the resources of the first-level cache and affecting the execution of instructions on the correct branch path, but also avoid the processor or processor core repeatedly obtaining data from the memory, thereby improving the performance of the processor.
[0029] As an optional implementation of the content disclosed in this application, the embodiment of this application discloses a branch prediction processing method, which is applied to a processor, such as Figure 2 As shown, Figure 2 A flow chart of a branch prediction processing method disclosed in an embodiment of the present application, the method comprising:
[0030] S101: Obtain a branch prediction result of a branch instruction.
[0031] In the embodiment of the present application, the processor includes a branch predictor, which is used to perform branch prediction on a branch instruction so that the processor can fetch the next instruction of the branch instruction according to the branch prediction result. The processor can obtain the branch prediction result of the branch predictor for the branch instruction, and determine whether the branch prediction result is a correct branch prediction or an incorrect branch prediction according to the execution result of the branch instruction.
[0032] S102: When the branch prediction result is an erroneous branch prediction, determine whether to execute a partial resource release operation according to the type of the branch instruction.
[0033] Among them, the partial resource release operation is used to release the resources of the first-level cache occupied by the target instructions on the erroneous branch path, and retain the resources of other caches occupied by all instructions on the erroneous branch path. The target instructions at least include memory access instructions in which the data accessed in instructions younger than the branch instructions is not in the first-level cache.
[0034] Based on this, not only can the target instructions on the wrong branch path be prevented from occupying the resources of the first-level cache and affecting the execution of the instructions on the correct branch path by releasing the resources of the first-level cache occupied by the target instructions, but also the data accessed by all instructions on the wrong branch path can be retained by retaining the resources of other caches occupied by all instructions on the wrong branch path, thereby avoiding the processor or processor core repeatedly obtaining this data from the memory, thereby improving the performance of the processor.
[0035] In some embodiments of the present application, a partial resource release operation is used to release the resources of the first-level cache occupied by the target instruction on the erroneous branch path, retain the resources of the second-level cache occupied by all instructions on the erroneous branch path, and control the second-level cache not to backfill the data accessed by the target instruction to the first-level cache. The target instruction includes a memory access instruction in which the data accessed in the instruction younger than the branch instruction is not in the first-level cache. It is understandable that the instruction younger than the branch instruction refers to the instruction whose execution order is after the branch instruction.
[0036] It should be noted that the resources of the first-level cache may include not only the storage resources of the first-level cache, but also the storage resources of the first-level TLB (Translation Lookaside Buffer, page table cache). The resources of the second-level cache may include not only the storage resources of the second-level cache, but also the storage resources of the second-level TLB. It should be noted that the resources of the first-level cache occupied by the target instruction may be released by releasing the first-level cache access request and the first-level TLB access request of the target instruction in the first-level cache access request queue and the first-level TLB access request queue.
[0037] It should also be noted that the instruction for accessing data that is not in the first-level cache may include instructions for accessing data that is not in the first-level cache, but no data access request is initiated to the lower-level cache (such as the second-level cache). It may also include instructions for accessing data that is not in the first-level cache, and a data access request has been initiated to the lower-level cache (such as the second-level cache), but the data to be accessed has not been backfilled into the first-level cache. It does not include instructions for accessing data that is not in the first-level cache, and a data access request has been initiated to the lower-level cache (such as the second-level cache), and the data to be accessed has been backfilled into the first-level cache.
[0038] It is understandable that, because the data that the target instruction needs to access is not in the first-level cache, there is no need to occupy the resources of the first-level cache, and the resources of the first-level cache occupied by the target instruction can be released. However, in the case where the availability of the data that the target instruction needs to access is good, the resources of the second-level cache occupied by the target instruction can be retained so that the data that the target instruction needs to access is stored in the second-level cache. When the data that the target instruction needs to access needs to be obtained next time, the data in the second-level cache can be directly backfilled into the first-level cache, so that there is no need to repeatedly obtain data from the memory.
[0039] Based on this, not only can the resources of the first-level cache occupied by at least part of the instructions be released and the second-level cache can be controlled not to backfill the data accessed by at least part of the instructions to the first-level cache, so as to avoid at least part of the instructions on the wrong branch path occupying the resources of the first-level cache and affecting the execution of the instructions on the correct branch path, but also the resources of the second-level cache occupied by all instructions on the wrong branch path can be retained to retain the data accessed by all instructions on the wrong branch path in the second-level cache, thereby avoiding the processor or processor core repeatedly obtaining this data from the memory, thereby improving the performance of the processor.
[0040] Of course, the present invention is not limited to this, and the partial resource release operation can also be used to release the resources of the first-level cache and the second-level cache occupied by the target instruction on the wrong branch path, retain the resources of the third-level cache occupied by all instructions on the wrong branch path, and control the third-level cache not to backfill the data accessed by the target instruction to the second-level cache. The target instruction includes a memory access instruction whose data accessed by the instruction younger than the branch instruction is not in the first-level cache and the second-level cache.
[0041] In some embodiments of the present application, the memory access status and new and old identifiers of the instructions on the error branch path can be obtained, the new and old identifiers are used to indicate the new and old relationship between the instructions, the memory access status is used to indicate the state of the data accessed by the instruction in the cache, and it is determined based on the memory access status whether the instruction on the error branch path is an instruction that accesses data that is not in the first-level cache, and based on the new and old identifiers, it is determined whether the instruction on the error branch path is an instruction younger than the branch instruction. In other embodiments, it is also possible to determine based on the memory access status whether the instruction on the error branch path is an instruction that accesses data that is not in the first-level cache and the second-level cache, which will not be repeated here.
[0042] Because the type of branch instruction can reflect the behavioral characteristics of the computer program to a certain extent, for example, an unconditional branch instruction indicates that the computer program will definitely jump instructions. After a branch prediction error occurs, the data availability of the instruction predicted to be executed is poor, so the memory resources occupied by the target instruction on the wrong branch path can be released. However, a conditional branch instruction does not necessarily jump instructions, that is, the conditional branch instruction jumps under the current judgment condition, but may not jump under the next judgment condition. After a branch prediction error occurs, the data availability of the instruction predicted to be executed is good, so the memory resources occupied by all instructions on the wrong branch path may not be released.
[0043] Based on this, in some embodiments of the present application, Figure 3 As shown, Figure 3 This is a flowchart of another branch prediction processing method disclosed in an embodiment of the present application. When the branch prediction result is an erroneous branch prediction, execute step S1020; S1020: determine whether the branch instruction is an unconditional branch instruction; if the branch instruction is an unconditional branch instruction, execute step S1021; S1021: execute a partial resource release operation, which is the same as the above, so as to avoid the target instruction on the erroneous branch path occupying the resources of the first-level cache while avoiding the processor or processor core repeatedly obtaining the data of the unconditional branch instruction; if the branch instruction is not an unconditional branch instruction, the branch instruction can be any instruction other than the unconditional branch instruction, and execute step S1022; S1022: determine whether to execute a partial resource release operation based on the remaining amount of resources in the first-level cache.
[0044] In some embodiments of the present application, if the remaining amount of resources in the first-level cache is less than a preset value, the above-mentioned partial resource release operation is performed; if the remaining amount of resources in the first-level cache is greater than or equal to the preset value, the above-mentioned partial resource release operation is not performed, and the resources of the first-level cache occupied by all instructions on the error branch path are retained. In other words, when the remaining amount of resources in the first-level cache is large, the above-mentioned partial resource release operation may not be performed; when the remaining amount of resources in the first-level cache is small, the above-mentioned partial resource release operation may be performed.
[0045] Of course, the present application is not limited to this. In other embodiments, the preset value may not be set. Instead, whether to execute the above-mentioned partial resource release operation is determined based on the comparison result of the remaining amount of resources in the first-level cache and the amount of resources in the first-level cache that need to be occupied. No further details will be given here.
[0046] Of course, the present application is not limited to this. In other embodiments, such as Figure 4 As shown, Figure 4 This is a flowchart of another branch prediction processing method disclosed in an embodiment of the present application. If the branch instruction is not an unconditional branch instruction, and the branch instruction can be any instruction other than the unconditional branch instruction, then S1023 is executed; S1023: Determine whether to execute a partial resource release operation based on the availability of data accessed by the instructions on the erroneous branch path.
[0047] That is, if the data accessed by the instructions on the erroneous branch path has good availability, the above-mentioned partial resource release operation may not be performed; if the data accessed by the instructions on the erroneous branch path has poor availability, the above-mentioned partial resource release operation may be performed.
[0048] In some embodiments, after refreshing the pipeline where the branch instruction is located, the above-mentioned partial resource release operation may not be performed first, but the number of times the data accessed by the instruction on the wrong branch path and the data backfilled to the first-level cache after refreshing before being replaced is recorded. If the number of times it has not been accessed is greater than the preset number of times, it means that the availability of the data is poor, and the resources of the first-level cache occupied by the data can be released. Then, the above-mentioned partial resource release operation can be performed when the next branch prediction result is a branch prediction error. If the number of times it has not been accessed is less than or equal to the preset number of times, it means that the availability of the data is good, and the resources of the cache occupied by the data may not be released.
[0049] In some embodiments, a counter may be used to record the number of times the data has not been accessed. For example, the number of times the data has been accessed may be counted every preset time. If the data has not been accessed, the counter is incremented by 1 until the value of the counter is equal to the preset number of times. The preset number of times may be 512 or 1024, etc.
[0050] In other embodiments, if the remaining amount of resources in the first-level cache is less than a preset value and the availability of data accessed by instructions on the erroneous branch path is poor, the above-mentioned partial resource release operation may be performed.
[0051] It should be noted that the present application only takes conditional branch instructions and unconditional branch instructions as examples to illustrate determining whether to execute a partial resource release operation according to the type of branch instruction, but is not limited to this.
[0052] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a processor configured to execute the branch prediction processing method disclosed in any of the above embodiments.
[0053] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses an electronic device, including a processor and a memory; wherein the memory is connected to the processor, and the memory is used to store a computer program; the processor is used to implement the branch prediction processing method disclosed in any of the above embodiments by running the computer program stored in the memory.
[0054] As another optional implementation of the contents disclosed in the present application, an embodiment of the present application further discloses a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the branch prediction processing method disclosed in any of the above embodiments is executed.
[0055] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0056] The above embodiments only express several implementation methods of this specification, and the descriptions are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of this specification, which all belong to the protection scope of this specification. Therefore, the protection scope of the patent of this specification shall be based on the attached claims.
Claims
1. A branch prediction processing method, characterized in that: include: Get the branch prediction result of the branch instruction; In the case where the branch prediction result is an erroneous branch prediction, determining whether to execute a partial resource release operation according to the type of the branch instruction; The partial resource release operation is at least used to release the resources of the first-level cache occupied by the target instruction on the erroneous branch path, and retain the resources of other caches occupied by all instructions on the erroneous branch path; the target instructions at least include memory access instructions in which the data accessed in instructions younger than the branch instructions is not in the first-level cache.
2. The method according to claim 1, characterized in that The partial resource release operation is used to release the resources of the first-level cache occupied by the target instruction on the erroneous branch path, retain the resources of the second-level cache occupied by all instructions on the erroneous branch path, and control the second-level cache not to backfill the data accessed by the target instruction to the first-level cache; the target instruction includes a memory access instruction in which the data accessed by the instruction younger than the branch instruction is not in the first-level cache.
3. The method according to claim 1 or 2, characterized in that: The determining whether to execute a partial resource release operation according to the type of the branch instruction includes: Determining whether the branch instruction is an unconditional branch instruction; If the branch instruction is an unconditional branch instruction, the partial resource release operation is performed.
4. The method according to claim 3, characterized in that Also includes: If the branch instruction is not an unconditional branch instruction, it is determined whether to execute the partial resource release operation according to the remaining amount of resources in the first-level cache and / or the availability of data accessed by the instructions on the erroneous branch path.
5. The method according to claim 4, characterized in that Determining whether to perform the partial resource release operation according to the remaining amount of the resources in the first-level cache includes: If the remaining amount of the resources in the first-level cache is less than a preset value, executing the partial resource release operation; If the remaining amount of the resources of the first-level cache is greater than or equal to the preset value, the partial resource release operation is not performed, and the cache resources occupied by all instructions on the erroneous branch path are retained.
6. The method according to claim 4, characterized in that Determining whether to execute the partial resource release operation according to the availability of data accessed by the instruction on the error branch path includes: After refreshing the pipeline where the branch instruction is located, recording the number of times that the data accessed by the instruction on the erroneous branch path and backfilled into the first-level cache is not accessed; If the number of times that the access is not performed is greater than the preset number, then when the next branch prediction result is a branch prediction error, the partial resource release operation is performed.
7. The method according to claim 1, characterized in that Before determining whether to execute a partial resource release operation according to the type of the branch instruction, the method further includes: Obtaining a memory access status and a new and old identifier of the instruction on the error branch path, wherein the new and old identifier is used to indicate the new and old relationship between the instructions, and the memory access status is used to indicate the status of the data accessed by the instruction in the cache; Determine, according to the memory access status, whether the instruction on the error branch path is an instruction that accesses data that is not in the first-level cache; According to the new and old identifiers, it is determined whether the instruction on the erroneous branch path is an instruction younger than the branch instruction.
8. A processor, characterized in that: The method is configured to execute the branch prediction processing method according to any one of claims 1 to 7.
9. An electronic device, characterized in that: It comprises a processor and a memory; wherein the memory is connected to the processor, and the memory is used to store a computer program; the processor is used to implement the branch prediction processing method according to any one of claims 1 to 7 by running the computer program stored in the memory.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the branch prediction processing method according to any one of claims 1 to 7 is executed.